./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.04.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 839c364b Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_243d7bef-cedc-44de-a9bb-da9fc6938811/bin/uautomizer-DrprNOufMa/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_243d7bef-cedc-44de-a9bb-da9fc6938811/bin/uautomizer-DrprNOufMa/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_243d7bef-cedc-44de-a9bb-da9fc6938811/bin/uautomizer-DrprNOufMa/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_243d7bef-cedc-44de-a9bb-da9fc6938811/bin/uautomizer-DrprNOufMa/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.04.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_243d7bef-cedc-44de-a9bb-da9fc6938811/bin/uautomizer-DrprNOufMa/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_243d7bef-cedc-44de-a9bb-da9fc6938811/bin/uautomizer-DrprNOufMa --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d4710f8f3a918a0191222414f5c33a367ff98c09c2e8598fa3213223c4c35dba --- Real Ultimate output --- This is Ultimate 0.2.2-hotfix-svcomp22-839c364 [2021-12-07 00:18:26,024 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-07 00:18:26,026 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-07 00:18:26,056 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-07 00:18:26,057 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-07 00:18:26,058 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-07 00:18:26,059 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-07 00:18:26,061 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-07 00:18:26,063 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-07 00:18:26,064 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-07 00:18:26,066 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-07 00:18:26,067 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-07 00:18:26,067 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-07 00:18:26,069 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-07 00:18:26,070 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-07 00:18:26,071 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-07 00:18:26,072 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-07 00:18:26,073 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-07 00:18:26,075 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-07 00:18:26,078 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-07 00:18:26,079 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-07 00:18:26,081 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-07 00:18:26,082 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-07 00:18:26,083 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-07 00:18:26,087 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-07 00:18:26,087 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-07 00:18:26,087 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-07 00:18:26,088 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-07 00:18:26,089 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-07 00:18:26,090 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-07 00:18:26,090 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-07 00:18:26,091 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-07 00:18:26,092 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-07 00:18:26,093 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-07 00:18:26,094 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-07 00:18:26,094 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-07 00:18:26,095 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-07 00:18:26,095 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-07 00:18:26,095 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-07 00:18:26,096 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-07 00:18:26,096 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-07 00:18:26,097 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_243d7bef-cedc-44de-a9bb-da9fc6938811/bin/uautomizer-DrprNOufMa/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-07 00:18:26,119 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-07 00:18:26,120 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-07 00:18:26,120 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-07 00:18:26,120 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-07 00:18:26,121 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-07 00:18:26,121 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-07 00:18:26,121 INFO L138 SettingsManager]: * Use SBE=true [2021-12-07 00:18:26,121 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-07 00:18:26,121 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-07 00:18:26,121 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-07 00:18:26,122 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-07 00:18:26,122 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-07 00:18:26,122 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-07 00:18:26,122 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-07 00:18:26,122 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-07 00:18:26,122 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-07 00:18:26,123 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-07 00:18:26,123 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-07 00:18:26,123 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-07 00:18:26,123 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-07 00:18:26,123 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-07 00:18:26,123 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-07 00:18:26,123 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-07 00:18:26,123 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-07 00:18:26,123 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-07 00:18:26,123 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-07 00:18:26,124 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-07 00:18:26,124 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-07 00:18:26,124 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-07 00:18:26,124 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-07 00:18:26,124 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-07 00:18:26,125 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-07 00:18:26,125 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-07 00:18:26,126 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_243d7bef-cedc-44de-a9bb-da9fc6938811/bin/uautomizer-DrprNOufMa/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_243d7bef-cedc-44de-a9bb-da9fc6938811/bin/uautomizer-DrprNOufMa Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d4710f8f3a918a0191222414f5c33a367ff98c09c2e8598fa3213223c4c35dba [2021-12-07 00:18:26,312 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-07 00:18:26,329 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-07 00:18:26,330 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-07 00:18:26,331 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-07 00:18:26,332 INFO L275 PluginConnector]: CDTParser initialized [2021-12-07 00:18:26,333 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_243d7bef-cedc-44de-a9bb-da9fc6938811/bin/uautomizer-DrprNOufMa/../../sv-benchmarks/c/systemc/token_ring.04.cil-1.c [2021-12-07 00:18:26,380 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_243d7bef-cedc-44de-a9bb-da9fc6938811/bin/uautomizer-DrprNOufMa/data/16bc1e380/5615ef9a04e048219eb7c4af81040e0b/FLAGe73ea7b6a [2021-12-07 00:18:26,780 INFO L306 CDTParser]: Found 1 translation units. [2021-12-07 00:18:26,781 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_243d7bef-cedc-44de-a9bb-da9fc6938811/sv-benchmarks/c/systemc/token_ring.04.cil-1.c [2021-12-07 00:18:26,789 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_243d7bef-cedc-44de-a9bb-da9fc6938811/bin/uautomizer-DrprNOufMa/data/16bc1e380/5615ef9a04e048219eb7c4af81040e0b/FLAGe73ea7b6a [2021-12-07 00:18:26,798 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_243d7bef-cedc-44de-a9bb-da9fc6938811/bin/uautomizer-DrprNOufMa/data/16bc1e380/5615ef9a04e048219eb7c4af81040e0b [2021-12-07 00:18:26,801 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-07 00:18:26,802 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-07 00:18:26,803 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-07 00:18:26,803 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-07 00:18:26,805 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-07 00:18:26,806 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 12:18:26" (1/1) ... [2021-12-07 00:18:26,807 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@560db043 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:18:26, skipping insertion in model container [2021-12-07 00:18:26,807 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 12:18:26" (1/1) ... [2021-12-07 00:18:26,812 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-07 00:18:26,836 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-07 00:18:26,946 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_243d7bef-cedc-44de-a9bb-da9fc6938811/sv-benchmarks/c/systemc/token_ring.04.cil-1.c[671,684] [2021-12-07 00:18:26,990 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-07 00:18:26,997 INFO L203 MainTranslator]: Completed pre-run [2021-12-07 00:18:27,005 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_243d7bef-cedc-44de-a9bb-da9fc6938811/sv-benchmarks/c/systemc/token_ring.04.cil-1.c[671,684] [2021-12-07 00:18:27,029 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-07 00:18:27,040 INFO L208 MainTranslator]: Completed translation [2021-12-07 00:18:27,041 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:18:27 WrapperNode [2021-12-07 00:18:27,041 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-07 00:18:27,041 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-07 00:18:27,042 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-07 00:18:27,042 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-07 00:18:27,047 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:18:27" (1/1) ... [2021-12-07 00:18:27,054 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:18:27" (1/1) ... [2021-12-07 00:18:27,086 INFO L137 Inliner]: procedures = 36, calls = 43, calls flagged for inlining = 38, calls inlined = 77, statements flattened = 1062 [2021-12-07 00:18:27,086 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-07 00:18:27,087 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-07 00:18:27,087 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-07 00:18:27,087 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-07 00:18:27,093 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:18:27" (1/1) ... [2021-12-07 00:18:27,093 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:18:27" (1/1) ... [2021-12-07 00:18:27,099 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:18:27" (1/1) ... [2021-12-07 00:18:27,099 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:18:27" (1/1) ... [2021-12-07 00:18:27,115 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:18:27" (1/1) ... [2021-12-07 00:18:27,125 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:18:27" (1/1) ... [2021-12-07 00:18:27,127 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:18:27" (1/1) ... [2021-12-07 00:18:27,132 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-07 00:18:27,133 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-07 00:18:27,133 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-07 00:18:27,133 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-07 00:18:27,134 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:18:27" (1/1) ... [2021-12-07 00:18:27,139 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-07 00:18:27,147 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_243d7bef-cedc-44de-a9bb-da9fc6938811/bin/uautomizer-DrprNOufMa/z3 [2021-12-07 00:18:27,157 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_243d7bef-cedc-44de-a9bb-da9fc6938811/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-07 00:18:27,160 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_243d7bef-cedc-44de-a9bb-da9fc6938811/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-07 00:18:27,197 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-07 00:18:27,198 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-07 00:18:27,198 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-07 00:18:27,198 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-07 00:18:27,271 INFO L236 CfgBuilder]: Building ICFG [2021-12-07 00:18:27,273 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-07 00:18:27,808 INFO L277 CfgBuilder]: Performing block encoding [2021-12-07 00:18:27,817 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-07 00:18:27,817 INFO L301 CfgBuilder]: Removed 7 assume(true) statements. [2021-12-07 00:18:27,819 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 12:18:27 BoogieIcfgContainer [2021-12-07 00:18:27,819 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-07 00:18:27,820 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-07 00:18:27,820 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-07 00:18:27,822 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-07 00:18:27,823 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-07 00:18:27,823 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 07.12 12:18:26" (1/3) ... [2021-12-07 00:18:27,824 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@37e4a78f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.12 12:18:27, skipping insertion in model container [2021-12-07 00:18:27,824 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-07 00:18:27,824 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:18:27" (2/3) ... [2021-12-07 00:18:27,824 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@37e4a78f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.12 12:18:27, skipping insertion in model container [2021-12-07 00:18:27,824 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-07 00:18:27,824 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 12:18:27" (3/3) ... [2021-12-07 00:18:27,825 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.04.cil-1.c [2021-12-07 00:18:27,855 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-07 00:18:27,855 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-07 00:18:27,855 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-07 00:18:27,856 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-07 00:18:27,856 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-07 00:18:27,856 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-07 00:18:27,856 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-07 00:18:27,856 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-07 00:18:27,877 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 431 states, 430 states have (on average 1.5325581395348837) internal successors, (659), 430 states have internal predecessors, (659), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:27,908 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 360 [2021-12-07 00:18:27,908 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:18:27,908 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:18:27,916 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:27,917 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:27,917 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-07 00:18:27,918 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 431 states, 430 states have (on average 1.5325581395348837) internal successors, (659), 430 states have internal predecessors, (659), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:27,942 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 360 [2021-12-07 00:18:27,942 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:18:27,943 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:18:27,945 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:27,945 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:27,951 INFO L791 eck$LassoCheckResult]: Stem: 425#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 363#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 219#L766true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45#L346true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 76#L353true assume !(1 == ~m_i~0);~m_st~0 := 2; 298#L353-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 368#L358-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 48#L363-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 411#L368-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 123#L373-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 65#L514true assume !(0 == ~M_E~0); 382#L514-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 327#L519-1true assume !(0 == ~T2_E~0); 40#L524-1true assume !(0 == ~T3_E~0); 106#L529-1true assume !(0 == ~T4_E~0); 330#L534-1true assume !(0 == ~E_M~0); 267#L539-1true assume !(0 == ~E_1~0); 296#L544-1true assume !(0 == ~E_2~0); 297#L549-1true assume !(0 == ~E_3~0); 335#L554-1true assume 0 == ~E_4~0;~E_4~0 := 1; 38#L559-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 176#L250true assume 1 == ~m_pc~0; 396#L251true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 328#L261true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 149#L262true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 300#L637true assume !(0 != activate_threads_~tmp~1#1); 41#L637-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56#L269true assume !(1 == ~t1_pc~0); 103#L269-2true is_transmit1_triggered_~__retres1~1#1 := 0; 181#L280true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 120#L281true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 329#L645true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 147#L645-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 238#L288true assume 1 == ~t2_pc~0; 359#L289true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 251#L299true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 157#L300true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 260#L653true assume !(0 != activate_threads_~tmp___1~0#1); 313#L653-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 164#L307true assume !(1 == ~t3_pc~0); 226#L307-2true is_transmit3_triggered_~__retres1~3#1 := 0; 210#L318true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 432#L319true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 308#L661true assume !(0 != activate_threads_~tmp___2~0#1); 130#L661-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 352#L326true assume 1 == ~t4_pc~0; 345#L327true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 162#L337true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 266#L338true activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 309#L669true assume !(0 != activate_threads_~tmp___3~0#1); 264#L669-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 304#L572true assume !(1 == ~M_E~0); 346#L572-2true assume !(1 == ~T1_E~0); 46#L577-1true assume !(1 == ~T2_E~0); 247#L582-1true assume !(1 == ~T3_E~0); 254#L587-1true assume !(1 == ~T4_E~0); 372#L592-1true assume !(1 == ~E_M~0); 14#L597-1true assume 1 == ~E_1~0;~E_1~0 := 2; 412#L602-1true assume !(1 == ~E_2~0); 141#L607-1true assume !(1 == ~E_3~0); 416#L612-1true assume !(1 == ~E_4~0); 105#L617-1true assume { :end_inline_reset_delta_events } true; 430#L803-2true [2021-12-07 00:18:27,956 INFO L793 eck$LassoCheckResult]: Loop: 430#L803-2true assume !false; 220#L804true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 201#L489true assume !true; 389#L504true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 232#L346-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 198#L514-3true assume 0 == ~M_E~0;~M_E~0 := 1; 153#L514-5true assume !(0 == ~T1_E~0); 318#L519-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 244#L524-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 86#L529-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 173#L534-3true assume 0 == ~E_M~0;~E_M~0 := 1; 9#L539-3true assume 0 == ~E_1~0;~E_1~0 := 1; 333#L544-3true assume 0 == ~E_2~0;~E_2~0 := 1; 400#L549-3true assume 0 == ~E_3~0;~E_3~0 := 1; 119#L554-3true assume !(0 == ~E_4~0); 194#L559-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 274#L250-18true assume 1 == ~m_pc~0; 231#L251-6true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 208#L261-6true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54#L262-6true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 272#L637-18true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 91#L637-20true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32#L269-18true assume !(1 == ~t1_pc~0); 353#L269-20true is_transmit1_triggered_~__retres1~1#1 := 0; 72#L280-6true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 102#L281-6true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 185#L645-18true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 290#L645-20true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 112#L288-18true assume !(1 == ~t2_pc~0); 397#L288-20true is_transmit2_triggered_~__retres1~2#1 := 0; 13#L299-6true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62#L300-6true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 171#L653-18true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 95#L653-20true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 316#L307-18true assume !(1 == ~t3_pc~0); 81#L307-20true is_transmit3_triggered_~__retres1~3#1 := 0; 122#L318-6true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 125#L319-6true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 85#L661-18true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 348#L661-20true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 275#L326-18true assume !(1 == ~t4_pc~0); 361#L326-20true is_transmit4_triggered_~__retres1~4#1 := 0; 286#L337-6true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 246#L338-6true activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7#L669-18true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 369#L669-20true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 420#L572-3true assume 1 == ~M_E~0;~M_E~0 := 2; 94#L572-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 111#L577-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 37#L582-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 371#L587-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 193#L592-3true assume 1 == ~E_M~0;~E_M~0 := 2; 252#L597-3true assume !(1 == ~E_1~0); 134#L602-3true assume 1 == ~E_2~0;~E_2~0 := 2; 324#L607-3true assume 1 == ~E_3~0;~E_3~0 := 2; 100#L612-3true assume 1 == ~E_4~0;~E_4~0 := 2; 196#L617-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 138#L386-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 128#L413-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 373#L414-1true start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 163#L822true assume !(0 == start_simulation_~tmp~3#1); 271#L822-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 395#L386-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 405#L413-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 165#L414-2true stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 24#L777true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 203#L784true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 213#L785true start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 317#L835true assume !(0 != start_simulation_~tmp___0~1#1); 430#L803-2true [2021-12-07 00:18:27,962 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:27,962 INFO L85 PathProgramCache]: Analyzing trace with hash 1553035642, now seen corresponding path program 1 times [2021-12-07 00:18:27,968 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:27,969 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [125440218] [2021-12-07 00:18:27,969 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:27,970 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:28,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:18:28,105 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:18:28,106 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:18:28,106 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [125440218] [2021-12-07 00:18:28,106 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [125440218] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:18:28,107 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:18:28,107 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:18:28,108 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1693376891] [2021-12-07 00:18:28,109 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:18:28,112 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:18:28,112 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:28,112 INFO L85 PathProgramCache]: Analyzing trace with hash -1756395876, now seen corresponding path program 1 times [2021-12-07 00:18:28,113 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:28,113 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [242291904] [2021-12-07 00:18:28,113 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:28,113 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:28,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:18:28,137 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:18:28,137 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:18:28,137 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [242291904] [2021-12-07 00:18:28,138 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [242291904] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:18:28,138 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:18:28,138 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-07 00:18:28,138 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1944628123] [2021-12-07 00:18:28,138 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:18:28,139 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:18:28,140 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:18:28,162 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:18:28,163 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:18:28,165 INFO L87 Difference]: Start difference. First operand has 431 states, 430 states have (on average 1.5325581395348837) internal successors, (659), 430 states have internal predecessors, (659), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:28,207 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:18:28,207 INFO L93 Difference]: Finished difference Result 430 states and 642 transitions. [2021-12-07 00:18:28,208 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:18:28,212 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 642 transitions. [2021-12-07 00:18:28,217 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2021-12-07 00:18:28,224 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 425 states and 637 transitions. [2021-12-07 00:18:28,225 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 425 [2021-12-07 00:18:28,226 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 425 [2021-12-07 00:18:28,227 INFO L73 IsDeterministic]: Start isDeterministic. Operand 425 states and 637 transitions. [2021-12-07 00:18:28,230 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:18:28,230 INFO L681 BuchiCegarLoop]: Abstraction has 425 states and 637 transitions. [2021-12-07 00:18:28,242 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 425 states and 637 transitions. [2021-12-07 00:18:28,267 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 425 to 425. [2021-12-07 00:18:28,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 425 states, 425 states have (on average 1.4988235294117647) internal successors, (637), 424 states have internal predecessors, (637), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:28,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 425 states to 425 states and 637 transitions. [2021-12-07 00:18:28,271 INFO L704 BuchiCegarLoop]: Abstraction has 425 states and 637 transitions. [2021-12-07 00:18:28,271 INFO L587 BuchiCegarLoop]: Abstraction has 425 states and 637 transitions. [2021-12-07 00:18:28,271 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-07 00:18:28,271 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 425 states and 637 transitions. [2021-12-07 00:18:28,275 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2021-12-07 00:18:28,275 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:18:28,275 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:18:28,277 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:28,277 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:28,278 INFO L791 eck$LassoCheckResult]: Stem: 1294#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 1287#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1205#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 958#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 959#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 1014#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1260#L358-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 964#L363-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 965#L368-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1087#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 996#L514 assume !(0 == ~M_E~0); 997#L514-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1276#L519-1 assume !(0 == ~T2_E~0); 950#L524-1 assume !(0 == ~T3_E~0); 951#L529-1 assume !(0 == ~T4_E~0); 1066#L534-1 assume !(0 == ~E_M~0); 1242#L539-1 assume !(0 == ~E_1~0); 1243#L544-1 assume !(0 == ~E_2~0); 1258#L549-1 assume !(0 == ~E_3~0); 1259#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 945#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 946#L250 assume 1 == ~m_pc~0; 1155#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1264#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1120#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1121#L637 assume !(0 != activate_threads_~tmp~1#1); 952#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 953#L269 assume !(1 == ~t1_pc~0); 890#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 889#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1084#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1085#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1117#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1118#L288 assume 1 == ~t2_pc~0; 1220#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1114#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1130#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1131#L653 assume !(0 != activate_threads_~tmp___1~0#1); 1237#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1144#L307 assume !(1 == ~t3_pc~0); 1078#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1079#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1195#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1269#L661 assume !(0 != activate_threads_~tmp___2~0#1); 1093#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1094#L326 assume 1 == ~t4_pc~0; 1283#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 904#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1140#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1241#L669 assume !(0 != activate_threads_~tmp___3~0#1); 1238#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1239#L572 assume !(1 == ~M_E~0); 1265#L572-2 assume !(1 == ~T1_E~0); 960#L577-1 assume !(1 == ~T2_E~0); 961#L582-1 assume !(1 == ~T3_E~0); 1226#L587-1 assume !(1 == ~T4_E~0); 1233#L592-1 assume !(1 == ~E_M~0); 895#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 896#L602-1 assume !(1 == ~E_2~0); 1110#L607-1 assume !(1 == ~E_3~0); 1111#L612-1 assume !(1 == ~E_4~0); 1064#L617-1 assume { :end_inline_reset_delta_events } true; 1065#L803-2 [2021-12-07 00:18:28,278 INFO L793 eck$LassoCheckResult]: Loop: 1065#L803-2 assume !false; 1206#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 988#L489 assume !false; 1183#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1146#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1004#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1060#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1293#L428 assume !(0 != eval_~tmp~0#1); 1291#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1216#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1182#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1124#L514-5 assume !(0 == ~T1_E~0); 1125#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1224#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1034#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1035#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 884#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 885#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1278#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1082#L554-3 assume !(0 == ~E_4~0); 1083#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1180#L250-18 assume 1 == ~m_pc~0; 1214#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1192#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 975#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 976#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1044#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 932#L269-18 assume !(1 == ~t1_pc~0); 933#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 1006#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1007#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1061#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1168#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1070#L288-18 assume 1 == ~t2_pc~0; 1056#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 893#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 894#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 991#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1051#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1052#L307-18 assume 1 == ~t3_pc~0; 1112#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1024#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1086#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1032#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1033#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1247#L326-18 assume 1 == ~t4_pc~0; 1248#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1254#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1225#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 880#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 881#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1288#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1049#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1050#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 943#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 944#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1178#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1179#L597-3 assume !(1 == ~E_1~0); 1099#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1100#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1058#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1059#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1105#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1074#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1091#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1141#L822 assume !(0 == start_simulation_~tmp~3#1); 1143#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1245#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1187#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1145#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 916#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 917#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1185#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1201#L835 assume !(0 != start_simulation_~tmp___0~1#1); 1065#L803-2 [2021-12-07 00:18:28,278 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:28,278 INFO L85 PathProgramCache]: Analyzing trace with hash 1119306556, now seen corresponding path program 1 times [2021-12-07 00:18:28,279 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:28,279 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1580137509] [2021-12-07 00:18:28,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:28,279 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:28,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:18:28,318 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:18:28,319 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:18:28,319 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1580137509] [2021-12-07 00:18:28,319 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1580137509] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:18:28,320 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:18:28,320 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:18:28,320 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1581133839] [2021-12-07 00:18:28,320 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:18:28,321 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:18:28,321 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:28,322 INFO L85 PathProgramCache]: Analyzing trace with hash -387617298, now seen corresponding path program 1 times [2021-12-07 00:18:28,322 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:28,322 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1126957368] [2021-12-07 00:18:28,322 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:28,322 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:28,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:18:28,379 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:18:28,379 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:18:28,379 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1126957368] [2021-12-07 00:18:28,379 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1126957368] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:18:28,379 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:18:28,379 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:18:28,379 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [305593234] [2021-12-07 00:18:28,380 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:18:28,380 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:18:28,380 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:18:28,380 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:18:28,380 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:18:28,381 INFO L87 Difference]: Start difference. First operand 425 states and 637 transitions. cyclomatic complexity: 213 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:28,408 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:18:28,408 INFO L93 Difference]: Finished difference Result 425 states and 636 transitions. [2021-12-07 00:18:28,409 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:18:28,409 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 425 states and 636 transitions. [2021-12-07 00:18:28,414 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2021-12-07 00:18:28,420 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 425 states to 425 states and 636 transitions. [2021-12-07 00:18:28,420 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 425 [2021-12-07 00:18:28,421 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 425 [2021-12-07 00:18:28,421 INFO L73 IsDeterministic]: Start isDeterministic. Operand 425 states and 636 transitions. [2021-12-07 00:18:28,424 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:18:28,424 INFO L681 BuchiCegarLoop]: Abstraction has 425 states and 636 transitions. [2021-12-07 00:18:28,425 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 425 states and 636 transitions. [2021-12-07 00:18:28,443 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 425 to 425. [2021-12-07 00:18:28,445 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 425 states, 425 states have (on average 1.4964705882352942) internal successors, (636), 424 states have internal predecessors, (636), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:28,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 425 states to 425 states and 636 transitions. [2021-12-07 00:18:28,448 INFO L704 BuchiCegarLoop]: Abstraction has 425 states and 636 transitions. [2021-12-07 00:18:28,448 INFO L587 BuchiCegarLoop]: Abstraction has 425 states and 636 transitions. [2021-12-07 00:18:28,448 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-07 00:18:28,448 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 425 states and 636 transitions. [2021-12-07 00:18:28,451 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2021-12-07 00:18:28,451 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:18:28,451 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:18:28,454 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:28,454 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:28,455 INFO L791 eck$LassoCheckResult]: Stem: 2151#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2144#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2062#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1815#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1816#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 1871#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2117#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1821#L363-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1822#L368-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1944#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1853#L514 assume !(0 == ~M_E~0); 1854#L514-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2133#L519-1 assume !(0 == ~T2_E~0); 1807#L524-1 assume !(0 == ~T3_E~0); 1808#L529-1 assume !(0 == ~T4_E~0); 1923#L534-1 assume !(0 == ~E_M~0); 2099#L539-1 assume !(0 == ~E_1~0); 2100#L544-1 assume !(0 == ~E_2~0); 2115#L549-1 assume !(0 == ~E_3~0); 2116#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 1802#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1803#L250 assume 1 == ~m_pc~0; 2012#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2121#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1977#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1978#L637 assume !(0 != activate_threads_~tmp~1#1); 1809#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1810#L269 assume !(1 == ~t1_pc~0); 1747#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1746#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1941#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1942#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1974#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1975#L288 assume 1 == ~t2_pc~0; 2077#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1971#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1987#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1988#L653 assume !(0 != activate_threads_~tmp___1~0#1); 2094#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2001#L307 assume !(1 == ~t3_pc~0); 1935#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1936#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2052#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2126#L661 assume !(0 != activate_threads_~tmp___2~0#1); 1950#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1951#L326 assume 1 == ~t4_pc~0; 2140#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1761#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1997#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2098#L669 assume !(0 != activate_threads_~tmp___3~0#1); 2095#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2096#L572 assume !(1 == ~M_E~0); 2122#L572-2 assume !(1 == ~T1_E~0); 1817#L577-1 assume !(1 == ~T2_E~0); 1818#L582-1 assume !(1 == ~T3_E~0); 2083#L587-1 assume !(1 == ~T4_E~0); 2090#L592-1 assume !(1 == ~E_M~0); 1752#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1753#L602-1 assume !(1 == ~E_2~0); 1967#L607-1 assume !(1 == ~E_3~0); 1968#L612-1 assume !(1 == ~E_4~0); 1921#L617-1 assume { :end_inline_reset_delta_events } true; 1922#L803-2 [2021-12-07 00:18:28,455 INFO L793 eck$LassoCheckResult]: Loop: 1922#L803-2 assume !false; 2063#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1845#L489 assume !false; 2040#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2003#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1861#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1917#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2150#L428 assume !(0 != eval_~tmp~0#1); 2148#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2073#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2039#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1981#L514-5 assume !(0 == ~T1_E~0); 1982#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2081#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1891#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1892#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1741#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1742#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2135#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1939#L554-3 assume !(0 == ~E_4~0); 1940#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2037#L250-18 assume 1 == ~m_pc~0; 2071#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2049#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1832#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1833#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1901#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1789#L269-18 assume !(1 == ~t1_pc~0); 1790#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 1863#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1864#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1918#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2025#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1927#L288-18 assume 1 == ~t2_pc~0; 1913#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1750#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1751#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1848#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1908#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1909#L307-18 assume 1 == ~t3_pc~0; 1969#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1881#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1943#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1889#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1890#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2104#L326-18 assume 1 == ~t4_pc~0; 2105#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2111#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2082#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1737#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1738#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2145#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1906#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1907#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1800#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1801#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2035#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2036#L597-3 assume !(1 == ~E_1~0); 1956#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1957#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1915#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1916#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1962#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1931#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1948#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1998#L822 assume !(0 == start_simulation_~tmp~3#1); 2000#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2102#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2044#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2002#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 1773#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1774#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2042#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 2058#L835 assume !(0 != start_simulation_~tmp___0~1#1); 1922#L803-2 [2021-12-07 00:18:28,455 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:28,456 INFO L85 PathProgramCache]: Analyzing trace with hash 1078631806, now seen corresponding path program 1 times [2021-12-07 00:18:28,456 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:28,456 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1451942662] [2021-12-07 00:18:28,456 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:28,456 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:28,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:18:28,487 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:18:28,487 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:18:28,487 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1451942662] [2021-12-07 00:18:28,487 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1451942662] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:18:28,487 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:18:28,487 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:18:28,488 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1718320966] [2021-12-07 00:18:28,488 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:18:28,488 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:18:28,489 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:28,489 INFO L85 PathProgramCache]: Analyzing trace with hash -387617298, now seen corresponding path program 2 times [2021-12-07 00:18:28,489 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:28,489 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1257160200] [2021-12-07 00:18:28,489 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:28,489 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:28,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:18:28,539 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:18:28,539 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:18:28,539 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1257160200] [2021-12-07 00:18:28,540 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1257160200] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:18:28,540 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:18:28,540 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:18:28,540 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1691535330] [2021-12-07 00:18:28,540 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:18:28,541 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:18:28,541 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:18:28,541 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:18:28,541 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:18:28,542 INFO L87 Difference]: Start difference. First operand 425 states and 636 transitions. cyclomatic complexity: 212 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:28,555 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:18:28,555 INFO L93 Difference]: Finished difference Result 425 states and 635 transitions. [2021-12-07 00:18:28,555 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:18:28,556 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 425 states and 635 transitions. [2021-12-07 00:18:28,560 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2021-12-07 00:18:28,564 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 425 states to 425 states and 635 transitions. [2021-12-07 00:18:28,564 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 425 [2021-12-07 00:18:28,565 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 425 [2021-12-07 00:18:28,565 INFO L73 IsDeterministic]: Start isDeterministic. Operand 425 states and 635 transitions. [2021-12-07 00:18:28,566 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:18:28,566 INFO L681 BuchiCegarLoop]: Abstraction has 425 states and 635 transitions. [2021-12-07 00:18:28,567 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 425 states and 635 transitions. [2021-12-07 00:18:28,583 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 425 to 425. [2021-12-07 00:18:28,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 425 states, 425 states have (on average 1.4941176470588236) internal successors, (635), 424 states have internal predecessors, (635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:28,585 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 425 states to 425 states and 635 transitions. [2021-12-07 00:18:28,585 INFO L704 BuchiCegarLoop]: Abstraction has 425 states and 635 transitions. [2021-12-07 00:18:28,585 INFO L587 BuchiCegarLoop]: Abstraction has 425 states and 635 transitions. [2021-12-07 00:18:28,585 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-07 00:18:28,586 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 425 states and 635 transitions. [2021-12-07 00:18:28,587 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2021-12-07 00:18:28,588 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:18:28,588 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:18:28,589 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:28,589 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:28,589 INFO L791 eck$LassoCheckResult]: Stem: 3008#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 3001#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2919#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2672#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2673#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 2728#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2974#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2678#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2679#L368-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2801#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2710#L514 assume !(0 == ~M_E~0); 2711#L514-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2990#L519-1 assume !(0 == ~T2_E~0); 2664#L524-1 assume !(0 == ~T3_E~0); 2665#L529-1 assume !(0 == ~T4_E~0); 2780#L534-1 assume !(0 == ~E_M~0); 2956#L539-1 assume !(0 == ~E_1~0); 2957#L544-1 assume !(0 == ~E_2~0); 2972#L549-1 assume !(0 == ~E_3~0); 2973#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2659#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2660#L250 assume 1 == ~m_pc~0; 2869#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2978#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2834#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2835#L637 assume !(0 != activate_threads_~tmp~1#1); 2666#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2667#L269 assume !(1 == ~t1_pc~0); 2604#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2603#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2798#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2799#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2831#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2832#L288 assume 1 == ~t2_pc~0; 2934#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2828#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2844#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2845#L653 assume !(0 != activate_threads_~tmp___1~0#1); 2951#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2858#L307 assume !(1 == ~t3_pc~0); 2792#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2793#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2909#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2983#L661 assume !(0 != activate_threads_~tmp___2~0#1); 2807#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2808#L326 assume 1 == ~t4_pc~0; 2997#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2618#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2854#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2955#L669 assume !(0 != activate_threads_~tmp___3~0#1); 2952#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2953#L572 assume !(1 == ~M_E~0); 2979#L572-2 assume !(1 == ~T1_E~0); 2674#L577-1 assume !(1 == ~T2_E~0); 2675#L582-1 assume !(1 == ~T3_E~0); 2940#L587-1 assume !(1 == ~T4_E~0); 2947#L592-1 assume !(1 == ~E_M~0); 2609#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2610#L602-1 assume !(1 == ~E_2~0); 2824#L607-1 assume !(1 == ~E_3~0); 2825#L612-1 assume !(1 == ~E_4~0); 2778#L617-1 assume { :end_inline_reset_delta_events } true; 2779#L803-2 [2021-12-07 00:18:28,589 INFO L793 eck$LassoCheckResult]: Loop: 2779#L803-2 assume !false; 2920#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2702#L489 assume !false; 2897#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2860#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2718#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2774#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3007#L428 assume !(0 != eval_~tmp~0#1); 3005#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2930#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2896#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2838#L514-5 assume !(0 == ~T1_E~0); 2839#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2938#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2748#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2749#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2598#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2599#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2992#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2796#L554-3 assume !(0 == ~E_4~0); 2797#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2894#L250-18 assume 1 == ~m_pc~0; 2928#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2906#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2689#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2690#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2758#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2646#L269-18 assume !(1 == ~t1_pc~0); 2647#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 2720#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2721#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2775#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2882#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2784#L288-18 assume 1 == ~t2_pc~0; 2770#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2607#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2608#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2705#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2765#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2766#L307-18 assume !(1 == ~t3_pc~0); 2737#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 2738#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2800#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2746#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2747#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2961#L326-18 assume 1 == ~t4_pc~0; 2962#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2968#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2939#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2594#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2595#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3002#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2763#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2764#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2657#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2658#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2892#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2893#L597-3 assume !(1 == ~E_1~0); 2813#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2814#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2772#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2773#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2819#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2788#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2805#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 2855#L822 assume !(0 == start_simulation_~tmp~3#1); 2857#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2959#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2901#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2859#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 2630#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2631#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2899#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 2915#L835 assume !(0 != start_simulation_~tmp___0~1#1); 2779#L803-2 [2021-12-07 00:18:28,590 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:28,590 INFO L85 PathProgramCache]: Analyzing trace with hash -308153604, now seen corresponding path program 1 times [2021-12-07 00:18:28,590 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:28,590 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [767477629] [2021-12-07 00:18:28,590 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:28,591 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:28,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:18:28,612 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:18:28,613 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:18:28,613 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [767477629] [2021-12-07 00:18:28,613 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [767477629] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:18:28,613 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:18:28,613 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:18:28,613 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1290076647] [2021-12-07 00:18:28,614 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:18:28,614 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:18:28,614 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:28,614 INFO L85 PathProgramCache]: Analyzing trace with hash 663831791, now seen corresponding path program 1 times [2021-12-07 00:18:28,614 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:28,615 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [403104662] [2021-12-07 00:18:28,615 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:28,615 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:28,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:18:28,649 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:18:28,649 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:18:28,649 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [403104662] [2021-12-07 00:18:28,650 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [403104662] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:18:28,650 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:18:28,650 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:18:28,650 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1713038301] [2021-12-07 00:18:28,650 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:18:28,651 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:18:28,651 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:18:28,651 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:18:28,651 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:18:28,652 INFO L87 Difference]: Start difference. First operand 425 states and 635 transitions. cyclomatic complexity: 211 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:28,662 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:18:28,662 INFO L93 Difference]: Finished difference Result 425 states and 634 transitions. [2021-12-07 00:18:28,663 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:18:28,663 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 425 states and 634 transitions. [2021-12-07 00:18:28,666 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2021-12-07 00:18:28,669 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 425 states to 425 states and 634 transitions. [2021-12-07 00:18:28,669 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 425 [2021-12-07 00:18:28,669 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 425 [2021-12-07 00:18:28,669 INFO L73 IsDeterministic]: Start isDeterministic. Operand 425 states and 634 transitions. [2021-12-07 00:18:28,670 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:18:28,670 INFO L681 BuchiCegarLoop]: Abstraction has 425 states and 634 transitions. [2021-12-07 00:18:28,671 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 425 states and 634 transitions. [2021-12-07 00:18:28,675 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 425 to 425. [2021-12-07 00:18:28,676 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 425 states, 425 states have (on average 1.4917647058823529) internal successors, (634), 424 states have internal predecessors, (634), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:28,678 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 425 states to 425 states and 634 transitions. [2021-12-07 00:18:28,678 INFO L704 BuchiCegarLoop]: Abstraction has 425 states and 634 transitions. [2021-12-07 00:18:28,678 INFO L587 BuchiCegarLoop]: Abstraction has 425 states and 634 transitions. [2021-12-07 00:18:28,678 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-07 00:18:28,678 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 425 states and 634 transitions. [2021-12-07 00:18:28,680 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2021-12-07 00:18:28,680 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:18:28,680 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:18:28,681 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:28,681 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:28,682 INFO L791 eck$LassoCheckResult]: Stem: 3865#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 3858#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3776#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3529#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3530#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 3585#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3832#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3535#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3536#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3659#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3567#L514 assume !(0 == ~M_E~0); 3568#L514-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3847#L519-1 assume !(0 == ~T2_E~0); 3521#L524-1 assume !(0 == ~T3_E~0); 3522#L529-1 assume !(0 == ~T4_E~0); 3637#L534-1 assume !(0 == ~E_M~0); 3813#L539-1 assume !(0 == ~E_1~0); 3814#L544-1 assume !(0 == ~E_2~0); 3829#L549-1 assume !(0 == ~E_3~0); 3830#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 3516#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3517#L250 assume 1 == ~m_pc~0; 3729#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3836#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3691#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3692#L637 assume !(0 != activate_threads_~tmp~1#1); 3523#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3524#L269 assume !(1 == ~t1_pc~0); 3461#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3460#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3655#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3656#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3688#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3689#L288 assume 1 == ~t2_pc~0; 3792#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3685#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3701#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3702#L653 assume !(0 != activate_threads_~tmp___1~0#1); 3808#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3716#L307 assume !(1 == ~t3_pc~0); 3649#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3650#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3771#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3840#L661 assume !(0 != activate_threads_~tmp___2~0#1); 3664#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3665#L326 assume 1 == ~t4_pc~0; 3854#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3475#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3714#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3812#L669 assume !(0 != activate_threads_~tmp___3~0#1); 3809#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3810#L572 assume !(1 == ~M_E~0); 3835#L572-2 assume !(1 == ~T1_E~0); 3531#L577-1 assume !(1 == ~T2_E~0); 3532#L582-1 assume !(1 == ~T3_E~0); 3797#L587-1 assume !(1 == ~T4_E~0); 3804#L592-1 assume !(1 == ~E_M~0); 3466#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3467#L602-1 assume !(1 == ~E_2~0); 3681#L607-1 assume !(1 == ~E_3~0); 3682#L612-1 assume !(1 == ~E_4~0); 3635#L617-1 assume { :end_inline_reset_delta_events } true; 3636#L803-2 [2021-12-07 00:18:28,682 INFO L793 eck$LassoCheckResult]: Loop: 3636#L803-2 assume !false; 3777#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3559#L489 assume !false; 3754#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3717#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3575#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3631#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3864#L428 assume !(0 != eval_~tmp~0#1); 3862#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3787#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3753#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3695#L514-5 assume !(0 == ~T1_E~0); 3696#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3795#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3605#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3606#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3455#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3456#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3849#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3653#L554-3 assume !(0 == ~E_4~0); 3654#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3751#L250-18 assume 1 == ~m_pc~0; 3785#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3763#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3546#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3547#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3615#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3503#L269-18 assume !(1 == ~t1_pc~0); 3504#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 3577#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3578#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3632#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3739#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3641#L288-18 assume 1 == ~t2_pc~0; 3627#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3464#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3465#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3562#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3622#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3623#L307-18 assume 1 == ~t3_pc~0; 3683#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3595#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3657#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3603#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3604#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3818#L326-18 assume 1 == ~t4_pc~0; 3819#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3825#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3796#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3451#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3452#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3859#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3620#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3621#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3514#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3515#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3749#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3750#L597-3 assume !(1 == ~E_1~0); 3670#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3671#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3629#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3630#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3676#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3645#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3662#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 3711#L822 assume !(0 == start_simulation_~tmp~3#1); 3713#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3816#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3758#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3715#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 3487#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3488#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3756#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 3772#L835 assume !(0 != start_simulation_~tmp___0~1#1); 3636#L803-2 [2021-12-07 00:18:28,682 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:28,682 INFO L85 PathProgramCache]: Analyzing trace with hash -1184172610, now seen corresponding path program 1 times [2021-12-07 00:18:28,682 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:28,683 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [87766085] [2021-12-07 00:18:28,683 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:28,683 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:28,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:18:28,717 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:18:28,717 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:18:28,717 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [87766085] [2021-12-07 00:18:28,717 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [87766085] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:18:28,718 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:18:28,718 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:18:28,718 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1932647615] [2021-12-07 00:18:28,718 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:18:28,718 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:18:28,718 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:28,719 INFO L85 PathProgramCache]: Analyzing trace with hash -387617298, now seen corresponding path program 3 times [2021-12-07 00:18:28,719 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:28,719 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1367693636] [2021-12-07 00:18:28,719 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:28,719 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:28,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:18:28,743 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:18:28,743 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:18:28,744 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1367693636] [2021-12-07 00:18:28,744 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1367693636] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:18:28,744 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:18:28,744 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:18:28,744 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [472724304] [2021-12-07 00:18:28,744 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:18:28,744 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:18:28,745 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:18:28,745 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-07 00:18:28,745 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-07 00:18:28,745 INFO L87 Difference]: Start difference. First operand 425 states and 634 transitions. cyclomatic complexity: 210 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:28,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:18:28,800 INFO L93 Difference]: Finished difference Result 746 states and 1107 transitions. [2021-12-07 00:18:28,800 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-07 00:18:28,800 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 746 states and 1107 transitions. [2021-12-07 00:18:28,805 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 669 [2021-12-07 00:18:28,809 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 746 states to 746 states and 1107 transitions. [2021-12-07 00:18:28,810 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 746 [2021-12-07 00:18:28,810 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 746 [2021-12-07 00:18:28,810 INFO L73 IsDeterministic]: Start isDeterministic. Operand 746 states and 1107 transitions. [2021-12-07 00:18:28,811 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:18:28,811 INFO L681 BuchiCegarLoop]: Abstraction has 746 states and 1107 transitions. [2021-12-07 00:18:28,812 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 746 states and 1107 transitions. [2021-12-07 00:18:28,821 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 746 to 746. [2021-12-07 00:18:28,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 746 states, 746 states have (on average 1.4839142091152815) internal successors, (1107), 745 states have internal predecessors, (1107), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:28,824 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 746 states to 746 states and 1107 transitions. [2021-12-07 00:18:28,824 INFO L704 BuchiCegarLoop]: Abstraction has 746 states and 1107 transitions. [2021-12-07 00:18:28,824 INFO L587 BuchiCegarLoop]: Abstraction has 746 states and 1107 transitions. [2021-12-07 00:18:28,824 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-07 00:18:28,824 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 746 states and 1107 transitions. [2021-12-07 00:18:28,827 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 669 [2021-12-07 00:18:28,827 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:18:28,827 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:18:28,828 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:28,828 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:28,828 INFO L791 eck$LassoCheckResult]: Stem: 5056#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 5049#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4960#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4710#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4711#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 4766#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5017#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4716#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4717#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4840#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4748#L514 assume !(0 == ~M_E~0); 4749#L514-2 assume !(0 == ~T1_E~0); 5037#L519-1 assume !(0 == ~T2_E~0); 4702#L524-1 assume !(0 == ~T3_E~0); 4703#L529-1 assume !(0 == ~T4_E~0); 4818#L534-1 assume !(0 == ~E_M~0); 4997#L539-1 assume !(0 == ~E_1~0); 4998#L544-1 assume !(0 == ~E_2~0); 5014#L549-1 assume !(0 == ~E_3~0); 5015#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4697#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4698#L250 assume 1 == ~m_pc~0; 4912#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5020#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4873#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4874#L637 assume !(0 != activate_threads_~tmp~1#1); 4704#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4705#L269 assume !(1 == ~t1_pc~0); 4642#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4641#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4836#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4837#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4870#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4871#L288 assume 1 == ~t2_pc~0; 4975#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4866#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4883#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4884#L653 assume !(0 != activate_threads_~tmp___1~0#1); 4992#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4898#L307 assume !(1 == ~t3_pc~0); 4830#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4831#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4952#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5026#L661 assume !(0 != activate_threads_~tmp___2~0#1); 4845#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4846#L326 assume 1 == ~t4_pc~0; 5044#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4656#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4896#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4996#L669 assume !(0 != activate_threads_~tmp___3~0#1); 4993#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4994#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 5021#L572-2 assume !(1 == ~T1_E~0); 5045#L577-1 assume !(1 == ~T2_E~0); 5302#L582-1 assume !(1 == ~T3_E~0); 5300#L587-1 assume !(1 == ~T4_E~0); 5298#L592-1 assume !(1 == ~E_M~0); 5296#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 5108#L602-1 assume !(1 == ~E_2~0); 5091#L607-1 assume !(1 == ~E_3~0); 5090#L612-1 assume !(1 == ~E_4~0); 5083#L617-1 assume { :end_inline_reset_delta_events } true; 5077#L803-2 [2021-12-07 00:18:28,828 INFO L793 eck$LassoCheckResult]: Loop: 5077#L803-2 assume !false; 5072#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5071#L489 assume !false; 5070#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5069#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5064#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5063#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5061#L428 assume !(0 != eval_~tmp~0#1); 5060#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5059#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5057#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5058#L514-5 assume !(0 == ~T1_E~0); 5282#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5281#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5280#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5279#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5278#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5277#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5276#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5275#L554-3 assume !(0 == ~E_4~0); 5274#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5273#L250-18 assume 1 == ~m_pc~0; 5271#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5270#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5269#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5268#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5267#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5266#L269-18 assume 1 == ~t1_pc~0; 5264#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5263#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5262#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5261#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5260#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5259#L288-18 assume 1 == ~t2_pc~0; 5257#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5256#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5255#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5253#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5250#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5030#L307-18 assume 1 == ~t3_pc~0; 4864#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4776#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4838#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4784#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4785#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5002#L326-18 assume 1 == ~t4_pc~0; 5003#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5009#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4979#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4632#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4633#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5050#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4801#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4802#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4695#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4696#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4933#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4934#L597-3 assume !(1 == ~E_1~0); 4851#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4852#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4810#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4811#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4857#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4826#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4843#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 4893#L822 assume !(0 == start_simulation_~tmp~3#1); 4895#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4999#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4942#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4897#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 4668#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4669#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4940#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 4956#L835 assume !(0 != start_simulation_~tmp___0~1#1); 5077#L803-2 [2021-12-07 00:18:28,829 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:28,829 INFO L85 PathProgramCache]: Analyzing trace with hash 381143998, now seen corresponding path program 1 times [2021-12-07 00:18:28,829 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:28,829 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [409122222] [2021-12-07 00:18:28,829 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:28,829 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:28,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:18:28,850 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:18:28,850 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:18:28,850 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [409122222] [2021-12-07 00:18:28,850 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [409122222] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:18:28,850 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:18:28,850 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:18:28,850 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [653173468] [2021-12-07 00:18:28,850 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:18:28,851 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:18:28,851 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:28,851 INFO L85 PathProgramCache]: Analyzing trace with hash 1505824877, now seen corresponding path program 1 times [2021-12-07 00:18:28,851 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:28,851 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1790247049] [2021-12-07 00:18:28,851 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:28,852 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:28,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:18:28,872 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:18:28,872 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:18:28,872 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1790247049] [2021-12-07 00:18:28,872 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1790247049] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:18:28,872 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:18:28,872 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:18:28,872 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1558804837] [2021-12-07 00:18:28,873 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:18:28,873 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:18:28,873 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:18:28,873 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-07 00:18:28,873 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-07 00:18:28,873 INFO L87 Difference]: Start difference. First operand 746 states and 1107 transitions. cyclomatic complexity: 363 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:28,939 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:18:28,939 INFO L93 Difference]: Finished difference Result 1306 states and 1932 transitions. [2021-12-07 00:18:28,939 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-07 00:18:28,940 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1306 states and 1932 transitions. [2021-12-07 00:18:28,947 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1217 [2021-12-07 00:18:28,954 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1306 states to 1306 states and 1932 transitions. [2021-12-07 00:18:28,954 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1306 [2021-12-07 00:18:28,955 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1306 [2021-12-07 00:18:28,955 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1306 states and 1932 transitions. [2021-12-07 00:18:28,957 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:18:28,957 INFO L681 BuchiCegarLoop]: Abstraction has 1306 states and 1932 transitions. [2021-12-07 00:18:28,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1306 states and 1932 transitions. [2021-12-07 00:18:28,973 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1306 to 1304. [2021-12-07 00:18:28,975 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1304 states, 1304 states have (on average 1.4800613496932515) internal successors, (1930), 1303 states have internal predecessors, (1930), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:28,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1304 states to 1304 states and 1930 transitions. [2021-12-07 00:18:28,978 INFO L704 BuchiCegarLoop]: Abstraction has 1304 states and 1930 transitions. [2021-12-07 00:18:28,979 INFO L587 BuchiCegarLoop]: Abstraction has 1304 states and 1930 transitions. [2021-12-07 00:18:28,979 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-07 00:18:28,979 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1304 states and 1930 transitions. [2021-12-07 00:18:28,991 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1217 [2021-12-07 00:18:28,991 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:18:28,991 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:18:28,992 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:28,992 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:28,993 INFO L791 eck$LassoCheckResult]: Stem: 7159#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 7139#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 7030#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6772#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6773#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 6829#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7104#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6778#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6779#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6906#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6811#L514 assume !(0 == ~M_E~0); 6812#L514-2 assume !(0 == ~T1_E~0); 7123#L519-1 assume !(0 == ~T2_E~0); 6764#L524-1 assume !(0 == ~T3_E~0); 6765#L529-1 assume !(0 == ~T4_E~0); 6884#L534-1 assume !(0 == ~E_M~0); 7080#L539-1 assume !(0 == ~E_1~0); 7081#L544-1 assume !(0 == ~E_2~0); 7102#L549-1 assume !(0 == ~E_3~0); 7103#L554-1 assume !(0 == ~E_4~0); 6759#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6760#L250 assume 1 == ~m_pc~0; 6978#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7108#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6938#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6939#L637 assume !(0 != activate_threads_~tmp~1#1); 6766#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6767#L269 assume !(1 == ~t1_pc~0); 6704#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6703#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6902#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6903#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6935#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6936#L288 assume 1 == ~t2_pc~0; 7050#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6932#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6950#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6951#L653 assume !(0 != activate_threads_~tmp___1~0#1); 7074#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6965#L307 assume !(1 == ~t3_pc~0); 6896#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6897#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7020#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7114#L661 assume !(0 != activate_threads_~tmp___2~0#1); 6911#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6912#L326 assume 1 == ~t4_pc~0; 7132#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6718#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6963#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7079#L669 assume !(0 != activate_threads_~tmp___3~0#1); 7076#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7077#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 7109#L572-2 assume !(1 == ~T1_E~0); 6774#L577-1 assume !(1 == ~T2_E~0); 6775#L582-1 assume !(1 == ~T3_E~0); 7069#L587-1 assume !(1 == ~T4_E~0); 7070#L592-1 assume !(1 == ~E_M~0); 6709#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 6710#L602-1 assume !(1 == ~E_2~0); 6928#L607-1 assume !(1 == ~E_3~0); 6929#L612-1 assume !(1 == ~E_4~0); 7185#L617-1 assume { :end_inline_reset_delta_events } true; 7179#L803-2 [2021-12-07 00:18:28,993 INFO L793 eck$LassoCheckResult]: Loop: 7179#L803-2 assume !false; 7174#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7173#L489 assume !false; 7172#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7171#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7166#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7165#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7163#L428 assume !(0 != eval_~tmp~0#1); 7162#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7161#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7160#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6945#L514-5 assume !(0 == ~T1_E~0); 6946#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7058#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7059#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7951#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7948#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7125#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7126#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6900#L554-3 assume !(0 == ~E_4~0); 6901#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7001#L250-18 assume 1 == ~m_pc~0; 7042#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7015#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6789#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6790#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6859#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6746#L269-18 assume !(1 == ~t1_pc~0); 6747#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 6821#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6822#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7924#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7100#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6888#L288-18 assume 1 == ~t2_pc~0; 6869#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6707#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6708#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7394#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7380#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7377#L307-18 assume !(1 == ~t3_pc~0); 7355#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 7353#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7351#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7350#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7134#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7086#L326-18 assume !(1 == ~t4_pc~0); 7088#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 7095#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7096#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7293#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7291#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7288#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7156#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7282#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7277#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7275#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7269#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7265#L597-3 assume !(1 == ~E_1~0); 7260#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7255#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7248#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7246#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7243#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7237#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7235#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 7233#L822 assume !(0 == start_simulation_~tmp~3#1); 7075#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7226#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7224#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7221#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 7219#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7217#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7215#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 7186#L835 assume !(0 != start_simulation_~tmp___0~1#1); 7179#L803-2 [2021-12-07 00:18:28,993 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:28,993 INFO L85 PathProgramCache]: Analyzing trace with hash -516249280, now seen corresponding path program 1 times [2021-12-07 00:18:28,994 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:28,994 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1950470160] [2021-12-07 00:18:28,994 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:28,994 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:29,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:18:29,016 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:18:29,016 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:18:29,016 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1950470160] [2021-12-07 00:18:29,016 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1950470160] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:18:29,016 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:18:29,016 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-07 00:18:29,016 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1504428603] [2021-12-07 00:18:29,016 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:18:29,017 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:18:29,017 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:29,017 INFO L85 PathProgramCache]: Analyzing trace with hash -307842896, now seen corresponding path program 1 times [2021-12-07 00:18:29,017 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:29,017 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [715996720] [2021-12-07 00:18:29,017 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:29,017 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:29,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:18:29,035 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:18:29,035 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:18:29,035 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [715996720] [2021-12-07 00:18:29,035 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [715996720] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:18:29,035 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:18:29,036 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:18:29,036 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [322271860] [2021-12-07 00:18:29,036 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:18:29,036 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:18:29,036 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:18:29,036 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:18:29,036 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:18:29,037 INFO L87 Difference]: Start difference. First operand 1304 states and 1930 transitions. cyclomatic complexity: 630 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:29,075 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:18:29,075 INFO L93 Difference]: Finished difference Result 2485 states and 3631 transitions. [2021-12-07 00:18:29,075 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:18:29,075 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2485 states and 3631 transitions. [2021-12-07 00:18:29,089 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2395 [2021-12-07 00:18:29,103 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2485 states to 2485 states and 3631 transitions. [2021-12-07 00:18:29,103 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2485 [2021-12-07 00:18:29,105 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2485 [2021-12-07 00:18:29,105 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2485 states and 3631 transitions. [2021-12-07 00:18:29,108 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:18:29,108 INFO L681 BuchiCegarLoop]: Abstraction has 2485 states and 3631 transitions. [2021-12-07 00:18:29,110 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2485 states and 3631 transitions. [2021-12-07 00:18:29,138 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2485 to 2349. [2021-12-07 00:18:29,142 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2349 states, 2349 states have (on average 1.465730097914006) internal successors, (3443), 2348 states have internal predecessors, (3443), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:29,148 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2349 states to 2349 states and 3443 transitions. [2021-12-07 00:18:29,149 INFO L704 BuchiCegarLoop]: Abstraction has 2349 states and 3443 transitions. [2021-12-07 00:18:29,149 INFO L587 BuchiCegarLoop]: Abstraction has 2349 states and 3443 transitions. [2021-12-07 00:18:29,149 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-07 00:18:29,149 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2349 states and 3443 transitions. [2021-12-07 00:18:29,158 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2259 [2021-12-07 00:18:29,158 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:18:29,158 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:18:29,159 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:29,159 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:29,159 INFO L791 eck$LassoCheckResult]: Stem: 11002#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 10976#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 10843#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10569#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10570#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 10628#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10927#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10575#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10576#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10703#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10609#L514 assume !(0 == ~M_E~0); 10610#L514-2 assume !(0 == ~T1_E~0); 10958#L519-1 assume !(0 == ~T2_E~0); 10561#L524-1 assume !(0 == ~T3_E~0); 10562#L529-1 assume !(0 == ~T4_E~0); 10679#L534-1 assume !(0 == ~E_M~0); 10896#L539-1 assume !(0 == ~E_1~0); 10897#L544-1 assume !(0 == ~E_2~0); 10924#L549-1 assume !(0 == ~E_3~0); 10925#L554-1 assume !(0 == ~E_4~0); 10556#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10557#L250 assume !(1 == ~m_pc~0); 10783#L250-2 is_master_triggered_~__retres1~0#1 := 0; 10930#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10743#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10744#L637 assume !(0 != activate_threads_~tmp~1#1); 10563#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10564#L269 assume !(1 == ~t1_pc~0); 10500#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10499#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10698#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 10699#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10739#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10740#L288 assume 1 == ~t2_pc~0; 10868#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10733#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10754#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10755#L653 assume !(0 != activate_threads_~tmp___1~0#1); 10889#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10769#L307 assume !(1 == ~t3_pc~0); 10692#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10693#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10834#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10936#L661 assume !(0 != activate_threads_~tmp___2~0#1); 10709#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10710#L326 assume 1 == ~t4_pc~0; 10971#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10514#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10767#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10895#L669 assume !(0 != activate_threads_~tmp___3~0#1); 10892#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10893#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 10931#L572-2 assume !(1 == ~T1_E~0); 10571#L577-1 assume !(1 == ~T2_E~0); 10572#L582-1 assume !(1 == ~T3_E~0); 10876#L587-1 assume !(1 == ~T4_E~0); 10883#L592-1 assume !(1 == ~E_M~0); 10511#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 10512#L602-1 assume !(1 == ~E_2~0); 10996#L607-1 assume !(1 == ~E_3~0); 10997#L612-1 assume !(1 == ~E_4~0); 10677#L617-1 assume { :end_inline_reset_delta_events } true; 10678#L803-2 [2021-12-07 00:18:29,159 INFO L793 eck$LassoCheckResult]: Loop: 10678#L803-2 assume !false; 10845#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10601#L489 assume !false; 10814#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 10772#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 10617#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 10674#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10998#L428 assume !(0 != eval_~tmp~0#1); 10989#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10858#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10811#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10749#L514-5 assume !(0 == ~T1_E~0); 10750#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10872#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10648#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10649#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10494#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10495#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10960#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10696#L554-3 assume !(0 == ~E_4~0); 10697#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10905#L250-18 assume !(1 == ~m_pc~0); 10906#L250-20 is_master_triggered_~__retres1~0#1 := 0; 11268#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10588#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10589#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10658#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10542#L269-18 assume 1 == ~t1_pc~0; 10544#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10620#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10621#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 10673#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10793#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10684#L288-18 assume 1 == ~t2_pc~0; 10669#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10503#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10504#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10604#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10665#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10666#L307-18 assume 1 == ~t3_pc~0; 10731#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10638#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10700#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10646#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10647#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10907#L326-18 assume 1 == ~t4_pc~0; 10908#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10917#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10874#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10490#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10491#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10977#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10663#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10664#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10554#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10555#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10806#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10807#L597-3 assume !(1 == ~E_1~0); 10716#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10717#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10671#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10672#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 10723#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 10688#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 10706#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 10764#L822 assume !(0 == start_simulation_~tmp~3#1); 10766#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 11212#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 11207#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 11205#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 11204#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11203#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11196#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 11195#L835 assume !(0 != start_simulation_~tmp___0~1#1); 10678#L803-2 [2021-12-07 00:18:29,159 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:29,160 INFO L85 PathProgramCache]: Analyzing trace with hash -1001423999, now seen corresponding path program 1 times [2021-12-07 00:18:29,160 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:29,160 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1864649745] [2021-12-07 00:18:29,160 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:29,160 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:29,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:18:29,184 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:18:29,184 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:18:29,185 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1864649745] [2021-12-07 00:18:29,185 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1864649745] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:18:29,185 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:18:29,185 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-07 00:18:29,185 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [164111801] [2021-12-07 00:18:29,185 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:18:29,185 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:18:29,186 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:29,186 INFO L85 PathProgramCache]: Analyzing trace with hash 1232046382, now seen corresponding path program 1 times [2021-12-07 00:18:29,186 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:29,186 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [149693549] [2021-12-07 00:18:29,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:29,187 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:29,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:18:29,211 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:18:29,212 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:18:29,212 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [149693549] [2021-12-07 00:18:29,212 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [149693549] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:18:29,212 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:18:29,212 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:18:29,212 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [272403064] [2021-12-07 00:18:29,213 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:18:29,213 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:18:29,213 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:18:29,213 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-07 00:18:29,214 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-07 00:18:29,214 INFO L87 Difference]: Start difference. First operand 2349 states and 3443 transitions. cyclomatic complexity: 1102 Second operand has 5 states, 5 states have (on average 12.4) internal successors, (62), 5 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:29,356 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:18:29,357 INFO L93 Difference]: Finished difference Result 6327 states and 9245 transitions. [2021-12-07 00:18:29,357 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-07 00:18:29,357 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6327 states and 9245 transitions. [2021-12-07 00:18:29,393 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6120 [2021-12-07 00:18:29,429 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6327 states to 6327 states and 9245 transitions. [2021-12-07 00:18:29,429 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6327 [2021-12-07 00:18:29,434 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6327 [2021-12-07 00:18:29,434 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6327 states and 9245 transitions. [2021-12-07 00:18:29,441 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:18:29,441 INFO L681 BuchiCegarLoop]: Abstraction has 6327 states and 9245 transitions. [2021-12-07 00:18:29,446 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6327 states and 9245 transitions. [2021-12-07 00:18:29,506 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6327 to 2478. [2021-12-07 00:18:29,511 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2478 states, 2478 states have (on average 1.4414850686037126) internal successors, (3572), 2477 states have internal predecessors, (3572), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:29,520 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2478 states to 2478 states and 3572 transitions. [2021-12-07 00:18:29,520 INFO L704 BuchiCegarLoop]: Abstraction has 2478 states and 3572 transitions. [2021-12-07 00:18:29,520 INFO L587 BuchiCegarLoop]: Abstraction has 2478 states and 3572 transitions. [2021-12-07 00:18:29,520 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-07 00:18:29,520 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2478 states and 3572 transitions. [2021-12-07 00:18:29,529 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2385 [2021-12-07 00:18:29,529 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:18:29,529 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:18:29,530 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:29,530 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:29,530 INFO L791 eck$LassoCheckResult]: Stem: 19682#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 19660#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 19530#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19260#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19261#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 19318#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19609#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19266#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19267#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19396#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19300#L514 assume !(0 == ~M_E~0); 19301#L514-2 assume !(0 == ~T1_E~0); 19633#L519-1 assume !(0 == ~T2_E~0); 19252#L524-1 assume !(0 == ~T3_E~0); 19253#L529-1 assume !(0 == ~T4_E~0); 19373#L534-1 assume !(0 == ~E_M~0); 19577#L539-1 assume !(0 == ~E_1~0); 19578#L544-1 assume !(0 == ~E_2~0); 19606#L549-1 assume !(0 == ~E_3~0); 19607#L554-1 assume !(0 == ~E_4~0); 19247#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19248#L250 assume !(1 == ~m_pc~0); 19471#L250-2 is_master_triggered_~__retres1~0#1 := 0; 19612#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19432#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 19433#L637 assume !(0 != activate_threads_~tmp~1#1); 19254#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19255#L269 assume !(1 == ~t1_pc~0); 19189#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19368#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19476#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 19634#L645 assume !(0 != activate_threads_~tmp___0~0#1); 19429#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19430#L288 assume 1 == ~t2_pc~0; 19549#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19424#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19443#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 19444#L653 assume !(0 != activate_threads_~tmp___1~0#1); 19570#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19458#L307 assume !(1 == ~t3_pc~0); 19386#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19387#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19519#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 19618#L661 assume !(0 != activate_threads_~tmp___2~0#1); 19402#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19403#L326 assume 1 == ~t4_pc~0; 19648#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19205#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19456#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 19576#L669 assume !(0 != activate_threads_~tmp___3~0#1); 19573#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19574#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 19613#L572-2 assume !(1 == ~T1_E~0); 19262#L577-1 assume !(1 == ~T2_E~0); 19263#L582-1 assume !(1 == ~T3_E~0); 19558#L587-1 assume !(1 == ~T4_E~0); 19564#L592-1 assume !(1 == ~E_M~0); 19196#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 19197#L602-1 assume !(1 == ~E_2~0); 19420#L607-1 assume !(1 == ~E_3~0); 19421#L612-1 assume !(1 == ~E_4~0); 20055#L617-1 assume { :end_inline_reset_delta_events } true; 20054#L803-2 [2021-12-07 00:18:29,531 INFO L793 eck$LassoCheckResult]: Loop: 20054#L803-2 assume !false; 20031#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20015#L489 assume !false; 20014#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 20013#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 19985#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 19984#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 19981#L428 assume !(0 != eval_~tmp~0#1); 19982#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20377#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20374#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20372#L514-5 assume !(0 == ~T1_E~0); 20370#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20369#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20367#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20365#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20363#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20361#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20359#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20357#L554-3 assume !(0 == ~E_4~0); 20355#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20354#L250-18 assume !(1 == ~m_pc~0); 20353#L250-20 is_master_triggered_~__retres1~0#1 := 0; 20352#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20351#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 20350#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20349#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20348#L269-18 assume 1 == ~t1_pc~0; 20346#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20344#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20342#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 20340#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20338#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20336#L288-18 assume 1 == ~t2_pc~0; 20333#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20331#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20329#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 20326#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 20324#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20322#L307-18 assume 1 == ~t3_pc~0; 20320#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20317#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20315#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20312#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20310#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20308#L326-18 assume 1 == ~t4_pc~0; 20305#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20303#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20302#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20301#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20300#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20299#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19679#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20162#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20160#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20158#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20156#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 20154#L597-3 assume !(1 == ~E_1~0); 20152#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20149#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20147#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20143#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 20136#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 20131#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 20129#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 20127#L822 assume !(0 == start_simulation_~tmp~3#1); 19572#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 20121#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 20117#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 20115#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 20063#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20061#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20059#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 20056#L835 assume !(0 != start_simulation_~tmp___0~1#1); 20054#L803-2 [2021-12-07 00:18:29,531 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:29,531 INFO L85 PathProgramCache]: Analyzing trace with hash -299824125, now seen corresponding path program 1 times [2021-12-07 00:18:29,531 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:29,531 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1700801863] [2021-12-07 00:18:29,531 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:29,532 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:29,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:18:29,557 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:18:29,557 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:18:29,557 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1700801863] [2021-12-07 00:18:29,557 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1700801863] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:18:29,558 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:18:29,558 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:18:29,558 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [929720924] [2021-12-07 00:18:29,558 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:18:29,558 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:18:29,559 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:29,559 INFO L85 PathProgramCache]: Analyzing trace with hash 1232046382, now seen corresponding path program 2 times [2021-12-07 00:18:29,559 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:29,559 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [139370551] [2021-12-07 00:18:29,559 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:29,559 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:29,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:18:29,583 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:18:29,583 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:18:29,584 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [139370551] [2021-12-07 00:18:29,584 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [139370551] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:18:29,584 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:18:29,584 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:18:29,584 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [232168477] [2021-12-07 00:18:29,584 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:18:29,585 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:18:29,585 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:18:29,585 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-07 00:18:29,585 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-07 00:18:29,585 INFO L87 Difference]: Start difference. First operand 2478 states and 3572 transitions. cyclomatic complexity: 1102 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:29,689 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:18:29,689 INFO L93 Difference]: Finished difference Result 5740 states and 8174 transitions. [2021-12-07 00:18:29,689 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-07 00:18:29,690 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5740 states and 8174 transitions. [2021-12-07 00:18:29,710 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 5468 [2021-12-07 00:18:29,744 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5740 states to 5740 states and 8174 transitions. [2021-12-07 00:18:29,744 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5740 [2021-12-07 00:18:29,748 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5740 [2021-12-07 00:18:29,749 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5740 states and 8174 transitions. [2021-12-07 00:18:29,753 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:18:29,754 INFO L681 BuchiCegarLoop]: Abstraction has 5740 states and 8174 transitions. [2021-12-07 00:18:29,758 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5740 states and 8174 transitions. [2021-12-07 00:18:29,822 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5740 to 4492. [2021-12-07 00:18:29,828 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4492 states, 4492 states have (on average 1.4341050756901157) internal successors, (6442), 4491 states have internal predecessors, (6442), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:29,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4492 states to 4492 states and 6442 transitions. [2021-12-07 00:18:29,837 INFO L704 BuchiCegarLoop]: Abstraction has 4492 states and 6442 transitions. [2021-12-07 00:18:29,837 INFO L587 BuchiCegarLoop]: Abstraction has 4492 states and 6442 transitions. [2021-12-07 00:18:29,837 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-07 00:18:29,837 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4492 states and 6442 transitions. [2021-12-07 00:18:29,847 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4396 [2021-12-07 00:18:29,847 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:18:29,847 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:18:29,848 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:29,848 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:29,848 INFO L791 eck$LassoCheckResult]: Stem: 27887#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 27860#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 27745#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27485#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27486#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 27539#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27813#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27491#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27492#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27615#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27521#L514 assume !(0 == ~M_E~0); 27522#L514-2 assume !(0 == ~T1_E~0); 27832#L519-1 assume !(0 == ~T2_E~0); 27477#L524-1 assume !(0 == ~T3_E~0); 27478#L529-1 assume !(0 == ~T4_E~0); 27592#L534-1 assume !(0 == ~E_M~0); 27785#L539-1 assume !(0 == ~E_1~0); 27786#L544-1 assume !(0 == ~E_2~0); 27810#L549-1 assume !(0 == ~E_3~0); 27811#L554-1 assume !(0 == ~E_4~0); 27472#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27473#L250 assume !(1 == ~m_pc~0); 27693#L250-2 is_master_triggered_~__retres1~0#1 := 0; 27816#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27652#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 27653#L637 assume !(0 != activate_threads_~tmp~1#1); 27479#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27480#L269 assume !(1 == ~t1_pc~0); 27417#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 27587#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27889#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 27833#L645 assume !(0 != activate_threads_~tmp___0~0#1); 27649#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27650#L288 assume !(1 == ~t2_pc~0); 27642#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 27643#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27665#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 27666#L653 assume !(0 != activate_threads_~tmp___1~0#1); 27779#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27680#L307 assume !(1 == ~t3_pc~0); 27605#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 27606#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27735#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 27821#L661 assume !(0 != activate_threads_~tmp___2~0#1); 27623#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27624#L326 assume 1 == ~t4_pc~0; 27848#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27431#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27678#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 27784#L669 assume !(0 != activate_threads_~tmp___3~0#1); 27781#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27782#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 27817#L572-2 assume !(1 == ~T1_E~0); 27487#L577-1 assume !(1 == ~T2_E~0); 27488#L582-1 assume !(1 == ~T3_E~0); 27769#L587-1 assume !(1 == ~T4_E~0); 27775#L592-1 assume !(1 == ~E_M~0); 27428#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 27429#L602-1 assume !(1 == ~E_2~0); 27639#L607-1 assume !(1 == ~E_3~0); 27640#L612-1 assume !(1 == ~E_4~0); 27590#L617-1 assume { :end_inline_reset_delta_events } true; 27591#L803-2 [2021-12-07 00:18:29,848 INFO L793 eck$LassoCheckResult]: Loop: 27591#L803-2 assume !false; 27747#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27513#L489 assume !false; 27718#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 27683#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 27529#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 27585#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 27882#L428 assume !(0 != eval_~tmp~0#1); 27875#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27757#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27716#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 27658#L514-5 assume !(0 == ~T1_E~0); 27659#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27766#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 27559#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 27560#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 27411#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27412#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27835#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27609#L554-3 assume !(0 == ~E_4~0); 27610#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27714#L250-18 assume !(1 == ~m_pc~0); 27795#L250-20 is_master_triggered_~__retres1~0#1 := 0; 27727#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27502#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 27503#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27569#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27459#L269-18 assume !(1 == ~t1_pc~0); 27460#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 27531#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27532#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 27586#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 27702#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27596#L288-18 assume !(1 == ~t2_pc~0); 27597#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 27420#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27421#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 27516#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27576#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27577#L307-18 assume 1 == ~t3_pc~0; 27641#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27549#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27613#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 27557#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27558#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27792#L326-18 assume 1 == ~t4_pc~0; 27793#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27803#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27767#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 27407#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 27408#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27863#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 27572#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27573#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27470#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27471#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27712#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 27713#L597-3 assume !(1 == ~E_1~0); 27628#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27629#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27583#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27584#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 27633#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 27601#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 27864#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 27675#L822 assume !(0 == start_simulation_~tmp~3#1); 27677#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 27790#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 27722#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 27679#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 27443#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27444#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27720#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 27736#L835 assume !(0 != start_simulation_~tmp___0~1#1); 27591#L803-2 [2021-12-07 00:18:29,848 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:29,849 INFO L85 PathProgramCache]: Analyzing trace with hash -1271498812, now seen corresponding path program 1 times [2021-12-07 00:18:29,849 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:29,849 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [384241023] [2021-12-07 00:18:29,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:29,849 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:29,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:18:29,868 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:18:29,869 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:18:29,869 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [384241023] [2021-12-07 00:18:29,869 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [384241023] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:18:29,869 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:18:29,869 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-07 00:18:29,869 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [226605482] [2021-12-07 00:18:29,869 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:18:29,869 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:18:29,870 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:29,870 INFO L85 PathProgramCache]: Analyzing trace with hash -2043963790, now seen corresponding path program 1 times [2021-12-07 00:18:29,870 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:29,870 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [744231779] [2021-12-07 00:18:29,870 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:29,870 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:29,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:18:29,891 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:18:29,891 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:18:29,891 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [744231779] [2021-12-07 00:18:29,891 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [744231779] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:18:29,891 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:18:29,891 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:18:29,891 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1173401954] [2021-12-07 00:18:29,892 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:18:29,892 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:18:29,892 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:18:29,892 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:18:29,892 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:18:29,893 INFO L87 Difference]: Start difference. First operand 4492 states and 6442 transitions. cyclomatic complexity: 1958 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:29,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:18:29,946 INFO L93 Difference]: Finished difference Result 8195 states and 11703 transitions. [2021-12-07 00:18:29,946 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:18:29,947 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8195 states and 11703 transitions. [2021-12-07 00:18:29,974 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8060 [2021-12-07 00:18:30,015 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8195 states to 8195 states and 11703 transitions. [2021-12-07 00:18:30,015 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8195 [2021-12-07 00:18:30,021 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8195 [2021-12-07 00:18:30,021 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8195 states and 11703 transitions. [2021-12-07 00:18:30,029 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:18:30,029 INFO L681 BuchiCegarLoop]: Abstraction has 8195 states and 11703 transitions. [2021-12-07 00:18:30,035 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8195 states and 11703 transitions. [2021-12-07 00:18:30,152 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8195 to 8163. [2021-12-07 00:18:30,166 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8163 states, 8163 states have (on average 1.4297439666789171) internal successors, (11671), 8162 states have internal predecessors, (11671), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:30,186 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8163 states to 8163 states and 11671 transitions. [2021-12-07 00:18:30,186 INFO L704 BuchiCegarLoop]: Abstraction has 8163 states and 11671 transitions. [2021-12-07 00:18:30,186 INFO L587 BuchiCegarLoop]: Abstraction has 8163 states and 11671 transitions. [2021-12-07 00:18:30,186 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-07 00:18:30,186 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8163 states and 11671 transitions. [2021-12-07 00:18:30,206 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8028 [2021-12-07 00:18:30,206 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:18:30,206 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:18:30,207 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:30,207 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:30,207 INFO L791 eck$LassoCheckResult]: Stem: 40609#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 40576#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 40452#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40182#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 40183#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 40239#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40531#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40188#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40189#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40319#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40221#L514 assume !(0 == ~M_E~0); 40222#L514-2 assume !(0 == ~T1_E~0); 40550#L519-1 assume !(0 == ~T2_E~0); 40172#L524-1 assume !(0 == ~T3_E~0); 40173#L529-1 assume !(0 == ~T4_E~0); 40294#L534-1 assume !(0 == ~E_M~0); 40503#L539-1 assume !(0 == ~E_1~0); 40504#L544-1 assume !(0 == ~E_2~0); 40527#L549-1 assume !(0 == ~E_3~0); 40528#L554-1 assume !(0 == ~E_4~0); 40167#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40168#L250 assume !(1 == ~m_pc~0); 40393#L250-2 is_master_triggered_~__retres1~0#1 := 0; 40534#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40356#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 40357#L637 assume !(0 != activate_threads_~tmp~1#1); 40176#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40177#L269 assume !(1 == ~t1_pc~0); 40111#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 40289#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40614#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 40551#L645 assume !(0 != activate_threads_~tmp___0~0#1); 40353#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40354#L288 assume !(1 == ~t2_pc~0); 40348#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 40349#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40367#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 40368#L653 assume !(0 != activate_threads_~tmp___1~0#1); 40497#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40382#L307 assume !(1 == ~t3_pc~0); 40308#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 40309#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40444#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 40539#L661 assume !(0 != activate_threads_~tmp___2~0#1); 40326#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40327#L326 assume !(1 == ~t4_pc~0); 40124#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 40125#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40380#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 40502#L669 assume !(0 != activate_threads_~tmp___3~0#1); 40499#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40500#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 40535#L572-2 assume !(1 == ~T1_E~0); 40184#L577-1 assume !(1 == ~T2_E~0); 40185#L582-1 assume !(1 == ~T3_E~0); 40485#L587-1 assume !(1 == ~T4_E~0); 40493#L592-1 assume !(1 == ~E_M~0); 40122#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 40123#L602-1 assume !(1 == ~E_2~0); 40345#L607-1 assume !(1 == ~E_3~0); 40346#L612-1 assume !(1 == ~E_4~0); 44207#L617-1 assume { :end_inline_reset_delta_events } true; 44695#L803-2 [2021-12-07 00:18:30,207 INFO L793 eck$LassoCheckResult]: Loop: 44695#L803-2 assume !false; 44645#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44643#L489 assume !false; 44641#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 44588#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 44566#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 44557#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 44548#L428 assume !(0 != eval_~tmp~0#1); 44549#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 45436#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 45434#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 45432#L514-5 assume !(0 == ~T1_E~0); 45430#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 45428#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 45426#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45424#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 45422#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 45420#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 45419#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 45418#L554-3 assume !(0 == ~E_4~0); 45417#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45416#L250-18 assume !(1 == ~m_pc~0); 45415#L250-20 is_master_triggered_~__retres1~0#1 := 0; 45414#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45408#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 45406#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 45404#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45402#L269-18 assume 1 == ~t1_pc~0; 45396#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 45395#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45394#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 45386#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 45384#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45383#L288-18 assume !(1 == ~t2_pc~0); 44908#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 45381#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45380#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 45378#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 44782#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44779#L307-18 assume !(1 == ~t3_pc~0); 44776#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 44774#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44772#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 44770#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 44768#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44766#L326-18 assume !(1 == ~t4_pc~0); 44764#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 44762#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44760#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 44758#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44756#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44754#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 44261#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44748#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44746#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44744#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 44742#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 44740#L597-3 assume !(1 == ~E_1~0); 44738#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44736#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 44735#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 44249#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 44733#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 44728#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 44726#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 44724#L822 assume !(0 == start_simulation_~tmp~3#1); 44721#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 44709#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 44707#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 44704#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 44702#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44700#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 44699#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 44697#L835 assume !(0 != start_simulation_~tmp___0~1#1); 44695#L803-2 [2021-12-07 00:18:30,207 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:30,207 INFO L85 PathProgramCache]: Analyzing trace with hash 843496709, now seen corresponding path program 1 times [2021-12-07 00:18:30,207 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:30,208 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [69755962] [2021-12-07 00:18:30,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:30,208 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:30,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:18:30,225 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:18:30,225 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:18:30,225 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [69755962] [2021-12-07 00:18:30,225 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [69755962] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:18:30,225 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:18:30,225 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-07 00:18:30,225 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [819692503] [2021-12-07 00:18:30,225 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:18:30,226 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:18:30,226 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:30,226 INFO L85 PathProgramCache]: Analyzing trace with hash 826646065, now seen corresponding path program 1 times [2021-12-07 00:18:30,226 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:30,226 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [341272935] [2021-12-07 00:18:30,227 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:30,227 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:30,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:18:30,248 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:18:30,249 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:18:30,249 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [341272935] [2021-12-07 00:18:30,249 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [341272935] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:18:30,249 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:18:30,249 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:18:30,249 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [647506635] [2021-12-07 00:18:30,249 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:18:30,249 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:18:30,250 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:18:30,250 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:18:30,250 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:18:30,250 INFO L87 Difference]: Start difference. First operand 8163 states and 11671 transitions. cyclomatic complexity: 3524 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:30,314 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:18:30,314 INFO L93 Difference]: Finished difference Result 10310 states and 14716 transitions. [2021-12-07 00:18:30,314 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:18:30,315 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10310 states and 14716 transitions. [2021-12-07 00:18:30,346 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 10172 [2021-12-07 00:18:30,375 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10310 states to 10310 states and 14716 transitions. [2021-12-07 00:18:30,375 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10310 [2021-12-07 00:18:30,382 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10310 [2021-12-07 00:18:30,382 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10310 states and 14716 transitions. [2021-12-07 00:18:30,389 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:18:30,389 INFO L681 BuchiCegarLoop]: Abstraction has 10310 states and 14716 transitions. [2021-12-07 00:18:30,396 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10310 states and 14716 transitions. [2021-12-07 00:18:30,469 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10310 to 4687. [2021-12-07 00:18:30,475 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4687 states, 4687 states have (on average 1.4288457435459783) internal successors, (6697), 4686 states have internal predecessors, (6697), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:30,483 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4687 states to 4687 states and 6697 transitions. [2021-12-07 00:18:30,484 INFO L704 BuchiCegarLoop]: Abstraction has 4687 states and 6697 transitions. [2021-12-07 00:18:30,484 INFO L587 BuchiCegarLoop]: Abstraction has 4687 states and 6697 transitions. [2021-12-07 00:18:30,484 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-07 00:18:30,484 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4687 states and 6697 transitions. [2021-12-07 00:18:30,494 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4596 [2021-12-07 00:18:30,494 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:18:30,494 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:18:30,495 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:30,495 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:30,495 INFO L791 eck$LassoCheckResult]: Stem: 59082#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 59054#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 58930#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 58660#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 58661#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 58718#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 59007#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 58666#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 58667#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 58795#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 58699#L514 assume !(0 == ~M_E~0); 58700#L514-2 assume !(0 == ~T1_E~0); 59034#L519-1 assume !(0 == ~T2_E~0); 58652#L524-1 assume !(0 == ~T3_E~0); 58653#L529-1 assume !(0 == ~T4_E~0); 58770#L534-1 assume !(0 == ~E_M~0); 58974#L539-1 assume !(0 == ~E_1~0); 58975#L544-1 assume !(0 == ~E_2~0); 59004#L549-1 assume !(0 == ~E_3~0); 59005#L554-1 assume !(0 == ~E_4~0); 58647#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 58648#L250 assume !(1 == ~m_pc~0); 58871#L250-2 is_master_triggered_~__retres1~0#1 := 0; 59010#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58832#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 58833#L637 assume !(0 != activate_threads_~tmp~1#1); 58654#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 58655#L269 assume !(1 == ~t1_pc~0); 58591#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 58765#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59084#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 59035#L645 assume !(0 != activate_threads_~tmp___0~0#1); 58829#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 58830#L288 assume !(1 == ~t2_pc~0); 58823#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 58824#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58844#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 58845#L653 assume !(0 != activate_threads_~tmp___1~0#1); 58967#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 58859#L307 assume !(1 == ~t3_pc~0); 58783#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 58784#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58919#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 59016#L661 assume !(0 != activate_threads_~tmp___2~0#1); 58802#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58803#L326 assume !(1 == ~t4_pc~0); 58604#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 58605#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58857#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 58973#L669 assume !(0 != activate_threads_~tmp___3~0#1); 58970#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 58971#L572 assume !(1 == ~M_E~0); 59011#L572-2 assume !(1 == ~T1_E~0); 58662#L577-1 assume !(1 == ~T2_E~0); 58663#L582-1 assume !(1 == ~T3_E~0); 58956#L587-1 assume !(1 == ~T4_E~0); 58962#L592-1 assume !(1 == ~E_M~0); 58602#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 58603#L602-1 assume !(1 == ~E_2~0); 58820#L607-1 assume !(1 == ~E_3~0); 58821#L612-1 assume !(1 == ~E_4~0); 58768#L617-1 assume { :end_inline_reset_delta_events } true; 58769#L803-2 [2021-12-07 00:18:30,495 INFO L793 eck$LassoCheckResult]: Loop: 58769#L803-2 assume !false; 62969#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 62967#L489 assume !false; 62965#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 62963#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 62957#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 62956#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 62955#L428 assume !(0 != eval_~tmp~0#1); 59066#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 58943#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 58896#L514-3 assume !(0 == ~M_E~0); 58837#L514-5 assume !(0 == ~T1_E~0); 58838#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 58952#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 58738#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 58739#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 58585#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 58586#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 63184#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 63183#L554-3 assume !(0 == ~E_4~0); 63182#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 63181#L250-18 assume !(1 == ~m_pc~0); 63180#L250-20 is_master_triggered_~__retres1~0#1 := 0; 63179#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 63178#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 63177#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 63176#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63175#L269-18 assume !(1 == ~t1_pc~0); 63173#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 63171#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63169#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 63168#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 63050#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 58774#L288-18 assume !(1 == ~t2_pc~0); 58775#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 61698#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61696#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 61694#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 61692#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 61690#L307-18 assume !(1 == ~t3_pc~0); 61687#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 61685#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 61682#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 61680#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 61678#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 61676#L326-18 assume !(1 == ~t4_pc~0); 61674#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 61672#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61670#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 61668#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 61666#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 61664#L572-3 assume !(1 == ~M_E~0); 61197#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 61661#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 61660#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 61658#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 61589#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 59247#L597-3 assume !(1 == ~E_1~0); 59246#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 59245#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 59244#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 59243#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 59216#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 59207#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 59201#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 59199#L822 assume !(0 == start_simulation_~tmp~3#1); 59200#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 63013#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 63011#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 63010#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 63009#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 63008#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 63007#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 63006#L835 assume !(0 != start_simulation_~tmp___0~1#1); 58769#L803-2 [2021-12-07 00:18:30,495 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:30,495 INFO L85 PathProgramCache]: Analyzing trace with hash 1544561287, now seen corresponding path program 1 times [2021-12-07 00:18:30,495 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:30,496 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1568444196] [2021-12-07 00:18:30,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:30,496 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:30,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:18:30,515 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:18:30,515 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:18:30,515 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1568444196] [2021-12-07 00:18:30,516 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1568444196] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:18:30,516 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:18:30,516 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:18:30,516 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1261777899] [2021-12-07 00:18:30,516 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:18:30,516 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:18:30,516 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:30,516 INFO L85 PathProgramCache]: Analyzing trace with hash 470946676, now seen corresponding path program 1 times [2021-12-07 00:18:30,516 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:30,516 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1715765105] [2021-12-07 00:18:30,517 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:30,517 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:30,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:18:30,533 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:18:30,533 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:18:30,533 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1715765105] [2021-12-07 00:18:30,533 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1715765105] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:18:30,533 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:18:30,533 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:18:30,534 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1195349924] [2021-12-07 00:18:30,534 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:18:30,534 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:18:30,534 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:18:30,534 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-07 00:18:30,534 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-07 00:18:30,534 INFO L87 Difference]: Start difference. First operand 4687 states and 6697 transitions. cyclomatic complexity: 2014 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:30,629 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:18:30,630 INFO L93 Difference]: Finished difference Result 6415 states and 9008 transitions. [2021-12-07 00:18:30,633 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-07 00:18:30,634 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6415 states and 9008 transitions. [2021-12-07 00:18:30,663 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 6230 [2021-12-07 00:18:30,703 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6415 states to 6415 states and 9008 transitions. [2021-12-07 00:18:30,703 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6415 [2021-12-07 00:18:30,707 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6415 [2021-12-07 00:18:30,707 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6415 states and 9008 transitions. [2021-12-07 00:18:30,711 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:18:30,711 INFO L681 BuchiCegarLoop]: Abstraction has 6415 states and 9008 transitions. [2021-12-07 00:18:30,716 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6415 states and 9008 transitions. [2021-12-07 00:18:30,770 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6415 to 5274. [2021-12-07 00:18:30,776 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5274 states, 5274 states have (on average 1.4125900644671976) internal successors, (7450), 5273 states have internal predecessors, (7450), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:30,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5274 states to 5274 states and 7450 transitions. [2021-12-07 00:18:30,788 INFO L704 BuchiCegarLoop]: Abstraction has 5274 states and 7450 transitions. [2021-12-07 00:18:30,788 INFO L587 BuchiCegarLoop]: Abstraction has 5274 states and 7450 transitions. [2021-12-07 00:18:30,788 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-07 00:18:30,789 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5274 states and 7450 transitions. [2021-12-07 00:18:30,810 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5140 [2021-12-07 00:18:30,810 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:18:30,810 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:18:30,811 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:30,811 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:30,812 INFO L791 eck$LassoCheckResult]: Stem: 70189#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 70167#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 70040#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 69772#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 69773#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 69827#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 70119#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 69778#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 69779#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 69905#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 69810#L514 assume !(0 == ~M_E~0); 69811#L514-2 assume !(0 == ~T1_E~0); 70147#L519-1 assume !(0 == ~T2_E~0); 69762#L524-1 assume !(0 == ~T3_E~0); 69763#L529-1 assume !(0 == ~T4_E~0); 69880#L534-1 assume !(0 == ~E_M~0); 70088#L539-1 assume 0 == ~E_1~0;~E_1~0 := 1; 70089#L544-1 assume !(0 == ~E_2~0); 70231#L549-1 assume !(0 == ~E_3~0); 70230#L554-1 assume !(0 == ~E_4~0); 70229#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 70228#L250 assume !(1 == ~m_pc~0); 70227#L250-2 is_master_triggered_~__retres1~0#1 := 0; 70226#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 70225#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 70224#L637 assume !(0 != activate_threads_~tmp~1#1); 69766#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69767#L269 assume !(1 == ~t1_pc~0); 69796#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 70233#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 70232#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 70219#L645 assume !(0 != activate_threads_~tmp___0~0#1); 70218#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 70217#L288 assume !(1 == ~t2_pc~0); 70216#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 70215#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 70214#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 70213#L653 assume !(0 != activate_threads_~tmp___1~0#1); 70212#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 70211#L307 assume !(1 == ~t3_pc~0); 70209#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 70208#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 70207#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 70206#L661 assume !(0 != activate_threads_~tmp___2~0#1); 70205#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 70204#L326 assume !(1 == ~t4_pc~0); 70203#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 70202#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 70201#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 70200#L669 assume !(0 != activate_threads_~tmp___3~0#1); 70199#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 70198#L572 assume !(1 == ~M_E~0); 70197#L572-2 assume !(1 == ~T1_E~0); 70196#L577-1 assume !(1 == ~T2_E~0); 70195#L582-1 assume !(1 == ~T3_E~0); 70194#L587-1 assume !(1 == ~T4_E~0); 70193#L592-1 assume !(1 == ~E_M~0); 70192#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 69715#L602-1 assume !(1 == ~E_2~0); 69931#L607-1 assume !(1 == ~E_3~0); 69932#L612-1 assume !(1 == ~E_4~0); 69878#L617-1 assume { :end_inline_reset_delta_events } true; 69879#L803-2 [2021-12-07 00:18:30,812 INFO L793 eck$LassoCheckResult]: Loop: 69879#L803-2 assume !false; 70042#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 69802#L489 assume !false; 70011#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 69973#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 69818#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 69874#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 70183#L428 assume !(0 != eval_~tmp~0#1); 70184#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 74799#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 70009#L514-3 assume !(0 == ~M_E~0); 70010#L514-5 assume !(0 == ~T1_E~0); 74795#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 74794#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 74793#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 74792#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 74791#L539-3 assume !(0 == ~E_1~0); 70149#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 70150#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 69898#L554-3 assume !(0 == ~E_4~0); 69899#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 70004#L250-18 assume !(1 == ~m_pc~0); 70099#L250-20 is_master_triggered_~__retres1~0#1 := 0; 70021#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69789#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 69790#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 69856#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69743#L269-18 assume !(1 == ~t1_pc~0); 69744#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 69820#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69821#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 69873#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 69991#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 70113#L288-18 assume !(1 == ~t2_pc~0); 74615#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 74613#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 74611#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 74608#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 74606#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 74545#L307-18 assume !(1 == ~t3_pc~0); 74535#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 74532#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 74528#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 74526#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 74522#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 74518#L326-18 assume !(1 == ~t4_pc~0); 74514#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 74510#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 74505#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 74501#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 74497#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 74493#L572-3 assume !(1 == ~M_E~0); 72924#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 74477#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 74452#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 74446#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 74441#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 74413#L597-3 assume !(1 == ~E_1~0); 74411#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 74407#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 74404#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 74400#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 74396#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 74391#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 74388#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 69965#L822 assume !(0 == start_simulation_~tmp~3#1); 69967#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 70094#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 70016#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 69969#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 69728#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 69729#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 70012#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 70031#L835 assume !(0 != start_simulation_~tmp___0~1#1); 69879#L803-2 [2021-12-07 00:18:30,812 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:30,812 INFO L85 PathProgramCache]: Analyzing trace with hash -383711415, now seen corresponding path program 1 times [2021-12-07 00:18:30,812 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:30,813 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [591582567] [2021-12-07 00:18:30,813 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:30,813 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:30,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:18:30,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:18:30,836 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:18:30,836 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [591582567] [2021-12-07 00:18:30,837 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [591582567] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:18:30,837 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:18:30,837 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:18:30,837 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2061877899] [2021-12-07 00:18:30,837 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:18:30,837 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:18:30,837 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:30,837 INFO L85 PathProgramCache]: Analyzing trace with hash 904675762, now seen corresponding path program 1 times [2021-12-07 00:18:30,838 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:30,838 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [528443900] [2021-12-07 00:18:30,838 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:30,838 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:30,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:18:30,863 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:18:30,863 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:18:30,864 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [528443900] [2021-12-07 00:18:30,864 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [528443900] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:18:30,864 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:18:30,864 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-07 00:18:30,864 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1396036128] [2021-12-07 00:18:30,864 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:18:30,865 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:18:30,865 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:18:30,865 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-07 00:18:30,865 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-07 00:18:30,865 INFO L87 Difference]: Start difference. First operand 5274 states and 7450 transitions. cyclomatic complexity: 2180 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:30,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:18:30,934 INFO L93 Difference]: Finished difference Result 5366 states and 7524 transitions. [2021-12-07 00:18:30,935 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-07 00:18:30,935 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5366 states and 7524 transitions. [2021-12-07 00:18:30,958 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5262 [2021-12-07 00:18:30,972 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5366 states to 5366 states and 7524 transitions. [2021-12-07 00:18:30,972 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5366 [2021-12-07 00:18:30,975 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5366 [2021-12-07 00:18:30,975 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5366 states and 7524 transitions. [2021-12-07 00:18:30,978 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:18:30,978 INFO L681 BuchiCegarLoop]: Abstraction has 5366 states and 7524 transitions. [2021-12-07 00:18:30,981 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5366 states and 7524 transitions. [2021-12-07 00:18:31,021 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5366 to 4468. [2021-12-07 00:18:31,026 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4468 states, 4468 states have (on average 1.4059982094897046) internal successors, (6282), 4467 states have internal predecessors, (6282), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:31,037 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4468 states to 4468 states and 6282 transitions. [2021-12-07 00:18:31,037 INFO L704 BuchiCegarLoop]: Abstraction has 4468 states and 6282 transitions. [2021-12-07 00:18:31,037 INFO L587 BuchiCegarLoop]: Abstraction has 4468 states and 6282 transitions. [2021-12-07 00:18:31,037 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-07 00:18:31,037 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4468 states and 6282 transitions. [2021-12-07 00:18:31,048 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4380 [2021-12-07 00:18:31,048 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:18:31,048 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:18:31,049 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:31,049 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:31,050 INFO L791 eck$LassoCheckResult]: Stem: 80821#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 80800#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 80682#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 80420#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 80421#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 80476#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 80756#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 80426#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 80427#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 80550#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 80457#L514 assume !(0 == ~M_E~0); 80458#L514-2 assume !(0 == ~T1_E~0); 80782#L519-1 assume !(0 == ~T2_E~0); 80412#L524-1 assume !(0 == ~T3_E~0); 80413#L529-1 assume !(0 == ~T4_E~0); 80528#L534-1 assume !(0 == ~E_M~0); 80727#L539-1 assume !(0 == ~E_1~0); 80728#L544-1 assume !(0 == ~E_2~0); 80754#L549-1 assume !(0 == ~E_3~0); 80755#L554-1 assume !(0 == ~E_4~0); 80407#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 80408#L250 assume !(1 == ~m_pc~0); 80626#L250-2 is_master_triggered_~__retres1~0#1 := 0; 80761#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 80589#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 80590#L637 assume !(0 != activate_threads_~tmp~1#1); 80414#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 80415#L269 assume !(1 == ~t1_pc~0); 80354#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 80523#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 80547#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 80548#L645 assume !(0 != activate_threads_~tmp___0~0#1); 80586#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 80587#L288 assume !(1 == ~t2_pc~0); 80579#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 80580#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 80600#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 80601#L653 assume !(0 != activate_threads_~tmp___1~0#1); 80720#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 80614#L307 assume !(1 == ~t3_pc~0); 80541#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 80542#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 80669#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 80766#L661 assume !(0 != activate_threads_~tmp___2~0#1); 80559#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 80560#L326 assume !(1 == ~t4_pc~0); 80367#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 80368#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 80610#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 80726#L669 assume !(0 != activate_threads_~tmp___3~0#1); 80723#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 80724#L572 assume !(1 == ~M_E~0); 80762#L572-2 assume !(1 == ~T1_E~0); 80422#L577-1 assume !(1 == ~T2_E~0); 80423#L582-1 assume !(1 == ~T3_E~0); 80708#L587-1 assume !(1 == ~T4_E~0); 80715#L592-1 assume !(1 == ~E_M~0); 80359#L597-1 assume !(1 == ~E_1~0); 80360#L602-1 assume !(1 == ~E_2~0); 80576#L607-1 assume !(1 == ~E_3~0); 80577#L612-1 assume !(1 == ~E_4~0); 80526#L617-1 assume { :end_inline_reset_delta_events } true; 80527#L803-2 [2021-12-07 00:18:31,050 INFO L793 eck$LassoCheckResult]: Loop: 80527#L803-2 assume !false; 84499#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 84493#L489 assume !false; 84487#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 84475#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 84470#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 84468#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 84465#L428 assume !(0 != eval_~tmp~0#1); 84463#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 84461#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 84459#L514-3 assume !(0 == ~M_E~0); 84457#L514-5 assume !(0 == ~T1_E~0); 84455#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 84453#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 84451#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 84449#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 84446#L539-3 assume !(0 == ~E_1~0); 84443#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 84441#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 84439#L554-3 assume !(0 == ~E_4~0); 84435#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 84429#L250-18 assume !(1 == ~m_pc~0); 84425#L250-20 is_master_triggered_~__retres1~0#1 := 0; 84419#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 84414#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 84401#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 84399#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 84368#L269-18 assume !(1 == ~t1_pc~0); 84362#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 84356#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 84349#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 84342#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 84335#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 84328#L288-18 assume !(1 == ~t2_pc~0); 84254#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 84319#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 84317#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 84315#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 84309#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 84308#L307-18 assume 1 == ~t3_pc~0; 84307#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 84304#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 84302#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 84300#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 84298#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 84296#L326-18 assume !(1 == ~t4_pc~0); 84294#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 84292#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 84290#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 84288#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 84286#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 84284#L572-3 assume !(1 == ~M_E~0); 83291#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 84281#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 84279#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 84277#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 84275#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 84273#L597-3 assume !(1 == ~E_1~0); 84271#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 84268#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 84266#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 84264#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 84261#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 84256#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 83481#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 83455#L822 assume !(0 == start_simulation_~tmp~3#1); 83456#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 84589#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 84587#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 84586#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 84582#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 84580#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 84578#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 84576#L835 assume !(0 != start_simulation_~tmp___0~1#1); 80527#L803-2 [2021-12-07 00:18:31,050 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:31,050 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 1 times [2021-12-07 00:18:31,050 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:31,050 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1099621946] [2021-12-07 00:18:31,050 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:31,051 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:31,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:18:31,058 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 00:18:31,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:18:31,087 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 00:18:31,088 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:31,088 INFO L85 PathProgramCache]: Analyzing trace with hash -146773327, now seen corresponding path program 1 times [2021-12-07 00:18:31,088 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:31,088 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1390297013] [2021-12-07 00:18:31,088 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:31,088 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:31,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:18:31,114 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:18:31,114 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:18:31,114 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1390297013] [2021-12-07 00:18:31,114 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1390297013] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:18:31,114 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:18:31,114 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-07 00:18:31,114 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [776912145] [2021-12-07 00:18:31,114 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:18:31,115 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:18:31,115 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:18:31,115 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-07 00:18:31,115 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-07 00:18:31,116 INFO L87 Difference]: Start difference. First operand 4468 states and 6282 transitions. cyclomatic complexity: 1818 Second operand has 5 states, 5 states have (on average 14.8) internal successors, (74), 5 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:31,204 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:18:31,204 INFO L93 Difference]: Finished difference Result 7888 states and 10918 transitions. [2021-12-07 00:18:31,204 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-07 00:18:31,204 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7888 states and 10918 transitions. [2021-12-07 00:18:31,227 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7776 [2021-12-07 00:18:31,245 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7888 states to 7888 states and 10918 transitions. [2021-12-07 00:18:31,245 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7888 [2021-12-07 00:18:31,249 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7888 [2021-12-07 00:18:31,249 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7888 states and 10918 transitions. [2021-12-07 00:18:31,253 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:18:31,253 INFO L681 BuchiCegarLoop]: Abstraction has 7888 states and 10918 transitions. [2021-12-07 00:18:31,258 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7888 states and 10918 transitions. [2021-12-07 00:18:31,292 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7888 to 4516. [2021-12-07 00:18:31,296 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4516 states, 4516 states have (on average 1.4016829052258637) internal successors, (6330), 4515 states have internal predecessors, (6330), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:31,303 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4516 states to 4516 states and 6330 transitions. [2021-12-07 00:18:31,304 INFO L704 BuchiCegarLoop]: Abstraction has 4516 states and 6330 transitions. [2021-12-07 00:18:31,304 INFO L587 BuchiCegarLoop]: Abstraction has 4516 states and 6330 transitions. [2021-12-07 00:18:31,304 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-07 00:18:31,304 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4516 states and 6330 transitions. [2021-12-07 00:18:31,312 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4428 [2021-12-07 00:18:31,312 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:18:31,312 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:18:31,313 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:31,313 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:31,314 INFO L791 eck$LassoCheckResult]: Stem: 93231#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 93191#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 93068#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 92795#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 92796#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 92851#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 93142#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 92801#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 92802#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 92929#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 92833#L514 assume !(0 == ~M_E~0); 92834#L514-2 assume !(0 == ~T1_E~0); 93165#L519-1 assume !(0 == ~T2_E~0); 92785#L524-1 assume !(0 == ~T3_E~0); 92786#L529-1 assume !(0 == ~T4_E~0); 92906#L534-1 assume !(0 == ~E_M~0); 93115#L539-1 assume !(0 == ~E_1~0); 93116#L544-1 assume !(0 == ~E_2~0); 93140#L549-1 assume !(0 == ~E_3~0); 93141#L554-1 assume !(0 == ~E_4~0); 92780#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 92781#L250 assume !(1 == ~m_pc~0); 93008#L250-2 is_master_triggered_~__retres1~0#1 := 0; 93146#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 92969#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 92970#L637 assume !(0 != activate_threads_~tmp~1#1); 92787#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 92788#L269 assume !(1 == ~t1_pc~0); 92726#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 92901#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 92926#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 92927#L645 assume !(0 != activate_threads_~tmp___0~0#1); 92966#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 92967#L288 assume !(1 == ~t2_pc~0); 92959#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 92960#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 92980#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 92981#L653 assume !(0 != activate_threads_~tmp___1~0#1); 93108#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 92994#L307 assume !(1 == ~t3_pc~0); 92919#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 92920#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 93052#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 93150#L661 assume !(0 != activate_threads_~tmp___2~0#1); 92940#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 92941#L326 assume !(1 == ~t4_pc~0); 92739#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 92740#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 92990#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 93114#L669 assume !(0 != activate_threads_~tmp___3~0#1); 93111#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 93112#L572 assume !(1 == ~M_E~0); 93147#L572-2 assume !(1 == ~T1_E~0); 92797#L577-1 assume !(1 == ~T2_E~0); 92798#L582-1 assume !(1 == ~T3_E~0); 93096#L587-1 assume !(1 == ~T4_E~0); 93103#L592-1 assume !(1 == ~E_M~0); 92731#L597-1 assume !(1 == ~E_1~0); 92732#L602-1 assume !(1 == ~E_2~0); 92956#L607-1 assume !(1 == ~E_3~0); 92957#L612-1 assume !(1 == ~E_4~0); 92904#L617-1 assume { :end_inline_reset_delta_events } true; 92905#L803-2 [2021-12-07 00:18:31,314 INFO L793 eck$LassoCheckResult]: Loop: 92905#L803-2 assume !false; 93069#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 92824#L489 assume !false; 93039#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 97036#L386 assume !(0 == ~m_st~0); 97033#L390 assume !(0 == ~t1_st~0); 97034#L394 assume !(0 == ~t2_st~0); 97035#L398 assume !(0 == ~t3_st~0); 97031#L402 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 97032#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 94768#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 94769#L428 assume !(0 != eval_~tmp~0#1); 93206#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 93080#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 93038#L514-3 assume !(0 == ~M_E~0); 92974#L514-5 assume !(0 == ~T1_E~0); 92975#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 93090#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 93091#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 97147#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 97146#L539-3 assume !(0 == ~E_1~0); 97145#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 93213#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 92924#L554-3 assume !(0 == ~E_4~0); 92925#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 93032#L250-18 assume !(1 == ~m_pc~0); 93199#L250-20 is_master_triggered_~__retres1~0#1 := 0; 93048#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 92813#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 92814#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 93122#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 92766#L269-18 assume !(1 == ~t1_pc~0); 92767#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 92844#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 92845#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 96437#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 96438#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 92910#L288-18 assume !(1 == ~t2_pc~0); 92911#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 92729#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 92730#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 93003#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 93004#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 93157#L307-18 assume 1 == ~t3_pc~0; 93159#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 97078#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 92931#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 92932#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 93180#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 93181#L326-18 assume !(1 == ~t4_pc~0); 97077#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 93132#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 93133#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 92717#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 92718#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 93226#L572-3 assume !(1 == ~M_E~0); 93227#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 97142#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 97141#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 97140#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 97139#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 97138#L597-3 assume !(1 == ~E_1~0); 97137#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 97136#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 97135#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 93034#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 92951#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 92915#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 92936#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 92991#L822 assume !(0 == start_simulation_~tmp~3#1); 92993#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 93121#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 97211#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 97210#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 97209#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 97208#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 93058#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 93059#L835 assume !(0 != start_simulation_~tmp___0~1#1); 92905#L803-2 [2021-12-07 00:18:31,314 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:31,314 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 2 times [2021-12-07 00:18:31,314 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:31,314 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [139063545] [2021-12-07 00:18:31,314 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:31,314 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:31,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:18:31,320 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 00:18:31,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:18:31,335 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 00:18:31,335 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:31,335 INFO L85 PathProgramCache]: Analyzing trace with hash -1258608987, now seen corresponding path program 1 times [2021-12-07 00:18:31,335 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:31,335 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [262184452] [2021-12-07 00:18:31,335 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:31,336 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:31,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:18:31,379 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:18:31,379 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:18:31,379 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [262184452] [2021-12-07 00:18:31,379 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [262184452] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:18:31,379 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:18:31,379 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-07 00:18:31,379 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [503852510] [2021-12-07 00:18:31,379 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:18:31,380 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:18:31,380 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:18:31,380 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-07 00:18:31,380 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-07 00:18:31,380 INFO L87 Difference]: Start difference. First operand 4516 states and 6330 transitions. cyclomatic complexity: 1818 Second operand has 5 states, 5 states have (on average 15.6) internal successors, (78), 5 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:31,510 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:18:31,511 INFO L93 Difference]: Finished difference Result 8960 states and 12457 transitions. [2021-12-07 00:18:31,511 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-07 00:18:31,511 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8960 states and 12457 transitions. [2021-12-07 00:18:31,538 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8856 [2021-12-07 00:18:31,561 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8960 states to 8960 states and 12457 transitions. [2021-12-07 00:18:31,561 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8960 [2021-12-07 00:18:31,567 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8960 [2021-12-07 00:18:31,567 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8960 states and 12457 transitions. [2021-12-07 00:18:31,572 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:18:31,572 INFO L681 BuchiCegarLoop]: Abstraction has 8960 states and 12457 transitions. [2021-12-07 00:18:31,577 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8960 states and 12457 transitions. [2021-12-07 00:18:31,617 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8960 to 4648. [2021-12-07 00:18:31,622 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4648 states, 4648 states have (on average 1.382314974182444) internal successors, (6425), 4647 states have internal predecessors, (6425), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:31,631 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4648 states to 4648 states and 6425 transitions. [2021-12-07 00:18:31,631 INFO L704 BuchiCegarLoop]: Abstraction has 4648 states and 6425 transitions. [2021-12-07 00:18:31,631 INFO L587 BuchiCegarLoop]: Abstraction has 4648 states and 6425 transitions. [2021-12-07 00:18:31,631 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-07 00:18:31,631 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4648 states and 6425 transitions. [2021-12-07 00:18:31,641 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4560 [2021-12-07 00:18:31,641 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:18:31,641 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:18:31,642 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:31,642 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:31,642 INFO L791 eck$LassoCheckResult]: Stem: 106734#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 106692#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 106561#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 106284#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 106285#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 106338#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 106642#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 106290#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 106291#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 106418#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 106320#L514 assume !(0 == ~M_E~0); 106321#L514-2 assume !(0 == ~T1_E~0); 106672#L519-1 assume !(0 == ~T2_E~0); 106274#L524-1 assume !(0 == ~T3_E~0); 106275#L529-1 assume !(0 == ~T4_E~0); 106393#L534-1 assume !(0 == ~E_M~0); 106609#L539-1 assume !(0 == ~E_1~0); 106610#L544-1 assume !(0 == ~E_2~0); 106638#L549-1 assume !(0 == ~E_3~0); 106639#L554-1 assume !(0 == ~E_4~0); 106269#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 106270#L250 assume !(1 == ~m_pc~0); 106501#L250-2 is_master_triggered_~__retres1~0#1 := 0; 106645#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 106461#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 106462#L637 assume !(0 != activate_threads_~tmp~1#1); 106278#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 106279#L269 assume !(1 == ~t1_pc~0); 106215#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 106388#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 106414#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 106415#L645 assume !(0 != activate_threads_~tmp___0~0#1); 106457#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 106458#L288 assume !(1 == ~t2_pc~0); 106451#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 106452#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 106472#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 106473#L653 assume !(0 != activate_threads_~tmp___1~0#1); 106603#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 106487#L307 assume !(1 == ~t3_pc~0); 106407#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 106408#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 106552#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 106650#L661 assume !(0 != activate_threads_~tmp___2~0#1); 106428#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 106429#L326 assume !(1 == ~t4_pc~0); 106228#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 106229#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 106485#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 106608#L669 assume !(0 != activate_threads_~tmp___3~0#1); 106605#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 106606#L572 assume !(1 == ~M_E~0); 106646#L572-2 assume !(1 == ~T1_E~0); 106286#L577-1 assume !(1 == ~T2_E~0); 106287#L582-1 assume !(1 == ~T3_E~0); 106593#L587-1 assume !(1 == ~T4_E~0); 106599#L592-1 assume !(1 == ~E_M~0); 106226#L597-1 assume !(1 == ~E_1~0); 106227#L602-1 assume !(1 == ~E_2~0); 106448#L607-1 assume !(1 == ~E_3~0); 106449#L612-1 assume !(1 == ~E_4~0); 106391#L617-1 assume { :end_inline_reset_delta_events } true; 106392#L803-2 [2021-12-07 00:18:31,642 INFO L793 eck$LassoCheckResult]: Loop: 106392#L803-2 assume !false; 108556#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 107063#L489 assume !false; 108555#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 108554#L386 assume !(0 == ~m_st~0); 108551#L390 assume !(0 == ~t1_st~0); 108552#L394 assume !(0 == ~t2_st~0); 108553#L398 assume !(0 == ~t3_st~0); 108549#L402 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 108550#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 108338#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 108339#L428 assume !(0 != eval_~tmp~0#1); 108761#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 108759#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 108757#L514-3 assume !(0 == ~M_E~0); 108755#L514-5 assume !(0 == ~T1_E~0); 108753#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 108751#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 108749#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 108747#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 108745#L539-3 assume !(0 == ~E_1~0); 108743#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 108741#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 108739#L554-3 assume !(0 == ~E_4~0); 108737#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 108735#L250-18 assume !(1 == ~m_pc~0); 108733#L250-20 is_master_triggered_~__retres1~0#1 := 0; 108731#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 108729#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 108727#L637-18 assume !(0 != activate_threads_~tmp~1#1); 108725#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 108722#L269-18 assume !(1 == ~t1_pc~0); 108717#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 108714#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 108711#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 108707#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 108704#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 108701#L288-18 assume !(1 == ~t2_pc~0); 108488#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 108697#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 108694#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 108691#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 108689#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 108686#L307-18 assume 1 == ~t3_pc~0; 108683#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 108678#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 108675#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 108672#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 108668#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 108664#L326-18 assume !(1 == ~t4_pc~0); 108660#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 108656#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 108652#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 108648#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 108644#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 108640#L572-3 assume !(1 == ~M_E~0); 108635#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 108631#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 108628#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 108619#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 108615#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 108611#L597-3 assume !(1 == ~E_1~0); 108607#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 108603#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 108599#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 108596#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 108586#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 108579#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 108336#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 108337#L822 assume !(0 == start_simulation_~tmp~3#1); 108568#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 108563#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 108562#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 108561#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 108560#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 108559#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 108558#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 108557#L835 assume !(0 != start_simulation_~tmp___0~1#1); 106392#L803-2 [2021-12-07 00:18:31,643 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:31,643 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 3 times [2021-12-07 00:18:31,643 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:31,643 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [434136041] [2021-12-07 00:18:31,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:31,643 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:31,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:18:31,652 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 00:18:31,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:18:31,669 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 00:18:31,670 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:31,670 INFO L85 PathProgramCache]: Analyzing trace with hash -1274127705, now seen corresponding path program 1 times [2021-12-07 00:18:31,670 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:31,670 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [449068634] [2021-12-07 00:18:31,670 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:31,670 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:31,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:18:31,690 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:18:31,690 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:18:31,690 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [449068634] [2021-12-07 00:18:31,691 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [449068634] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:18:31,691 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:18:31,691 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:18:31,691 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [752591303] [2021-12-07 00:18:31,691 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:18:31,691 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:18:31,691 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:18:31,691 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:18:31,691 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:18:31,692 INFO L87 Difference]: Start difference. First operand 4648 states and 6425 transitions. cyclomatic complexity: 1781 Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 3 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:31,739 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:18:31,740 INFO L93 Difference]: Finished difference Result 7304 states and 9945 transitions. [2021-12-07 00:18:31,740 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:18:31,740 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7304 states and 9945 transitions. [2021-12-07 00:18:31,764 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 7206 [2021-12-07 00:18:31,782 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7304 states to 7304 states and 9945 transitions. [2021-12-07 00:18:31,783 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7304 [2021-12-07 00:18:31,787 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7304 [2021-12-07 00:18:31,787 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7304 states and 9945 transitions. [2021-12-07 00:18:31,791 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:18:31,791 INFO L681 BuchiCegarLoop]: Abstraction has 7304 states and 9945 transitions. [2021-12-07 00:18:31,795 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7304 states and 9945 transitions. [2021-12-07 00:18:31,846 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7304 to 7048. [2021-12-07 00:18:31,853 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7048 states, 7048 states have (on average 1.3633654937570943) internal successors, (9609), 7047 states have internal predecessors, (9609), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:31,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7048 states to 7048 states and 9609 transitions. [2021-12-07 00:18:31,868 INFO L704 BuchiCegarLoop]: Abstraction has 7048 states and 9609 transitions. [2021-12-07 00:18:31,868 INFO L587 BuchiCegarLoop]: Abstraction has 7048 states and 9609 transitions. [2021-12-07 00:18:31,868 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-07 00:18:31,868 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7048 states and 9609 transitions. [2021-12-07 00:18:31,885 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 6950 [2021-12-07 00:18:31,885 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:18:31,886 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:18:31,886 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:31,886 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:31,886 INFO L791 eck$LassoCheckResult]: Stem: 118648#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 118616#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 118503#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 118242#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 118243#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 118296#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 118578#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 118248#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 118249#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 118373#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 118278#L514 assume !(0 == ~M_E~0); 118279#L514-2 assume !(0 == ~T1_E~0); 118595#L519-1 assume !(0 == ~T2_E~0); 118232#L524-1 assume !(0 == ~T3_E~0); 118233#L529-1 assume !(0 == ~T4_E~0); 118348#L534-1 assume !(0 == ~E_M~0); 118555#L539-1 assume !(0 == ~E_1~0); 118556#L544-1 assume !(0 == ~E_2~0); 118575#L549-1 assume !(0 == ~E_3~0); 118576#L554-1 assume !(0 == ~E_4~0); 118227#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 118228#L250 assume !(1 == ~m_pc~0); 118447#L250-2 is_master_triggered_~__retres1~0#1 := 0; 118581#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 118409#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 118410#L637 assume !(0 != activate_threads_~tmp~1#1); 118236#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 118237#L269 assume !(1 == ~t1_pc~0); 118173#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 118343#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 118369#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 118370#L645 assume !(0 != activate_threads_~tmp___0~0#1); 118406#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 118407#L288 assume !(1 == ~t2_pc~0); 118400#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 118401#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 118421#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 118422#L653 assume !(0 != activate_threads_~tmp___1~0#1); 118547#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 118435#L307 assume !(1 == ~t3_pc~0); 118362#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 118363#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 118492#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 118586#L661 assume !(0 != activate_threads_~tmp___2~0#1); 118380#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 118381#L326 assume !(1 == ~t4_pc~0); 118186#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 118187#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 118433#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 118554#L669 assume !(0 != activate_threads_~tmp___3~0#1); 118551#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 118552#L572 assume !(1 == ~M_E~0); 118582#L572-2 assume !(1 == ~T1_E~0); 118244#L577-1 assume !(1 == ~T2_E~0); 118245#L582-1 assume !(1 == ~T3_E~0); 118534#L587-1 assume !(1 == ~T4_E~0); 118542#L592-1 assume !(1 == ~E_M~0); 118184#L597-1 assume !(1 == ~E_1~0); 118185#L602-1 assume !(1 == ~E_2~0); 118397#L607-1 assume !(1 == ~E_3~0); 118398#L612-1 assume !(1 == ~E_4~0); 118346#L617-1 assume { :end_inline_reset_delta_events } true; 118347#L803-2 assume !false; 119409#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 119410#L489 [2021-12-07 00:18:31,887 INFO L793 eck$LassoCheckResult]: Loop: 119410#L489 assume !false; 119374#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 119375#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 119736#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 119728#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 119720#L428 assume 0 != eval_~tmp~0#1; 119715#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 119710#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 119700#L433 assume !(0 == ~t1_st~0); 119693#L447 assume !(0 == ~t2_st~0); 119689#L461 assume !(0 == ~t3_st~0); 119413#L475 assume !(0 == ~t4_st~0); 119410#L489 [2021-12-07 00:18:31,887 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:31,887 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 1 times [2021-12-07 00:18:31,887 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:31,887 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [339656330] [2021-12-07 00:18:31,887 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:31,887 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:31,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:18:31,895 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 00:18:31,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:18:31,911 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 00:18:31,912 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:31,912 INFO L85 PathProgramCache]: Analyzing trace with hash 1577382650, now seen corresponding path program 1 times [2021-12-07 00:18:31,912 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:31,912 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [414432921] [2021-12-07 00:18:31,912 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:31,912 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:31,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:18:31,915 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 00:18:31,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:18:31,919 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 00:18:31,920 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:31,920 INFO L85 PathProgramCache]: Analyzing trace with hash 189250340, now seen corresponding path program 1 times [2021-12-07 00:18:31,920 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:31,920 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1406957934] [2021-12-07 00:18:31,920 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:31,921 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:31,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:18:31,943 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:18:31,944 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:18:31,944 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1406957934] [2021-12-07 00:18:31,944 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1406957934] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:18:31,944 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:18:31,944 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:18:31,944 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [913496921] [2021-12-07 00:18:31,945 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:18:32,002 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:18:32,003 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:18:32,003 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:18:32,003 INFO L87 Difference]: Start difference. First operand 7048 states and 9609 transitions. cyclomatic complexity: 2567 Second operand has 3 states, 3 states have (on average 25.333333333333332) internal successors, (76), 3 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:32,060 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:18:32,060 INFO L93 Difference]: Finished difference Result 11326 states and 15303 transitions. [2021-12-07 00:18:32,061 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:18:32,061 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11326 states and 15303 transitions. [2021-12-07 00:18:32,113 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 11136 [2021-12-07 00:18:32,142 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11326 states to 11326 states and 15303 transitions. [2021-12-07 00:18:32,142 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11326 [2021-12-07 00:18:32,148 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11326 [2021-12-07 00:18:32,148 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11326 states and 15303 transitions. [2021-12-07 00:18:32,155 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:18:32,155 INFO L681 BuchiCegarLoop]: Abstraction has 11326 states and 15303 transitions. [2021-12-07 00:18:32,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11326 states and 15303 transitions. [2021-12-07 00:18:32,254 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11326 to 11326. [2021-12-07 00:18:32,264 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11326 states, 11326 states have (on average 1.3511389722761786) internal successors, (15303), 11325 states have internal predecessors, (15303), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:32,286 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11326 states to 11326 states and 15303 transitions. [2021-12-07 00:18:32,286 INFO L704 BuchiCegarLoop]: Abstraction has 11326 states and 15303 transitions. [2021-12-07 00:18:32,286 INFO L587 BuchiCegarLoop]: Abstraction has 11326 states and 15303 transitions. [2021-12-07 00:18:32,286 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-07 00:18:32,286 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11326 states and 15303 transitions. [2021-12-07 00:18:32,311 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 11136 [2021-12-07 00:18:32,311 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:18:32,311 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:18:32,312 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:32,312 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:32,312 INFO L791 eck$LassoCheckResult]: Stem: 137106#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 137059#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 136910#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 136625#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 136626#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 136682#L353-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 136991#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 136631#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 136632#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 136762#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 136763#L514 assume !(0 == ~M_E~0); 137077#L514-2 assume !(0 == ~T1_E~0); 137078#L519-1 assume !(0 == ~T2_E~0); 136615#L524-1 assume !(0 == ~T3_E~0); 136616#L529-1 assume !(0 == ~T4_E~0); 137026#L534-1 assume !(0 == ~E_M~0); 137027#L539-1 assume !(0 == ~E_1~0); 136986#L544-1 assume !(0 == ~E_2~0); 136987#L549-1 assume !(0 == ~E_3~0); 137031#L554-1 assume !(0 == ~E_4~0); 137032#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 136844#L250 assume !(1 == ~m_pc~0); 136845#L250-2 is_master_triggered_~__retres1~0#1 := 0; 137021#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 137022#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 136993#L637 assume !(0 != activate_threads_~tmp~1#1); 136994#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 136649#L269 assume !(1 == ~t1_pc~0); 136555#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 136850#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 136851#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 137023#L645 assume !(0 != activate_threads_~tmp___0~0#1); 137024#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 136929#L288 assume !(1 == ~t2_pc~0); 136930#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 136947#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 136948#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 136955#L653 assume !(0 != activate_threads_~tmp___1~0#1); 136956#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 136828#L307 assume !(1 == ~t3_pc~0); 136829#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 136896#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 136897#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 137003#L661 assume !(0 != activate_threads_~tmp___2~0#1); 137004#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 137053#L326 assume !(1 == ~t4_pc~0); 137054#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 136825#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 136826#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 137009#L669 assume !(0 != activate_threads_~tmp___3~0#1); 137010#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 136999#L572 assume !(1 == ~M_E~0); 137000#L572-2 assume !(1 == ~T1_E~0); 137525#L577-1 assume !(1 == ~T2_E~0); 137524#L582-1 assume !(1 == ~T3_E~0); 136949#L587-1 assume !(1 == ~T4_E~0); 136950#L592-1 assume !(1 == ~E_M~0); 136566#L597-1 assume !(1 == ~E_1~0); 136567#L602-1 assume !(1 == ~E_2~0); 137501#L607-1 assume !(1 == ~E_3~0); 137097#L612-1 assume !(1 == ~E_4~0); 137098#L617-1 assume { :end_inline_reset_delta_events } true; 137486#L803-2 assume !false; 137479#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 137475#L489 [2021-12-07 00:18:32,312 INFO L793 eck$LassoCheckResult]: Loop: 137475#L489 assume !false; 137471#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 137466#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 137460#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 137457#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 137449#L428 assume 0 != eval_~tmp~0#1; 137442#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 137436#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 137430#L433 assume !(0 == ~t1_st~0); 137425#L447 assume !(0 == ~t2_st~0); 137420#L461 assume !(0 == ~t3_st~0); 137482#L475 assume !(0 == ~t4_st~0); 137475#L489 [2021-12-07 00:18:32,312 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:32,312 INFO L85 PathProgramCache]: Analyzing trace with hash 600428717, now seen corresponding path program 1 times [2021-12-07 00:18:32,312 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:32,312 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [367015041] [2021-12-07 00:18:32,312 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:32,312 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:32,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:18:32,324 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:18:32,324 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:18:32,324 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [367015041] [2021-12-07 00:18:32,324 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [367015041] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:18:32,324 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:18:32,324 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:18:32,324 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [33674123] [2021-12-07 00:18:32,324 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:18:32,324 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:18:32,325 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:32,325 INFO L85 PathProgramCache]: Analyzing trace with hash 1577382650, now seen corresponding path program 2 times [2021-12-07 00:18:32,325 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:32,325 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [616560208] [2021-12-07 00:18:32,325 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:32,325 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:32,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:18:32,327 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 00:18:32,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:18:32,329 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 00:18:32,377 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:18:32,377 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:18:32,377 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:18:32,377 INFO L87 Difference]: Start difference. First operand 11326 states and 15303 transitions. cyclomatic complexity: 3983 Second operand has 3 states, 3 states have (on average 21.333333333333332) internal successors, (64), 3 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:32,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:18:32,411 INFO L93 Difference]: Finished difference Result 11266 states and 15222 transitions. [2021-12-07 00:18:32,412 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:18:32,412 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11266 states and 15222 transitions. [2021-12-07 00:18:32,445 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 11136 [2021-12-07 00:18:32,466 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11266 states to 11266 states and 15222 transitions. [2021-12-07 00:18:32,467 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11266 [2021-12-07 00:18:32,472 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11266 [2021-12-07 00:18:32,472 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11266 states and 15222 transitions. [2021-12-07 00:18:32,477 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:18:32,477 INFO L681 BuchiCegarLoop]: Abstraction has 11266 states and 15222 transitions. [2021-12-07 00:18:32,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11266 states and 15222 transitions. [2021-12-07 00:18:32,539 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11266 to 11266. [2021-12-07 00:18:32,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11266 states, 11266 states have (on average 1.3511450381679388) internal successors, (15222), 11265 states have internal predecessors, (15222), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:32,565 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11266 states to 11266 states and 15222 transitions. [2021-12-07 00:18:32,565 INFO L704 BuchiCegarLoop]: Abstraction has 11266 states and 15222 transitions. [2021-12-07 00:18:32,565 INFO L587 BuchiCegarLoop]: Abstraction has 11266 states and 15222 transitions. [2021-12-07 00:18:32,565 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-07 00:18:32,566 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11266 states and 15222 transitions. [2021-12-07 00:18:32,590 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 11136 [2021-12-07 00:18:32,590 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:18:32,591 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:18:32,591 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:32,591 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:32,591 INFO L791 eck$LassoCheckResult]: Stem: 159657#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 159616#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 159488#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 159224#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 159225#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 159281#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 159566#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 159230#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 159231#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 159357#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 159262#L514 assume !(0 == ~M_E~0); 159263#L514-2 assume !(0 == ~T1_E~0); 159590#L519-1 assume !(0 == ~T2_E~0); 159214#L524-1 assume !(0 == ~T3_E~0); 159215#L529-1 assume !(0 == ~T4_E~0); 159334#L534-1 assume !(0 == ~E_M~0); 159538#L539-1 assume !(0 == ~E_1~0); 159539#L544-1 assume !(0 == ~E_2~0); 159564#L549-1 assume !(0 == ~E_3~0); 159565#L554-1 assume !(0 == ~E_4~0); 159209#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 159210#L250 assume !(1 == ~m_pc~0); 159429#L250-2 is_master_triggered_~__retres1~0#1 := 0; 159570#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 159394#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 159395#L637 assume !(0 != activate_threads_~tmp~1#1); 159216#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 159217#L269 assume !(1 == ~t1_pc~0); 159153#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 159329#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 159354#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 159355#L645 assume !(0 != activate_threads_~tmp___0~0#1); 159391#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 159392#L288 assume !(1 == ~t2_pc~0); 159384#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 159385#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 159405#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 159406#L653 assume !(0 != activate_threads_~tmp___1~0#1); 159532#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 159418#L307 assume !(1 == ~t3_pc~0); 159347#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 159348#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 159472#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 159574#L661 assume !(0 != activate_threads_~tmp___2~0#1); 159365#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 159366#L326 assume !(1 == ~t4_pc~0); 159168#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 159169#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 159414#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 159537#L669 assume !(0 != activate_threads_~tmp___3~0#1); 159534#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 159535#L572 assume !(1 == ~M_E~0); 159571#L572-2 assume !(1 == ~T1_E~0); 159226#L577-1 assume !(1 == ~T2_E~0); 159227#L582-1 assume !(1 == ~T3_E~0); 159520#L587-1 assume !(1 == ~T4_E~0); 159527#L592-1 assume !(1 == ~E_M~0); 159158#L597-1 assume !(1 == ~E_1~0); 159159#L602-1 assume !(1 == ~E_2~0); 159381#L607-1 assume !(1 == ~E_3~0); 159382#L612-1 assume !(1 == ~E_4~0); 159332#L617-1 assume { :end_inline_reset_delta_events } true; 159333#L803-2 assume !false; 160047#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 160044#L489 [2021-12-07 00:18:32,591 INFO L793 eck$LassoCheckResult]: Loop: 160044#L489 assume !false; 160041#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 160035#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 160029#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 160025#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 160021#L428 assume 0 != eval_~tmp~0#1; 160014#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 160006#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 159998#L433 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 159984#L450 assume !(0 != eval_~tmp_ndt_2~0#1); 159986#L447 assume !(0 == ~t2_st~0); 159980#L461 assume !(0 == ~t3_st~0); 160050#L475 assume !(0 == ~t4_st~0); 160044#L489 [2021-12-07 00:18:32,592 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:32,592 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 2 times [2021-12-07 00:18:32,592 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:32,592 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [649915880] [2021-12-07 00:18:32,592 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:32,592 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:32,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:18:32,598 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 00:18:32,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:18:32,610 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 00:18:32,610 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:32,610 INFO L85 PathProgramCache]: Analyzing trace with hash 1507047706, now seen corresponding path program 1 times [2021-12-07 00:18:32,611 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:32,611 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2005276300] [2021-12-07 00:18:32,611 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:32,611 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:32,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:18:32,613 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 00:18:32,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:18:32,616 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 00:18:32,616 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:32,616 INFO L85 PathProgramCache]: Analyzing trace with hash 1424619056, now seen corresponding path program 1 times [2021-12-07 00:18:32,616 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:32,616 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1808165616] [2021-12-07 00:18:32,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:32,616 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:32,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:18:32,665 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:18:32,666 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:18:32,666 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1808165616] [2021-12-07 00:18:32,666 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1808165616] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:18:32,666 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:18:32,666 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:18:32,666 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1992708076] [2021-12-07 00:18:32,666 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:18:32,726 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:18:32,726 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:18:32,726 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:18:32,727 INFO L87 Difference]: Start difference. First operand 11266 states and 15222 transitions. cyclomatic complexity: 3962 Second operand has 3 states, 3 states have (on average 25.666666666666668) internal successors, (77), 3 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:32,804 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:18:32,804 INFO L93 Difference]: Finished difference Result 20858 states and 28034 transitions. [2021-12-07 00:18:32,805 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:18:32,805 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20858 states and 28034 transitions. [2021-12-07 00:18:32,869 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 20664 [2021-12-07 00:18:32,910 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20858 states to 20858 states and 28034 transitions. [2021-12-07 00:18:32,910 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20858 [2021-12-07 00:18:32,921 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20858 [2021-12-07 00:18:32,921 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20858 states and 28034 transitions. [2021-12-07 00:18:32,933 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:18:32,933 INFO L681 BuchiCegarLoop]: Abstraction has 20858 states and 28034 transitions. [2021-12-07 00:18:32,944 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20858 states and 28034 transitions. [2021-12-07 00:18:33,061 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20858 to 20368. [2021-12-07 00:18:33,074 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20368 states, 20368 states have (on average 1.3454438334642576) internal successors, (27404), 20367 states have internal predecessors, (27404), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:33,144 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20368 states to 20368 states and 27404 transitions. [2021-12-07 00:18:33,144 INFO L704 BuchiCegarLoop]: Abstraction has 20368 states and 27404 transitions. [2021-12-07 00:18:33,144 INFO L587 BuchiCegarLoop]: Abstraction has 20368 states and 27404 transitions. [2021-12-07 00:18:33,144 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-07 00:18:33,145 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20368 states and 27404 transitions. [2021-12-07 00:18:33,174 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 20174 [2021-12-07 00:18:33,174 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:18:33,174 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:18:33,175 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:33,175 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:33,175 INFO L791 eck$LassoCheckResult]: Stem: 191822#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 191771#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 191636#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 191354#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 191355#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 191414#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 191719#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 191360#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 191361#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 191493#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 191392#L514 assume !(0 == ~M_E~0); 191393#L514-2 assume !(0 == ~T1_E~0); 191743#L519-1 assume !(0 == ~T2_E~0); 191344#L524-1 assume !(0 == ~T3_E~0); 191345#L529-1 assume !(0 == ~T4_E~0); 191470#L534-1 assume !(0 == ~E_M~0); 191688#L539-1 assume !(0 == ~E_1~0); 191689#L544-1 assume !(0 == ~E_2~0); 191717#L549-1 assume !(0 == ~E_3~0); 191718#L554-1 assume !(0 == ~E_4~0); 191339#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 191340#L250 assume !(1 == ~m_pc~0); 191574#L250-2 is_master_triggered_~__retres1~0#1 := 0; 191724#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 191534#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 191535#L637 assume !(0 != activate_threads_~tmp~1#1); 191346#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 191347#L269 assume !(1 == ~t1_pc~0); 191285#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 191465#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 191490#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 191491#L645 assume !(0 != activate_threads_~tmp___0~0#1); 191531#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 191532#L288 assume !(1 == ~t2_pc~0); 191523#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 191524#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 191546#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 191547#L653 assume !(0 != activate_threads_~tmp___1~0#1); 191680#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 191559#L307 assume !(1 == ~t3_pc~0); 191483#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 191484#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 191620#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 191729#L661 assume !(0 != activate_threads_~tmp___2~0#1); 191503#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 191504#L326 assume !(1 == ~t4_pc~0); 191298#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 191299#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 191555#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 191687#L669 assume !(0 != activate_threads_~tmp___3~0#1); 191684#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 191685#L572 assume !(1 == ~M_E~0); 191725#L572-2 assume !(1 == ~T1_E~0); 191356#L577-1 assume !(1 == ~T2_E~0); 191357#L582-1 assume !(1 == ~T3_E~0); 191667#L587-1 assume !(1 == ~T4_E~0); 191675#L592-1 assume !(1 == ~E_M~0); 191290#L597-1 assume !(1 == ~E_1~0); 191291#L602-1 assume !(1 == ~E_2~0); 191520#L607-1 assume !(1 == ~E_3~0); 191521#L612-1 assume !(1 == ~E_4~0); 191468#L617-1 assume { :end_inline_reset_delta_events } true; 191469#L803-2 assume !false; 203714#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 203712#L489 [2021-12-07 00:18:33,175 INFO L793 eck$LassoCheckResult]: Loop: 203712#L489 assume !false; 203711#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 203709#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 203705#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 203701#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 203699#L428 assume 0 != eval_~tmp~0#1; 203696#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 203693#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 203691#L433 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 203676#L450 assume !(0 != eval_~tmp_ndt_2~0#1); 203689#L447 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 201691#L464 assume !(0 != eval_~tmp_ndt_3~0#1); 203721#L461 assume !(0 == ~t3_st~0); 203716#L475 assume !(0 == ~t4_st~0); 203712#L489 [2021-12-07 00:18:33,175 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:33,175 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 3 times [2021-12-07 00:18:33,175 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:33,175 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1353215072] [2021-12-07 00:18:33,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:33,176 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:33,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:18:33,181 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 00:18:33,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:18:33,191 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 00:18:33,191 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:33,191 INFO L85 PathProgramCache]: Analyzing trace with hash -530907670, now seen corresponding path program 1 times [2021-12-07 00:18:33,192 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:33,192 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1119997334] [2021-12-07 00:18:33,192 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:33,192 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:33,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:18:33,194 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 00:18:33,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:18:33,196 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 00:18:33,197 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:33,197 INFO L85 PathProgramCache]: Analyzing trace with hash 1208771476, now seen corresponding path program 1 times [2021-12-07 00:18:33,197 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:33,197 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1048086556] [2021-12-07 00:18:33,197 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:33,197 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:33,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:18:33,214 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:18:33,214 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:18:33,214 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1048086556] [2021-12-07 00:18:33,214 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1048086556] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:18:33,214 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:18:33,214 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:18:33,214 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [399716006] [2021-12-07 00:18:33,215 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:18:33,280 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:18:33,281 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:18:33,281 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:18:33,281 INFO L87 Difference]: Start difference. First operand 20368 states and 27404 transitions. cyclomatic complexity: 7042 Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 3 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:33,371 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:18:33,371 INFO L93 Difference]: Finished difference Result 35922 states and 48206 transitions. [2021-12-07 00:18:33,371 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:18:33,371 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35922 states and 48206 transitions. [2021-12-07 00:18:33,523 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 35600 [2021-12-07 00:18:33,593 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35922 states to 35922 states and 48206 transitions. [2021-12-07 00:18:33,593 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 35922 [2021-12-07 00:18:33,606 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 35922 [2021-12-07 00:18:33,606 INFO L73 IsDeterministic]: Start isDeterministic. Operand 35922 states and 48206 transitions. [2021-12-07 00:18:33,620 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:18:33,620 INFO L681 BuchiCegarLoop]: Abstraction has 35922 states and 48206 transitions. [2021-12-07 00:18:33,632 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35922 states and 48206 transitions. [2021-12-07 00:18:33,851 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35922 to 34746. [2021-12-07 00:18:33,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34746 states, 34746 states have (on average 1.347090312553963) internal successors, (46806), 34745 states have internal predecessors, (46806), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:33,993 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34746 states to 34746 states and 46806 transitions. [2021-12-07 00:18:33,993 INFO L704 BuchiCegarLoop]: Abstraction has 34746 states and 46806 transitions. [2021-12-07 00:18:33,993 INFO L587 BuchiCegarLoop]: Abstraction has 34746 states and 46806 transitions. [2021-12-07 00:18:33,993 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-07 00:18:33,993 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34746 states and 46806 transitions. [2021-12-07 00:18:34,050 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 34424 [2021-12-07 00:18:34,050 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:18:34,050 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:18:34,051 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:34,051 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:34,051 INFO L791 eck$LassoCheckResult]: Stem: 248105#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 248060#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 247926#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 247651#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 247652#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 247708#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 248007#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 247657#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 247658#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 247787#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 247689#L514 assume !(0 == ~M_E~0); 247690#L514-2 assume !(0 == ~T1_E~0); 248032#L519-1 assume !(0 == ~T2_E~0); 247641#L524-1 assume !(0 == ~T3_E~0); 247642#L529-1 assume !(0 == ~T4_E~0); 247763#L534-1 assume !(0 == ~E_M~0); 247977#L539-1 assume !(0 == ~E_1~0); 247978#L544-1 assume !(0 == ~E_2~0); 248005#L549-1 assume !(0 == ~E_3~0); 248006#L554-1 assume !(0 == ~E_4~0); 247636#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 247637#L250 assume !(1 == ~m_pc~0); 247867#L250-2 is_master_triggered_~__retres1~0#1 := 0; 248012#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 247827#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 247828#L637 assume !(0 != activate_threads_~tmp~1#1); 247643#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 247644#L269 assume !(1 == ~t1_pc~0); 247582#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 247758#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 247784#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 247785#L645 assume !(0 != activate_threads_~tmp___0~0#1); 247824#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 247825#L288 assume !(1 == ~t2_pc~0); 247819#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 247820#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 247839#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 247840#L653 assume !(0 != activate_threads_~tmp___1~0#1); 247970#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 247852#L307 assume !(1 == ~t3_pc~0); 247777#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 247778#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 247913#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 248017#L661 assume !(0 != activate_threads_~tmp___2~0#1); 247797#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 247798#L326 assume !(1 == ~t4_pc~0); 247595#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 247596#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 247848#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 247976#L669 assume !(0 != activate_threads_~tmp___3~0#1); 247973#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 247974#L572 assume !(1 == ~M_E~0); 248013#L572-2 assume !(1 == ~T1_E~0); 247653#L577-1 assume !(1 == ~T2_E~0); 247654#L582-1 assume !(1 == ~T3_E~0); 247956#L587-1 assume !(1 == ~T4_E~0); 247964#L592-1 assume !(1 == ~E_M~0); 247587#L597-1 assume !(1 == ~E_1~0); 247588#L602-1 assume !(1 == ~E_2~0); 247816#L607-1 assume !(1 == ~E_3~0); 247817#L612-1 assume !(1 == ~E_4~0); 247761#L617-1 assume { :end_inline_reset_delta_events } true; 247762#L803-2 assume !false; 258328#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 258169#L489 [2021-12-07 00:18:34,051 INFO L793 eck$LassoCheckResult]: Loop: 258169#L489 assume !false; 258326#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 258321#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 258319#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 258315#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 258313#L428 assume 0 != eval_~tmp~0#1; 258311#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 258309#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 255773#L433 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 255770#L450 assume !(0 != eval_~tmp_ndt_2~0#1); 255154#L447 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 255151#L464 assume !(0 != eval_~tmp_ndt_3~0#1); 255152#L461 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 258172#L478 assume !(0 != eval_~tmp_ndt_4~0#1); 258170#L475 assume !(0 == ~t4_st~0); 258169#L489 [2021-12-07 00:18:34,052 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:34,052 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 4 times [2021-12-07 00:18:34,052 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:34,052 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [240342145] [2021-12-07 00:18:34,052 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:34,052 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:34,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:18:34,059 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 00:18:34,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:18:34,073 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 00:18:34,073 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:34,073 INFO L85 PathProgramCache]: Analyzing trace with hash 721579562, now seen corresponding path program 1 times [2021-12-07 00:18:34,073 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:34,073 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [197515836] [2021-12-07 00:18:34,073 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:34,073 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:34,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:18:34,076 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 00:18:34,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:18:34,079 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 00:18:34,079 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:34,079 INFO L85 PathProgramCache]: Analyzing trace with hash -1182941760, now seen corresponding path program 1 times [2021-12-07 00:18:34,080 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:34,080 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1080011503] [2021-12-07 00:18:34,080 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:34,080 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:34,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:18:34,096 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:18:34,096 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:18:34,096 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1080011503] [2021-12-07 00:18:34,096 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1080011503] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:18:34,096 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:18:34,096 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-07 00:18:34,096 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1489564161] [2021-12-07 00:18:34,096 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:18:34,169 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:18:34,170 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:18:34,170 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:18:34,170 INFO L87 Difference]: Start difference. First operand 34746 states and 46806 transitions. cyclomatic complexity: 12066 Second operand has 3 states, 2 states have (on average 39.5) internal successors, (79), 3 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:34,302 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:18:34,303 INFO L93 Difference]: Finished difference Result 39504 states and 52956 transitions. [2021-12-07 00:18:34,303 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:18:34,303 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39504 states and 52956 transitions. [2021-12-07 00:18:34,424 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 39262 [2021-12-07 00:18:34,504 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39504 states to 39504 states and 52956 transitions. [2021-12-07 00:18:34,504 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39504 [2021-12-07 00:18:34,521 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39504 [2021-12-07 00:18:34,521 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39504 states and 52956 transitions. [2021-12-07 00:18:34,537 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:18:34,537 INFO L681 BuchiCegarLoop]: Abstraction has 39504 states and 52956 transitions. [2021-12-07 00:18:34,552 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39504 states and 52956 transitions. [2021-12-07 00:18:34,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39504 to 39056. [2021-12-07 00:18:34,826 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39056 states, 39056 states have (on average 1.3444285129045472) internal successors, (52508), 39055 states have internal predecessors, (52508), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:18:34,892 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39056 states to 39056 states and 52508 transitions. [2021-12-07 00:18:34,892 INFO L704 BuchiCegarLoop]: Abstraction has 39056 states and 52508 transitions. [2021-12-07 00:18:34,892 INFO L587 BuchiCegarLoop]: Abstraction has 39056 states and 52508 transitions. [2021-12-07 00:18:34,892 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-07 00:18:34,892 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39056 states and 52508 transitions. [2021-12-07 00:18:35,029 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 38814 [2021-12-07 00:18:35,030 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:18:35,030 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:18:35,030 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:35,030 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:18:35,031 INFO L791 eck$LassoCheckResult]: Stem: 322390#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 322334#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 322184#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 321910#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 321911#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 321965#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 322274#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 321916#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 321917#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 322045#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 321946#L514 assume !(0 == ~M_E~0); 321947#L514-2 assume !(0 == ~T1_E~0); 322306#L519-1 assume !(0 == ~T2_E~0); 321900#L524-1 assume !(0 == ~T3_E~0); 321901#L529-1 assume !(0 == ~T4_E~0); 322020#L534-1 assume !(0 == ~E_M~0); 322238#L539-1 assume !(0 == ~E_1~0); 322239#L544-1 assume !(0 == ~E_2~0); 322272#L549-1 assume !(0 == ~E_3~0); 322273#L554-1 assume !(0 == ~E_4~0); 321895#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 321896#L250 assume !(1 == ~m_pc~0); 322124#L250-2 is_master_triggered_~__retres1~0#1 := 0; 322279#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 322085#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 322086#L637 assume !(0 != activate_threads_~tmp~1#1); 321902#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 321903#L269 assume !(1 == ~t1_pc~0); 321841#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 322015#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 322042#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 322043#L645 assume !(0 != activate_threads_~tmp___0~0#1); 322082#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 322083#L288 assume !(1 == ~t2_pc~0); 322077#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 322078#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 322096#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 322097#L653 assume !(0 != activate_threads_~tmp___1~0#1); 322231#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 322109#L307 assume !(1 == ~t3_pc~0); 322035#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 322036#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 322170#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 322285#L661 assume !(0 != activate_threads_~tmp___2~0#1); 322054#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 322055#L326 assume !(1 == ~t4_pc~0); 321854#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 321855#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 322105#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 322237#L669 assume !(0 != activate_threads_~tmp___3~0#1); 322234#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 322235#L572 assume !(1 == ~M_E~0); 322280#L572-2 assume !(1 == ~T1_E~0); 321912#L577-1 assume !(1 == ~T2_E~0); 321913#L582-1 assume !(1 == ~T3_E~0); 322218#L587-1 assume !(1 == ~T4_E~0); 322226#L592-1 assume !(1 == ~E_M~0); 321846#L597-1 assume !(1 == ~E_1~0); 321847#L602-1 assume !(1 == ~E_2~0); 322074#L607-1 assume !(1 == ~E_3~0); 322075#L612-1 assume !(1 == ~E_4~0); 322018#L617-1 assume { :end_inline_reset_delta_events } true; 322019#L803-2 assume !false; 332411#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 331493#L489 [2021-12-07 00:18:35,031 INFO L793 eck$LassoCheckResult]: Loop: 331493#L489 assume !false; 332406#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 332388#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 332390#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 332371#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 332372#L428 assume 0 != eval_~tmp~0#1; 332353#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 332354#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 332337#L433 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 332335#L450 assume !(0 != eval_~tmp_ndt_2~0#1); 332298#L447 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 332294#L464 assume !(0 != eval_~tmp_ndt_3~0#1); 332268#L461 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 331499#L478 assume !(0 != eval_~tmp_ndt_4~0#1); 331501#L475 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 331492#L492 assume !(0 != eval_~tmp_ndt_5~0#1); 331493#L489 [2021-12-07 00:18:35,031 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:35,031 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 5 times [2021-12-07 00:18:35,031 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:35,031 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [373602004] [2021-12-07 00:18:35,032 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:35,032 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:35,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:18:35,039 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 00:18:35,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:18:35,055 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 00:18:35,055 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:35,055 INFO L85 PathProgramCache]: Analyzing trace with hash 894126298, now seen corresponding path program 1 times [2021-12-07 00:18:35,055 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:35,056 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1106590950] [2021-12-07 00:18:35,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:35,056 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:35,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:18:35,058 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 00:18:35,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:18:35,061 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 00:18:35,061 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:18:35,061 INFO L85 PathProgramCache]: Analyzing trace with hash 1983507460, now seen corresponding path program 1 times [2021-12-07 00:18:35,061 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:18:35,061 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1536841276] [2021-12-07 00:18:35,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:18:35,061 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:18:35,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:18:35,066 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 00:18:35,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:18:35,081 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 00:18:35,855 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 07.12 12:18:35 BoogieIcfgContainer [2021-12-07 00:18:35,856 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-12-07 00:18:35,856 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-12-07 00:18:35,856 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-12-07 00:18:35,856 INFO L275 PluginConnector]: Witness Printer initialized [2021-12-07 00:18:35,856 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 12:18:27" (3/4) ... [2021-12-07 00:18:35,858 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-12-07 00:18:35,905 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_243d7bef-cedc-44de-a9bb-da9fc6938811/bin/uautomizer-DrprNOufMa/witness.graphml [2021-12-07 00:18:35,905 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-12-07 00:18:35,906 INFO L158 Benchmark]: Toolchain (without parser) took 9103.93ms. Allocated memory was 138.4MB in the beginning and 926.9MB in the end (delta: 788.5MB). Free memory was 102.6MB in the beginning and 300.2MB in the end (delta: -197.6MB). Peak memory consumption was 590.5MB. Max. memory is 16.1GB. [2021-12-07 00:18:35,906 INFO L158 Benchmark]: CDTParser took 0.13ms. Allocated memory is still 138.4MB. Free memory is still 119.2MB. There was no memory consumed. Max. memory is 16.1GB. [2021-12-07 00:18:35,906 INFO L158 Benchmark]: CACSL2BoogieTranslator took 238.19ms. Allocated memory is still 138.4MB. Free memory was 102.3MB in the beginning and 111.0MB in the end (delta: -8.7MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2021-12-07 00:18:35,906 INFO L158 Benchmark]: Boogie Procedure Inliner took 44.78ms. Allocated memory is still 138.4MB. Free memory was 111.0MB in the beginning and 106.8MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-07 00:18:35,907 INFO L158 Benchmark]: Boogie Preprocessor took 45.47ms. Allocated memory is still 138.4MB. Free memory was 106.8MB in the beginning and 103.3MB in the end (delta: 3.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-07 00:18:35,907 INFO L158 Benchmark]: RCFGBuilder took 686.70ms. Allocated memory is still 138.4MB. Free memory was 103.3MB in the beginning and 64.9MB in the end (delta: 38.4MB). Peak memory consumption was 37.7MB. Max. memory is 16.1GB. [2021-12-07 00:18:35,907 INFO L158 Benchmark]: BuchiAutomizer took 8035.64ms. Allocated memory was 138.4MB in the beginning and 926.9MB in the end (delta: 788.5MB). Free memory was 64.9MB in the beginning and 303.4MB in the end (delta: -238.5MB). Peak memory consumption was 553.0MB. Max. memory is 16.1GB. [2021-12-07 00:18:35,908 INFO L158 Benchmark]: Witness Printer took 49.16ms. Allocated memory is still 926.9MB. Free memory was 303.4MB in the beginning and 300.2MB in the end (delta: 3.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-12-07 00:18:35,909 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.13ms. Allocated memory is still 138.4MB. Free memory is still 119.2MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 238.19ms. Allocated memory is still 138.4MB. Free memory was 102.3MB in the beginning and 111.0MB in the end (delta: -8.7MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 44.78ms. Allocated memory is still 138.4MB. Free memory was 111.0MB in the beginning and 106.8MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 45.47ms. Allocated memory is still 138.4MB. Free memory was 106.8MB in the beginning and 103.3MB in the end (delta: 3.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 686.70ms. Allocated memory is still 138.4MB. Free memory was 103.3MB in the beginning and 64.9MB in the end (delta: 38.4MB). Peak memory consumption was 37.7MB. Max. memory is 16.1GB. * BuchiAutomizer took 8035.64ms. Allocated memory was 138.4MB in the beginning and 926.9MB in the end (delta: 788.5MB). Free memory was 64.9MB in the beginning and 303.4MB in the end (delta: -238.5MB). Peak memory consumption was 553.0MB. Max. memory is 16.1GB. * Witness Printer took 49.16ms. Allocated memory is still 926.9MB. Free memory was 303.4MB in the beginning and 300.2MB in the end (delta: 3.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 21 terminating modules (21 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.21 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 39056 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 7.9s and 22 iterations. TraceHistogramMax:1. Analysis of lassos took 2.4s. Construction of modules took 0.4s. Büchi inclusion checks took 1.0s. Highest rank in rank-based complementation 0. Minimization of det autom 21. Minimization of nondet autom 0. Automata minimization 2.0s AutomataMinimizationTime, 21 MinimizatonAttempts, 22983 StatesRemovedByMinimization, 14 NontrivialMinimizations. Non-live state removal took 1.2s Buchi closure took 0.1s. Biggest automaton had 39056 states and ocurred in iteration 21. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 17825 SdHoareTripleChecker+Valid, 0.6s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 17825 mSDsluCounter, 29348 SdHoareTripleChecker+Invalid, 0.5s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 14532 mSDsCounter, 253 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 693 IncrementalHoareTripleChecker+Invalid, 946 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 253 mSolverCounterUnsat, 14816 mSDtfsCounter, 693 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc4 concLT0 SILN1 SILU0 SILI13 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 423]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {tmp_ndt_3=0, NULL=0, t3_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@47cb1011=0, token=0, NULL=1, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5ba897fa=0, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6eb7e0bf=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@41a33064=0, tmp_ndt_2=0, t4_i=1, \result=0, E_3=2, t4_pc=0, E_1=2, tmp_ndt_1=0, __retres1=1, tmp=1, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@68af99cc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@22c03f08=0, m_st=0, NULL=0, t3_pc=0, tmp___3=0, __retres1=0, tmp___0=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@c8d63da=0, tmp___2=0, m_pc=0, \result=0, \result=1, \result=0, \result=0, tmp___1=0, __retres1=0, T2_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1e66478c=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5822b822=0, tmp=0, t1_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@14ea4a82=0, E_2=2, tmp___0=0, E_4=2, T1_E=2, __retres1=0, M_E=2, t2_i=1, T4_E=2, \result=0, t3_i=1, t4_st=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1547122d=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3c801bee=0, t1_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7249bbcd=0, __retres1=0, local=0, t2_pc=0, tmp_ndt_5=0, __retres1=0, tmp_ndt_4=0, E_M=2, kernel_st=1, T3_E=2, t1_i=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 423]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int m_i ; [L35] int t1_i ; [L36] int t2_i ; [L37] int t3_i ; [L38] int t4_i ; [L39] int M_E = 2; [L40] int T1_E = 2; [L41] int T2_E = 2; [L42] int T3_E = 2; [L43] int T4_E = 2; [L44] int E_M = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; [L55] int token ; [L57] int local ; [L848] int __retres1 ; [L852] CALL init_model() [L760] m_i = 1 [L761] t1_i = 1 [L762] t2_i = 1 [L763] t3_i = 1 [L764] t4_i = 1 [L852] RET init_model() [L853] CALL start_simulation() [L789] int kernel_st ; [L790] int tmp ; [L791] int tmp___0 ; [L795] kernel_st = 0 [L796] FCALL update_channels() [L797] CALL init_threads() [L353] COND TRUE m_i == 1 [L354] m_st = 0 [L358] COND TRUE t1_i == 1 [L359] t1_st = 0 [L363] COND TRUE t2_i == 1 [L364] t2_st = 0 [L368] COND TRUE t3_i == 1 [L369] t3_st = 0 [L373] COND TRUE t4_i == 1 [L374] t4_st = 0 [L797] RET init_threads() [L798] CALL fire_delta_events() [L514] COND FALSE !(M_E == 0) [L519] COND FALSE !(T1_E == 0) [L524] COND FALSE !(T2_E == 0) [L529] COND FALSE !(T3_E == 0) [L534] COND FALSE !(T4_E == 0) [L539] COND FALSE !(E_M == 0) [L544] COND FALSE !(E_1 == 0) [L549] COND FALSE !(E_2 == 0) [L554] COND FALSE !(E_3 == 0) [L559] COND FALSE !(E_4 == 0) [L798] RET fire_delta_events() [L799] CALL activate_threads() [L627] int tmp ; [L628] int tmp___0 ; [L629] int tmp___1 ; [L630] int tmp___2 ; [L631] int tmp___3 ; [L635] CALL, EXPR is_master_triggered() [L247] int __retres1 ; [L250] COND FALSE !(m_pc == 1) [L260] __retres1 = 0 [L262] return (__retres1); [L635] RET, EXPR is_master_triggered() [L635] tmp = is_master_triggered() [L637] COND FALSE !(\read(tmp)) [L643] CALL, EXPR is_transmit1_triggered() [L266] int __retres1 ; [L269] COND FALSE !(t1_pc == 1) [L279] __retres1 = 0 [L281] return (__retres1); [L643] RET, EXPR is_transmit1_triggered() [L643] tmp___0 = is_transmit1_triggered() [L645] COND FALSE !(\read(tmp___0)) [L651] CALL, EXPR is_transmit2_triggered() [L285] int __retres1 ; [L288] COND FALSE !(t2_pc == 1) [L298] __retres1 = 0 [L300] return (__retres1); [L651] RET, EXPR is_transmit2_triggered() [L651] tmp___1 = is_transmit2_triggered() [L653] COND FALSE !(\read(tmp___1)) [L659] CALL, EXPR is_transmit3_triggered() [L304] int __retres1 ; [L307] COND FALSE !(t3_pc == 1) [L317] __retres1 = 0 [L319] return (__retres1); [L659] RET, EXPR is_transmit3_triggered() [L659] tmp___2 = is_transmit3_triggered() [L661] COND FALSE !(\read(tmp___2)) [L667] CALL, EXPR is_transmit4_triggered() [L323] int __retres1 ; [L326] COND FALSE !(t4_pc == 1) [L336] __retres1 = 0 [L338] return (__retres1); [L667] RET, EXPR is_transmit4_triggered() [L667] tmp___3 = is_transmit4_triggered() [L669] COND FALSE !(\read(tmp___3)) [L799] RET activate_threads() [L800] CALL reset_delta_events() [L572] COND FALSE !(M_E == 1) [L577] COND FALSE !(T1_E == 1) [L582] COND FALSE !(T2_E == 1) [L587] COND FALSE !(T3_E == 1) [L592] COND FALSE !(T4_E == 1) [L597] COND FALSE !(E_M == 1) [L602] COND FALSE !(E_1 == 1) [L607] COND FALSE !(E_2 == 1) [L612] COND FALSE !(E_3 == 1) [L617] COND FALSE !(E_4 == 1) [L800] RET reset_delta_events() [L803] COND TRUE 1 [L806] kernel_st = 1 [L807] CALL eval() [L419] int tmp ; Loop: [L423] COND TRUE 1 [L426] CALL, EXPR exists_runnable_thread() [L383] int __retres1 ; [L386] COND TRUE m_st == 0 [L387] __retres1 = 1 [L414] return (__retres1); [L426] RET, EXPR exists_runnable_thread() [L426] tmp = exists_runnable_thread() [L428] COND TRUE \read(tmp) [L433] COND TRUE m_st == 0 [L434] int tmp_ndt_1; [L435] tmp_ndt_1 = __VERIFIER_nondet_int() [L436] COND FALSE !(\read(tmp_ndt_1)) [L447] COND TRUE t1_st == 0 [L448] int tmp_ndt_2; [L449] tmp_ndt_2 = __VERIFIER_nondet_int() [L450] COND FALSE !(\read(tmp_ndt_2)) [L461] COND TRUE t2_st == 0 [L462] int tmp_ndt_3; [L463] tmp_ndt_3 = __VERIFIER_nondet_int() [L464] COND FALSE !(\read(tmp_ndt_3)) [L475] COND TRUE t3_st == 0 [L476] int tmp_ndt_4; [L477] tmp_ndt_4 = __VERIFIER_nondet_int() [L478] COND FALSE !(\read(tmp_ndt_4)) [L489] COND TRUE t4_st == 0 [L490] int tmp_ndt_5; [L491] tmp_ndt_5 = __VERIFIER_nondet_int() [L492] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-12-07 00:18:35,949 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_243d7bef-cedc-44de-a9bb-da9fc6938811/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)