./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.04.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 839c364b Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5b09e43-d5a2-457e-befc-0eb09998c173/bin/uautomizer-DrprNOufMa/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5b09e43-d5a2-457e-befc-0eb09998c173/bin/uautomizer-DrprNOufMa/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5b09e43-d5a2-457e-befc-0eb09998c173/bin/uautomizer-DrprNOufMa/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5b09e43-d5a2-457e-befc-0eb09998c173/bin/uautomizer-DrprNOufMa/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.04.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5b09e43-d5a2-457e-befc-0eb09998c173/bin/uautomizer-DrprNOufMa/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5b09e43-d5a2-457e-befc-0eb09998c173/bin/uautomizer-DrprNOufMa --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 05d3b7d21cc48825b4a0189c75f03d768acc6241312029d3e223c1b9b2a509ea --- Real Ultimate output --- This is Ultimate 0.2.2-hotfix-svcomp22-839c364 [2021-12-06 17:16:05,674 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-06 17:16:05,676 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-06 17:16:05,706 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-06 17:16:05,706 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-06 17:16:05,708 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-06 17:16:05,709 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-06 17:16:05,712 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-06 17:16:05,714 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-06 17:16:05,715 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-06 17:16:05,716 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-06 17:16:05,717 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-06 17:16:05,717 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-06 17:16:05,719 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-06 17:16:05,720 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-06 17:16:05,721 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-06 17:16:05,722 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-06 17:16:05,723 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-06 17:16:05,726 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-06 17:16:05,728 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-06 17:16:05,730 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-06 17:16:05,732 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-06 17:16:05,733 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-06 17:16:05,734 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-06 17:16:05,737 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-06 17:16:05,738 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-06 17:16:05,738 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-06 17:16:05,739 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-06 17:16:05,740 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-06 17:16:05,741 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-06 17:16:05,741 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-06 17:16:05,742 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-06 17:16:05,743 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-06 17:16:05,744 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-06 17:16:05,745 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-06 17:16:05,745 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-06 17:16:05,746 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-06 17:16:05,746 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-06 17:16:05,746 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-06 17:16:05,747 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-06 17:16:05,747 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-06 17:16:05,748 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5b09e43-d5a2-457e-befc-0eb09998c173/bin/uautomizer-DrprNOufMa/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-06 17:16:05,767 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-06 17:16:05,767 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-06 17:16:05,767 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-06 17:16:05,767 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-06 17:16:05,768 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-06 17:16:05,768 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-06 17:16:05,769 INFO L138 SettingsManager]: * Use SBE=true [2021-12-06 17:16:05,769 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-06 17:16:05,769 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-06 17:16:05,769 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-06 17:16:05,769 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-06 17:16:05,769 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-06 17:16:05,769 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-06 17:16:05,770 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-06 17:16:05,770 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-06 17:16:05,770 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-06 17:16:05,770 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-06 17:16:05,770 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-06 17:16:05,770 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-06 17:16:05,770 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-06 17:16:05,770 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-06 17:16:05,771 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-06 17:16:05,771 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-06 17:16:05,771 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-06 17:16:05,771 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-06 17:16:05,771 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-06 17:16:05,771 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-06 17:16:05,771 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-06 17:16:05,772 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-06 17:16:05,772 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-06 17:16:05,772 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-06 17:16:05,772 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-06 17:16:05,773 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-06 17:16:05,773 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5b09e43-d5a2-457e-befc-0eb09998c173/bin/uautomizer-DrprNOufMa/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5b09e43-d5a2-457e-befc-0eb09998c173/bin/uautomizer-DrprNOufMa Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 05d3b7d21cc48825b4a0189c75f03d768acc6241312029d3e223c1b9b2a509ea [2021-12-06 17:16:05,943 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-06 17:16:05,960 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-06 17:16:05,962 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-06 17:16:05,963 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-06 17:16:05,963 INFO L275 PluginConnector]: CDTParser initialized [2021-12-06 17:16:05,964 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5b09e43-d5a2-457e-befc-0eb09998c173/bin/uautomizer-DrprNOufMa/../../sv-benchmarks/c/systemc/token_ring.04.cil-2.c [2021-12-06 17:16:06,004 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5b09e43-d5a2-457e-befc-0eb09998c173/bin/uautomizer-DrprNOufMa/data/b8a383c07/9498f00cc7304296a0c35f8055d60a5f/FLAG3b10e1d50 [2021-12-06 17:16:06,376 INFO L306 CDTParser]: Found 1 translation units. [2021-12-06 17:16:06,376 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5b09e43-d5a2-457e-befc-0eb09998c173/sv-benchmarks/c/systemc/token_ring.04.cil-2.c [2021-12-06 17:16:06,384 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5b09e43-d5a2-457e-befc-0eb09998c173/bin/uautomizer-DrprNOufMa/data/b8a383c07/9498f00cc7304296a0c35f8055d60a5f/FLAG3b10e1d50 [2021-12-06 17:16:06,393 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5b09e43-d5a2-457e-befc-0eb09998c173/bin/uautomizer-DrprNOufMa/data/b8a383c07/9498f00cc7304296a0c35f8055d60a5f [2021-12-06 17:16:06,395 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-06 17:16:06,396 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-06 17:16:06,397 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-06 17:16:06,397 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-06 17:16:06,400 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-06 17:16:06,401 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 05:16:06" (1/1) ... [2021-12-06 17:16:06,402 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@775d0504 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:06, skipping insertion in model container [2021-12-06 17:16:06,402 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 05:16:06" (1/1) ... [2021-12-06 17:16:06,408 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-06 17:16:06,442 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-06 17:16:06,557 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5b09e43-d5a2-457e-befc-0eb09998c173/sv-benchmarks/c/systemc/token_ring.04.cil-2.c[671,684] [2021-12-06 17:16:06,603 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-06 17:16:06,610 INFO L203 MainTranslator]: Completed pre-run [2021-12-06 17:16:06,619 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5b09e43-d5a2-457e-befc-0eb09998c173/sv-benchmarks/c/systemc/token_ring.04.cil-2.c[671,684] [2021-12-06 17:16:06,646 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-06 17:16:06,658 INFO L208 MainTranslator]: Completed translation [2021-12-06 17:16:06,658 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:06 WrapperNode [2021-12-06 17:16:06,659 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-06 17:16:06,659 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-06 17:16:06,659 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-06 17:16:06,660 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-06 17:16:06,665 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:06" (1/1) ... [2021-12-06 17:16:06,672 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:06" (1/1) ... [2021-12-06 17:16:06,706 INFO L137 Inliner]: procedures = 36, calls = 44, calls flagged for inlining = 39, calls inlined = 78, statements flattened = 1074 [2021-12-06 17:16:06,706 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-06 17:16:06,707 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-06 17:16:06,707 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-06 17:16:06,707 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-06 17:16:06,713 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:06" (1/1) ... [2021-12-06 17:16:06,714 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:06" (1/1) ... [2021-12-06 17:16:06,718 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:06" (1/1) ... [2021-12-06 17:16:06,719 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:06" (1/1) ... [2021-12-06 17:16:06,731 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:06" (1/1) ... [2021-12-06 17:16:06,744 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:06" (1/1) ... [2021-12-06 17:16:06,747 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:06" (1/1) ... [2021-12-06 17:16:06,753 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-06 17:16:06,754 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-06 17:16:06,754 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-06 17:16:06,754 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-06 17:16:06,755 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:06" (1/1) ... [2021-12-06 17:16:06,762 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 17:16:06,774 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5b09e43-d5a2-457e-befc-0eb09998c173/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 17:16:06,785 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5b09e43-d5a2-457e-befc-0eb09998c173/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 17:16:06,787 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5b09e43-d5a2-457e-befc-0eb09998c173/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-06 17:16:06,818 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-06 17:16:06,818 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-06 17:16:06,819 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-06 17:16:06,819 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-06 17:16:06,883 INFO L236 CfgBuilder]: Building ICFG [2021-12-06 17:16:06,884 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-06 17:16:07,423 INFO L277 CfgBuilder]: Performing block encoding [2021-12-06 17:16:07,434 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-06 17:16:07,434 INFO L301 CfgBuilder]: Removed 7 assume(true) statements. [2021-12-06 17:16:07,437 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 05:16:07 BoogieIcfgContainer [2021-12-06 17:16:07,437 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-06 17:16:07,438 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-06 17:16:07,438 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-06 17:16:07,441 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-06 17:16:07,442 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 17:16:07,442 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.12 05:16:06" (1/3) ... [2021-12-06 17:16:07,443 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6b867b42 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.12 05:16:07, skipping insertion in model container [2021-12-06 17:16:07,443 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 17:16:07,443 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:06" (2/3) ... [2021-12-06 17:16:07,443 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6b867b42 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.12 05:16:07, skipping insertion in model container [2021-12-06 17:16:07,443 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 17:16:07,444 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 05:16:07" (3/3) ... [2021-12-06 17:16:07,445 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.04.cil-2.c [2021-12-06 17:16:07,473 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-06 17:16:07,473 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-06 17:16:07,473 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-06 17:16:07,474 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-06 17:16:07,474 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-06 17:16:07,474 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-06 17:16:07,474 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-06 17:16:07,474 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-06 17:16:07,497 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 438 states, 437 states have (on average 1.5354691075514875) internal successors, (671), 437 states have internal predecessors, (671), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:07,530 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 367 [2021-12-06 17:16:07,530 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:07,530 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:07,539 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:07,539 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:07,539 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-06 17:16:07,541 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 438 states, 437 states have (on average 1.5354691075514875) internal successors, (671), 437 states have internal predecessors, (671), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:07,554 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 367 [2021-12-06 17:16:07,554 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:07,555 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:07,558 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:07,558 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:07,564 INFO L791 eck$LassoCheckResult]: Stem: 430#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 351#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 126#L778true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12#L358true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50#L365true assume !(1 == ~m_i~0);~m_st~0 := 2; 325#L365-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 229#L370-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 182#L375-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 333#L380-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 211#L385-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 191#L526true assume !(0 == ~M_E~0); 414#L526-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 232#L531-1true assume !(0 == ~T2_E~0); 180#L536-1true assume !(0 == ~T3_E~0); 287#L541-1true assume !(0 == ~T4_E~0); 178#L546-1true assume !(0 == ~E_M~0); 240#L551-1true assume !(0 == ~E_1~0); 161#L556-1true assume !(0 == ~E_2~0); 189#L561-1true assume !(0 == ~E_3~0); 167#L566-1true assume 0 == ~E_4~0;~E_4~0 := 1; 363#L571-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 164#L262true assume 1 == ~m_pc~0; 437#L263true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 369#L273true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76#L274true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 366#L649true assume !(0 != activate_threads_~tmp~1#1); 433#L649-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 128#L281true assume !(1 == ~t1_pc~0); 386#L281-2true is_transmit1_triggered_~__retres1~1#1 := 0; 78#L292true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 210#L293true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 112#L657true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 349#L657-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 169#L300true assume 1 == ~t2_pc~0; 297#L301true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 269#L311true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 108#L312true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 187#L665true assume !(0 != activate_threads_~tmp___1~0#1); 39#L665-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 439#L319true assume !(1 == ~t3_pc~0); 19#L319-2true is_transmit3_triggered_~__retres1~3#1 := 0; 272#L330true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 123#L331true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 141#L673true assume !(0 != activate_threads_~tmp___2~0#1); 29#L673-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 273#L338true assume 1 == ~t4_pc~0; 109#L339true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 73#L349true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 86#L350true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 373#L681true assume !(0 != activate_threads_~tmp___3~0#1); 3#L681-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 360#L584true assume !(1 == ~M_E~0); 110#L584-2true assume !(1 == ~T1_E~0); 85#L589-1true assume !(1 == ~T2_E~0); 257#L594-1true assume !(1 == ~T3_E~0); 143#L599-1true assume !(1 == ~T4_E~0); 18#L604-1true assume !(1 == ~E_M~0); 10#L609-1true assume 1 == ~E_1~0;~E_1~0 := 2; 72#L614-1true assume !(1 == ~E_2~0); 122#L619-1true assume !(1 == ~E_3~0); 183#L624-1true assume !(1 == ~E_4~0); 393#L629-1true assume { :end_inline_reset_delta_events } true; 201#L815-2true [2021-12-06 17:16:07,566 INFO L793 eck$LassoCheckResult]: Loop: 201#L815-2true assume !false; 378#L816true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 354#L501true assume !true; 396#L516true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 356#L358-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 144#L526-3true assume 0 == ~M_E~0;~M_E~0 := 1; 263#L526-5true assume !(0 == ~T1_E~0); 74#L531-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 387#L536-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 15#L541-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 186#L546-3true assume 0 == ~E_M~0;~E_M~0 := 1; 434#L551-3true assume 0 == ~E_1~0;~E_1~0 := 1; 150#L556-3true assume 0 == ~E_2~0;~E_2~0 := 1; 235#L561-3true assume 0 == ~E_3~0;~E_3~0 := 1; 307#L566-3true assume !(0 == ~E_4~0); 80#L571-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 262#L262-18true assume !(1 == ~m_pc~0); 137#L262-20true is_master_triggered_~__retres1~0#1 := 0; 283#L273-6true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 71#L274-6true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 359#L649-18true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22#L649-20true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 159#L281-18true assume !(1 == ~t1_pc~0); 266#L281-20true is_transmit1_triggered_~__retres1~1#1 := 0; 171#L292-6true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 289#L293-6true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 411#L657-18true assume !(0 != activate_threads_~tmp___0~0#1); 284#L657-20true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 324#L300-18true assume 1 == ~t2_pc~0; 156#L301-6true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47#L311-6true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58#L312-6true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 249#L665-18true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 308#L665-20true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 79#L319-18true assume !(1 == ~t3_pc~0); 239#L319-20true is_transmit3_triggered_~__retres1~3#1 := 0; 91#L330-6true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 114#L331-6true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 217#L673-18true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 198#L673-20true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 127#L338-18true assume !(1 == ~t4_pc~0); 157#L338-20true is_transmit4_triggered_~__retres1~4#1 := 0; 102#L349-6true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 350#L350-6true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 32#L681-18true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 173#L681-20true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 140#L584-3true assume 1 == ~M_E~0;~M_E~0 := 2; 281#L584-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 30#L589-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 135#L594-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 214#L599-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 152#L604-3true assume 1 == ~E_M~0;~E_M~0 := 2; 399#L609-3true assume !(1 == ~E_1~0); 197#L614-3true assume 1 == ~E_2~0;~E_2~0 := 2; 26#L619-3true assume 1 == ~E_3~0;~E_3~0 := 2; 212#L624-3true assume 1 == ~E_4~0;~E_4~0 := 2; 241#L629-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 251#L398-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 68#L425-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 294#L426-1true start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 96#L834true assume !(0 == start_simulation_~tmp~3#1); 220#L834-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 344#L398-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 216#L425-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 252#L426-2true stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 286#L789true assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 296#L796true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 184#L797true start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 199#L847true assume !(0 != start_simulation_~tmp___0~1#1); 201#L815-2true [2021-12-06 17:16:07,569 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:07,570 INFO L85 PathProgramCache]: Analyzing trace with hash 1553035642, now seen corresponding path program 1 times [2021-12-06 17:16:07,576 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:07,576 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1823360671] [2021-12-06 17:16:07,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:07,577 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:07,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:07,750 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:07,750 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:07,750 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1823360671] [2021-12-06 17:16:07,751 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1823360671] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:07,751 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:07,751 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:07,753 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1532418026] [2021-12-06 17:16:07,754 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:07,758 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:07,759 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:07,759 INFO L85 PathProgramCache]: Analyzing trace with hash 15069021, now seen corresponding path program 1 times [2021-12-06 17:16:07,759 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:07,760 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [162897216] [2021-12-06 17:16:07,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:07,760 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:07,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:07,789 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:07,789 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:07,789 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [162897216] [2021-12-06 17:16:07,789 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [162897216] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:07,790 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:07,790 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 17:16:07,790 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [492329890] [2021-12-06 17:16:07,790 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:07,792 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:07,792 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:07,818 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:16:07,818 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:16:07,820 INFO L87 Difference]: Start difference. First operand has 438 states, 437 states have (on average 1.5354691075514875) internal successors, (671), 437 states have internal predecessors, (671), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:07,863 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:07,863 INFO L93 Difference]: Finished difference Result 436 states and 652 transitions. [2021-12-06 17:16:07,864 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:16:07,868 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 436 states and 652 transitions. [2021-12-06 17:16:07,873 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2021-12-06 17:16:07,881 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 436 states to 430 states and 646 transitions. [2021-12-06 17:16:07,882 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430 [2021-12-06 17:16:07,883 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430 [2021-12-06 17:16:07,884 INFO L73 IsDeterministic]: Start isDeterministic. Operand 430 states and 646 transitions. [2021-12-06 17:16:07,887 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:07,887 INFO L681 BuchiCegarLoop]: Abstraction has 430 states and 646 transitions. [2021-12-06 17:16:07,901 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states and 646 transitions. [2021-12-06 17:16:07,921 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2021-12-06 17:16:07,922 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 430 states have (on average 1.5023255813953489) internal successors, (646), 429 states have internal predecessors, (646), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:07,924 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 646 transitions. [2021-12-06 17:16:07,925 INFO L704 BuchiCegarLoop]: Abstraction has 430 states and 646 transitions. [2021-12-06 17:16:07,925 INFO L587 BuchiCegarLoop]: Abstraction has 430 states and 646 transitions. [2021-12-06 17:16:07,925 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-06 17:16:07,925 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 430 states and 646 transitions. [2021-12-06 17:16:07,927 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2021-12-06 17:16:07,927 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:07,927 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:07,929 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:07,929 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:07,930 INFO L791 eck$LassoCheckResult]: Stem: 1312#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 1295#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1107#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 905#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 906#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 980#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1226#L370-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1184#L375-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1185#L380-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1212#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1194#L526 assume !(0 == ~M_E~0); 1195#L526-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1227#L531-1 assume !(0 == ~T2_E~0); 1180#L536-1 assume !(0 == ~T3_E~0); 1181#L541-1 assume !(0 == ~T4_E~0); 1176#L546-1 assume !(0 == ~E_M~0); 1177#L551-1 assume !(0 == ~E_1~0); 1153#L556-1 assume !(0 == ~E_2~0); 1154#L561-1 assume !(0 == ~E_3~0); 1164#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 1165#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1158#L262 assume 1 == ~m_pc~0; 1159#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1299#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1024#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1025#L649 assume !(0 != activate_threads_~tmp~1#1); 1298#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1111#L281 assume !(1 == ~t1_pc~0); 1112#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1028#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1029#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1087#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1088#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1166#L300 assume 1 == ~t2_pc~0; 1167#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1257#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1081#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1082#L665 assume !(0 != activate_threads_~tmp___1~0#1); 960#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 961#L319 assume !(1 == ~t3_pc~0); 918#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 919#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1102#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1103#L673 assume !(0 != activate_threads_~tmp___2~0#1); 939#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 940#L338 assume 1 == ~t4_pc~0; 1083#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1004#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1018#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1045#L681 assume !(0 != activate_threads_~tmp___3~0#1); 883#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 884#L584 assume !(1 == ~M_E~0); 1084#L584-2 assume !(1 == ~T1_E~0); 1043#L589-1 assume !(1 == ~T2_E~0); 1044#L594-1 assume !(1 == ~T3_E~0); 1132#L599-1 assume !(1 == ~T4_E~0); 917#L604-1 assume !(1 == ~E_M~0); 901#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 902#L614-1 assume !(1 == ~E_2~0); 1017#L619-1 assume !(1 == ~E_3~0); 1101#L624-1 assume !(1 == ~E_4~0); 1186#L629-1 assume { :end_inline_reset_delta_events } true; 1203#L815-2 [2021-12-06 17:16:07,930 INFO L793 eck$LassoCheckResult]: Loop: 1203#L815-2 assume !false; 1204#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1287#L501 assume !false; 1293#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1294#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1022#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1207#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1208#L440 assume !(0 != eval_~tmp~0#1); 1306#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1296#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1133#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1134#L526-5 assume !(0 == ~T1_E~0); 1019#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1020#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 911#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 912#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1190#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1139#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1140#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1233#L566-3 assume !(0 == ~E_4~0); 1033#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1034#L262-18 assume 1 == ~m_pc~0; 1251#L263-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1124#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1015#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1016#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 924#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 925#L281-18 assume !(1 == ~t1_pc~0); 1150#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 1169#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1170#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1269#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 1265#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1266#L300-18 assume !(1 == ~t2_pc~0); 913#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 914#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 977#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 994#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1241#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1030#L319-18 assume !(1 == ~t3_pc~0); 1031#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 1037#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1053#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1090#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1202#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1108#L338-18 assume 1 == ~t4_pc~0; 1109#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1072#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1073#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 945#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 946#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1128#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1129#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 941#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 942#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1121#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1142#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1143#L609-3 assume !(1 == ~E_1~0); 1201#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 933#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 934#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1213#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1236#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1011#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1012#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1059#L834 assume !(0 == start_simulation_~tmp~3#1); 1061#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1220#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1179#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1216#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 1244#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1267#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1187#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 1188#L847 assume !(0 != start_simulation_~tmp___0~1#1); 1203#L815-2 [2021-12-06 17:16:07,930 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:07,930 INFO L85 PathProgramCache]: Analyzing trace with hash 1119306556, now seen corresponding path program 1 times [2021-12-06 17:16:07,931 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:07,931 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1826032541] [2021-12-06 17:16:07,931 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:07,931 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:07,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:07,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:07,966 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:07,967 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1826032541] [2021-12-06 17:16:07,967 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1826032541] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:07,967 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:07,967 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:07,967 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1300446295] [2021-12-06 17:16:07,967 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:07,967 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:07,968 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:07,968 INFO L85 PathProgramCache]: Analyzing trace with hash 330425744, now seen corresponding path program 1 times [2021-12-06 17:16:07,968 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:07,968 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [900219808] [2021-12-06 17:16:07,968 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:07,969 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:07,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:08,020 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:08,020 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:08,020 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [900219808] [2021-12-06 17:16:08,020 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [900219808] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:08,020 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:08,020 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:08,020 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1540773534] [2021-12-06 17:16:08,021 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:08,021 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:08,021 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:08,021 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:16:08,021 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:16:08,022 INFO L87 Difference]: Start difference. First operand 430 states and 646 transitions. cyclomatic complexity: 217 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:08,045 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:08,045 INFO L93 Difference]: Finished difference Result 430 states and 645 transitions. [2021-12-06 17:16:08,045 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:16:08,046 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 645 transitions. [2021-12-06 17:16:08,049 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2021-12-06 17:16:08,053 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 430 states and 645 transitions. [2021-12-06 17:16:08,053 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430 [2021-12-06 17:16:08,053 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430 [2021-12-06 17:16:08,054 INFO L73 IsDeterministic]: Start isDeterministic. Operand 430 states and 645 transitions. [2021-12-06 17:16:08,056 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:08,056 INFO L681 BuchiCegarLoop]: Abstraction has 430 states and 645 transitions. [2021-12-06 17:16:08,065 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states and 645 transitions. [2021-12-06 17:16:08,078 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2021-12-06 17:16:08,079 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 430 states have (on average 1.5) internal successors, (645), 429 states have internal predecessors, (645), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:08,082 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 645 transitions. [2021-12-06 17:16:08,082 INFO L704 BuchiCegarLoop]: Abstraction has 430 states and 645 transitions. [2021-12-06 17:16:08,082 INFO L587 BuchiCegarLoop]: Abstraction has 430 states and 645 transitions. [2021-12-06 17:16:08,082 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-06 17:16:08,082 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 430 states and 645 transitions. [2021-12-06 17:16:08,085 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2021-12-06 17:16:08,085 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:08,085 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:08,087 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:08,088 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:08,088 INFO L791 eck$LassoCheckResult]: Stem: 2179#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2162#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1974#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1772#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1773#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 1847#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2093#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2051#L375-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2052#L380-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2079#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2061#L526 assume !(0 == ~M_E~0); 2062#L526-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2094#L531-1 assume !(0 == ~T2_E~0); 2047#L536-1 assume !(0 == ~T3_E~0); 2048#L541-1 assume !(0 == ~T4_E~0); 2043#L546-1 assume !(0 == ~E_M~0); 2044#L551-1 assume !(0 == ~E_1~0); 2020#L556-1 assume !(0 == ~E_2~0); 2021#L561-1 assume !(0 == ~E_3~0); 2031#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2032#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2025#L262 assume 1 == ~m_pc~0; 2026#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2166#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1891#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1892#L649 assume !(0 != activate_threads_~tmp~1#1); 2165#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1978#L281 assume !(1 == ~t1_pc~0); 1979#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1895#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1896#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1954#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1955#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2033#L300 assume 1 == ~t2_pc~0; 2034#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2124#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1948#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1949#L665 assume !(0 != activate_threads_~tmp___1~0#1); 1827#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1828#L319 assume !(1 == ~t3_pc~0); 1785#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1786#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1969#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1970#L673 assume !(0 != activate_threads_~tmp___2~0#1); 1806#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1807#L338 assume 1 == ~t4_pc~0; 1950#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1871#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1885#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1912#L681 assume !(0 != activate_threads_~tmp___3~0#1); 1750#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1751#L584 assume !(1 == ~M_E~0); 1951#L584-2 assume !(1 == ~T1_E~0); 1910#L589-1 assume !(1 == ~T2_E~0); 1911#L594-1 assume !(1 == ~T3_E~0); 1999#L599-1 assume !(1 == ~T4_E~0); 1784#L604-1 assume !(1 == ~E_M~0); 1768#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1769#L614-1 assume !(1 == ~E_2~0); 1884#L619-1 assume !(1 == ~E_3~0); 1968#L624-1 assume !(1 == ~E_4~0); 2053#L629-1 assume { :end_inline_reset_delta_events } true; 2070#L815-2 [2021-12-06 17:16:08,088 INFO L793 eck$LassoCheckResult]: Loop: 2070#L815-2 assume !false; 2071#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2154#L501 assume !false; 2160#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2161#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1889#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2074#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2075#L440 assume !(0 != eval_~tmp~0#1); 2173#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2163#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2000#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2001#L526-5 assume !(0 == ~T1_E~0); 1886#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1887#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1778#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1779#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2057#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2006#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2007#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2100#L566-3 assume !(0 == ~E_4~0); 1900#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1901#L262-18 assume 1 == ~m_pc~0; 2118#L263-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1991#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1882#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1883#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1791#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1792#L281-18 assume !(1 == ~t1_pc~0); 2017#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 2036#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2037#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2136#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 2132#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2133#L300-18 assume !(1 == ~t2_pc~0); 1780#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 1781#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1844#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1861#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2108#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1897#L319-18 assume !(1 == ~t3_pc~0); 1898#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 1904#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1920#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1957#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2069#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1975#L338-18 assume 1 == ~t4_pc~0; 1976#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1939#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1940#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1812#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1813#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1995#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1996#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1808#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1809#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1988#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2009#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2010#L609-3 assume !(1 == ~E_1~0); 2068#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1800#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1801#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2080#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2103#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1878#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1879#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1926#L834 assume !(0 == start_simulation_~tmp~3#1); 1928#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2087#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2046#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2083#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 2111#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 2134#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2054#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 2055#L847 assume !(0 != start_simulation_~tmp___0~1#1); 2070#L815-2 [2021-12-06 17:16:08,089 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:08,089 INFO L85 PathProgramCache]: Analyzing trace with hash 1078631806, now seen corresponding path program 1 times [2021-12-06 17:16:08,089 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:08,089 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [916443228] [2021-12-06 17:16:08,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:08,090 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:08,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:08,127 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:08,127 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:08,128 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [916443228] [2021-12-06 17:16:08,128 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [916443228] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:08,128 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:08,128 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:08,128 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [127422576] [2021-12-06 17:16:08,128 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:08,129 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:08,129 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:08,129 INFO L85 PathProgramCache]: Analyzing trace with hash 330425744, now seen corresponding path program 2 times [2021-12-06 17:16:08,130 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:08,130 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [120437172] [2021-12-06 17:16:08,130 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:08,130 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:08,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:08,176 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:08,176 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:08,176 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [120437172] [2021-12-06 17:16:08,176 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [120437172] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:08,176 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:08,177 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:08,177 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1094552676] [2021-12-06 17:16:08,177 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:08,177 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:08,178 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:08,178 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:16:08,178 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:16:08,178 INFO L87 Difference]: Start difference. First operand 430 states and 645 transitions. cyclomatic complexity: 216 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:08,192 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:08,192 INFO L93 Difference]: Finished difference Result 430 states and 644 transitions. [2021-12-06 17:16:08,193 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:16:08,194 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 644 transitions. [2021-12-06 17:16:08,196 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2021-12-06 17:16:08,199 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 430 states and 644 transitions. [2021-12-06 17:16:08,199 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430 [2021-12-06 17:16:08,200 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430 [2021-12-06 17:16:08,200 INFO L73 IsDeterministic]: Start isDeterministic. Operand 430 states and 644 transitions. [2021-12-06 17:16:08,200 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:08,201 INFO L681 BuchiCegarLoop]: Abstraction has 430 states and 644 transitions. [2021-12-06 17:16:08,201 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states and 644 transitions. [2021-12-06 17:16:08,206 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2021-12-06 17:16:08,206 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 430 states have (on average 1.4976744186046511) internal successors, (644), 429 states have internal predecessors, (644), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:08,208 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 644 transitions. [2021-12-06 17:16:08,208 INFO L704 BuchiCegarLoop]: Abstraction has 430 states and 644 transitions. [2021-12-06 17:16:08,208 INFO L587 BuchiCegarLoop]: Abstraction has 430 states and 644 transitions. [2021-12-06 17:16:08,208 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-06 17:16:08,208 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 430 states and 644 transitions. [2021-12-06 17:16:08,210 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2021-12-06 17:16:08,210 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:08,210 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:08,212 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:08,212 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:08,212 INFO L791 eck$LassoCheckResult]: Stem: 3046#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 3029#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2841#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2639#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2640#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 2714#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2960#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2918#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2919#L380-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2946#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2928#L526 assume !(0 == ~M_E~0); 2929#L526-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2961#L531-1 assume !(0 == ~T2_E~0); 2914#L536-1 assume !(0 == ~T3_E~0); 2915#L541-1 assume !(0 == ~T4_E~0); 2910#L546-1 assume !(0 == ~E_M~0); 2911#L551-1 assume !(0 == ~E_1~0); 2887#L556-1 assume !(0 == ~E_2~0); 2888#L561-1 assume !(0 == ~E_3~0); 2898#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2899#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2892#L262 assume 1 == ~m_pc~0; 2893#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3033#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2758#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2759#L649 assume !(0 != activate_threads_~tmp~1#1); 3032#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2845#L281 assume !(1 == ~t1_pc~0); 2846#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2762#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2763#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2821#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2822#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2900#L300 assume 1 == ~t2_pc~0; 2901#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2991#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2815#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2816#L665 assume !(0 != activate_threads_~tmp___1~0#1); 2694#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2695#L319 assume !(1 == ~t3_pc~0); 2652#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2653#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2836#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2837#L673 assume !(0 != activate_threads_~tmp___2~0#1); 2673#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2674#L338 assume 1 == ~t4_pc~0; 2817#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2738#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2752#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2779#L681 assume !(0 != activate_threads_~tmp___3~0#1); 2617#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2618#L584 assume !(1 == ~M_E~0); 2818#L584-2 assume !(1 == ~T1_E~0); 2777#L589-1 assume !(1 == ~T2_E~0); 2778#L594-1 assume !(1 == ~T3_E~0); 2866#L599-1 assume !(1 == ~T4_E~0); 2651#L604-1 assume !(1 == ~E_M~0); 2635#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2636#L614-1 assume !(1 == ~E_2~0); 2751#L619-1 assume !(1 == ~E_3~0); 2835#L624-1 assume !(1 == ~E_4~0); 2920#L629-1 assume { :end_inline_reset_delta_events } true; 2937#L815-2 [2021-12-06 17:16:08,213 INFO L793 eck$LassoCheckResult]: Loop: 2937#L815-2 assume !false; 2938#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3021#L501 assume !false; 3027#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3028#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2756#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2941#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2942#L440 assume !(0 != eval_~tmp~0#1); 3040#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3030#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2867#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2868#L526-5 assume !(0 == ~T1_E~0); 2753#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2754#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2645#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2646#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2924#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2873#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2874#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2967#L566-3 assume !(0 == ~E_4~0); 2767#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2768#L262-18 assume 1 == ~m_pc~0; 2985#L263-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2858#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2749#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2750#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2658#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2659#L281-18 assume !(1 == ~t1_pc~0); 2884#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 2903#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2904#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3003#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 2999#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3000#L300-18 assume 1 == ~t2_pc~0; 2882#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2648#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2711#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2728#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2975#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2764#L319-18 assume !(1 == ~t3_pc~0); 2765#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 2771#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2787#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2824#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2936#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2842#L338-18 assume 1 == ~t4_pc~0; 2843#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2806#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2807#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2679#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2680#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2862#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2863#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2675#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2676#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2855#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2876#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2877#L609-3 assume !(1 == ~E_1~0); 2935#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2667#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2668#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2947#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2970#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2745#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2746#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 2793#L834 assume !(0 == start_simulation_~tmp~3#1); 2795#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2954#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2913#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2950#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 2978#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 3001#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2921#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 2922#L847 assume !(0 != start_simulation_~tmp___0~1#1); 2937#L815-2 [2021-12-06 17:16:08,213 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:08,213 INFO L85 PathProgramCache]: Analyzing trace with hash -308153604, now seen corresponding path program 1 times [2021-12-06 17:16:08,213 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:08,214 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [89801925] [2021-12-06 17:16:08,214 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:08,214 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:08,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:08,242 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:08,242 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:08,242 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [89801925] [2021-12-06 17:16:08,242 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [89801925] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:08,242 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:08,243 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:08,243 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [818941467] [2021-12-06 17:16:08,243 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:08,243 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:08,244 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:08,244 INFO L85 PathProgramCache]: Analyzing trace with hash 815600463, now seen corresponding path program 1 times [2021-12-06 17:16:08,244 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:08,244 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2031465461] [2021-12-06 17:16:08,245 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:08,245 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:08,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:08,283 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:08,283 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:08,284 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2031465461] [2021-12-06 17:16:08,284 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2031465461] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:08,284 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:08,284 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:08,284 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1151796637] [2021-12-06 17:16:08,285 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:08,285 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:08,285 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:08,286 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:16:08,286 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:16:08,286 INFO L87 Difference]: Start difference. First operand 430 states and 644 transitions. cyclomatic complexity: 215 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:08,296 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:08,296 INFO L93 Difference]: Finished difference Result 430 states and 643 transitions. [2021-12-06 17:16:08,296 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:16:08,297 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 643 transitions. [2021-12-06 17:16:08,299 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2021-12-06 17:16:08,302 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 430 states and 643 transitions. [2021-12-06 17:16:08,302 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430 [2021-12-06 17:16:08,303 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430 [2021-12-06 17:16:08,303 INFO L73 IsDeterministic]: Start isDeterministic. Operand 430 states and 643 transitions. [2021-12-06 17:16:08,303 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:08,303 INFO L681 BuchiCegarLoop]: Abstraction has 430 states and 643 transitions. [2021-12-06 17:16:08,304 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states and 643 transitions. [2021-12-06 17:16:08,315 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2021-12-06 17:16:08,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 430 states have (on average 1.4953488372093022) internal successors, (643), 429 states have internal predecessors, (643), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:08,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 643 transitions. [2021-12-06 17:16:08,317 INFO L704 BuchiCegarLoop]: Abstraction has 430 states and 643 transitions. [2021-12-06 17:16:08,317 INFO L587 BuchiCegarLoop]: Abstraction has 430 states and 643 transitions. [2021-12-06 17:16:08,317 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-06 17:16:08,318 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 430 states and 643 transitions. [2021-12-06 17:16:08,319 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2021-12-06 17:16:08,320 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:08,320 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:08,321 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:08,321 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:08,322 INFO L791 eck$LassoCheckResult]: Stem: 3913#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 3896#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3711#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3506#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3507#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 3581#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3827#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3786#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3787#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3814#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3796#L526 assume !(0 == ~M_E~0); 3797#L526-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3829#L531-1 assume !(0 == ~T2_E~0); 3781#L536-1 assume !(0 == ~T3_E~0); 3782#L541-1 assume !(0 == ~T4_E~0); 3777#L546-1 assume !(0 == ~E_M~0); 3778#L551-1 assume !(0 == ~E_1~0); 3754#L556-1 assume !(0 == ~E_2~0); 3755#L561-1 assume !(0 == ~E_3~0); 3765#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 3766#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3759#L262 assume 1 == ~m_pc~0; 3760#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3900#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3625#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3626#L649 assume !(0 != activate_threads_~tmp~1#1); 3899#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3712#L281 assume !(1 == ~t1_pc~0); 3713#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3629#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3630#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3688#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3689#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3767#L300 assume 1 == ~t2_pc~0; 3768#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3858#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3682#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3683#L665 assume !(0 != activate_threads_~tmp___1~0#1); 3561#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3562#L319 assume !(1 == ~t3_pc~0); 3519#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3520#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3703#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3704#L673 assume !(0 != activate_threads_~tmp___2~0#1); 3540#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3541#L338 assume 1 == ~t4_pc~0; 3684#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3605#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3619#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3646#L681 assume !(0 != activate_threads_~tmp___3~0#1); 3484#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3485#L584 assume !(1 == ~M_E~0); 3685#L584-2 assume !(1 == ~T1_E~0); 3644#L589-1 assume !(1 == ~T2_E~0); 3645#L594-1 assume !(1 == ~T3_E~0); 3733#L599-1 assume !(1 == ~T4_E~0); 3518#L604-1 assume !(1 == ~E_M~0); 3502#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3503#L614-1 assume !(1 == ~E_2~0); 3618#L619-1 assume !(1 == ~E_3~0); 3702#L624-1 assume !(1 == ~E_4~0); 3785#L629-1 assume { :end_inline_reset_delta_events } true; 3804#L815-2 [2021-12-06 17:16:08,322 INFO L793 eck$LassoCheckResult]: Loop: 3804#L815-2 assume !false; 3805#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3888#L501 assume !false; 3894#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3895#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3623#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3808#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3809#L440 assume !(0 != eval_~tmp~0#1); 3907#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3897#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3734#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3735#L526-5 assume !(0 == ~T1_E~0); 3620#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3621#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3512#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3513#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3791#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3740#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3741#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3834#L566-3 assume !(0 == ~E_4~0); 3634#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3635#L262-18 assume 1 == ~m_pc~0; 3852#L263-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3725#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3616#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3617#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3525#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3526#L281-18 assume !(1 == ~t1_pc~0); 3751#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 3770#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3771#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3870#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 3866#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3867#L300-18 assume 1 == ~t2_pc~0; 3749#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3515#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3578#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3595#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3842#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3631#L319-18 assume !(1 == ~t3_pc~0); 3632#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 3638#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3654#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3691#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3803#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3708#L338-18 assume 1 == ~t4_pc~0; 3709#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3673#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3674#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3546#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3547#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3729#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3730#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3542#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3543#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3722#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3743#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3744#L609-3 assume !(1 == ~E_1~0); 3802#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3534#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3535#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3813#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3837#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3612#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3613#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 3660#L834 assume !(0 == start_simulation_~tmp~3#1); 3662#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3821#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3780#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3817#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 3845#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 3868#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3788#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 3789#L847 assume !(0 != start_simulation_~tmp___0~1#1); 3804#L815-2 [2021-12-06 17:16:08,322 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:08,322 INFO L85 PathProgramCache]: Analyzing trace with hash -1184172610, now seen corresponding path program 1 times [2021-12-06 17:16:08,322 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:08,323 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1269159698] [2021-12-06 17:16:08,323 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:08,323 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:08,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:08,359 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:08,360 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:08,360 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1269159698] [2021-12-06 17:16:08,360 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1269159698] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:08,360 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:08,360 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:08,360 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1443188114] [2021-12-06 17:16:08,361 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:08,361 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:08,361 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:08,362 INFO L85 PathProgramCache]: Analyzing trace with hash 815600463, now seen corresponding path program 2 times [2021-12-06 17:16:08,362 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:08,362 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [841978706] [2021-12-06 17:16:08,362 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:08,362 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:08,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:08,396 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:08,396 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:08,397 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [841978706] [2021-12-06 17:16:08,397 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [841978706] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:08,397 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:08,397 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:08,397 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1673883490] [2021-12-06 17:16:08,397 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:08,398 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:08,398 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:08,398 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 17:16:08,399 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 17:16:08,399 INFO L87 Difference]: Start difference. First operand 430 states and 643 transitions. cyclomatic complexity: 214 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:08,451 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:08,452 INFO L93 Difference]: Finished difference Result 756 states and 1125 transitions. [2021-12-06 17:16:08,452 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 17:16:08,452 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 756 states and 1125 transitions. [2021-12-06 17:16:08,457 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 679 [2021-12-06 17:16:08,461 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 756 states to 756 states and 1125 transitions. [2021-12-06 17:16:08,461 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 756 [2021-12-06 17:16:08,462 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 756 [2021-12-06 17:16:08,462 INFO L73 IsDeterministic]: Start isDeterministic. Operand 756 states and 1125 transitions. [2021-12-06 17:16:08,463 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:08,463 INFO L681 BuchiCegarLoop]: Abstraction has 756 states and 1125 transitions. [2021-12-06 17:16:08,464 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 756 states and 1125 transitions. [2021-12-06 17:16:08,473 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 756 to 756. [2021-12-06 17:16:08,474 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 756 states, 756 states have (on average 1.4880952380952381) internal successors, (1125), 755 states have internal predecessors, (1125), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:08,476 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 756 states to 756 states and 1125 transitions. [2021-12-06 17:16:08,476 INFO L704 BuchiCegarLoop]: Abstraction has 756 states and 1125 transitions. [2021-12-06 17:16:08,477 INFO L587 BuchiCegarLoop]: Abstraction has 756 states and 1125 transitions. [2021-12-06 17:16:08,477 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-06 17:16:08,477 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 756 states and 1125 transitions. [2021-12-06 17:16:08,479 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 679 [2021-12-06 17:16:08,480 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:08,480 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:08,481 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:08,481 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:08,481 INFO L791 eck$LassoCheckResult]: Stem: 5138#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 5113#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4908#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4702#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4703#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 4777#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5031#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4985#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4986#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5016#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4996#L526 assume !(0 == ~M_E~0); 4997#L526-2 assume !(0 == ~T1_E~0); 5033#L531-1 assume !(0 == ~T2_E~0); 4981#L536-1 assume !(0 == ~T3_E~0); 4982#L541-1 assume !(0 == ~T4_E~0); 4977#L546-1 assume !(0 == ~E_M~0); 4978#L551-1 assume !(0 == ~E_1~0); 4953#L556-1 assume !(0 == ~E_2~0); 4954#L561-1 assume !(0 == ~E_3~0); 4964#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4965#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4958#L262 assume 1 == ~m_pc~0; 4959#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5119#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4824#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4825#L649 assume !(0 != activate_threads_~tmp~1#1); 5118#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4909#L281 assume !(1 == ~t1_pc~0); 4910#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4826#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4827#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4885#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4886#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4966#L300 assume 1 == ~t2_pc~0; 4967#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5066#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4879#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4880#L665 assume !(0 != activate_threads_~tmp___1~0#1); 4757#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4758#L319 assume !(1 == ~t3_pc~0); 4715#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4716#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4900#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4901#L673 assume !(0 != activate_threads_~tmp___2~0#1); 4736#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4737#L338 assume 1 == ~t4_pc~0; 4881#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4802#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4816#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4843#L681 assume !(0 != activate_threads_~tmp___3~0#1); 4680#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4681#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 4882#L584-2 assume !(1 == ~T1_E~0); 4841#L589-1 assume !(1 == ~T2_E~0); 4842#L594-1 assume !(1 == ~T3_E~0); 4932#L599-1 assume !(1 == ~T4_E~0); 4714#L604-1 assume !(1 == ~E_M~0); 4698#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4699#L614-1 assume !(1 == ~E_2~0); 4815#L619-1 assume !(1 == ~E_3~0); 4899#L624-1 assume !(1 == ~E_4~0); 4987#L629-1 assume { :end_inline_reset_delta_events } true; 5005#L815-2 [2021-12-06 17:16:08,481 INFO L793 eck$LassoCheckResult]: Loop: 5005#L815-2 assume !false; 5153#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5152#L501 assume !false; 5151#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5150#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5145#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5144#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5143#L440 assume !(0 != eval_~tmp~0#1); 5142#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5141#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5140#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5060#L526-5 assume !(0 == ~T1_E~0); 4817#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4818#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4708#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4709#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4991#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4939#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4940#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5037#L566-3 assume !(0 == ~E_4~0); 4831#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4832#L262-18 assume 1 == ~m_pc~0; 5059#L263-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4923#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4813#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4814#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4721#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4722#L281-18 assume !(1 == ~t1_pc~0); 4950#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 4969#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4970#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5078#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 5132#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5384#L300-18 assume 1 == ~t2_pc~0; 5381#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5380#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5379#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5378#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5377#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5376#L319-18 assume !(1 == ~t3_pc~0); 5374#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 5373#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5372#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5371#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5370#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5368#L338-18 assume 1 == ~t4_pc~0; 5365#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5364#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5363#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5360#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5358#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4928#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4929#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4738#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4739#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5328#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4942#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4943#L609-3 assume !(1 == ~E_1~0); 5002#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4730#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4731#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5015#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5050#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4809#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4810#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 4857#L834 assume !(0 == start_simulation_~tmp~3#1); 4859#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5024#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4980#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5020#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 5051#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 5076#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5175#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 5004#L847 assume !(0 != start_simulation_~tmp___0~1#1); 5005#L815-2 [2021-12-06 17:16:08,481 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:08,481 INFO L85 PathProgramCache]: Analyzing trace with hash 381143998, now seen corresponding path program 1 times [2021-12-06 17:16:08,482 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:08,482 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [953742729] [2021-12-06 17:16:08,482 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:08,482 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:08,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:08,503 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:08,503 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:08,503 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [953742729] [2021-12-06 17:16:08,504 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [953742729] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:08,504 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:08,504 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:08,504 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1386961025] [2021-12-06 17:16:08,504 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:08,504 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:08,504 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:08,505 INFO L85 PathProgramCache]: Analyzing trace with hash 815600463, now seen corresponding path program 3 times [2021-12-06 17:16:08,505 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:08,505 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1328297425] [2021-12-06 17:16:08,505 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:08,505 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:08,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:08,525 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:08,525 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:08,526 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1328297425] [2021-12-06 17:16:08,526 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1328297425] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:08,526 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:08,526 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:08,526 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [132304639] [2021-12-06 17:16:08,526 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:08,526 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:08,527 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:08,527 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 17:16:08,527 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 17:16:08,527 INFO L87 Difference]: Start difference. First operand 756 states and 1125 transitions. cyclomatic complexity: 371 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:08,600 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:08,600 INFO L93 Difference]: Finished difference Result 1326 states and 1968 transitions. [2021-12-06 17:16:08,600 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 17:16:08,601 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1326 states and 1968 transitions. [2021-12-06 17:16:08,611 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1237 [2021-12-06 17:16:08,621 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1326 states to 1326 states and 1968 transitions. [2021-12-06 17:16:08,622 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1326 [2021-12-06 17:16:08,623 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1326 [2021-12-06 17:16:08,623 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1326 states and 1968 transitions. [2021-12-06 17:16:08,625 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:08,626 INFO L681 BuchiCegarLoop]: Abstraction has 1326 states and 1968 transitions. [2021-12-06 17:16:08,627 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1326 states and 1968 transitions. [2021-12-06 17:16:08,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1326 to 1324. [2021-12-06 17:16:08,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1324 states, 1324 states have (on average 1.4848942598187311) internal successors, (1966), 1323 states have internal predecessors, (1966), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:08,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1324 states to 1324 states and 1966 transitions. [2021-12-06 17:16:08,655 INFO L704 BuchiCegarLoop]: Abstraction has 1324 states and 1966 transitions. [2021-12-06 17:16:08,655 INFO L587 BuchiCegarLoop]: Abstraction has 1324 states and 1966 transitions. [2021-12-06 17:16:08,655 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-06 17:16:08,655 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1324 states and 1966 transitions. [2021-12-06 17:16:08,663 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1237 [2021-12-06 17:16:08,663 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:08,663 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:08,664 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:08,664 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:08,664 INFO L791 eck$LassoCheckResult]: Stem: 7239#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 7211#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 7001#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6794#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6795#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 6870#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7128#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7079#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7080#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7113#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7092#L526 assume !(0 == ~M_E~0); 7093#L526-2 assume !(0 == ~T1_E~0); 7129#L531-1 assume !(0 == ~T2_E~0); 7075#L536-1 assume !(0 == ~T3_E~0); 7076#L541-1 assume !(0 == ~T4_E~0); 7071#L546-1 assume !(0 == ~E_M~0); 7072#L551-1 assume !(0 == ~E_1~0); 7046#L556-1 assume !(0 == ~E_2~0); 7047#L561-1 assume !(0 == ~E_3~0); 7058#L566-1 assume !(0 == ~E_4~0); 7059#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7051#L262 assume 1 == ~m_pc~0; 7052#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7217#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6916#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6917#L649 assume !(0 != activate_threads_~tmp~1#1); 7216#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7002#L281 assume !(1 == ~t1_pc~0); 7003#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6918#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6919#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6978#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6979#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7060#L300 assume 1 == ~t2_pc~0; 7061#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7162#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6971#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6972#L665 assume !(0 != activate_threads_~tmp___1~0#1); 6850#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6851#L319 assume !(1 == ~t3_pc~0); 6808#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6809#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6993#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6994#L673 assume !(0 != activate_threads_~tmp___2~0#1); 6829#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6830#L338 assume 1 == ~t4_pc~0; 6973#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6894#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6908#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6935#L681 assume !(0 != activate_threads_~tmp___3~0#1); 6772#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6773#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 7213#L584-2 assume !(1 == ~T1_E~0); 7353#L589-1 assume !(1 == ~T2_E~0); 7350#L594-1 assume !(1 == ~T3_E~0); 7348#L599-1 assume !(1 == ~T4_E~0); 6806#L604-1 assume !(1 == ~E_M~0); 6807#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7297#L614-1 assume !(1 == ~E_2~0); 7278#L619-1 assume !(1 == ~E_3~0); 7276#L624-1 assume !(1 == ~E_4~0); 7267#L629-1 assume { :end_inline_reset_delta_events } true; 7261#L815-2 [2021-12-06 17:16:08,665 INFO L793 eck$LassoCheckResult]: Loop: 7261#L815-2 assume !false; 7256#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7255#L501 assume !false; 7254#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7253#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7248#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7247#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7245#L440 assume !(0 != eval_~tmp~0#1); 7244#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7243#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7241#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7242#L526-5 assume !(0 == ~T1_E~0); 7656#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7654#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7652#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7650#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7648#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7646#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7644#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7641#L566-3 assume !(0 == ~E_4~0); 7639#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7630#L262-18 assume !(1 == ~m_pc~0); 7619#L262-20 is_master_triggered_~__retres1~0#1 := 0; 7613#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7607#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7601#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7588#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7584#L281-18 assume 1 == ~t1_pc~0; 7579#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7574#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7569#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7565#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 7562#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7559#L300-18 assume 1 == ~t2_pc~0; 7544#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7542#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7540#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7538#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7536#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7534#L319-18 assume !(1 == ~t3_pc~0); 7528#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 7525#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7522#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7519#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7516#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7513#L338-18 assume 1 == ~t4_pc~0; 7507#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7503#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7498#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7494#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7490#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7018#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7019#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7170#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7475#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7470#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7466#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7462#L609-3 assume !(1 == ~E_1~0); 7457#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7453#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7449#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7444#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7441#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7436#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7432#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 7346#L834 assume !(0 == start_simulation_~tmp~3#1); 7009#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7303#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7300#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7299#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 7298#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 7279#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7277#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 7268#L847 assume !(0 != start_simulation_~tmp___0~1#1); 7261#L815-2 [2021-12-06 17:16:08,665 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:08,665 INFO L85 PathProgramCache]: Analyzing trace with hash -516249280, now seen corresponding path program 1 times [2021-12-06 17:16:08,665 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:08,665 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [809493437] [2021-12-06 17:16:08,665 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:08,665 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:08,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:08,685 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:08,685 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:08,685 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [809493437] [2021-12-06 17:16:08,685 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [809493437] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:08,685 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:08,685 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 17:16:08,685 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [638464754] [2021-12-06 17:16:08,685 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:08,685 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:08,686 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:08,686 INFO L85 PathProgramCache]: Analyzing trace with hash -1859703153, now seen corresponding path program 1 times [2021-12-06 17:16:08,686 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:08,686 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1793976061] [2021-12-06 17:16:08,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:08,686 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:08,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:08,707 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:08,707 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:08,707 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1793976061] [2021-12-06 17:16:08,707 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1793976061] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:08,708 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:08,708 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:08,708 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1821445520] [2021-12-06 17:16:08,708 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:08,708 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:08,708 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:08,709 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:16:08,709 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:16:08,709 INFO L87 Difference]: Start difference. First operand 1324 states and 1966 transitions. cyclomatic complexity: 646 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:08,752 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:08,752 INFO L93 Difference]: Finished difference Result 2505 states and 3667 transitions. [2021-12-06 17:16:08,753 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:16:08,753 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2505 states and 3667 transitions. [2021-12-06 17:16:08,768 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2415 [2021-12-06 17:16:08,782 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2505 states to 2505 states and 3667 transitions. [2021-12-06 17:16:08,782 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2505 [2021-12-06 17:16:08,784 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2505 [2021-12-06 17:16:08,784 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2505 states and 3667 transitions. [2021-12-06 17:16:08,787 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:08,787 INFO L681 BuchiCegarLoop]: Abstraction has 2505 states and 3667 transitions. [2021-12-06 17:16:08,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2505 states and 3667 transitions. [2021-12-06 17:16:08,823 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2505 to 2369. [2021-12-06 17:16:08,828 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2369 states, 2369 states have (on average 1.4685521317011396) internal successors, (3479), 2368 states have internal predecessors, (3479), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:08,836 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2369 states to 2369 states and 3479 transitions. [2021-12-06 17:16:08,836 INFO L704 BuchiCegarLoop]: Abstraction has 2369 states and 3479 transitions. [2021-12-06 17:16:08,836 INFO L587 BuchiCegarLoop]: Abstraction has 2369 states and 3479 transitions. [2021-12-06 17:16:08,836 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-06 17:16:08,837 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2369 states and 3479 transitions. [2021-12-06 17:16:08,849 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2279 [2021-12-06 17:16:08,849 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:08,849 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:08,851 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:08,851 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:08,851 INFO L791 eck$LassoCheckResult]: Stem: 11109#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 11065#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 10842#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10630#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10631#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 10708#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10973#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10920#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10921#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10954#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10935#L526 assume !(0 == ~M_E~0); 10936#L526-2 assume !(0 == ~T1_E~0); 10975#L531-1 assume !(0 == ~T2_E~0); 10916#L536-1 assume !(0 == ~T3_E~0); 10917#L541-1 assume !(0 == ~T4_E~0); 10912#L546-1 assume !(0 == ~E_M~0); 10913#L551-1 assume !(0 == ~E_1~0); 10890#L556-1 assume !(0 == ~E_2~0); 10891#L561-1 assume !(0 == ~E_3~0); 10900#L566-1 assume !(0 == ~E_4~0); 10901#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10895#L262 assume !(1 == ~m_pc~0); 10896#L262-2 is_master_triggered_~__retres1~0#1 := 0; 11075#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10753#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 10754#L649 assume !(0 != activate_threads_~tmp~1#1); 11074#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10843#L281 assume !(1 == ~t1_pc~0); 10844#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10755#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10756#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10816#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10817#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10902#L300 assume 1 == ~t2_pc~0; 10903#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11010#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10809#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10810#L665 assume !(0 != activate_threads_~tmp___1~0#1); 10686#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10687#L319 assume !(1 == ~t3_pc~0); 10643#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10644#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10834#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10835#L673 assume !(0 != activate_threads_~tmp___2~0#1); 10665#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10666#L338 assume 1 == ~t4_pc~0; 10811#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10731#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10747#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10772#L681 assume !(0 != activate_threads_~tmp___3~0#1); 10608#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10609#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 11071#L584-2 assume !(1 == ~T1_E~0); 12129#L589-1 assume !(1 == ~T2_E~0); 12127#L594-1 assume !(1 == ~T3_E~0); 12126#L599-1 assume !(1 == ~T4_E~0); 12125#L604-1 assume !(1 == ~E_M~0); 12123#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 12121#L614-1 assume !(1 == ~E_2~0); 12105#L619-1 assume !(1 == ~E_3~0); 12103#L624-1 assume !(1 == ~E_4~0); 12094#L629-1 assume { :end_inline_reset_delta_events } true; 12088#L815-2 [2021-12-06 17:16:08,851 INFO L793 eck$LassoCheckResult]: Loop: 12088#L815-2 assume !false; 12083#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12082#L501 assume !false; 12081#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 12080#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 12075#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 12074#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12072#L440 assume !(0 != eval_~tmp~0#1); 12073#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12494#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12493#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12492#L526-5 assume !(0 == ~T1_E~0); 12491#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12458#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12450#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12443#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12434#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12427#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12423#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12418#L566-3 assume !(0 == ~E_4~0); 12414#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12410#L262-18 assume !(1 == ~m_pc~0); 12407#L262-20 is_master_triggered_~__retres1~0#1 := 0; 12405#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12402#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12399#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12395#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12391#L281-18 assume 1 == ~t1_pc~0; 12386#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12383#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12380#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12377#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 12371#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12368#L300-18 assume 1 == ~t2_pc~0; 12364#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12360#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12356#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12352#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12346#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12342#L319-18 assume !(1 == ~t3_pc~0); 12337#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 12333#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12328#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12324#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12318#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12314#L338-18 assume 1 == ~t4_pc~0; 12309#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12305#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12300#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12296#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12290#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12286#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10863#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12193#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12191#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12189#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12187#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12185#L609-3 assume !(1 == ~E_1~0); 12182#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12180#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12178#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12175#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 12168#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 12163#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 12161#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 12159#L834 assume !(0 == start_simulation_~tmp~3#1); 10852#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 12145#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 12117#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 12114#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 12110#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 12106#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12104#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 12095#L847 assume !(0 != start_simulation_~tmp___0~1#1); 12088#L815-2 [2021-12-06 17:16:08,852 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:08,852 INFO L85 PathProgramCache]: Analyzing trace with hash -1001423999, now seen corresponding path program 1 times [2021-12-06 17:16:08,852 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:08,852 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1410796838] [2021-12-06 17:16:08,852 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:08,852 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:08,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:08,878 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:08,878 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:08,879 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1410796838] [2021-12-06 17:16:08,879 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1410796838] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:08,879 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:08,879 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 17:16:08,879 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [696333019] [2021-12-06 17:16:08,879 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:08,880 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:08,880 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:08,880 INFO L85 PathProgramCache]: Analyzing trace with hash -1859703153, now seen corresponding path program 2 times [2021-12-06 17:16:08,880 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:08,880 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1755105741] [2021-12-06 17:16:08,881 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:08,881 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:08,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:08,905 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:08,905 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:08,905 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1755105741] [2021-12-06 17:16:08,905 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1755105741] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:08,905 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:08,905 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:08,905 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [678365247] [2021-12-06 17:16:08,905 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:08,906 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:08,906 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:08,906 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-06 17:16:08,906 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-06 17:16:08,906 INFO L87 Difference]: Start difference. First operand 2369 states and 3479 transitions. cyclomatic complexity: 1118 Second operand has 5 states, 5 states have (on average 12.4) internal successors, (62), 5 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:09,033 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:09,034 INFO L93 Difference]: Finished difference Result 6387 states and 9353 transitions. [2021-12-06 17:16:09,034 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-06 17:16:09,035 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6387 states and 9353 transitions. [2021-12-06 17:16:09,085 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6180 [2021-12-06 17:16:09,119 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6387 states to 6387 states and 9353 transitions. [2021-12-06 17:16:09,119 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6387 [2021-12-06 17:16:09,123 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6387 [2021-12-06 17:16:09,123 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6387 states and 9353 transitions. [2021-12-06 17:16:09,130 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:09,130 INFO L681 BuchiCegarLoop]: Abstraction has 6387 states and 9353 transitions. [2021-12-06 17:16:09,134 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6387 states and 9353 transitions. [2021-12-06 17:16:09,181 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6387 to 2498. [2021-12-06 17:16:09,185 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2498 states, 2498 states have (on average 1.44435548438751) internal successors, (3608), 2497 states have internal predecessors, (3608), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:09,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2498 states to 2498 states and 3608 transitions. [2021-12-06 17:16:09,191 INFO L704 BuchiCegarLoop]: Abstraction has 2498 states and 3608 transitions. [2021-12-06 17:16:09,191 INFO L587 BuchiCegarLoop]: Abstraction has 2498 states and 3608 transitions. [2021-12-06 17:16:09,191 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-06 17:16:09,191 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2498 states and 3608 transitions. [2021-12-06 17:16:09,198 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2405 [2021-12-06 17:16:09,198 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:09,198 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:09,205 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:09,206 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:09,206 INFO L791 eck$LassoCheckResult]: Stem: 19968#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 19892#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 19618#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19399#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19400#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 19476#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19765#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19705#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19706#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19743#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19717#L526 assume !(0 == ~M_E~0); 19718#L526-2 assume !(0 == ~T1_E~0); 19768#L531-1 assume !(0 == ~T2_E~0); 19701#L536-1 assume !(0 == ~T3_E~0); 19702#L541-1 assume !(0 == ~T4_E~0); 19697#L546-1 assume !(0 == ~E_M~0); 19698#L551-1 assume !(0 == ~E_1~0); 19672#L556-1 assume !(0 == ~E_2~0); 19673#L561-1 assume !(0 == ~E_3~0); 19682#L566-1 assume !(0 == ~E_4~0); 19683#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19677#L262 assume !(1 == ~m_pc~0); 19678#L262-2 is_master_triggered_~__retres1~0#1 := 0; 19908#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19520#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 19521#L649 assume !(0 != activate_threads_~tmp~1#1); 19907#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19619#L281 assume !(1 == ~t1_pc~0); 19620#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19524#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19525#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 19589#L657 assume !(0 != activate_threads_~tmp___0~0#1); 19590#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19685#L300 assume 1 == ~t2_pc~0; 19686#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19813#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19582#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 19583#L665 assume !(0 != activate_threads_~tmp___1~0#1); 19456#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19457#L319 assume !(1 == ~t3_pc~0); 19413#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19414#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19608#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 19609#L673 assume !(0 != activate_threads_~tmp___2~0#1); 19435#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19436#L338 assume 1 == ~t4_pc~0; 19584#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19499#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19516#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19541#L681 assume !(0 != activate_threads_~tmp___3~0#1); 19377#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19378#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 19900#L584-2 assume !(1 == ~T1_E~0); 20343#L589-1 assume !(1 == ~T2_E~0); 19795#L594-1 assume !(1 == ~T3_E~0); 19796#L599-1 assume !(1 == ~T4_E~0); 19411#L604-1 assume !(1 == ~E_M~0); 19412#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 19512#L614-1 assume !(1 == ~E_2~0); 19513#L619-1 assume !(1 == ~E_3~0); 20335#L624-1 assume !(1 == ~E_4~0); 20324#L629-1 assume { :end_inline_reset_delta_events } true; 20318#L815-2 [2021-12-06 17:16:09,206 INFO L793 eck$LassoCheckResult]: Loop: 20318#L815-2 assume !false; 20313#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20312#L501 assume !false; 20311#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 20310#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 20305#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 20304#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 20302#L440 assume !(0 != eval_~tmp~0#1); 20301#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20300#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20297#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20298#L526-5 assume !(0 == ~T1_E~0); 20715#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20714#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20713#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20712#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20711#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20656#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20654#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20625#L566-3 assume !(0 == ~E_4~0); 20623#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20622#L262-18 assume !(1 == ~m_pc~0); 20621#L262-20 is_master_triggered_~__retres1~0#1 := 0; 20620#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20619#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 20618#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20617#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20616#L281-18 assume !(1 == ~t1_pc~0); 20614#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 20612#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20610#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 20608#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 20606#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20604#L300-18 assume 1 == ~t2_pc~0; 20601#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20599#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20597#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20594#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 20592#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20590#L319-18 assume !(1 == ~t3_pc~0); 20555#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 20552#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20550#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20548#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20546#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20543#L338-18 assume 1 == ~t4_pc~0; 20540#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20538#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20537#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20536#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20535#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20490#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20486#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20454#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20419#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20415#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20413#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 20393#L609-3 assume !(1 == ~E_1~0); 20388#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20386#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20370#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20366#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 20362#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 20358#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 20357#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 20356#L834 assume !(0 == start_simulation_~tmp~3#1); 19628#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 20353#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 20350#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 20349#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 20348#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 20347#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20346#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 20325#L847 assume !(0 != start_simulation_~tmp___0~1#1); 20318#L815-2 [2021-12-06 17:16:09,206 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:09,207 INFO L85 PathProgramCache]: Analyzing trace with hash -299824125, now seen corresponding path program 1 times [2021-12-06 17:16:09,207 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:09,207 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1354370316] [2021-12-06 17:16:09,207 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:09,207 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:09,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:09,234 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:09,234 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:09,234 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1354370316] [2021-12-06 17:16:09,234 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1354370316] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:09,234 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:09,234 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:09,235 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1201737911] [2021-12-06 17:16:09,235 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:09,235 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:09,235 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:09,236 INFO L85 PathProgramCache]: Analyzing trace with hash 541821968, now seen corresponding path program 1 times [2021-12-06 17:16:09,236 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:09,236 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [322786655] [2021-12-06 17:16:09,236 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:09,236 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:09,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:09,256 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:09,256 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:09,256 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [322786655] [2021-12-06 17:16:09,256 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [322786655] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:09,256 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:09,257 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:09,257 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1701211163] [2021-12-06 17:16:09,257 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:09,257 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:09,257 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:09,258 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 17:16:09,258 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 17:16:09,258 INFO L87 Difference]: Start difference. First operand 2498 states and 3608 transitions. cyclomatic complexity: 1118 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:09,379 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:09,379 INFO L93 Difference]: Finished difference Result 5780 states and 8246 transitions. [2021-12-06 17:16:09,379 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 17:16:09,380 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5780 states and 8246 transitions. [2021-12-06 17:16:09,411 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 5508 [2021-12-06 17:16:09,448 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5780 states to 5780 states and 8246 transitions. [2021-12-06 17:16:09,449 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5780 [2021-12-06 17:16:09,453 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5780 [2021-12-06 17:16:09,453 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5780 states and 8246 transitions. [2021-12-06 17:16:09,460 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:09,460 INFO L681 BuchiCegarLoop]: Abstraction has 5780 states and 8246 transitions. [2021-12-06 17:16:09,464 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5780 states and 8246 transitions. [2021-12-06 17:16:09,528 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5780 to 4532. [2021-12-06 17:16:09,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4532 states, 4532 states have (on average 1.437334510150044) internal successors, (6514), 4531 states have internal predecessors, (6514), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:09,543 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4532 states to 4532 states and 6514 transitions. [2021-12-06 17:16:09,543 INFO L704 BuchiCegarLoop]: Abstraction has 4532 states and 6514 transitions. [2021-12-06 17:16:09,543 INFO L587 BuchiCegarLoop]: Abstraction has 4532 states and 6514 transitions. [2021-12-06 17:16:09,543 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-06 17:16:09,543 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4532 states and 6514 transitions. [2021-12-06 17:16:09,556 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4436 [2021-12-06 17:16:09,556 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:09,556 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:09,557 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:09,557 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:09,557 INFO L791 eck$LassoCheckResult]: Stem: 28216#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 28158#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 27901#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27685#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27686#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 27760#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28048#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27990#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27991#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28027#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28003#L526 assume !(0 == ~M_E~0); 28004#L526-2 assume !(0 == ~T1_E~0); 28050#L531-1 assume !(0 == ~T2_E~0); 27986#L536-1 assume !(0 == ~T3_E~0); 27987#L541-1 assume !(0 == ~T4_E~0); 27982#L546-1 assume !(0 == ~E_M~0); 27983#L551-1 assume !(0 == ~E_1~0); 27957#L556-1 assume !(0 == ~E_2~0); 27958#L561-1 assume !(0 == ~E_3~0); 27967#L566-1 assume !(0 == ~E_4~0); 27968#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27962#L262 assume !(1 == ~m_pc~0); 27963#L262-2 is_master_triggered_~__retres1~0#1 := 0; 28172#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27806#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 27807#L649 assume !(0 != activate_threads_~tmp~1#1); 28171#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27902#L281 assume !(1 == ~t1_pc~0); 27903#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28186#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28024#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 27873#L657 assume !(0 != activate_threads_~tmp___0~0#1); 27874#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27969#L300 assume !(1 == ~t2_pc~0); 27970#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 28086#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27866#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 27867#L665 assume !(0 != activate_threads_~tmp___1~0#1); 27741#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27742#L319 assume !(1 == ~t3_pc~0); 27699#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 27700#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27892#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 27893#L673 assume !(0 != activate_threads_~tmp___2~0#1); 27720#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27721#L338 assume 1 == ~t4_pc~0; 27868#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27785#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27802#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 27827#L681 assume !(0 != activate_threads_~tmp___3~0#1); 27665#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27666#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 27869#L584-2 assume !(1 == ~T1_E~0); 27870#L589-1 assume !(1 == ~T2_E~0); 28074#L594-1 assume !(1 == ~T3_E~0); 28075#L599-1 assume !(1 == ~T4_E~0); 27697#L604-1 assume !(1 == ~E_M~0); 27698#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 27798#L614-1 assume !(1 == ~E_2~0); 27799#L619-1 assume !(1 == ~E_3~0); 27992#L624-1 assume !(1 == ~E_4~0); 27993#L629-1 assume { :end_inline_reset_delta_events } true; 29763#L815-2 [2021-12-06 17:16:09,557 INFO L793 eck$LassoCheckResult]: Loop: 29763#L815-2 assume !false; 29747#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29745#L501 assume !false; 29743#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 29741#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 29735#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 29731#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 29728#L440 assume !(0 != eval_~tmp~0#1); 29729#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30223#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30222#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30221#L526-5 assume !(0 == ~T1_E~0); 30219#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30217#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30215#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30213#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 30211#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30209#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30207#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30204#L566-3 assume !(0 == ~E_4~0); 30202#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30200#L262-18 assume !(1 == ~m_pc~0); 30199#L262-20 is_master_triggered_~__retres1~0#1 := 0; 30198#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30197#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 30195#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30193#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30186#L281-18 assume !(1 == ~t1_pc~0); 30177#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 30170#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30163#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 30158#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 30146#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30145#L300-18 assume !(1 == ~t2_pc~0); 28877#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 30144#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30142#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 30140#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30138#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30136#L319-18 assume !(1 == ~t3_pc~0); 30133#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 30131#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30129#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 30126#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30124#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30122#L338-18 assume 1 == ~t4_pc~0; 30092#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30090#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30088#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30085#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30083#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30077#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29524#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30065#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30061#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30055#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30050#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30043#L609-3 assume !(1 == ~E_1~0); 30037#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30031#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30022#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29502#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 30016#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 30011#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 30009#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 30005#L834 assume !(0 == start_simulation_~tmp~3#1); 30002#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 29953#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 29949#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 29947#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 29945#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 29936#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29774#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 29765#L847 assume !(0 != start_simulation_~tmp___0~1#1); 29763#L815-2 [2021-12-06 17:16:09,557 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:09,558 INFO L85 PathProgramCache]: Analyzing trace with hash -1271498812, now seen corresponding path program 1 times [2021-12-06 17:16:09,558 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:09,558 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [851104829] [2021-12-06 17:16:09,558 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:09,558 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:09,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:09,576 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:09,577 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:09,577 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [851104829] [2021-12-06 17:16:09,577 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [851104829] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:09,577 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:09,577 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 17:16:09,577 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [196233340] [2021-12-06 17:16:09,577 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:09,577 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:09,578 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:09,578 INFO L85 PathProgramCache]: Analyzing trace with hash 56647249, now seen corresponding path program 1 times [2021-12-06 17:16:09,578 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:09,578 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [510604711] [2021-12-06 17:16:09,578 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:09,578 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:09,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:09,597 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:09,597 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:09,598 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [510604711] [2021-12-06 17:16:09,598 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [510604711] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:09,598 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:09,598 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:09,598 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1955690933] [2021-12-06 17:16:09,598 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:09,598 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:09,599 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:09,599 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:16:09,599 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:16:09,599 INFO L87 Difference]: Start difference. First operand 4532 states and 6514 transitions. cyclomatic complexity: 1990 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:09,661 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:09,661 INFO L93 Difference]: Finished difference Result 8275 states and 11847 transitions. [2021-12-06 17:16:09,661 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:16:09,662 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8275 states and 11847 transitions. [2021-12-06 17:16:09,691 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8140 [2021-12-06 17:16:09,743 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8275 states to 8275 states and 11847 transitions. [2021-12-06 17:16:09,743 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8275 [2021-12-06 17:16:09,748 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8275 [2021-12-06 17:16:09,748 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8275 states and 11847 transitions. [2021-12-06 17:16:09,756 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:09,757 INFO L681 BuchiCegarLoop]: Abstraction has 8275 states and 11847 transitions. [2021-12-06 17:16:09,762 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8275 states and 11847 transitions. [2021-12-06 17:16:09,872 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8275 to 8243. [2021-12-06 17:16:09,886 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8243 states, 8243 states have (on average 1.4333373771685065) internal successors, (11815), 8242 states have internal predecessors, (11815), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:09,911 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8243 states to 8243 states and 11815 transitions. [2021-12-06 17:16:09,911 INFO L704 BuchiCegarLoop]: Abstraction has 8243 states and 11815 transitions. [2021-12-06 17:16:09,911 INFO L587 BuchiCegarLoop]: Abstraction has 8243 states and 11815 transitions. [2021-12-06 17:16:09,912 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-06 17:16:09,912 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8243 states and 11815 transitions. [2021-12-06 17:16:09,936 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8108 [2021-12-06 17:16:09,937 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:09,937 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:09,938 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:09,938 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:09,938 INFO L791 eck$LassoCheckResult]: Stem: 40988#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 40943#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 40710#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40499#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 40500#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 40576#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40843#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40789#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40790#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40825#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40803#L526 assume !(0 == ~M_E~0); 40804#L526-2 assume !(0 == ~T1_E~0); 40845#L531-1 assume !(0 == ~T2_E~0); 40785#L536-1 assume !(0 == ~T3_E~0); 40786#L541-1 assume !(0 == ~T4_E~0); 40781#L546-1 assume !(0 == ~E_M~0); 40782#L551-1 assume !(0 == ~E_1~0); 40758#L556-1 assume !(0 == ~E_2~0); 40759#L561-1 assume !(0 == ~E_3~0); 40768#L566-1 assume !(0 == ~E_4~0); 40769#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40763#L262 assume !(1 == ~m_pc~0); 40764#L262-2 is_master_triggered_~__retres1~0#1 := 0; 40950#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40622#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 40623#L649 assume !(0 != activate_threads_~tmp~1#1); 40949#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40711#L281 assume !(1 == ~t1_pc~0); 40712#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 40958#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40823#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 40684#L657 assume !(0 != activate_threads_~tmp___0~0#1); 40685#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40770#L300 assume !(1 == ~t2_pc~0); 40771#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 40879#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40679#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 40680#L665 assume !(0 != activate_threads_~tmp___1~0#1); 40554#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40555#L319 assume !(1 == ~t3_pc~0); 40512#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 40513#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40701#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 40702#L673 assume !(0 != activate_threads_~tmp___2~0#1); 40533#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40534#L338 assume !(1 == ~t4_pc~0); 40599#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 40600#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40616#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 40641#L681 assume !(0 != activate_threads_~tmp___3~0#1); 40479#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40480#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 40681#L584-2 assume !(1 == ~T1_E~0); 40639#L589-1 assume !(1 == ~T2_E~0); 40640#L594-1 assume !(1 == ~T3_E~0); 40735#L599-1 assume !(1 == ~T4_E~0); 40511#L604-1 assume !(1 == ~E_M~0); 40495#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 40496#L614-1 assume !(1 == ~E_2~0); 40613#L619-1 assume !(1 == ~E_3~0); 40700#L624-1 assume !(1 == ~E_4~0); 40791#L629-1 assume { :end_inline_reset_delta_events } true; 44090#L815-2 [2021-12-06 17:16:09,938 INFO L793 eck$LassoCheckResult]: Loop: 44090#L815-2 assume !false; 44051#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44049#L501 assume !false; 44047#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 44045#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 44039#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 44037#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 44034#L440 assume !(0 != eval_~tmp~0#1); 44035#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 44255#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 44253#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44251#L526-5 assume !(0 == ~T1_E~0); 44249#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 44247#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44245#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44243#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 44242#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 44239#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 44237#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 44235#L566-3 assume !(0 == ~E_4~0); 44234#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44233#L262-18 assume !(1 == ~m_pc~0); 44232#L262-20 is_master_triggered_~__retres1~0#1 := 0; 44231#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44230#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 44229#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 44227#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44225#L281-18 assume !(1 == ~t1_pc~0); 44224#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 44228#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44226#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 44217#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 44215#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44213#L300-18 assume !(1 == ~t2_pc~0); 41300#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 44209#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44207#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 44205#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 44203#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44201#L319-18 assume !(1 == ~t3_pc~0); 44198#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 44196#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44194#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 44192#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 44190#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44188#L338-18 assume !(1 == ~t4_pc~0); 44186#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 44184#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44182#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 44180#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44178#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44176#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 41161#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 41158#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44173#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44172#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 44171#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 44170#L609-3 assume !(1 == ~E_1~0); 44169#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44168#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 44167#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 42262#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 44158#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 44154#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 44153#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 44151#L834 assume !(0 == start_simulation_~tmp~3#1); 44149#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 44106#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 44102#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 44099#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 44097#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 44095#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 44094#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 44092#L847 assume !(0 != start_simulation_~tmp___0~1#1); 44090#L815-2 [2021-12-06 17:16:09,939 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:09,939 INFO L85 PathProgramCache]: Analyzing trace with hash 843496709, now seen corresponding path program 1 times [2021-12-06 17:16:09,939 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:09,939 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [151550358] [2021-12-06 17:16:09,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:09,939 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:09,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:09,958 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:09,958 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:09,959 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [151550358] [2021-12-06 17:16:09,959 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [151550358] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:09,959 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:09,959 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 17:16:09,959 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1148770640] [2021-12-06 17:16:09,959 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:09,960 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:09,960 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:09,960 INFO L85 PathProgramCache]: Analyzing trace with hash -915027438, now seen corresponding path program 1 times [2021-12-06 17:16:09,960 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:09,960 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [432252836] [2021-12-06 17:16:09,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:09,961 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:09,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:10,003 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:10,003 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:10,003 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [432252836] [2021-12-06 17:16:10,003 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [432252836] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:10,003 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:10,003 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:10,003 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [821035383] [2021-12-06 17:16:10,003 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:10,004 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:10,004 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:10,004 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:16:10,004 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:16:10,004 INFO L87 Difference]: Start difference. First operand 8243 states and 11815 transitions. cyclomatic complexity: 3588 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:10,041 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:10,041 INFO L93 Difference]: Finished difference Result 10410 states and 14896 transitions. [2021-12-06 17:16:10,041 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:16:10,042 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10410 states and 14896 transitions. [2021-12-06 17:16:10,075 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 10272 [2021-12-06 17:16:10,117 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10410 states to 10410 states and 14896 transitions. [2021-12-06 17:16:10,117 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10410 [2021-12-06 17:16:10,123 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10410 [2021-12-06 17:16:10,123 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10410 states and 14896 transitions. [2021-12-06 17:16:10,132 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:10,132 INFO L681 BuchiCegarLoop]: Abstraction has 10410 states and 14896 transitions. [2021-12-06 17:16:10,140 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10410 states and 14896 transitions. [2021-12-06 17:16:10,202 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10410 to 4727. [2021-12-06 17:16:10,210 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4727 states, 4727 states have (on average 1.4319864607573514) internal successors, (6769), 4726 states have internal predecessors, (6769), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:10,220 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4727 states to 4727 states and 6769 transitions. [2021-12-06 17:16:10,220 INFO L704 BuchiCegarLoop]: Abstraction has 4727 states and 6769 transitions. [2021-12-06 17:16:10,220 INFO L587 BuchiCegarLoop]: Abstraction has 4727 states and 6769 transitions. [2021-12-06 17:16:10,220 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-06 17:16:10,220 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4727 states and 6769 transitions. [2021-12-06 17:16:10,248 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4636 [2021-12-06 17:16:10,248 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:10,248 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:10,249 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:10,250 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:10,250 INFO L791 eck$LassoCheckResult]: Stem: 59658#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 59610#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 59371#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 59159#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 59160#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 59234#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 59503#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 59451#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 59452#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 59486#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 59463#L526 assume !(0 == ~M_E~0); 59464#L526-2 assume !(0 == ~T1_E~0); 59505#L531-1 assume !(0 == ~T2_E~0); 59447#L536-1 assume !(0 == ~T3_E~0); 59448#L541-1 assume !(0 == ~T4_E~0); 59443#L546-1 assume !(0 == ~E_M~0); 59444#L551-1 assume !(0 == ~E_1~0); 59421#L556-1 assume !(0 == ~E_2~0); 59422#L561-1 assume !(0 == ~E_3~0); 59431#L566-1 assume !(0 == ~E_4~0); 59432#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59426#L262 assume !(1 == ~m_pc~0); 59427#L262-2 is_master_triggered_~__retres1~0#1 := 0; 59625#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59282#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 59283#L649 assume !(0 != activate_threads_~tmp~1#1); 59624#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59372#L281 assume !(1 == ~t1_pc~0); 59373#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 59636#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59483#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 59345#L657 assume !(0 != activate_threads_~tmp___0~0#1); 59346#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59433#L300 assume !(1 == ~t2_pc~0); 59434#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 59543#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59340#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 59341#L665 assume !(0 != activate_threads_~tmp___1~0#1); 59214#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59215#L319 assume !(1 == ~t3_pc~0); 59172#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 59173#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59363#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 59364#L673 assume !(0 != activate_threads_~tmp___2~0#1); 59193#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59194#L338 assume !(1 == ~t4_pc~0); 59257#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 59258#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59276#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 59301#L681 assume !(0 != activate_threads_~tmp___3~0#1); 59139#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59140#L584 assume !(1 == ~M_E~0); 59342#L584-2 assume !(1 == ~T1_E~0); 59299#L589-1 assume !(1 == ~T2_E~0); 59300#L594-1 assume !(1 == ~T3_E~0); 59398#L599-1 assume !(1 == ~T4_E~0); 59171#L604-1 assume !(1 == ~E_M~0); 59155#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 59156#L614-1 assume !(1 == ~E_2~0); 59273#L619-1 assume !(1 == ~E_3~0); 59362#L624-1 assume !(1 == ~E_4~0); 59453#L629-1 assume { :end_inline_reset_delta_events } true; 59641#L815-2 [2021-12-06 17:16:10,250 INFO L793 eck$LassoCheckResult]: Loop: 59641#L815-2 assume !false; 63596#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 63595#L501 assume !false; 59608#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 59609#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 59278#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 59477#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 59478#L440 assume !(0 != eval_~tmp~0#1); 59648#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 63823#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 63822#L526-3 assume !(0 == ~M_E~0); 63821#L526-5 assume !(0 == ~T1_E~0); 63820#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 63819#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 63818#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 63817#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 63816#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 63815#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 63814#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 63813#L566-3 assume !(0 == ~E_4~0); 63812#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 63811#L262-18 assume !(1 == ~m_pc~0); 63810#L262-20 is_master_triggered_~__retres1~0#1 := 0; 63809#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59271#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 59272#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 59178#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59179#L281-18 assume !(1 == ~t1_pc~0); 59418#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 59436#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59437#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 59560#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 59556#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59557#L300-18 assume !(1 == ~t2_pc~0); 62206#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 62204#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62202#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 62200#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 62198#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62196#L319-18 assume !(1 == ~t3_pc~0); 62194#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 62192#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62190#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 62188#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 62186#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62184#L338-18 assume !(1 == ~t4_pc~0); 62182#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 62180#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62178#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 62177#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 62170#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62160#L584-3 assume !(1 == ~M_E~0); 59823#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 59821#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 59819#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 59817#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 59815#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 59813#L609-3 assume !(1 == ~E_1~0); 59811#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 59809#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 59807#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 59805#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 59802#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 59778#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 59773#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 59767#L834 assume !(0 == start_simulation_~tmp~3#1); 59768#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 63727#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 63723#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 63721#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 63719#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 63628#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 63608#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 63602#L847 assume !(0 != start_simulation_~tmp___0~1#1); 59641#L815-2 [2021-12-06 17:16:10,250 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:10,251 INFO L85 PathProgramCache]: Analyzing trace with hash 1544561287, now seen corresponding path program 1 times [2021-12-06 17:16:10,251 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:10,251 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2075431270] [2021-12-06 17:16:10,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:10,251 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:10,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:10,286 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:10,286 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:10,286 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2075431270] [2021-12-06 17:16:10,286 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2075431270] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:10,286 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:10,286 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:10,286 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [406134357] [2021-12-06 17:16:10,287 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:10,287 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:10,287 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:10,287 INFO L85 PathProgramCache]: Analyzing trace with hash 1520108626, now seen corresponding path program 1 times [2021-12-06 17:16:10,287 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:10,288 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1642441682] [2021-12-06 17:16:10,288 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:10,288 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:10,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:10,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:10,307 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:10,307 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1642441682] [2021-12-06 17:16:10,307 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1642441682] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:10,307 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:10,307 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:10,307 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1199244198] [2021-12-06 17:16:10,307 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:10,307 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:10,308 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:10,308 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 17:16:10,308 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 17:16:10,308 INFO L87 Difference]: Start difference. First operand 4727 states and 6769 transitions. cyclomatic complexity: 2046 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:10,384 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:10,384 INFO L93 Difference]: Finished difference Result 6455 states and 9080 transitions. [2021-12-06 17:16:10,384 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 17:16:10,385 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6455 states and 9080 transitions. [2021-12-06 17:16:10,416 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 6270 [2021-12-06 17:16:10,434 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6455 states to 6455 states and 9080 transitions. [2021-12-06 17:16:10,434 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6455 [2021-12-06 17:16:10,437 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6455 [2021-12-06 17:16:10,437 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6455 states and 9080 transitions. [2021-12-06 17:16:10,441 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:10,442 INFO L681 BuchiCegarLoop]: Abstraction has 6455 states and 9080 transitions. [2021-12-06 17:16:10,446 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6455 states and 9080 transitions. [2021-12-06 17:16:10,492 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6455 to 5314. [2021-12-06 17:16:10,498 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5314 states, 5314 states have (on average 1.415506210011291) internal successors, (7522), 5313 states have internal predecessors, (7522), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:10,509 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5314 states to 5314 states and 7522 transitions. [2021-12-06 17:16:10,509 INFO L704 BuchiCegarLoop]: Abstraction has 5314 states and 7522 transitions. [2021-12-06 17:16:10,509 INFO L587 BuchiCegarLoop]: Abstraction has 5314 states and 7522 transitions. [2021-12-06 17:16:10,509 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-06 17:16:10,509 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5314 states and 7522 transitions. [2021-12-06 17:16:10,522 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5180 [2021-12-06 17:16:10,522 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:10,522 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:10,523 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:10,523 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:10,523 INFO L791 eck$LassoCheckResult]: Stem: 70831#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 70791#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 70563#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 70351#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 70352#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 70427#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 70690#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 70640#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 70641#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 70674#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 70653#L526 assume !(0 == ~M_E~0); 70654#L526-2 assume !(0 == ~T1_E~0); 70692#L531-1 assume !(0 == ~T2_E~0); 70636#L536-1 assume !(0 == ~T3_E~0); 70637#L541-1 assume !(0 == ~T4_E~0); 70632#L546-1 assume !(0 == ~E_M~0); 70633#L551-1 assume 0 == ~E_1~0;~E_1~0 := 1; 70702#L556-1 assume !(0 == ~E_2~0); 70651#L561-1 assume !(0 == ~E_3~0); 70621#L566-1 assume !(0 == ~E_4~0); 70622#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 70796#L262 assume !(1 == ~m_pc~0); 70871#L262-2 is_master_triggered_~__retres1~0#1 := 0; 70870#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 70474#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 70475#L649 assume !(0 != activate_threads_~tmp~1#1); 70832#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 70564#L281 assume !(1 == ~t1_pc~0); 70565#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 70476#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 70477#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 70865#L657 assume !(0 != activate_threads_~tmp___0~0#1); 70864#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 70863#L300 assume !(1 == ~t2_pc~0); 70862#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 70861#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 70860#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 70859#L665 assume !(0 != activate_threads_~tmp___1~0#1); 70858#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 70857#L319 assume !(1 == ~t3_pc~0); 70855#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 70854#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 70853#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 70852#L673 assume !(0 != activate_threads_~tmp___2~0#1); 70851#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 70850#L338 assume !(1 == ~t4_pc~0); 70849#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 70848#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 70847#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 70846#L681 assume !(0 != activate_threads_~tmp___3~0#1); 70845#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 70844#L584 assume !(1 == ~M_E~0); 70843#L584-2 assume !(1 == ~T1_E~0); 70842#L589-1 assume !(1 == ~T2_E~0); 70841#L594-1 assume !(1 == ~T3_E~0); 70840#L599-1 assume !(1 == ~T4_E~0); 70839#L604-1 assume !(1 == ~E_M~0); 70838#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 70348#L614-1 assume !(1 == ~E_2~0); 70465#L619-1 assume !(1 == ~E_3~0); 70555#L624-1 assume !(1 == ~E_4~0); 70642#L629-1 assume { :end_inline_reset_delta_events } true; 70662#L815-2 [2021-12-06 17:16:10,524 INFO L793 eck$LassoCheckResult]: Loop: 70662#L815-2 assume !false; 70663#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 70782#L501 assume !false; 70789#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 70790#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 70470#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 70826#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 70821#L440 assume !(0 != eval_~tmp~0#1); 70822#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 75618#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 75617#L526-3 assume !(0 == ~M_E~0); 75616#L526-5 assume !(0 == ~T1_E~0); 75615#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 75614#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 75613#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 75612#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 70833#L551-3 assume !(0 == ~E_1~0); 70835#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 75534#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 75532#L566-3 assume !(0 == ~E_4~0); 75530#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 75528#L262-18 assume !(1 == ~m_pc~0); 75526#L262-20 is_master_triggered_~__retres1~0#1 := 0; 75524#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75522#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 75520#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 75519#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 75515#L281-18 assume !(1 == ~t1_pc~0); 75512#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 75510#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 75508#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 75503#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 75500#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 70774#L300-18 assume !(1 == ~t2_pc~0); 70775#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 75632#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75630#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 75628#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 70757#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 70478#L319-18 assume 1 == ~t3_pc~0; 70480#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 70485#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 70501#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 70537#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 70661#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 70561#L338-18 assume !(1 == ~t4_pc~0); 70562#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 70520#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 70521#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 70391#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 70392#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 70584#L584-3 assume !(1 == ~M_E~0); 70585#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 70387#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 70388#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 70576#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 70599#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 70600#L609-3 assume !(1 == ~E_1~0); 70660#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 70379#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 70380#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 70673#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 70703#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 70457#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 70458#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 70507#L834 assume !(0 == start_simulation_~tmp~3#1); 70509#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 75642#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 70677#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 70678#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 70710#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 70743#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 70643#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 70644#L847 assume !(0 != start_simulation_~tmp___0~1#1); 70662#L815-2 [2021-12-06 17:16:10,524 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:10,524 INFO L85 PathProgramCache]: Analyzing trace with hash -383711415, now seen corresponding path program 1 times [2021-12-06 17:16:10,524 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:10,524 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2114501945] [2021-12-06 17:16:10,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:10,525 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:10,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:10,543 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:10,543 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:10,543 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2114501945] [2021-12-06 17:16:10,544 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2114501945] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:10,544 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:10,544 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:10,544 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1586991634] [2021-12-06 17:16:10,544 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:10,544 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:10,544 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:10,545 INFO L85 PathProgramCache]: Analyzing trace with hash 902388623, now seen corresponding path program 1 times [2021-12-06 17:16:10,545 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:10,545 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1144155246] [2021-12-06 17:16:10,545 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:10,545 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:10,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:10,568 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:10,568 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:10,569 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1144155246] [2021-12-06 17:16:10,569 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1144155246] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:10,569 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:10,569 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 17:16:10,569 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1216783423] [2021-12-06 17:16:10,569 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:10,570 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:10,570 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:10,570 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 17:16:10,570 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 17:16:10,570 INFO L87 Difference]: Start difference. First operand 5314 states and 7522 transitions. cyclomatic complexity: 2212 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:10,648 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:10,648 INFO L93 Difference]: Finished difference Result 5406 states and 7596 transitions. [2021-12-06 17:16:10,649 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 17:16:10,649 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5406 states and 7596 transitions. [2021-12-06 17:16:10,670 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5302 [2021-12-06 17:16:10,687 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5406 states to 5406 states and 7596 transitions. [2021-12-06 17:16:10,687 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5406 [2021-12-06 17:16:10,690 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5406 [2021-12-06 17:16:10,690 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5406 states and 7596 transitions. [2021-12-06 17:16:10,693 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:10,693 INFO L681 BuchiCegarLoop]: Abstraction has 5406 states and 7596 transitions. [2021-12-06 17:16:10,697 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5406 states and 7596 transitions. [2021-12-06 17:16:10,728 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5406 to 4508. [2021-12-06 17:16:10,733 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4508 states, 4508 states have (on average 1.409494232475599) internal successors, (6354), 4507 states have internal predecessors, (6354), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:10,741 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4508 states to 4508 states and 6354 transitions. [2021-12-06 17:16:10,741 INFO L704 BuchiCegarLoop]: Abstraction has 4508 states and 6354 transitions. [2021-12-06 17:16:10,741 INFO L587 BuchiCegarLoop]: Abstraction has 4508 states and 6354 transitions. [2021-12-06 17:16:10,741 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-06 17:16:10,742 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4508 states and 6354 transitions. [2021-12-06 17:16:10,750 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4420 [2021-12-06 17:16:10,750 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:10,750 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:10,751 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:10,751 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:10,751 INFO L791 eck$LassoCheckResult]: Stem: 81574#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 81531#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 81293#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 81083#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 81084#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 81159#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 81417#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 81373#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 81374#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 81402#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 81383#L526 assume !(0 == ~M_E~0); 81384#L526-2 assume !(0 == ~T1_E~0); 81419#L531-1 assume !(0 == ~T2_E~0); 81369#L536-1 assume !(0 == ~T3_E~0); 81370#L541-1 assume !(0 == ~T4_E~0); 81365#L546-1 assume !(0 == ~E_M~0); 81366#L551-1 assume !(0 == ~E_1~0); 81343#L556-1 assume !(0 == ~E_2~0); 81344#L561-1 assume !(0 == ~E_3~0); 81353#L566-1 assume !(0 == ~E_4~0); 81354#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 81348#L262 assume !(1 == ~m_pc~0); 81349#L262-2 is_master_triggered_~__retres1~0#1 := 0; 81541#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 81202#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 81203#L649 assume !(0 != activate_threads_~tmp~1#1); 81537#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 81296#L281 assume !(1 == ~t1_pc~0); 81297#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 81206#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 81207#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 81268#L657 assume !(0 != activate_threads_~tmp___0~0#1); 81269#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 81355#L300 assume !(1 == ~t2_pc~0); 81356#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 81458#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 81263#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 81264#L665 assume !(0 != activate_threads_~tmp___1~0#1); 81138#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81139#L319 assume !(1 == ~t3_pc~0); 81096#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 81097#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 81288#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 81289#L673 assume !(0 != activate_threads_~tmp___2~0#1); 81117#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 81118#L338 assume !(1 == ~t4_pc~0); 81181#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 81182#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81196#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 81223#L681 assume !(0 != activate_threads_~tmp___3~0#1); 81063#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81064#L584 assume !(1 == ~M_E~0); 81265#L584-2 assume !(1 == ~T1_E~0); 81221#L589-1 assume !(1 == ~T2_E~0); 81222#L594-1 assume !(1 == ~T3_E~0); 81319#L599-1 assume !(1 == ~T4_E~0); 81095#L604-1 assume !(1 == ~E_M~0); 81079#L609-1 assume !(1 == ~E_1~0); 81080#L614-1 assume !(1 == ~E_2~0); 81195#L619-1 assume !(1 == ~E_3~0); 81287#L624-1 assume !(1 == ~E_4~0); 81375#L629-1 assume { :end_inline_reset_delta_events } true; 81392#L815-2 [2021-12-06 17:16:10,751 INFO L793 eck$LassoCheckResult]: Loop: 81392#L815-2 assume !false; 81394#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 81521#L501 assume !false; 81529#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 81530#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 85244#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 85242#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 85240#L440 assume !(0 != eval_~tmp~0#1); 81554#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 81532#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 81320#L526-3 assume !(0 == ~M_E~0); 81321#L526-5 assume !(0 == ~T1_E~0); 85568#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 85567#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 85565#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 85563#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 85561#L551-3 assume !(0 == ~E_1~0); 85559#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 85557#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 85555#L566-3 assume !(0 == ~E_4~0); 85553#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 85551#L262-18 assume !(1 == ~m_pc~0); 85545#L262-20 is_master_triggered_~__retres1~0#1 := 0; 85544#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 85537#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 81535#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 81102#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 81103#L281-18 assume !(1 == ~t1_pc~0); 85469#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 85468#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 85467#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 85466#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 85365#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 83065#L300-18 assume !(1 == ~t2_pc~0); 83063#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 83061#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 83059#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 83057#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 83054#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 83052#L319-18 assume !(1 == ~t3_pc~0); 83049#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 83047#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 83045#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 83043#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 83040#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 83038#L338-18 assume !(1 == ~t4_pc~0); 83036#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 83034#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 83032#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 83031#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 83026#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 83024#L584-3 assume !(1 == ~M_E~0); 82946#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 83021#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 83015#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 83008#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 83005#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 83002#L609-3 assume !(1 == ~E_1~0); 82995#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 82992#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 82989#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 82986#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 82979#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 82970#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 82968#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 81740#L834 assume !(0 == start_simulation_~tmp~3#1); 81305#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 81410#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 81368#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 81406#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 81477#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 81478#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 81376#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 81377#L847 assume !(0 != start_simulation_~tmp___0~1#1); 81392#L815-2 [2021-12-06 17:16:10,752 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:10,752 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 1 times [2021-12-06 17:16:10,752 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:10,752 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [235135082] [2021-12-06 17:16:10,752 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:10,752 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:10,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:10,758 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:16:10,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:10,785 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:16:10,786 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:10,786 INFO L85 PathProgramCache]: Analyzing trace with hash 1953837712, now seen corresponding path program 1 times [2021-12-06 17:16:10,786 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:10,786 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1705834545] [2021-12-06 17:16:10,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:10,786 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:10,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:10,807 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:10,807 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:10,807 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1705834545] [2021-12-06 17:16:10,807 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1705834545] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:10,807 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:10,807 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 17:16:10,807 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1853121415] [2021-12-06 17:16:10,808 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:10,808 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:10,808 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:10,808 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-06 17:16:10,808 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-06 17:16:10,809 INFO L87 Difference]: Start difference. First operand 4508 states and 6354 transitions. cyclomatic complexity: 1850 Second operand has 5 states, 5 states have (on average 14.8) internal successors, (74), 5 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:10,881 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:10,881 INFO L93 Difference]: Finished difference Result 7968 states and 11062 transitions. [2021-12-06 17:16:10,881 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-06 17:16:10,881 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7968 states and 11062 transitions. [2021-12-06 17:16:10,904 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7856 [2021-12-06 17:16:10,922 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7968 states to 7968 states and 11062 transitions. [2021-12-06 17:16:10,922 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7968 [2021-12-06 17:16:10,926 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7968 [2021-12-06 17:16:10,926 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7968 states and 11062 transitions. [2021-12-06 17:16:10,930 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:10,930 INFO L681 BuchiCegarLoop]: Abstraction has 7968 states and 11062 transitions. [2021-12-06 17:16:10,936 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7968 states and 11062 transitions. [2021-12-06 17:16:10,981 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7968 to 4556. [2021-12-06 17:16:10,985 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4556 states, 4556 states have (on average 1.4051799824407374) internal successors, (6402), 4555 states have internal predecessors, (6402), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:10,993 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4556 states to 4556 states and 6402 transitions. [2021-12-06 17:16:10,993 INFO L704 BuchiCegarLoop]: Abstraction has 4556 states and 6402 transitions. [2021-12-06 17:16:10,993 INFO L587 BuchiCegarLoop]: Abstraction has 4556 states and 6402 transitions. [2021-12-06 17:16:10,993 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-06 17:16:10,993 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4556 states and 6402 transitions. [2021-12-06 17:16:11,003 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4468 [2021-12-06 17:16:11,003 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:11,003 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:11,004 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:11,004 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:11,005 INFO L791 eck$LassoCheckResult]: Stem: 94067#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 94025#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 93788#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 93575#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 93576#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 93652#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 93919#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 93867#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 93868#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 93899#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 93878#L526 assume !(0 == ~M_E~0); 93879#L526-2 assume !(0 == ~T1_E~0); 93921#L531-1 assume !(0 == ~T2_E~0); 93863#L536-1 assume !(0 == ~T3_E~0); 93864#L541-1 assume !(0 == ~T4_E~0); 93859#L546-1 assume !(0 == ~E_M~0); 93860#L551-1 assume !(0 == ~E_1~0); 93838#L556-1 assume !(0 == ~E_2~0); 93839#L561-1 assume !(0 == ~E_3~0); 93848#L566-1 assume !(0 == ~E_4~0); 93849#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 93843#L262 assume !(1 == ~m_pc~0); 93844#L262-2 is_master_triggered_~__retres1~0#1 := 0; 94040#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 93698#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 93699#L649 assume !(0 != activate_threads_~tmp~1#1); 94036#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 93791#L281 assume !(1 == ~t1_pc~0); 93792#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 93702#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 93703#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 93761#L657 assume !(0 != activate_threads_~tmp___0~0#1); 93762#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 93850#L300 assume !(1 == ~t2_pc~0); 93851#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 93959#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 93756#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 93757#L665 assume !(0 != activate_threads_~tmp___1~0#1); 93630#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 93631#L319 assume !(1 == ~t3_pc~0); 93588#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 93589#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 93783#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 93784#L673 assume !(0 != activate_threads_~tmp___2~0#1); 93609#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 93610#L338 assume !(1 == ~t4_pc~0); 93675#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 93676#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 93692#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 93719#L681 assume !(0 != activate_threads_~tmp___3~0#1); 93555#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 93556#L584 assume !(1 == ~M_E~0); 93758#L584-2 assume !(1 == ~T1_E~0); 93717#L589-1 assume !(1 == ~T2_E~0); 93718#L594-1 assume !(1 == ~T3_E~0); 93812#L599-1 assume !(1 == ~T4_E~0); 93587#L604-1 assume !(1 == ~E_M~0); 93571#L609-1 assume !(1 == ~E_1~0); 93572#L614-1 assume !(1 == ~E_2~0); 93691#L619-1 assume !(1 == ~E_3~0); 93782#L624-1 assume !(1 == ~E_4~0); 93869#L629-1 assume { :end_inline_reset_delta_events } true; 94051#L815-2 [2021-12-06 17:16:11,005 INFO L793 eck$LassoCheckResult]: Loop: 94051#L815-2 assume !false; 98047#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 94017#L501 assume !false; 97970#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 97835#L398 assume !(0 == ~m_st~0); 97832#L402 assume !(0 == ~t1_st~0); 97833#L406 assume !(0 == ~t2_st~0); 97834#L410 assume !(0 == ~t3_st~0); 97830#L414 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 97831#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 95286#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 95287#L440 assume !(0 != eval_~tmp~0#1); 97827#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 97826#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 93813#L526-3 assume !(0 == ~M_E~0); 93814#L526-5 assume !(0 == ~T1_E~0); 93951#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 97943#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 93581#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 93582#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 94069#L551-3 assume !(0 == ~E_1~0); 94070#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 93927#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 93928#L566-3 assume !(0 == ~E_4~0); 93992#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 93950#L262-18 assume !(1 == ~m_pc~0); 93803#L262-20 is_master_triggered_~__retres1~0#1 := 0; 93804#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 93689#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 93690#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 93594#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 93595#L281-18 assume !(1 == ~t1_pc~0); 93954#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 93955#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 93979#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 93980#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 97492#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 97493#L300-18 assume !(1 == ~t2_pc~0); 97410#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 97490#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 97485#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 97486#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 97479#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 97480#L319-18 assume 1 == ~t3_pc~0; 97473#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 97472#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 97466#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 97467#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 93886#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 93887#L338-18 assume !(1 == ~t4_pc~0); 93832#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 93746#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 93747#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 93615#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 93616#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 93808#L584-3 assume !(1 == ~M_E~0); 93809#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 93611#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 93612#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 93801#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 93823#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 93824#L609-3 assume !(1 == ~E_1~0); 93885#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 93603#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 93604#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 93900#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 93932#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 98076#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 98074#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 98073#L834 assume !(0 == start_simulation_~tmp~3#1); 98071#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 98068#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 98065#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 98064#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 98063#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 98062#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 98061#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 98055#L847 assume !(0 != start_simulation_~tmp___0~1#1); 94051#L815-2 [2021-12-06 17:16:11,005 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:11,005 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 2 times [2021-12-06 17:16:11,005 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:11,005 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1808566779] [2021-12-06 17:16:11,005 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:11,006 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:11,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:11,012 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:16:11,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:11,028 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:16:11,028 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:11,029 INFO L85 PathProgramCache]: Analyzing trace with hash -209447037, now seen corresponding path program 1 times [2021-12-06 17:16:11,029 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:11,029 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [311639587] [2021-12-06 17:16:11,029 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:11,029 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:11,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:11,054 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:11,054 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:11,054 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [311639587] [2021-12-06 17:16:11,054 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [311639587] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:11,054 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:11,054 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 17:16:11,055 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [628911304] [2021-12-06 17:16:11,055 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:11,055 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:11,055 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:11,055 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-06 17:16:11,055 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-06 17:16:11,055 INFO L87 Difference]: Start difference. First operand 4556 states and 6402 transitions. cyclomatic complexity: 1850 Second operand has 5 states, 5 states have (on average 15.6) internal successors, (78), 5 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:11,165 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:11,166 INFO L93 Difference]: Finished difference Result 15184 states and 21062 transitions. [2021-12-06 17:16:11,166 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-06 17:16:11,166 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15184 states and 21062 transitions. [2021-12-06 17:16:11,210 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 15024 [2021-12-06 17:16:11,257 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15184 states to 15184 states and 21062 transitions. [2021-12-06 17:16:11,257 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15184 [2021-12-06 17:16:11,263 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15184 [2021-12-06 17:16:11,263 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15184 states and 21062 transitions. [2021-12-06 17:16:11,269 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:11,269 INFO L681 BuchiCegarLoop]: Abstraction has 15184 states and 21062 transitions. [2021-12-06 17:16:11,275 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15184 states and 21062 transitions. [2021-12-06 17:16:11,327 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15184 to 4604. [2021-12-06 17:16:11,331 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4604 states, 4604 states have (on average 1.400955690703736) internal successors, (6450), 4603 states have internal predecessors, (6450), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:11,337 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4604 states to 4604 states and 6450 transitions. [2021-12-06 17:16:11,337 INFO L704 BuchiCegarLoop]: Abstraction has 4604 states and 6450 transitions. [2021-12-06 17:16:11,337 INFO L587 BuchiCegarLoop]: Abstraction has 4604 states and 6450 transitions. [2021-12-06 17:16:11,338 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-06 17:16:11,338 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4604 states and 6450 transitions. [2021-12-06 17:16:11,346 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4516 [2021-12-06 17:16:11,346 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:11,346 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:11,347 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:11,347 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:11,347 INFO L791 eck$LassoCheckResult]: Stem: 113813#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 113768#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 113540#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 113332#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 113333#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 113407#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 113669#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 113617#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 113618#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 113651#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 113628#L526 assume !(0 == ~M_E~0); 113629#L526-2 assume !(0 == ~T1_E~0); 113671#L531-1 assume !(0 == ~T2_E~0); 113613#L536-1 assume !(0 == ~T3_E~0); 113614#L541-1 assume !(0 == ~T4_E~0); 113608#L546-1 assume !(0 == ~E_M~0); 113609#L551-1 assume !(0 == ~E_1~0); 113587#L556-1 assume !(0 == ~E_2~0); 113588#L561-1 assume !(0 == ~E_3~0); 113597#L566-1 assume !(0 == ~E_4~0); 113598#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 113592#L262 assume !(1 == ~m_pc~0); 113593#L262-2 is_master_triggered_~__retres1~0#1 := 0; 113779#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 113454#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 113455#L649 assume !(0 != activate_threads_~tmp~1#1); 113778#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 113541#L281 assume !(1 == ~t1_pc~0); 113542#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 113456#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 113457#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 113517#L657 assume !(0 != activate_threads_~tmp___0~0#1); 113518#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 113599#L300 assume !(1 == ~t2_pc~0); 113600#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 113706#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 113512#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 113513#L665 assume !(0 != activate_threads_~tmp___1~0#1); 113387#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 113388#L319 assume !(1 == ~t3_pc~0); 113345#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 113346#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 113533#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 113534#L673 assume !(0 != activate_threads_~tmp___2~0#1); 113366#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 113367#L338 assume !(1 == ~t4_pc~0); 113429#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 113430#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 113448#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 113473#L681 assume !(0 != activate_threads_~tmp___3~0#1); 113312#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 113313#L584 assume !(1 == ~M_E~0); 113514#L584-2 assume !(1 == ~T1_E~0); 113471#L589-1 assume !(1 == ~T2_E~0); 113472#L594-1 assume !(1 == ~T3_E~0); 113566#L599-1 assume !(1 == ~T4_E~0); 113344#L604-1 assume !(1 == ~E_M~0); 113328#L609-1 assume !(1 == ~E_1~0); 113329#L614-1 assume !(1 == ~E_2~0); 113445#L619-1 assume !(1 == ~E_3~0); 113532#L624-1 assume !(1 == ~E_4~0); 113619#L629-1 assume { :end_inline_reset_delta_events } true; 113793#L815-2 [2021-12-06 17:16:11,347 INFO L793 eck$LassoCheckResult]: Loop: 113793#L815-2 assume !false; 116526#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 116501#L501 assume !false; 116494#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 116493#L398 assume !(0 == ~m_st~0); 116492#L402 assume !(0 == ~t1_st~0); 116491#L406 assume !(0 == ~t2_st~0); 116490#L410 assume !(0 == ~t3_st~0); 116488#L414 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 116487#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 116486#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 116484#L440 assume !(0 != eval_~tmp~0#1); 116483#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 116482#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 116481#L526-3 assume !(0 == ~M_E~0); 116480#L526-5 assume !(0 == ~T1_E~0); 116479#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 116478#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 116477#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 116476#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 116475#L551-3 assume !(0 == ~E_1~0); 116474#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 116473#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 116472#L566-3 assume !(0 == ~E_4~0); 116471#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 113697#L262-18 assume !(1 == ~m_pc~0); 113698#L262-20 is_master_triggered_~__retres1~0#1 := 0; 116806#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 116803#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 116800#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 116797#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 116793#L281-18 assume !(1 == ~t1_pc~0); 113702#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 113601#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 113602#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 113723#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 113719#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 113720#L300-18 assume !(1 == ~t2_pc~0); 113751#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 116942#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 116941#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 116940#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 116939#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 116938#L319-18 assume 1 == ~t3_pc~0; 116937#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 116935#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 116934#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 116933#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 116932#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 116931#L338-18 assume !(1 == ~t4_pc~0); 116930#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 116929#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 116928#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 116927#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 116926#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 116925#L584-3 assume !(1 == ~M_E~0); 115955#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 116924#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 116923#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 116922#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 116921#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 116920#L609-3 assume !(1 == ~E_1~0); 116919#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 116918#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 116917#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 116916#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 116914#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 116906#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 116904#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 113488#L834 assume !(0 == start_simulation_~tmp~3#1); 113490#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 116540#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 116537#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 116535#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 116533#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 116531#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 116530#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 116529#L847 assume !(0 != start_simulation_~tmp___0~1#1); 113793#L815-2 [2021-12-06 17:16:11,348 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:11,348 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 3 times [2021-12-06 17:16:11,348 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:11,348 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [111704894] [2021-12-06 17:16:11,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:11,348 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:11,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:11,354 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:16:11,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:11,366 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:16:11,366 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:11,366 INFO L85 PathProgramCache]: Analyzing trace with hash -209506619, now seen corresponding path program 1 times [2021-12-06 17:16:11,367 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:11,367 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1729512988] [2021-12-06 17:16:11,367 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:11,367 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:11,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:11,409 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:11,409 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:11,409 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1729512988] [2021-12-06 17:16:11,409 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1729512988] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:11,409 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:11,409 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 17:16:11,409 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [165364195] [2021-12-06 17:16:11,409 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:11,409 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:11,410 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:11,410 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-06 17:16:11,410 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-06 17:16:11,410 INFO L87 Difference]: Start difference. First operand 4604 states and 6450 transitions. cyclomatic complexity: 1850 Second operand has 5 states, 5 states have (on average 15.6) internal successors, (78), 5 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:11,515 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:11,515 INFO L93 Difference]: Finished difference Result 9176 states and 12769 transitions. [2021-12-06 17:16:11,515 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-06 17:16:11,516 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9176 states and 12769 transitions. [2021-12-06 17:16:11,541 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 9072 [2021-12-06 17:16:11,557 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9176 states to 9176 states and 12769 transitions. [2021-12-06 17:16:11,557 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9176 [2021-12-06 17:16:11,561 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9176 [2021-12-06 17:16:11,562 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9176 states and 12769 transitions. [2021-12-06 17:16:11,568 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:11,568 INFO L681 BuchiCegarLoop]: Abstraction has 9176 states and 12769 transitions. [2021-12-06 17:16:11,572 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9176 states and 12769 transitions. [2021-12-06 17:16:11,610 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9176 to 4736. [2021-12-06 17:16:11,614 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4736 states, 4736 states have (on average 1.3819679054054055) internal successors, (6545), 4735 states have internal predecessors, (6545), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:11,620 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4736 states to 4736 states and 6545 transitions. [2021-12-06 17:16:11,620 INFO L704 BuchiCegarLoop]: Abstraction has 4736 states and 6545 transitions. [2021-12-06 17:16:11,620 INFO L587 BuchiCegarLoop]: Abstraction has 4736 states and 6545 transitions. [2021-12-06 17:16:11,620 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-06 17:16:11,620 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4736 states and 6545 transitions. [2021-12-06 17:16:11,629 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4648 [2021-12-06 17:16:11,629 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:11,629 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:11,630 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:11,630 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:11,630 INFO L791 eck$LassoCheckResult]: Stem: 127641#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 127586#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 127336#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 127125#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 127126#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 127200#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 127477#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 127419#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 127420#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 127454#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 127430#L526 assume !(0 == ~M_E~0); 127431#L526-2 assume !(0 == ~T1_E~0); 127478#L531-1 assume !(0 == ~T2_E~0); 127415#L536-1 assume !(0 == ~T3_E~0); 127416#L541-1 assume !(0 == ~T4_E~0); 127410#L546-1 assume !(0 == ~E_M~0); 127411#L551-1 assume !(0 == ~E_1~0); 127388#L556-1 assume !(0 == ~E_2~0); 127389#L561-1 assume !(0 == ~E_3~0); 127398#L566-1 assume !(0 == ~E_4~0); 127399#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 127393#L262 assume !(1 == ~m_pc~0); 127394#L262-2 is_master_triggered_~__retres1~0#1 := 0; 127599#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 127244#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 127245#L649 assume !(0 != activate_threads_~tmp~1#1); 127596#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 127339#L281 assume !(1 == ~t1_pc~0); 127340#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 127248#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 127249#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 127312#L657 assume !(0 != activate_threads_~tmp___0~0#1); 127313#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 127400#L300 assume !(1 == ~t2_pc~0); 127401#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 127514#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 127307#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 127308#L665 assume !(0 != activate_threads_~tmp___1~0#1); 127180#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 127181#L319 assume !(1 == ~t3_pc~0); 127138#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 127139#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 127331#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 127332#L673 assume !(0 != activate_threads_~tmp___2~0#1); 127159#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 127160#L338 assume !(1 == ~t4_pc~0); 127223#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 127224#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 127238#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 127265#L681 assume !(0 != activate_threads_~tmp___3~0#1); 127105#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 127106#L584 assume !(1 == ~M_E~0); 127309#L584-2 assume !(1 == ~T1_E~0); 127263#L589-1 assume !(1 == ~T2_E~0); 127264#L594-1 assume !(1 == ~T3_E~0); 127361#L599-1 assume !(1 == ~T4_E~0); 127137#L604-1 assume !(1 == ~E_M~0); 127121#L609-1 assume !(1 == ~E_1~0); 127122#L614-1 assume !(1 == ~E_2~0); 127237#L619-1 assume !(1 == ~E_3~0); 127330#L624-1 assume !(1 == ~E_4~0); 127421#L629-1 assume { :end_inline_reset_delta_events } true; 127615#L815-2 [2021-12-06 17:16:11,630 INFO L793 eck$LassoCheckResult]: Loop: 127615#L815-2 assume !false; 128816#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 128814#L501 assume !false; 128812#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 128810#L398 assume !(0 == ~m_st~0); 128808#L402 assume !(0 == ~t1_st~0); 128806#L406 assume !(0 == ~t2_st~0); 128803#L410 assume !(0 == ~t3_st~0); 128800#L414 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 128798#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 128796#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 128793#L440 assume !(0 != eval_~tmp~0#1); 128791#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 128788#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 128787#L526-3 assume !(0 == ~M_E~0); 128784#L526-5 assume !(0 == ~T1_E~0); 128782#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 128780#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 128778#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 128776#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 128774#L551-3 assume !(0 == ~E_1~0); 128771#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 128769#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 128767#L566-3 assume !(0 == ~E_4~0); 128765#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 128763#L262-18 assume !(1 == ~m_pc~0); 128761#L262-20 is_master_triggered_~__retres1~0#1 := 0; 128758#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 128756#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 128754#L649-18 assume !(0 != activate_threads_~tmp~1#1); 128752#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 127858#L281-18 assume !(1 == ~t1_pc~0); 127851#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 127846#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 127842#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 127838#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 127834#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 127830#L300-18 assume !(1 == ~t2_pc~0); 127829#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 127828#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 127827#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 127826#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 127825#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 127824#L319-18 assume 1 == ~t3_pc~0; 127823#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 127821#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 127820#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 127819#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 127818#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 127816#L338-18 assume !(1 == ~t4_pc~0); 127817#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 127766#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 127764#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 127762#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 127760#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 127757#L584-3 assume !(1 == ~M_E~0); 127753#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 127754#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 129511#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 129509#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 129484#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 129482#L609-3 assume !(1 == ~E_1~0); 129352#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 129349#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 129345#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 129341#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 129329#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 128389#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 128390#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 127731#L834 assume !(0 == start_simulation_~tmp~3#1); 127733#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 128897#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 128893#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 128891#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 128890#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 128888#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 128887#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 128886#L847 assume !(0 != start_simulation_~tmp___0~1#1); 127615#L815-2 [2021-12-06 17:16:11,630 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:11,630 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 4 times [2021-12-06 17:16:11,630 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:11,631 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1983078406] [2021-12-06 17:16:11,631 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:11,631 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:11,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:11,636 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:16:11,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:11,647 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:16:11,648 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:11,648 INFO L85 PathProgramCache]: Analyzing trace with hash -225025337, now seen corresponding path program 1 times [2021-12-06 17:16:11,648 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:11,648 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1986832260] [2021-12-06 17:16:11,648 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:11,648 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:11,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:11,664 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:11,665 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:11,665 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1986832260] [2021-12-06 17:16:11,665 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1986832260] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:11,665 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:11,665 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:11,665 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2005676001] [2021-12-06 17:16:11,665 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:11,665 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:11,665 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:11,666 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:16:11,666 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:16:11,666 INFO L87 Difference]: Start difference. First operand 4736 states and 6545 transitions. cyclomatic complexity: 1813 Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 3 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:11,733 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:11,734 INFO L93 Difference]: Finished difference Result 7392 states and 10057 transitions. [2021-12-06 17:16:11,734 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:16:11,734 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7392 states and 10057 transitions. [2021-12-06 17:16:11,757 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 7294 [2021-12-06 17:16:11,771 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7392 states to 7392 states and 10057 transitions. [2021-12-06 17:16:11,771 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7392 [2021-12-06 17:16:11,775 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7392 [2021-12-06 17:16:11,775 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7392 states and 10057 transitions. [2021-12-06 17:16:11,778 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:11,779 INFO L681 BuchiCegarLoop]: Abstraction has 7392 states and 10057 transitions. [2021-12-06 17:16:11,782 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7392 states and 10057 transitions. [2021-12-06 17:16:11,830 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7392 to 7136. [2021-12-06 17:16:11,835 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7136 states, 7136 states have (on average 1.3622477578475336) internal successors, (9721), 7135 states have internal predecessors, (9721), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:11,847 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7136 states to 7136 states and 9721 transitions. [2021-12-06 17:16:11,847 INFO L704 BuchiCegarLoop]: Abstraction has 7136 states and 9721 transitions. [2021-12-06 17:16:11,847 INFO L587 BuchiCegarLoop]: Abstraction has 7136 states and 9721 transitions. [2021-12-06 17:16:11,847 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-06 17:16:11,847 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7136 states and 9721 transitions. [2021-12-06 17:16:11,863 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 7038 [2021-12-06 17:16:11,863 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:11,863 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:11,864 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:11,864 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:11,864 INFO L791 eck$LassoCheckResult]: Stem: 139734#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 139697#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 139468#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 139259#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 139260#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 139335#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 139598#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 139550#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 139551#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 139580#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 139560#L526 assume !(0 == ~M_E~0); 139561#L526-2 assume !(0 == ~T1_E~0); 139599#L531-1 assume !(0 == ~T2_E~0); 139546#L536-1 assume !(0 == ~T3_E~0); 139547#L541-1 assume !(0 == ~T4_E~0); 139541#L546-1 assume !(0 == ~E_M~0); 139542#L551-1 assume !(0 == ~E_1~0); 139519#L556-1 assume !(0 == ~E_2~0); 139520#L561-1 assume !(0 == ~E_3~0); 139529#L566-1 assume !(0 == ~E_4~0); 139530#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 139524#L262 assume !(1 == ~m_pc~0); 139525#L262-2 is_master_triggered_~__retres1~0#1 := 0; 139703#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 139379#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 139380#L649 assume !(0 != activate_threads_~tmp~1#1); 139701#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 139471#L281 assume !(1 == ~t1_pc~0); 139472#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 139383#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 139384#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 139443#L657 assume !(0 != activate_threads_~tmp___0~0#1); 139444#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 139531#L300 assume !(1 == ~t2_pc~0); 139532#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 139639#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 139438#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 139439#L665 assume !(0 != activate_threads_~tmp___1~0#1); 139314#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 139315#L319 assume !(1 == ~t3_pc~0); 139272#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 139273#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 139463#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 139464#L673 assume !(0 != activate_threads_~tmp___2~0#1); 139293#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 139294#L338 assume !(1 == ~t4_pc~0); 139358#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 139359#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 139373#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 139400#L681 assume !(0 != activate_threads_~tmp___3~0#1); 139239#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 139240#L584 assume !(1 == ~M_E~0); 139440#L584-2 assume !(1 == ~T1_E~0); 139398#L589-1 assume !(1 == ~T2_E~0); 139399#L594-1 assume !(1 == ~T3_E~0); 139494#L599-1 assume !(1 == ~T4_E~0); 139271#L604-1 assume !(1 == ~E_M~0); 139255#L609-1 assume !(1 == ~E_1~0); 139256#L614-1 assume !(1 == ~E_2~0); 139372#L619-1 assume !(1 == ~E_3~0); 139462#L624-1 assume !(1 == ~E_4~0); 139552#L629-1 assume { :end_inline_reset_delta_events } true; 139714#L815-2 assume !false; 140543#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 140544#L501 [2021-12-06 17:16:11,864 INFO L793 eck$LassoCheckResult]: Loop: 140544#L501 assume !false; 140519#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 140520#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 140828#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 140827#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 140818#L440 assume 0 != eval_~tmp~0#1; 140811#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 140807#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 140799#L445 assume !(0 == ~t1_st~0); 140795#L459 assume !(0 == ~t2_st~0); 140792#L473 assume !(0 == ~t3_st~0); 140547#L487 assume !(0 == ~t4_st~0); 140544#L501 [2021-12-06 17:16:11,865 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:11,865 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 1 times [2021-12-06 17:16:11,865 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:11,865 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2106196040] [2021-12-06 17:16:11,865 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:11,865 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:11,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:11,872 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:16:11,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:11,885 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:16:11,885 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:11,885 INFO L85 PathProgramCache]: Analyzing trace with hash 1608874715, now seen corresponding path program 1 times [2021-12-06 17:16:11,885 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:11,885 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1196968870] [2021-12-06 17:16:11,886 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:11,886 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:11,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:11,888 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:16:11,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:11,891 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:16:11,891 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:11,891 INFO L85 PathProgramCache]: Analyzing trace with hash 220742405, now seen corresponding path program 1 times [2021-12-06 17:16:11,892 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:11,892 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1295215770] [2021-12-06 17:16:11,892 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:11,892 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:11,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:11,911 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:11,912 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:11,912 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1295215770] [2021-12-06 17:16:11,912 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1295215770] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:11,912 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:11,912 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:11,912 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1264107246] [2021-12-06 17:16:11,912 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:11,966 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:11,966 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:16:11,967 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:16:11,967 INFO L87 Difference]: Start difference. First operand 7136 states and 9721 transitions. cyclomatic complexity: 2591 Second operand has 3 states, 3 states have (on average 25.333333333333332) internal successors, (76), 3 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:12,015 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:12,016 INFO L93 Difference]: Finished difference Result 11454 states and 15463 transitions. [2021-12-06 17:16:12,016 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:16:12,016 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11454 states and 15463 transitions. [2021-12-06 17:16:12,052 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 11264 [2021-12-06 17:16:12,075 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11454 states to 11454 states and 15463 transitions. [2021-12-06 17:16:12,076 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11454 [2021-12-06 17:16:12,081 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11454 [2021-12-06 17:16:12,081 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11454 states and 15463 transitions. [2021-12-06 17:16:12,086 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:12,087 INFO L681 BuchiCegarLoop]: Abstraction has 11454 states and 15463 transitions. [2021-12-06 17:16:12,092 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11454 states and 15463 transitions. [2021-12-06 17:16:12,171 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11454 to 11454. [2021-12-06 17:16:12,181 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11454 states, 11454 states have (on average 1.350008730574472) internal successors, (15463), 11453 states have internal predecessors, (15463), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:12,201 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11454 states to 11454 states and 15463 transitions. [2021-12-06 17:16:12,201 INFO L704 BuchiCegarLoop]: Abstraction has 11454 states and 15463 transitions. [2021-12-06 17:16:12,201 INFO L587 BuchiCegarLoop]: Abstraction has 11454 states and 15463 transitions. [2021-12-06 17:16:12,201 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-06 17:16:12,201 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11454 states and 15463 transitions. [2021-12-06 17:16:12,227 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 11264 [2021-12-06 17:16:12,227 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:12,227 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:12,228 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:12,228 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:12,228 INFO L791 eck$LassoCheckResult]: Stem: 158385#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 158333#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 158074#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 157857#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 157858#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 157934#L365-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 158314#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 158159#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 158160#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 158198#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 158199#L526 assume !(0 == ~M_E~0); 158375#L526-2 assume !(0 == ~T1_E~0); 158376#L531-1 assume !(0 == ~T2_E~0); 158155#L536-1 assume !(0 == ~T3_E~0); 158156#L541-1 assume !(0 == ~T4_E~0); 158150#L546-1 assume !(0 == ~E_M~0); 158151#L551-1 assume !(0 == ~E_1~0); 158129#L556-1 assume !(0 == ~E_2~0); 158130#L561-1 assume !(0 == ~E_3~0); 158139#L566-1 assume !(0 == ~E_4~0); 158140#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 158134#L262 assume !(1 == ~m_pc~0); 158135#L262-2 is_master_triggered_~__retres1~0#1 := 0; 158346#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 158347#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 158344#L649 assume !(0 != activate_threads_~tmp~1#1); 158345#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 158075#L281 assume !(1 == ~t1_pc~0); 158076#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 157982#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 157983#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 158046#L657 assume !(0 != activate_threads_~tmp___0~0#1); 158047#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 158141#L300 assume !(1 == ~t2_pc~0); 158142#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 158260#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 158261#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 158167#L665 assume !(0 != activate_threads_~tmp___1~0#1); 158168#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 158395#L319 assume !(1 == ~t3_pc~0); 158396#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 158263#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 158264#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 158096#L673 assume !(0 != activate_threads_~tmp___2~0#1); 158097#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 158265#L338 assume !(1 == ~t4_pc~0); 158266#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 157974#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 157975#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 158349#L681 assume !(0 != activate_threads_~tmp___3~0#1); 158350#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 158336#L584 assume !(1 == ~M_E~0); 158337#L584-2 assume !(1 == ~T1_E~0); 157997#L589-1 assume !(1 == ~T2_E~0); 157998#L594-1 assume !(1 == ~T3_E~0); 158102#L599-1 assume !(1 == ~T4_E~0); 158103#L604-1 assume !(1 == ~E_M~0); 157853#L609-1 assume !(1 == ~E_1~0); 157854#L614-1 assume !(1 == ~E_2~0); 158065#L619-1 assume !(1 == ~E_3~0); 158066#L624-1 assume !(1 == ~E_4~0); 158362#L629-1 assume { :end_inline_reset_delta_events } true; 158363#L815-2 assume !false; 159396#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 159329#L501 [2021-12-06 17:16:12,228 INFO L793 eck$LassoCheckResult]: Loop: 159329#L501 assume !false; 159388#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 159382#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 159376#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 159369#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 159359#L440 assume 0 != eval_~tmp~0#1; 159351#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 159344#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 159336#L445 assume !(0 == ~t1_st~0); 159332#L459 assume !(0 == ~t2_st~0); 159324#L473 assume !(0 == ~t3_st~0); 159333#L487 assume !(0 == ~t4_st~0); 159329#L501 [2021-12-06 17:16:12,229 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:12,229 INFO L85 PathProgramCache]: Analyzing trace with hash 600428717, now seen corresponding path program 1 times [2021-12-06 17:16:12,229 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:12,229 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1674278667] [2021-12-06 17:16:12,229 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:12,229 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:12,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:12,244 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:12,244 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:12,244 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1674278667] [2021-12-06 17:16:12,244 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1674278667] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:12,244 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:12,245 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:12,245 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1668235110] [2021-12-06 17:16:12,245 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:12,245 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:12,246 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:12,246 INFO L85 PathProgramCache]: Analyzing trace with hash 1608874715, now seen corresponding path program 2 times [2021-12-06 17:16:12,246 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:12,246 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [723352544] [2021-12-06 17:16:12,246 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:12,246 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:12,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:12,250 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:16:12,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:12,253 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:16:12,298 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:12,298 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:16:12,298 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:16:12,299 INFO L87 Difference]: Start difference. First operand 11454 states and 15463 transitions. cyclomatic complexity: 4015 Second operand has 3 states, 3 states have (on average 21.333333333333332) internal successors, (64), 3 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:12,328 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:12,328 INFO L93 Difference]: Finished difference Result 11394 states and 15382 transitions. [2021-12-06 17:16:12,329 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:16:12,329 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11394 states and 15382 transitions. [2021-12-06 17:16:12,363 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 11264 [2021-12-06 17:16:12,383 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11394 states to 11394 states and 15382 transitions. [2021-12-06 17:16:12,383 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11394 [2021-12-06 17:16:12,387 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11394 [2021-12-06 17:16:12,387 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11394 states and 15382 transitions. [2021-12-06 17:16:12,392 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:12,392 INFO L681 BuchiCegarLoop]: Abstraction has 11394 states and 15382 transitions. [2021-12-06 17:16:12,397 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11394 states and 15382 transitions. [2021-12-06 17:16:12,469 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11394 to 11394. [2021-12-06 17:16:12,477 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11394 states, 11394 states have (on average 1.350008776549061) internal successors, (15382), 11393 states have internal predecessors, (15382), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:12,492 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11394 states to 11394 states and 15382 transitions. [2021-12-06 17:16:12,493 INFO L704 BuchiCegarLoop]: Abstraction has 11394 states and 15382 transitions. [2021-12-06 17:16:12,493 INFO L587 BuchiCegarLoop]: Abstraction has 11394 states and 15382 transitions. [2021-12-06 17:16:12,493 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-06 17:16:12,493 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11394 states and 15382 transitions. [2021-12-06 17:16:12,514 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 11264 [2021-12-06 17:16:12,514 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:12,514 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:12,515 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:12,515 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:12,515 INFO L791 eck$LassoCheckResult]: Stem: 181208#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 181165#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 180925#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 180711#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 180712#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 180789#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 181057#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 181007#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 181008#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 181039#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 181018#L526 assume !(0 == ~M_E~0); 181019#L526-2 assume !(0 == ~T1_E~0); 181058#L531-1 assume !(0 == ~T2_E~0); 181003#L536-1 assume !(0 == ~T3_E~0); 181004#L541-1 assume !(0 == ~T4_E~0); 180998#L546-1 assume !(0 == ~E_M~0); 180999#L551-1 assume !(0 == ~E_1~0); 180977#L556-1 assume !(0 == ~E_2~0); 180978#L561-1 assume !(0 == ~E_3~0); 180987#L566-1 assume !(0 == ~E_4~0); 180988#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 180982#L262 assume !(1 == ~m_pc~0); 180983#L262-2 is_master_triggered_~__retres1~0#1 := 0; 181175#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 180834#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 180835#L649 assume !(0 != activate_threads_~tmp~1#1); 181171#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 180926#L281 assume !(1 == ~t1_pc~0); 180927#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 180838#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 180839#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 180899#L657 assume !(0 != activate_threads_~tmp___0~0#1); 180900#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 180989#L300 assume !(1 == ~t2_pc~0); 180990#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 181092#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 180894#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 180895#L665 assume !(0 != activate_threads_~tmp___1~0#1); 180766#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 180767#L319 assume !(1 == ~t3_pc~0); 180724#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 180725#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 180918#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 180919#L673 assume !(0 != activate_threads_~tmp___2~0#1); 180745#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 180746#L338 assume !(1 == ~t4_pc~0); 180811#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 180812#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 180829#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 180855#L681 assume !(0 != activate_threads_~tmp___3~0#1); 180691#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 180692#L584 assume !(1 == ~M_E~0); 180896#L584-2 assume !(1 == ~T1_E~0); 180853#L589-1 assume !(1 == ~T2_E~0); 180854#L594-1 assume !(1 == ~T3_E~0); 180951#L599-1 assume !(1 == ~T4_E~0); 180723#L604-1 assume !(1 == ~E_M~0); 180707#L609-1 assume !(1 == ~E_1~0); 180708#L614-1 assume !(1 == ~E_2~0); 180828#L619-1 assume !(1 == ~E_3~0); 180917#L624-1 assume !(1 == ~E_4~0); 181009#L629-1 assume { :end_inline_reset_delta_events } true; 181187#L815-2 assume !false; 181957#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 181955#L501 [2021-12-06 17:16:12,515 INFO L793 eck$LassoCheckResult]: Loop: 181955#L501 assume !false; 181953#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 181949#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 181947#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 181945#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 181943#L440 assume 0 != eval_~tmp~0#1; 181940#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 181937#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 181935#L445 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 181853#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 181932#L459 assume !(0 == ~t2_st~0); 181962#L473 assume !(0 == ~t3_st~0); 181960#L487 assume !(0 == ~t4_st~0); 181955#L501 [2021-12-06 17:16:12,515 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:12,516 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 2 times [2021-12-06 17:16:12,516 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:12,516 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1040358483] [2021-12-06 17:16:12,516 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:12,516 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:12,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:12,523 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:16:12,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:12,539 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:16:12,539 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:12,539 INFO L85 PathProgramCache]: Analyzing trace with hash -1811665542, now seen corresponding path program 1 times [2021-12-06 17:16:12,539 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:12,540 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1785354554] [2021-12-06 17:16:12,540 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:12,540 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:12,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:12,543 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:16:12,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:12,546 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:16:12,547 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:12,547 INFO L85 PathProgramCache]: Analyzing trace with hash -1894094192, now seen corresponding path program 1 times [2021-12-06 17:16:12,547 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:12,547 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [640107564] [2021-12-06 17:16:12,547 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:12,547 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:12,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:12,570 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:12,571 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:12,571 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [640107564] [2021-12-06 17:16:12,571 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [640107564] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:12,571 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:12,571 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:12,571 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1487211637] [2021-12-06 17:16:12,571 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:12,627 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:12,627 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:16:12,627 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:16:12,627 INFO L87 Difference]: Start difference. First operand 11394 states and 15382 transitions. cyclomatic complexity: 3994 Second operand has 3 states, 3 states have (on average 25.666666666666668) internal successors, (77), 3 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:12,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:12,692 INFO L93 Difference]: Finished difference Result 21066 states and 28290 transitions. [2021-12-06 17:16:12,693 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:16:12,693 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21066 states and 28290 transitions. [2021-12-06 17:16:12,753 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 20872 [2021-12-06 17:16:12,792 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21066 states to 21066 states and 28290 transitions. [2021-12-06 17:16:12,793 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21066 [2021-12-06 17:16:12,803 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21066 [2021-12-06 17:16:12,803 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21066 states and 28290 transitions. [2021-12-06 17:16:12,815 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:12,815 INFO L681 BuchiCegarLoop]: Abstraction has 21066 states and 28290 transitions. [2021-12-06 17:16:12,825 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21066 states and 28290 transitions. [2021-12-06 17:16:12,921 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21066 to 20576. [2021-12-06 17:16:12,933 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20576 states, 20576 states have (on average 1.344284603421462) internal successors, (27660), 20575 states have internal predecessors, (27660), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:12,964 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20576 states to 20576 states and 27660 transitions. [2021-12-06 17:16:12,964 INFO L704 BuchiCegarLoop]: Abstraction has 20576 states and 27660 transitions. [2021-12-06 17:16:12,964 INFO L587 BuchiCegarLoop]: Abstraction has 20576 states and 27660 transitions. [2021-12-06 17:16:12,964 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-06 17:16:12,965 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20576 states and 27660 transitions. [2021-12-06 17:16:13,013 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 20382 [2021-12-06 17:16:13,013 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:13,013 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:13,014 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:13,014 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:13,014 INFO L791 eck$LassoCheckResult]: Stem: 213704#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 213652#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 213393#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 213179#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 213180#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 213255#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 213530#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 213477#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 213478#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 213511#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 213490#L526 assume !(0 == ~M_E~0); 213491#L526-2 assume !(0 == ~T1_E~0); 213532#L531-1 assume !(0 == ~T2_E~0); 213473#L536-1 assume !(0 == ~T3_E~0); 213474#L541-1 assume !(0 == ~T4_E~0); 213468#L546-1 assume !(0 == ~E_M~0); 213469#L551-1 assume !(0 == ~E_1~0); 213447#L556-1 assume !(0 == ~E_2~0); 213448#L561-1 assume !(0 == ~E_3~0); 213457#L566-1 assume !(0 == ~E_4~0); 213458#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 213452#L262 assume !(1 == ~m_pc~0); 213453#L262-2 is_master_triggered_~__retres1~0#1 := 0; 213663#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 213300#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 213301#L649 assume !(0 != activate_threads_~tmp~1#1); 213662#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 213394#L281 assume !(1 == ~t1_pc~0); 213395#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 213302#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 213303#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 213363#L657 assume !(0 != activate_threads_~tmp___0~0#1); 213364#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 213459#L300 assume !(1 == ~t2_pc~0); 213460#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 213575#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 213358#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 213359#L665 assume !(0 != activate_threads_~tmp___1~0#1); 213235#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 213236#L319 assume !(1 == ~t3_pc~0); 213192#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 213193#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 213384#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 213385#L673 assume !(0 != activate_threads_~tmp___2~0#1); 213214#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 213215#L338 assume !(1 == ~t4_pc~0); 213278#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 213279#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 213295#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 213319#L681 assume !(0 != activate_threads_~tmp___3~0#1); 213159#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 213160#L584 assume !(1 == ~M_E~0); 213360#L584-2 assume !(1 == ~T1_E~0); 213317#L589-1 assume !(1 == ~T2_E~0); 213318#L594-1 assume !(1 == ~T3_E~0); 213421#L599-1 assume !(1 == ~T4_E~0); 213191#L604-1 assume !(1 == ~E_M~0); 213175#L609-1 assume !(1 == ~E_1~0); 213176#L614-1 assume !(1 == ~E_2~0); 213292#L619-1 assume !(1 == ~E_3~0); 213383#L624-1 assume !(1 == ~E_4~0); 213479#L629-1 assume { :end_inline_reset_delta_events } true; 213680#L815-2 assume !false; 218272#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 218273#L501 [2021-12-06 17:16:13,014 INFO L793 eck$LassoCheckResult]: Loop: 218273#L501 assume !false; 218263#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 218264#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 218256#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 218257#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 218250#L440 assume 0 != eval_~tmp~0#1; 218251#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 218242#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 218243#L445 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 218236#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 218237#L459 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 216609#L476 assume !(0 != eval_~tmp_ndt_3~0#1); 218336#L473 assume !(0 == ~t3_st~0); 218276#L487 assume !(0 == ~t4_st~0); 218273#L501 [2021-12-06 17:16:13,015 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:13,015 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 3 times [2021-12-06 17:16:13,015 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:13,015 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [368732840] [2021-12-06 17:16:13,015 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:13,015 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:13,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:13,025 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:16:13,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:13,044 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:16:13,044 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:13,044 INFO L85 PathProgramCache]: Analyzing trace with hash -331803221, now seen corresponding path program 1 times [2021-12-06 17:16:13,044 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:13,044 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2028844460] [2021-12-06 17:16:13,045 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:13,045 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:13,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:13,048 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:16:13,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:13,052 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:16:13,053 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:13,053 INFO L85 PathProgramCache]: Analyzing trace with hash 1407875925, now seen corresponding path program 1 times [2021-12-06 17:16:13,053 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:13,053 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [836189323] [2021-12-06 17:16:13,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:13,053 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:13,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:13,077 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:13,077 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:13,077 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [836189323] [2021-12-06 17:16:13,077 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [836189323] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:13,077 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:13,077 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:13,077 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [935219475] [2021-12-06 17:16:13,077 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:13,141 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:13,141 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:16:13,141 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:16:13,141 INFO L87 Difference]: Start difference. First operand 20576 states and 27660 transitions. cyclomatic complexity: 7090 Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 3 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:13,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:13,227 INFO L93 Difference]: Finished difference Result 36290 states and 48654 transitions. [2021-12-06 17:16:13,227 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:16:13,228 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 36290 states and 48654 transitions. [2021-12-06 17:16:13,359 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 35968 [2021-12-06 17:16:13,417 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 36290 states to 36290 states and 48654 transitions. [2021-12-06 17:16:13,417 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 36290 [2021-12-06 17:16:13,429 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 36290 [2021-12-06 17:16:13,429 INFO L73 IsDeterministic]: Start isDeterministic. Operand 36290 states and 48654 transitions. [2021-12-06 17:16:13,440 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:13,440 INFO L681 BuchiCegarLoop]: Abstraction has 36290 states and 48654 transitions. [2021-12-06 17:16:13,451 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36290 states and 48654 transitions. [2021-12-06 17:16:13,619 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36290 to 35114. [2021-12-06 17:16:13,639 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35114 states, 35114 states have (on average 1.3457310474454633) internal successors, (47254), 35113 states have internal predecessors, (47254), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:13,695 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35114 states to 35114 states and 47254 transitions. [2021-12-06 17:16:13,695 INFO L704 BuchiCegarLoop]: Abstraction has 35114 states and 47254 transitions. [2021-12-06 17:16:13,695 INFO L587 BuchiCegarLoop]: Abstraction has 35114 states and 47254 transitions. [2021-12-06 17:16:13,695 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-06 17:16:13,695 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35114 states and 47254 transitions. [2021-12-06 17:16:13,774 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 34792 [2021-12-06 17:16:13,774 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:13,774 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:13,774 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:13,774 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:13,775 INFO L791 eck$LassoCheckResult]: Stem: 270563#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 270515#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 270266#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 270053#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 270054#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 270131#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 270404#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 270349#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 270350#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 270382#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 270361#L526 assume !(0 == ~M_E~0); 270362#L526-2 assume !(0 == ~T1_E~0); 270407#L531-1 assume !(0 == ~T2_E~0); 270345#L536-1 assume !(0 == ~T3_E~0); 270346#L541-1 assume !(0 == ~T4_E~0); 270340#L546-1 assume !(0 == ~E_M~0); 270341#L551-1 assume !(0 == ~E_1~0); 270316#L556-1 assume !(0 == ~E_2~0); 270317#L561-1 assume !(0 == ~E_3~0); 270326#L566-1 assume !(0 == ~E_4~0); 270327#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 270321#L262 assume !(1 == ~m_pc~0); 270322#L262-2 is_master_triggered_~__retres1~0#1 := 0; 270530#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 270178#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 270179#L649 assume !(0 != activate_threads_~tmp~1#1); 270529#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 270267#L281 assume !(1 == ~t1_pc~0); 270268#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 270180#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 270181#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 270241#L657 assume !(0 != activate_threads_~tmp___0~0#1); 270242#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 270330#L300 assume !(1 == ~t2_pc~0); 270331#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 270450#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 270236#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 270237#L665 assume !(0 != activate_threads_~tmp___1~0#1); 270108#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 270109#L319 assume !(1 == ~t3_pc~0); 270066#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 270067#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 270258#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 270259#L673 assume !(0 != activate_threads_~tmp___2~0#1); 270087#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 270088#L338 assume !(1 == ~t4_pc~0); 270154#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 270155#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 270173#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 270197#L681 assume !(0 != activate_threads_~tmp___3~0#1); 270033#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 270034#L584 assume !(1 == ~M_E~0); 270238#L584-2 assume !(1 == ~T1_E~0); 270195#L589-1 assume !(1 == ~T2_E~0); 270196#L594-1 assume !(1 == ~T3_E~0); 270292#L599-1 assume !(1 == ~T4_E~0); 270065#L604-1 assume !(1 == ~E_M~0); 270049#L609-1 assume !(1 == ~E_1~0); 270050#L614-1 assume !(1 == ~E_2~0); 270170#L619-1 assume !(1 == ~E_3~0); 270257#L624-1 assume !(1 == ~E_4~0); 270351#L629-1 assume { :end_inline_reset_delta_events } true; 270542#L815-2 assume !false; 278818#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 278819#L501 [2021-12-06 17:16:13,775 INFO L793 eck$LassoCheckResult]: Loop: 278819#L501 assume !false; 279645#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 279643#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 279642#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 279641#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 279640#L440 assume 0 != eval_~tmp~0#1; 278798#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 278793#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 278567#L445 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 277469#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 277339#L459 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 277332#L476 assume !(0 != eval_~tmp_ndt_3~0#1); 277334#L473 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 277776#L490 assume !(0 != eval_~tmp_ndt_4~0#1); 278822#L487 assume !(0 == ~t4_st~0); 278819#L501 [2021-12-06 17:16:13,775 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:13,775 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 4 times [2021-12-06 17:16:13,775 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:13,776 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2095262034] [2021-12-06 17:16:13,776 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:13,776 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:13,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:13,781 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:16:13,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:13,793 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:16:13,793 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:13,794 INFO L85 PathProgramCache]: Analyzing trace with hash -1696117078, now seen corresponding path program 1 times [2021-12-06 17:16:13,794 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:13,794 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [803174676] [2021-12-06 17:16:13,794 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:13,794 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:13,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:13,796 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:16:13,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:13,799 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:16:13,800 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:13,800 INFO L85 PathProgramCache]: Analyzing trace with hash 694328896, now seen corresponding path program 1 times [2021-12-06 17:16:13,800 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:13,800 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1639820343] [2021-12-06 17:16:13,800 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:13,800 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:13,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:13,817 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:13,817 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:13,817 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1639820343] [2021-12-06 17:16:13,817 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1639820343] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:13,817 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:13,817 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 17:16:13,818 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1429292196] [2021-12-06 17:16:13,818 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:13,900 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:13,900 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:16:13,900 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:16:13,901 INFO L87 Difference]: Start difference. First operand 35114 states and 47254 transitions. cyclomatic complexity: 12146 Second operand has 3 states, 2 states have (on average 39.5) internal successors, (79), 3 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:14,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:14,058 INFO L93 Difference]: Finished difference Result 39904 states and 53492 transitions. [2021-12-06 17:16:14,058 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:16:14,058 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39904 states and 53492 transitions. [2021-12-06 17:16:14,177 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 39662 [2021-12-06 17:16:14,257 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39904 states to 39904 states and 53492 transitions. [2021-12-06 17:16:14,258 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39904 [2021-12-06 17:16:14,275 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39904 [2021-12-06 17:16:14,275 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39904 states and 53492 transitions. [2021-12-06 17:16:14,289 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:14,289 INFO L681 BuchiCegarLoop]: Abstraction has 39904 states and 53492 transitions. [2021-12-06 17:16:14,306 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39904 states and 53492 transitions. [2021-12-06 17:16:14,560 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39904 to 39456. [2021-12-06 17:16:14,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39456 states, 39456 states have (on average 1.3443836171938361) internal successors, (53044), 39455 states have internal predecessors, (53044), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:14,657 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39456 states to 39456 states and 53044 transitions. [2021-12-06 17:16:14,657 INFO L704 BuchiCegarLoop]: Abstraction has 39456 states and 53044 transitions. [2021-12-06 17:16:14,657 INFO L587 BuchiCegarLoop]: Abstraction has 39456 states and 53044 transitions. [2021-12-06 17:16:14,657 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-12-06 17:16:14,657 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39456 states and 53044 transitions. [2021-12-06 17:16:14,764 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 39214 [2021-12-06 17:16:14,764 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:14,764 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:14,765 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:14,765 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:14,765 INFO L791 eck$LassoCheckResult]: Stem: 345592#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 345550#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 345297#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 345080#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 345081#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 345158#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 345430#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 345376#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 345377#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 345409#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 345389#L526 assume !(0 == ~M_E~0); 345390#L526-2 assume !(0 == ~T1_E~0); 345432#L531-1 assume !(0 == ~T2_E~0); 345372#L536-1 assume !(0 == ~T3_E~0); 345373#L541-1 assume !(0 == ~T4_E~0); 345368#L546-1 assume !(0 == ~E_M~0); 345369#L551-1 assume !(0 == ~E_1~0); 345345#L556-1 assume !(0 == ~E_2~0); 345346#L561-1 assume !(0 == ~E_3~0); 345355#L566-1 assume !(0 == ~E_4~0); 345356#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 345350#L262 assume !(1 == ~m_pc~0); 345351#L262-2 is_master_triggered_~__retres1~0#1 := 0; 345562#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 345203#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 345204#L649 assume !(0 != activate_threads_~tmp~1#1); 345561#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 345298#L281 assume !(1 == ~t1_pc~0); 345299#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 345205#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 345206#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 345266#L657 assume !(0 != activate_threads_~tmp___0~0#1); 345267#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 345357#L300 assume !(1 == ~t2_pc~0); 345358#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 345471#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 345261#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 345262#L665 assume !(0 != activate_threads_~tmp___1~0#1); 345136#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 345137#L319 assume !(1 == ~t3_pc~0); 345093#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 345094#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 345289#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 345290#L673 assume !(0 != activate_threads_~tmp___2~0#1); 345114#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 345115#L338 assume !(1 == ~t4_pc~0); 345181#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 345182#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 345198#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 345222#L681 assume !(0 != activate_threads_~tmp___3~0#1); 345059#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 345060#L584 assume !(1 == ~M_E~0); 345263#L584-2 assume !(1 == ~T1_E~0); 345220#L589-1 assume !(1 == ~T2_E~0); 345221#L594-1 assume !(1 == ~T3_E~0); 345323#L599-1 assume !(1 == ~T4_E~0); 345092#L604-1 assume !(1 == ~E_M~0); 345076#L609-1 assume !(1 == ~E_1~0); 345077#L614-1 assume !(1 == ~E_2~0); 345195#L619-1 assume !(1 == ~E_3~0); 345288#L624-1 assume !(1 == ~E_4~0); 345378#L629-1 assume { :end_inline_reset_delta_events } true; 345576#L815-2 assume !false; 357069#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 356706#L501 [2021-12-06 17:16:14,765 INFO L793 eck$LassoCheckResult]: Loop: 356706#L501 assume !false; 357051#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 357048#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 357046#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 357044#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 357041#L440 assume 0 != eval_~tmp~0#1; 357038#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 357035#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 355082#L445 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 355077#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 355075#L459 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 355072#L476 assume !(0 != eval_~tmp_ndt_3~0#1); 355073#L473 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 356708#L490 assume !(0 != eval_~tmp_ndt_4~0#1); 356707#L487 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 356704#L504 assume !(0 != eval_~tmp_ndt_5~0#1); 356706#L501 [2021-12-06 17:16:14,766 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:14,766 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 5 times [2021-12-06 17:16:14,766 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:14,766 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1448166478] [2021-12-06 17:16:14,766 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:14,766 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:14,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:14,773 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:16:14,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:14,787 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:16:14,788 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:14,788 INFO L85 PathProgramCache]: Analyzing trace with hash -1040025477, now seen corresponding path program 1 times [2021-12-06 17:16:14,788 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:14,788 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [223477487] [2021-12-06 17:16:14,788 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:14,788 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:14,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:14,791 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:16:14,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:14,795 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:16:14,795 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:14,795 INFO L85 PathProgramCache]: Analyzing trace with hash 49355685, now seen corresponding path program 1 times [2021-12-06 17:16:14,795 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:14,795 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [586086739] [2021-12-06 17:16:14,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:14,796 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:14,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:14,803 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:16:14,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:16:14,819 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:16:15,656 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 06.12 05:16:15 BoogieIcfgContainer [2021-12-06 17:16:15,656 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-12-06 17:16:15,657 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-12-06 17:16:15,657 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-12-06 17:16:15,657 INFO L275 PluginConnector]: Witness Printer initialized [2021-12-06 17:16:15,657 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 05:16:07" (3/4) ... [2021-12-06 17:16:15,659 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-12-06 17:16:15,695 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5b09e43-d5a2-457e-befc-0eb09998c173/bin/uautomizer-DrprNOufMa/witness.graphml [2021-12-06 17:16:15,695 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-12-06 17:16:15,695 INFO L158 Benchmark]: Toolchain (without parser) took 9299.56ms. Allocated memory was 86.0MB in the beginning and 1.4GB in the end (delta: 1.3GB). Free memory was 49.5MB in the beginning and 871.9MB in the end (delta: -822.5MB). Peak memory consumption was 512.9MB. Max. memory is 16.1GB. [2021-12-06 17:16:15,696 INFO L158 Benchmark]: CDTParser took 0.12ms. Allocated memory is still 86.0MB. Free memory is still 66.1MB. There was no memory consumed. Max. memory is 16.1GB. [2021-12-06 17:16:15,696 INFO L158 Benchmark]: CACSL2BoogieTranslator took 261.88ms. Allocated memory was 86.0MB in the beginning and 104.9MB in the end (delta: 18.9MB). Free memory was 49.3MB in the beginning and 77.0MB in the end (delta: -27.7MB). Peak memory consumption was 7.9MB. Max. memory is 16.1GB. [2021-12-06 17:16:15,696 INFO L158 Benchmark]: Boogie Procedure Inliner took 47.12ms. Allocated memory is still 104.9MB. Free memory was 77.0MB in the beginning and 72.6MB in the end (delta: 4.3MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-06 17:16:15,696 INFO L158 Benchmark]: Boogie Preprocessor took 46.46ms. Allocated memory is still 104.9MB. Free memory was 72.6MB in the beginning and 69.0MB in the end (delta: 3.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-06 17:16:15,697 INFO L158 Benchmark]: RCFGBuilder took 683.25ms. Allocated memory is still 104.9MB. Free memory was 69.0MB in the beginning and 53.3MB in the end (delta: 15.7MB). Peak memory consumption was 19.4MB. Max. memory is 16.1GB. [2021-12-06 17:16:15,697 INFO L158 Benchmark]: BuchiAutomizer took 8218.44ms. Allocated memory was 104.9MB in the beginning and 1.4GB in the end (delta: 1.3GB). Free memory was 52.8MB in the beginning and 876.1MB in the end (delta: -823.4MB). Peak memory consumption was 493.6MB. Max. memory is 16.1GB. [2021-12-06 17:16:15,697 INFO L158 Benchmark]: Witness Printer took 38.30ms. Allocated memory is still 1.4GB. Free memory was 876.1MB in the beginning and 871.9MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-06 17:16:15,699 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.12ms. Allocated memory is still 86.0MB. Free memory is still 66.1MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 261.88ms. Allocated memory was 86.0MB in the beginning and 104.9MB in the end (delta: 18.9MB). Free memory was 49.3MB in the beginning and 77.0MB in the end (delta: -27.7MB). Peak memory consumption was 7.9MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 47.12ms. Allocated memory is still 104.9MB. Free memory was 77.0MB in the beginning and 72.6MB in the end (delta: 4.3MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 46.46ms. Allocated memory is still 104.9MB. Free memory was 72.6MB in the beginning and 69.0MB in the end (delta: 3.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 683.25ms. Allocated memory is still 104.9MB. Free memory was 69.0MB in the beginning and 53.3MB in the end (delta: 15.7MB). Peak memory consumption was 19.4MB. Max. memory is 16.1GB. * BuchiAutomizer took 8218.44ms. Allocated memory was 104.9MB in the beginning and 1.4GB in the end (delta: 1.3GB). Free memory was 52.8MB in the beginning and 876.1MB in the end (delta: -823.4MB). Peak memory consumption was 493.6MB. Max. memory is 16.1GB. * Witness Printer took 38.30ms. Allocated memory is still 1.4GB. Free memory was 876.1MB in the beginning and 871.9MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 22 terminating modules (22 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.22 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 39456 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 8.1s and 23 iterations. TraceHistogramMax:1. Analysis of lassos took 2.5s. Construction of modules took 0.4s. Büchi inclusion checks took 1.0s. Highest rank in rank-based complementation 0. Minimization of det autom 22. Minimization of nondet autom 0. Automata minimization 1.9s AutomataMinimizationTime, 22 MinimizatonAttempts, 33831 StatesRemovedByMinimization, 15 NontrivialMinimizations. Non-live state removal took 1.2s Buchi closure took 0.1s. Biggest automaton had 39456 states and ocurred in iteration 22. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 19785 SdHoareTripleChecker+Valid, 0.6s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 19785 mSDsluCounter, 33416 SdHoareTripleChecker+Invalid, 0.5s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 17252 mSDsCounter, 269 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 748 IncrementalHoareTripleChecker+Invalid, 1017 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 269 mSolverCounterUnsat, 16164 mSDtfsCounter, 748 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc4 concLT0 SILN1 SILU0 SILI13 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 435]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {tmp_ndt_3=0, NULL=0, t3_st=0, token=0, NULL=1, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@348b8cc5=0, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6b65576c=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@668b1ad9=0, tmp_ndt_2=0, t4_i=1, \result=0, E_3=2, t4_pc=0, E_1=2, tmp_ndt_1=0, __retres1=1, tmp=1, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2ae2cc46=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@98732bc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2b64854=0, m_st=0, NULL=0, t3_pc=0, tmp___3=0, __retres1=0, tmp___0=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@70546e26=0, tmp___2=0, m_pc=0, \result=0, \result=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@11b0bc34=0, \result=0, \result=0, tmp___1=0, __retres1=0, T2_E=2, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7adf21d3=0, t1_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@277c1d87=0, E_2=2, tmp___0=0, E_4=2, T1_E=2, __retres1=0, M_E=2, t2_i=1, T4_E=2, \result=0, t3_i=1, t4_st=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@20fb36fd=0, t1_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@63602539=0, __retres1=0, local=0, t2_pc=0, tmp_ndt_5=0, __retres1=0, tmp_ndt_4=0, E_M=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1851394d=0, kernel_st=1, T3_E=2, t1_i=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 435]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int m_i ; [L35] int t1_i ; [L36] int t2_i ; [L37] int t3_i ; [L38] int t4_i ; [L39] int M_E = 2; [L40] int T1_E = 2; [L41] int T2_E = 2; [L42] int T3_E = 2; [L43] int T4_E = 2; [L44] int E_M = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; [L55] int token ; [L57] int local ; [L860] int __retres1 ; [L864] CALL init_model() [L772] m_i = 1 [L773] t1_i = 1 [L774] t2_i = 1 [L775] t3_i = 1 [L776] t4_i = 1 [L864] RET init_model() [L865] CALL start_simulation() [L801] int kernel_st ; [L802] int tmp ; [L803] int tmp___0 ; [L807] kernel_st = 0 [L808] FCALL update_channels() [L809] CALL init_threads() [L365] COND TRUE m_i == 1 [L366] m_st = 0 [L370] COND TRUE t1_i == 1 [L371] t1_st = 0 [L375] COND TRUE t2_i == 1 [L376] t2_st = 0 [L380] COND TRUE t3_i == 1 [L381] t3_st = 0 [L385] COND TRUE t4_i == 1 [L386] t4_st = 0 [L809] RET init_threads() [L810] CALL fire_delta_events() [L526] COND FALSE !(M_E == 0) [L531] COND FALSE !(T1_E == 0) [L536] COND FALSE !(T2_E == 0) [L541] COND FALSE !(T3_E == 0) [L546] COND FALSE !(T4_E == 0) [L551] COND FALSE !(E_M == 0) [L556] COND FALSE !(E_1 == 0) [L561] COND FALSE !(E_2 == 0) [L566] COND FALSE !(E_3 == 0) [L571] COND FALSE !(E_4 == 0) [L810] RET fire_delta_events() [L811] CALL activate_threads() [L639] int tmp ; [L640] int tmp___0 ; [L641] int tmp___1 ; [L642] int tmp___2 ; [L643] int tmp___3 ; [L647] CALL, EXPR is_master_triggered() [L259] int __retres1 ; [L262] COND FALSE !(m_pc == 1) [L272] __retres1 = 0 [L274] return (__retres1); [L647] RET, EXPR is_master_triggered() [L647] tmp = is_master_triggered() [L649] COND FALSE !(\read(tmp)) [L655] CALL, EXPR is_transmit1_triggered() [L278] int __retres1 ; [L281] COND FALSE !(t1_pc == 1) [L291] __retres1 = 0 [L293] return (__retres1); [L655] RET, EXPR is_transmit1_triggered() [L655] tmp___0 = is_transmit1_triggered() [L657] COND FALSE !(\read(tmp___0)) [L663] CALL, EXPR is_transmit2_triggered() [L297] int __retres1 ; [L300] COND FALSE !(t2_pc == 1) [L310] __retres1 = 0 [L312] return (__retres1); [L663] RET, EXPR is_transmit2_triggered() [L663] tmp___1 = is_transmit2_triggered() [L665] COND FALSE !(\read(tmp___1)) [L671] CALL, EXPR is_transmit3_triggered() [L316] int __retres1 ; [L319] COND FALSE !(t3_pc == 1) [L329] __retres1 = 0 [L331] return (__retres1); [L671] RET, EXPR is_transmit3_triggered() [L671] tmp___2 = is_transmit3_triggered() [L673] COND FALSE !(\read(tmp___2)) [L679] CALL, EXPR is_transmit4_triggered() [L335] int __retres1 ; [L338] COND FALSE !(t4_pc == 1) [L348] __retres1 = 0 [L350] return (__retres1); [L679] RET, EXPR is_transmit4_triggered() [L679] tmp___3 = is_transmit4_triggered() [L681] COND FALSE !(\read(tmp___3)) [L811] RET activate_threads() [L812] CALL reset_delta_events() [L584] COND FALSE !(M_E == 1) [L589] COND FALSE !(T1_E == 1) [L594] COND FALSE !(T2_E == 1) [L599] COND FALSE !(T3_E == 1) [L604] COND FALSE !(T4_E == 1) [L609] COND FALSE !(E_M == 1) [L614] COND FALSE !(E_1 == 1) [L619] COND FALSE !(E_2 == 1) [L624] COND FALSE !(E_3 == 1) [L629] COND FALSE !(E_4 == 1) [L812] RET reset_delta_events() [L815] COND TRUE 1 [L818] kernel_st = 1 [L819] CALL eval() [L431] int tmp ; Loop: [L435] COND TRUE 1 [L438] CALL, EXPR exists_runnable_thread() [L395] int __retres1 ; [L398] COND TRUE m_st == 0 [L399] __retres1 = 1 [L426] return (__retres1); [L438] RET, EXPR exists_runnable_thread() [L438] tmp = exists_runnable_thread() [L440] COND TRUE \read(tmp) [L445] COND TRUE m_st == 0 [L446] int tmp_ndt_1; [L447] tmp_ndt_1 = __VERIFIER_nondet_int() [L448] COND FALSE !(\read(tmp_ndt_1)) [L459] COND TRUE t1_st == 0 [L460] int tmp_ndt_2; [L461] tmp_ndt_2 = __VERIFIER_nondet_int() [L462] COND FALSE !(\read(tmp_ndt_2)) [L473] COND TRUE t2_st == 0 [L474] int tmp_ndt_3; [L475] tmp_ndt_3 = __VERIFIER_nondet_int() [L476] COND FALSE !(\read(tmp_ndt_3)) [L487] COND TRUE t3_st == 0 [L488] int tmp_ndt_4; [L489] tmp_ndt_4 = __VERIFIER_nondet_int() [L490] COND FALSE !(\read(tmp_ndt_4)) [L501] COND TRUE t4_st == 0 [L502] int tmp_ndt_5; [L503] tmp_ndt_5 = __VERIFIER_nondet_int() [L504] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-12-06 17:16:15,742 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e5b09e43-d5a2-457e-befc-0eb09998c173/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)