./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.08.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 839c364b Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4848a372-466a-44ae-8e52-d87824d483ea/bin/uautomizer-DrprNOufMa/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4848a372-466a-44ae-8e52-d87824d483ea/bin/uautomizer-DrprNOufMa/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4848a372-466a-44ae-8e52-d87824d483ea/bin/uautomizer-DrprNOufMa/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4848a372-466a-44ae-8e52-d87824d483ea/bin/uautomizer-DrprNOufMa/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.08.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4848a372-466a-44ae-8e52-d87824d483ea/bin/uautomizer-DrprNOufMa/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4848a372-466a-44ae-8e52-d87824d483ea/bin/uautomizer-DrprNOufMa --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 19daebdfafed51668fa57cd9e9dbb1892c2070de71da48d425d8df389215d260 --- Real Ultimate output --- This is Ultimate 0.2.2-hotfix-svcomp22-839c364 [2021-12-06 18:37:46,826 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-06 18:37:46,828 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-06 18:37:46,861 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-06 18:37:46,861 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-06 18:37:46,863 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-06 18:37:46,864 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-06 18:37:46,867 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-06 18:37:46,869 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-06 18:37:46,870 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-06 18:37:46,871 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-06 18:37:46,873 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-06 18:37:46,873 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-06 18:37:46,875 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-06 18:37:46,876 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-06 18:37:46,878 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-06 18:37:46,879 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-06 18:37:46,880 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-06 18:37:46,883 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-06 18:37:46,885 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-06 18:37:46,887 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-06 18:37:46,889 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-06 18:37:46,890 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-06 18:37:46,891 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-06 18:37:46,895 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-06 18:37:46,895 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-06 18:37:46,895 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-06 18:37:46,897 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-06 18:37:46,897 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-06 18:37:46,898 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-06 18:37:46,899 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-06 18:37:46,899 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-06 18:37:46,900 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-06 18:37:46,901 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-06 18:37:46,902 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-06 18:37:46,903 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-06 18:37:46,903 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-06 18:37:46,903 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-06 18:37:46,904 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-06 18:37:46,905 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-06 18:37:46,905 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-06 18:37:46,906 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4848a372-466a-44ae-8e52-d87824d483ea/bin/uautomizer-DrprNOufMa/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-06 18:37:46,933 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-06 18:37:46,934 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-06 18:37:46,934 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-06 18:37:46,934 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-06 18:37:46,935 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-06 18:37:46,936 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-06 18:37:46,936 INFO L138 SettingsManager]: * Use SBE=true [2021-12-06 18:37:46,936 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-06 18:37:46,936 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-06 18:37:46,936 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-06 18:37:46,937 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-06 18:37:46,937 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-06 18:37:46,937 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-06 18:37:46,937 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-06 18:37:46,937 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-06 18:37:46,938 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-06 18:37:46,938 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-06 18:37:46,938 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-06 18:37:46,938 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-06 18:37:46,938 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-06 18:37:46,938 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-06 18:37:46,939 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-06 18:37:46,939 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-06 18:37:46,939 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-06 18:37:46,939 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-06 18:37:46,939 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-06 18:37:46,940 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-06 18:37:46,940 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-06 18:37:46,940 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-06 18:37:46,940 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-06 18:37:46,940 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-06 18:37:46,941 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-06 18:37:46,942 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-06 18:37:46,942 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4848a372-466a-44ae-8e52-d87824d483ea/bin/uautomizer-DrprNOufMa/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4848a372-466a-44ae-8e52-d87824d483ea/bin/uautomizer-DrprNOufMa Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 19daebdfafed51668fa57cd9e9dbb1892c2070de71da48d425d8df389215d260 [2021-12-06 18:37:47,184 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-06 18:37:47,202 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-06 18:37:47,204 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-06 18:37:47,205 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-06 18:37:47,205 INFO L275 PluginConnector]: CDTParser initialized [2021-12-06 18:37:47,206 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4848a372-466a-44ae-8e52-d87824d483ea/bin/uautomizer-DrprNOufMa/../../sv-benchmarks/c/systemc/token_ring.08.cil-2.c [2021-12-06 18:37:47,277 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4848a372-466a-44ae-8e52-d87824d483ea/bin/uautomizer-DrprNOufMa/data/561a337db/ba87e4c0f87348379aa52b8681462962/FLAG4a270a100 [2021-12-06 18:37:47,705 INFO L306 CDTParser]: Found 1 translation units. [2021-12-06 18:37:47,705 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4848a372-466a-44ae-8e52-d87824d483ea/sv-benchmarks/c/systemc/token_ring.08.cil-2.c [2021-12-06 18:37:47,718 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4848a372-466a-44ae-8e52-d87824d483ea/bin/uautomizer-DrprNOufMa/data/561a337db/ba87e4c0f87348379aa52b8681462962/FLAG4a270a100 [2021-12-06 18:37:47,733 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4848a372-466a-44ae-8e52-d87824d483ea/bin/uautomizer-DrprNOufMa/data/561a337db/ba87e4c0f87348379aa52b8681462962 [2021-12-06 18:37:47,735 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-06 18:37:47,737 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-06 18:37:47,738 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-06 18:37:47,738 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-06 18:37:47,741 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-06 18:37:47,742 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 06:37:47" (1/1) ... [2021-12-06 18:37:47,743 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@53cd2404 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:37:47, skipping insertion in model container [2021-12-06 18:37:47,743 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 06:37:47" (1/1) ... [2021-12-06 18:37:47,749 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-06 18:37:47,783 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-06 18:37:47,936 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4848a372-466a-44ae-8e52-d87824d483ea/sv-benchmarks/c/systemc/token_ring.08.cil-2.c[671,684] [2021-12-06 18:37:48,030 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-06 18:37:48,040 INFO L203 MainTranslator]: Completed pre-run [2021-12-06 18:37:48,050 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4848a372-466a-44ae-8e52-d87824d483ea/sv-benchmarks/c/systemc/token_ring.08.cil-2.c[671,684] [2021-12-06 18:37:48,104 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-06 18:37:48,120 INFO L208 MainTranslator]: Completed translation [2021-12-06 18:37:48,121 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:37:48 WrapperNode [2021-12-06 18:37:48,121 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-06 18:37:48,121 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-06 18:37:48,122 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-06 18:37:48,122 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-06 18:37:48,127 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:37:48" (1/1) ... [2021-12-06 18:37:48,139 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:37:48" (1/1) ... [2021-12-06 18:37:48,216 INFO L137 Inliner]: procedures = 44, calls = 56, calls flagged for inlining = 51, calls inlined = 158, statements flattened = 2370 [2021-12-06 18:37:48,217 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-06 18:37:48,217 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-06 18:37:48,218 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-06 18:37:48,218 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-06 18:37:48,224 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:37:48" (1/1) ... [2021-12-06 18:37:48,224 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:37:48" (1/1) ... [2021-12-06 18:37:48,232 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:37:48" (1/1) ... [2021-12-06 18:37:48,233 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:37:48" (1/1) ... [2021-12-06 18:37:48,263 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:37:48" (1/1) ... [2021-12-06 18:37:48,294 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:37:48" (1/1) ... [2021-12-06 18:37:48,299 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:37:48" (1/1) ... [2021-12-06 18:37:48,310 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-06 18:37:48,311 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-06 18:37:48,311 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-06 18:37:48,312 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-06 18:37:48,313 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:37:48" (1/1) ... [2021-12-06 18:37:48,321 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 18:37:48,336 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4848a372-466a-44ae-8e52-d87824d483ea/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:37:48,361 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4848a372-466a-44ae-8e52-d87824d483ea/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 18:37:48,375 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4848a372-466a-44ae-8e52-d87824d483ea/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-06 18:37:48,410 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-06 18:37:48,411 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-06 18:37:48,411 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-06 18:37:48,411 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-06 18:37:48,512 INFO L236 CfgBuilder]: Building ICFG [2021-12-06 18:37:48,513 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-06 18:37:49,630 INFO L277 CfgBuilder]: Performing block encoding [2021-12-06 18:37:49,649 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-06 18:37:49,650 INFO L301 CfgBuilder]: Removed 11 assume(true) statements. [2021-12-06 18:37:49,653 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 06:37:49 BoogieIcfgContainer [2021-12-06 18:37:49,653 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-06 18:37:49,654 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-06 18:37:49,654 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-06 18:37:49,656 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-06 18:37:49,657 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 18:37:49,657 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.12 06:37:47" (1/3) ... [2021-12-06 18:37:49,658 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@414d2d29 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.12 06:37:49, skipping insertion in model container [2021-12-06 18:37:49,658 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 18:37:49,658 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:37:48" (2/3) ... [2021-12-06 18:37:49,658 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@414d2d29 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.12 06:37:49, skipping insertion in model container [2021-12-06 18:37:49,658 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 18:37:49,658 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 06:37:49" (3/3) ... [2021-12-06 18:37:49,659 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.08.cil-2.c [2021-12-06 18:37:49,694 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-06 18:37:49,694 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-06 18:37:49,695 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-06 18:37:49,695 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-06 18:37:49,695 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-06 18:37:49,695 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-06 18:37:49,695 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-06 18:37:49,695 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-06 18:37:49,730 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1006 states, 1005 states have (on average 1.5154228855721392) internal successors, (1523), 1005 states have internal predecessors, (1523), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:37:49,792 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2021-12-06 18:37:49,792 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:37:49,792 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:37:49,805 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:37:49,805 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:37:49,805 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-06 18:37:49,808 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1006 states, 1005 states have (on average 1.5154228855721392) internal successors, (1523), 1005 states have internal predecessors, (1523), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:37:49,824 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 887 [2021-12-06 18:37:49,824 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:37:49,824 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:37:49,829 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:37:49,829 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:37:49,839 INFO L791 eck$LassoCheckResult]: Stem: 486#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 925#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 417#L1278true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 512#L602true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 305#L609true assume !(1 == ~m_i~0);~m_st~0 := 2; 1006#L609-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 66#L614-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 105#L619-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 711#L624-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 966#L629-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 51#L634-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 281#L639-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 855#L644-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 298#L649-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 108#L866true assume !(0 == ~M_E~0); 970#L866-2true assume !(0 == ~T1_E~0); 440#L871-1true assume !(0 == ~T2_E~0); 837#L876-1true assume !(0 == ~T3_E~0); 830#L881-1true assume !(0 == ~T4_E~0); 455#L886-1true assume 0 == ~T5_E~0;~T5_E~0 := 1; 276#L891-1true assume !(0 == ~T6_E~0); 443#L896-1true assume !(0 == ~T7_E~0); 575#L901-1true assume !(0 == ~T8_E~0); 466#L906-1true assume !(0 == ~E_M~0); 851#L911-1true assume !(0 == ~E_1~0); 304#L916-1true assume !(0 == ~E_2~0); 577#L921-1true assume !(0 == ~E_3~0); 732#L926-1true assume 0 == ~E_4~0;~E_4~0 := 1; 864#L931-1true assume !(0 == ~E_5~0); 891#L936-1true assume !(0 == ~E_6~0); 978#L941-1true assume !(0 == ~E_7~0); 307#L946-1true assume !(0 == ~E_8~0); 775#L951-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 896#L430true assume !(1 == ~m_pc~0); 679#L430-2true is_master_triggered_~__retres1~0#1 := 0; 20#L441true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 381#L442true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 390#L1073true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 817#L1073-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 559#L449true assume 1 == ~t1_pc~0; 580#L450true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 813#L460true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3#L461true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 902#L1081true assume !(0 != activate_threads_~tmp___0~0#1); 477#L1081-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 346#L468true assume !(1 == ~t2_pc~0); 226#L468-2true is_transmit2_triggered_~__retres1~2#1 := 0; 428#L479true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 280#L480true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 219#L1089true assume !(0 != activate_threads_~tmp___1~0#1); 21#L1089-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 894#L487true assume 1 == ~t3_pc~0; 818#L488true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 68#L498true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 542#L499true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 630#L1097true assume !(0 != activate_threads_~tmp___2~0#1); 262#L1097-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 343#L506true assume !(1 == ~t4_pc~0); 848#L506-2true is_transmit4_triggered_~__retres1~4#1 := 0; 971#L517true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 752#L518true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 819#L1105true assume !(0 != activate_threads_~tmp___3~0#1); 337#L1105-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 227#L525true assume 1 == ~t5_pc~0; 188#L526true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 700#L536true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 310#L537true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 955#L1113true assume !(0 != activate_threads_~tmp___4~0#1); 140#L1113-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 334#L544true assume !(1 == ~t6_pc~0); 228#L544-2true is_transmit6_triggered_~__retres1~6#1 := 0; 495#L555true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 998#L556true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32#L1121true assume !(0 != activate_threads_~tmp___5~0#1); 792#L1121-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 696#L563true assume 1 == ~t7_pc~0; 514#L564true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45#L574true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 368#L575true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 277#L1129true assume !(0 != activate_threads_~tmp___6~0#1); 112#L1129-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 496#L582true assume 1 == ~t8_pc~0; 73#L583true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 821#L593true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 981#L594true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 253#L1137true assume !(0 != activate_threads_~tmp___7~0#1); 190#L1137-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 561#L964true assume 1 == ~M_E~0;~M_E~0 := 2; 816#L964-2true assume !(1 == ~T1_E~0); 141#L969-1true assume !(1 == ~T2_E~0); 745#L974-1true assume !(1 == ~T3_E~0); 597#L979-1true assume !(1 == ~T4_E~0); 950#L984-1true assume !(1 == ~T5_E~0); 231#L989-1true assume !(1 == ~T6_E~0); 449#L994-1true assume !(1 == ~T7_E~0); 163#L999-1true assume 1 == ~T8_E~0;~T8_E~0 := 2; 566#L1004-1true assume !(1 == ~E_M~0); 33#L1009-1true assume !(1 == ~E_1~0); 157#L1014-1true assume !(1 == ~E_2~0); 549#L1019-1true assume !(1 == ~E_3~0); 791#L1024-1true assume !(1 == ~E_4~0); 120#L1029-1true assume !(1 == ~E_5~0); 172#L1034-1true assume !(1 == ~E_6~0); 982#L1039-1true assume 1 == ~E_7~0;~E_7~0 := 2; 760#L1044-1true assume !(1 == ~E_8~0); 286#L1049-1true assume { :end_inline_reset_delta_events } true; 104#L1315-2true [2021-12-06 18:37:49,842 INFO L793 eck$LassoCheckResult]: Loop: 104#L1315-2true assume !false; 873#L1316true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 173#L841true assume false; 617#L856true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 987#L602-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24#L866-3true assume 0 == ~M_E~0;~M_E~0 := 1; 826#L866-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 176#L871-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 265#L876-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 184#L881-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 666#L886-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 323#L891-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 452#L896-3true assume !(0 == ~T7_E~0); 240#L901-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 325#L906-3true assume 0 == ~E_M~0;~E_M~0 := 1; 587#L911-3true assume 0 == ~E_1~0;~E_1~0 := 1; 505#L916-3true assume 0 == ~E_2~0;~E_2~0 := 1; 200#L921-3true assume 0 == ~E_3~0;~E_3~0 := 1; 488#L926-3true assume 0 == ~E_4~0;~E_4~0 := 1; 583#L931-3true assume 0 == ~E_5~0;~E_5~0 := 1; 245#L936-3true assume !(0 == ~E_6~0); 336#L941-3true assume 0 == ~E_7~0;~E_7~0 := 1; 586#L946-3true assume 0 == ~E_8~0;~E_8~0 := 1; 177#L951-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 865#L430-30true assume !(1 == ~m_pc~0); 625#L430-32true is_master_triggered_~__retres1~0#1 := 0; 250#L441-10true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75#L442-10true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 531#L1073-30true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 917#L1073-32true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 539#L449-30true assume !(1 == ~t1_pc~0); 929#L449-32true is_transmit1_triggered_~__retres1~1#1 := 0; 31#L460-10true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 447#L461-10true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 230#L1081-30true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 71#L1081-32true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 382#L468-30true assume !(1 == ~t2_pc~0); 800#L468-32true is_transmit2_triggered_~__retres1~2#1 := 0; 593#L479-10true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 898#L480-10true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 318#L1089-30true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 773#L1089-32true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 222#L487-30true assume 1 == ~t3_pc~0; 211#L488-10true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 843#L498-10true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 306#L499-10true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 803#L1097-30true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 557#L1097-32true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 272#L506-30true assume 1 == ~t4_pc~0; 983#L507-10true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 288#L517-10true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 301#L518-10true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 614#L1105-30true assume !(0 != activate_threads_~tmp___3~0#1); 223#L1105-32true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 972#L525-30true assume 1 == ~t5_pc~0; 690#L526-10true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 920#L536-10true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63#L537-10true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 672#L1113-30true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 225#L1113-32true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 96#L544-30true assume !(1 == ~t6_pc~0); 741#L544-32true is_transmit6_triggered_~__retres1~6#1 := 0; 868#L555-10true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 992#L556-10true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 702#L1121-30true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 994#L1121-32true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 662#L563-30true assume !(1 == ~t7_pc~0); 165#L563-32true is_transmit7_triggered_~__retres1~7#1 := 0; 90#L574-10true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 939#L575-10true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 282#L1129-30true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 909#L1129-32true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 640#L582-30true assume 1 == ~t8_pc~0; 585#L583-10true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 274#L593-10true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 693#L594-10true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 991#L1137-30true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 904#L1137-32true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36#L964-3true assume 1 == ~M_E~0;~M_E~0 := 2; 102#L964-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 209#L969-3true assume !(1 == ~T2_E~0); 98#L974-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 921#L979-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 349#L984-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 986#L989-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 122#L994-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 824#L999-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 474#L1004-3true assume 1 == ~E_M~0;~E_M~0 := 2; 59#L1009-3true assume !(1 == ~E_1~0); 543#L1014-3true assume 1 == ~E_2~0;~E_2~0 := 2; 331#L1019-3true assume 1 == ~E_3~0;~E_3~0 := 2; 968#L1024-3true assume 1 == ~E_4~0;~E_4~0 := 2; 320#L1029-3true assume 1 == ~E_5~0;~E_5~0 := 2; 302#L1034-3true assume 1 == ~E_6~0;~E_6~0 := 2; 548#L1039-3true assume 1 == ~E_7~0;~E_7~0 := 2; 578#L1044-3true assume 1 == ~E_8~0;~E_8~0 := 2; 117#L1049-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 453#L662-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 687#L709-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 425#L710-1true start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 136#L1334true assume !(0 == start_simulation_~tmp~3#1); 812#L1334-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 146#L662-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5#L709-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 335#L710-2true stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 918#L1289true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 735#L1296true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 497#L1297true start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 710#L1347true assume !(0 != start_simulation_~tmp___0~1#1); 104#L1315-2true [2021-12-06 18:37:49,848 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:37:49,849 INFO L85 PathProgramCache]: Analyzing trace with hash -1103313420, now seen corresponding path program 1 times [2021-12-06 18:37:49,859 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:37:49,859 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2075403567] [2021-12-06 18:37:49,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:37:49,861 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:37:49,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:37:50,105 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:37:50,106 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:37:50,106 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2075403567] [2021-12-06 18:37:50,107 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2075403567] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:37:50,107 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:37:50,107 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:37:50,109 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1874864518] [2021-12-06 18:37:50,110 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:37:50,115 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 18:37:50,116 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:37:50,116 INFO L85 PathProgramCache]: Analyzing trace with hash 1133148117, now seen corresponding path program 1 times [2021-12-06 18:37:50,116 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:37:50,116 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1148956443] [2021-12-06 18:37:50,117 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:37:50,117 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:37:50,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:37:50,165 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:37:50,165 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:37:50,165 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1148956443] [2021-12-06 18:37:50,166 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1148956443] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:37:50,166 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:37:50,166 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 18:37:50,166 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [443418825] [2021-12-06 18:37:50,167 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:37:50,168 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 18:37:50,169 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:37:50,206 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 18:37:50,206 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 18:37:50,211 INFO L87 Difference]: Start difference. First operand has 1006 states, 1005 states have (on average 1.5154228855721392) internal successors, (1523), 1005 states have internal predecessors, (1523), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:37:50,323 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:37:50,323 INFO L93 Difference]: Finished difference Result 1004 states and 1496 transitions. [2021-12-06 18:37:50,327 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 18:37:50,332 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1004 states and 1496 transitions. [2021-12-06 18:37:50,344 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2021-12-06 18:37:50,359 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1004 states to 998 states and 1490 transitions. [2021-12-06 18:37:50,360 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 998 [2021-12-06 18:37:50,363 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 998 [2021-12-06 18:37:50,363 INFO L73 IsDeterministic]: Start isDeterministic. Operand 998 states and 1490 transitions. [2021-12-06 18:37:50,370 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:37:50,370 INFO L681 BuchiCegarLoop]: Abstraction has 998 states and 1490 transitions. [2021-12-06 18:37:50,389 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 998 states and 1490 transitions. [2021-12-06 18:37:50,432 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 998 to 998. [2021-12-06 18:37:50,434 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 998 states, 998 states have (on average 1.4929859719438878) internal successors, (1490), 997 states have internal predecessors, (1490), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:37:50,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 998 states to 998 states and 1490 transitions. [2021-12-06 18:37:50,440 INFO L704 BuchiCegarLoop]: Abstraction has 998 states and 1490 transitions. [2021-12-06 18:37:50,440 INFO L587 BuchiCegarLoop]: Abstraction has 998 states and 1490 transitions. [2021-12-06 18:37:50,440 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-06 18:37:50,440 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 998 states and 1490 transitions. [2021-12-06 18:37:50,447 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2021-12-06 18:37:50,447 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:37:50,447 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:37:50,450 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:37:50,450 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:37:50,451 INFO L791 eck$LassoCheckResult]: Stem: 2789#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 2790#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2716#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2717#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2569#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 2570#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2155#L614-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2156#L619-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2237#L624-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2948#L629-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2125#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2126#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2533#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2558#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2241#L866 assume !(0 == ~M_E~0); 2242#L866-2 assume !(0 == ~T1_E~0); 2744#L871-1 assume !(0 == ~T2_E~0); 2745#L876-1 assume !(0 == ~T3_E~0); 2995#L881-1 assume !(0 == ~T4_E~0); 2754#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2524#L891-1 assume !(0 == ~T6_E~0); 2525#L896-1 assume !(0 == ~T7_E~0); 2747#L901-1 assume !(0 == ~T8_E~0); 2765#L906-1 assume !(0 == ~E_M~0); 2766#L911-1 assume !(0 == ~E_1~0); 2567#L916-1 assume !(0 == ~E_2~0); 2568#L921-1 assume !(0 == ~E_3~0); 2861#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2960#L931-1 assume !(0 == ~E_5~0); 3000#L936-1 assume !(0 == ~E_6~0); 3007#L941-1 assume !(0 == ~E_7~0); 2573#L946-1 assume !(0 == ~E_8~0); 2574#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2979#L430 assume !(1 == ~m_pc~0); 2432#L430-2 is_master_triggered_~__retres1~0#1 := 0; 2060#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2061#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2674#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2684#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2845#L449 assume 1 == ~t1_pc~0; 2846#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2245#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2019#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2020#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 2780#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2629#L468 assume !(1 == ~t2_pc~0); 2044#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2043#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2532#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2439#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 2062#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2063#L487 assume 1 == ~t3_pc~0; 2992#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2159#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2160#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2834#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 2498#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2499#L506 assume !(1 == ~t4_pc~0); 2625#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2670#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2970#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2971#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 2620#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2450#L525 assume 1 == ~t5_pc~0; 2385#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2104#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2577#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2578#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 2301#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2302#L544 assume !(1 == ~t6_pc~0); 2451#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2452#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2796#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2086#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 2087#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2936#L563 assume 1 == ~t7_pc~0; 2814#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2114#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2115#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2526#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 2246#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2247#L582 assume 1 == ~t8_pc~0; 2170#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2171#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2993#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2487#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 2389#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2390#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 2848#L964-2 assume !(1 == ~T1_E~0); 2303#L969-1 assume !(1 == ~T2_E~0); 2304#L974-1 assume !(1 == ~T3_E~0); 2873#L979-1 assume !(1 == ~T4_E~0); 2874#L984-1 assume !(1 == ~T5_E~0); 2457#L989-1 assume !(1 == ~T6_E~0); 2458#L994-1 assume !(1 == ~T7_E~0); 2343#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2344#L1004-1 assume !(1 == ~E_M~0); 2088#L1009-1 assume !(1 == ~E_1~0); 2089#L1014-1 assume !(1 == ~E_2~0); 2332#L1019-1 assume !(1 == ~E_3~0); 2837#L1024-1 assume !(1 == ~E_4~0); 2265#L1029-1 assume !(1 == ~E_5~0); 2266#L1034-1 assume !(1 == ~E_6~0); 2360#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 2974#L1044-1 assume !(1 == ~E_8~0); 2542#L1049-1 assume { :end_inline_reset_delta_events } true; 2235#L1315-2 [2021-12-06 18:37:50,452 INFO L793 eck$LassoCheckResult]: Loop: 2235#L1315-2 assume !false; 2236#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2022#L841 assume !false; 2361#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2296#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2297#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2137#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2057#L724 assume !(0 != eval_~tmp~0#1); 2059#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2887#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2068#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2069#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2364#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2365#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2378#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2379#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2602#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2603#L896-3 assume !(0 == ~T7_E~0); 2470#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2471#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2604#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2807#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2410#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2411#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2791#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2477#L936-3 assume !(0 == ~E_6~0); 2478#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2619#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2366#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2367#L430-30 assume 1 == ~m_pc~0; 2391#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2392#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2175#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2176#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2825#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2829#L449-30 assume 1 == ~t1_pc~0; 2394#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2084#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2085#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2456#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2168#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2169#L468-30 assume 1 == ~t2_pc~0; 2260#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2261#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2870#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2593#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2594#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2444#L487-30 assume 1 == ~t3_pc~0; 2425#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2240#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2571#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2572#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2844#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2518#L506-30 assume !(1 == ~t4_pc~0); 2519#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2545#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2546#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2563#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 2445#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2446#L525-30 assume 1 == ~t5_pc~0; 2931#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2932#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2150#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2151#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2449#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2219#L544-30 assume 1 == ~t6_pc~0; 2027#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2028#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3001#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2941#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2942#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2918#L563-30 assume 1 == ~t7_pc~0; 2189#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2190#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2208#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2534#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2535#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2905#L582-30 assume 1 == ~t8_pc~0; 2867#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2287#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2522#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2935#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3008#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2093#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2094#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2231#L969-3 assume !(1 == ~T2_E~0); 2222#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2223#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2634#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2635#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2268#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2269#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2778#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2140#L1009-3 assume !(1 == ~E_1~0); 2141#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2615#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2616#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2597#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2564#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2565#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2836#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2258#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2259#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2388#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2725#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2292#L1334 assume !(0 == start_simulation_~tmp~3#1); 2294#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2312#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2023#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2024#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 2618#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2962#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2797#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2798#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 2235#L1315-2 [2021-12-06 18:37:50,453 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:37:50,453 INFO L85 PathProgramCache]: Analyzing trace with hash 763395254, now seen corresponding path program 1 times [2021-12-06 18:37:50,453 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:37:50,453 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [552352449] [2021-12-06 18:37:50,454 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:37:50,454 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:37:50,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:37:50,516 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:37:50,516 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:37:50,516 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [552352449] [2021-12-06 18:37:50,517 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [552352449] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:37:50,517 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:37:50,517 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:37:50,517 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [47006418] [2021-12-06 18:37:50,517 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:37:50,518 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 18:37:50,519 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:37:50,519 INFO L85 PathProgramCache]: Analyzing trace with hash 1016404398, now seen corresponding path program 1 times [2021-12-06 18:37:50,519 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:37:50,519 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [110269474] [2021-12-06 18:37:50,519 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:37:50,520 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:37:50,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:37:50,619 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:37:50,620 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:37:50,620 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [110269474] [2021-12-06 18:37:50,620 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [110269474] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:37:50,620 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:37:50,621 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:37:50,621 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [627632611] [2021-12-06 18:37:50,621 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:37:50,621 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 18:37:50,622 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:37:50,622 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 18:37:50,622 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 18:37:50,623 INFO L87 Difference]: Start difference. First operand 998 states and 1490 transitions. cyclomatic complexity: 493 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:37:50,662 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:37:50,662 INFO L93 Difference]: Finished difference Result 998 states and 1489 transitions. [2021-12-06 18:37:50,662 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 18:37:50,663 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 998 states and 1489 transitions. [2021-12-06 18:37:50,694 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2021-12-06 18:37:50,703 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 998 states to 998 states and 1489 transitions. [2021-12-06 18:37:50,703 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 998 [2021-12-06 18:37:50,705 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 998 [2021-12-06 18:37:50,705 INFO L73 IsDeterministic]: Start isDeterministic. Operand 998 states and 1489 transitions. [2021-12-06 18:37:50,707 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:37:50,707 INFO L681 BuchiCegarLoop]: Abstraction has 998 states and 1489 transitions. [2021-12-06 18:37:50,709 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 998 states and 1489 transitions. [2021-12-06 18:37:50,725 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 998 to 998. [2021-12-06 18:37:50,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 998 states, 998 states have (on average 1.4919839679358717) internal successors, (1489), 997 states have internal predecessors, (1489), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:37:50,732 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 998 states to 998 states and 1489 transitions. [2021-12-06 18:37:50,732 INFO L704 BuchiCegarLoop]: Abstraction has 998 states and 1489 transitions. [2021-12-06 18:37:50,732 INFO L587 BuchiCegarLoop]: Abstraction has 998 states and 1489 transitions. [2021-12-06 18:37:50,732 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-06 18:37:50,732 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 998 states and 1489 transitions. [2021-12-06 18:37:50,738 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2021-12-06 18:37:50,738 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:37:50,739 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:37:50,741 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:37:50,741 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:37:50,742 INFO L791 eck$LassoCheckResult]: Stem: 4792#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 4793#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 4719#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4720#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4572#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 4573#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4158#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4159#L619-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4240#L624-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4951#L629-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4128#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4129#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4536#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4561#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4244#L866 assume !(0 == ~M_E~0); 4245#L866-2 assume !(0 == ~T1_E~0); 4747#L871-1 assume !(0 == ~T2_E~0); 4748#L876-1 assume !(0 == ~T3_E~0); 4998#L881-1 assume !(0 == ~T4_E~0); 4757#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4527#L891-1 assume !(0 == ~T6_E~0); 4528#L896-1 assume !(0 == ~T7_E~0); 4750#L901-1 assume !(0 == ~T8_E~0); 4768#L906-1 assume !(0 == ~E_M~0); 4769#L911-1 assume !(0 == ~E_1~0); 4570#L916-1 assume !(0 == ~E_2~0); 4571#L921-1 assume !(0 == ~E_3~0); 4864#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4963#L931-1 assume !(0 == ~E_5~0); 5003#L936-1 assume !(0 == ~E_6~0); 5010#L941-1 assume !(0 == ~E_7~0); 4576#L946-1 assume !(0 == ~E_8~0); 4577#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4982#L430 assume !(1 == ~m_pc~0); 4435#L430-2 is_master_triggered_~__retres1~0#1 := 0; 4063#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4064#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4677#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4687#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4848#L449 assume 1 == ~t1_pc~0; 4849#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4248#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4022#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4023#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 4783#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4632#L468 assume !(1 == ~t2_pc~0); 4047#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4046#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4535#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4442#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 4065#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4066#L487 assume 1 == ~t3_pc~0; 4995#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4162#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4163#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4837#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 4501#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4502#L506 assume !(1 == ~t4_pc~0); 4628#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4673#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4973#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4974#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 4623#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4453#L525 assume 1 == ~t5_pc~0; 4388#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4107#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4580#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4581#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 4304#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4305#L544 assume !(1 == ~t6_pc~0); 4454#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4455#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4799#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4089#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 4090#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4939#L563 assume 1 == ~t7_pc~0; 4817#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4117#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4118#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4529#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 4249#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4250#L582 assume 1 == ~t8_pc~0; 4173#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4174#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4996#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4490#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 4392#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4393#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 4851#L964-2 assume !(1 == ~T1_E~0); 4306#L969-1 assume !(1 == ~T2_E~0); 4307#L974-1 assume !(1 == ~T3_E~0); 4876#L979-1 assume !(1 == ~T4_E~0); 4877#L984-1 assume !(1 == ~T5_E~0); 4460#L989-1 assume !(1 == ~T6_E~0); 4461#L994-1 assume !(1 == ~T7_E~0); 4346#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4347#L1004-1 assume !(1 == ~E_M~0); 4091#L1009-1 assume !(1 == ~E_1~0); 4092#L1014-1 assume !(1 == ~E_2~0); 4335#L1019-1 assume !(1 == ~E_3~0); 4840#L1024-1 assume !(1 == ~E_4~0); 4268#L1029-1 assume !(1 == ~E_5~0); 4269#L1034-1 assume !(1 == ~E_6~0); 4363#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 4977#L1044-1 assume !(1 == ~E_8~0); 4545#L1049-1 assume { :end_inline_reset_delta_events } true; 4238#L1315-2 [2021-12-06 18:37:50,742 INFO L793 eck$LassoCheckResult]: Loop: 4238#L1315-2 assume !false; 4239#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4025#L841 assume !false; 4364#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4299#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4300#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4140#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4060#L724 assume !(0 != eval_~tmp~0#1); 4062#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4890#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4071#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4072#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4367#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4368#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4381#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4382#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4605#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4606#L896-3 assume !(0 == ~T7_E~0); 4473#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4474#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4607#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4810#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4413#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4414#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4794#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4480#L936-3 assume !(0 == ~E_6~0); 4481#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4622#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4369#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4370#L430-30 assume 1 == ~m_pc~0; 4394#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4395#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4178#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4179#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4828#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4832#L449-30 assume 1 == ~t1_pc~0; 4397#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4087#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4088#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4459#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4171#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4172#L468-30 assume 1 == ~t2_pc~0; 4263#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4264#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4873#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4596#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4597#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4447#L487-30 assume !(1 == ~t3_pc~0); 4242#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 4243#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4574#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4575#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4847#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4521#L506-30 assume !(1 == ~t4_pc~0); 4522#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 4548#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4549#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4566#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 4448#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4449#L525-30 assume 1 == ~t5_pc~0; 4934#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4935#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4153#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4154#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4452#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4222#L544-30 assume !(1 == ~t6_pc~0); 4032#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 4031#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5004#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4944#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4945#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4921#L563-30 assume 1 == ~t7_pc~0; 4192#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4193#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4211#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4537#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4538#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4908#L582-30 assume !(1 == ~t8_pc~0); 4289#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 4290#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4525#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4938#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5011#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4096#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4097#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4234#L969-3 assume !(1 == ~T2_E~0); 4225#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4226#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4637#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4638#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4271#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4272#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4781#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4143#L1009-3 assume !(1 == ~E_1~0); 4144#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4618#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4619#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4600#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4567#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4568#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4839#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4261#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4262#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4391#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4728#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 4295#L1334 assume !(0 == start_simulation_~tmp~3#1); 4297#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4315#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4026#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4027#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 4621#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4965#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4800#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 4801#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 4238#L1315-2 [2021-12-06 18:37:50,743 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:37:50,743 INFO L85 PathProgramCache]: Analyzing trace with hash -1134101512, now seen corresponding path program 1 times [2021-12-06 18:37:50,743 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:37:50,744 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [622944623] [2021-12-06 18:37:50,744 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:37:50,744 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:37:50,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:37:50,789 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:37:50,789 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:37:50,789 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [622944623] [2021-12-06 18:37:50,790 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [622944623] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:37:50,790 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:37:50,790 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:37:50,790 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [30138046] [2021-12-06 18:37:50,790 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:37:50,791 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 18:37:50,791 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:37:50,792 INFO L85 PathProgramCache]: Analyzing trace with hash 1452394673, now seen corresponding path program 1 times [2021-12-06 18:37:50,792 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:37:50,792 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [300104048] [2021-12-06 18:37:50,792 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:37:50,792 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:37:50,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:37:50,855 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:37:50,855 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:37:50,856 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [300104048] [2021-12-06 18:37:50,856 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [300104048] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:37:50,856 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:37:50,856 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:37:50,856 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [994650672] [2021-12-06 18:37:50,857 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:37:50,857 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 18:37:50,857 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:37:50,858 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 18:37:50,858 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 18:37:50,858 INFO L87 Difference]: Start difference. First operand 998 states and 1489 transitions. cyclomatic complexity: 492 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:37:50,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:37:50,885 INFO L93 Difference]: Finished difference Result 998 states and 1488 transitions. [2021-12-06 18:37:50,885 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 18:37:50,886 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 998 states and 1488 transitions. [2021-12-06 18:37:50,895 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2021-12-06 18:37:50,904 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 998 states to 998 states and 1488 transitions. [2021-12-06 18:37:50,904 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 998 [2021-12-06 18:37:50,905 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 998 [2021-12-06 18:37:50,905 INFO L73 IsDeterministic]: Start isDeterministic. Operand 998 states and 1488 transitions. [2021-12-06 18:37:50,907 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:37:50,907 INFO L681 BuchiCegarLoop]: Abstraction has 998 states and 1488 transitions. [2021-12-06 18:37:50,909 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 998 states and 1488 transitions. [2021-12-06 18:37:50,925 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 998 to 998. [2021-12-06 18:37:50,928 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 998 states, 998 states have (on average 1.4909819639278556) internal successors, (1488), 997 states have internal predecessors, (1488), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:37:50,932 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 998 states to 998 states and 1488 transitions. [2021-12-06 18:37:50,933 INFO L704 BuchiCegarLoop]: Abstraction has 998 states and 1488 transitions. [2021-12-06 18:37:50,933 INFO L587 BuchiCegarLoop]: Abstraction has 998 states and 1488 transitions. [2021-12-06 18:37:50,933 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-06 18:37:50,933 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 998 states and 1488 transitions. [2021-12-06 18:37:50,939 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2021-12-06 18:37:50,939 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:37:50,939 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:37:50,941 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:37:50,942 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:37:50,942 INFO L791 eck$LassoCheckResult]: Stem: 6795#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 6796#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 6722#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6723#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6575#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 6576#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6161#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6162#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6243#L624-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6954#L629-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6131#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6132#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6539#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6564#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6247#L866 assume !(0 == ~M_E~0); 6248#L866-2 assume !(0 == ~T1_E~0); 6750#L871-1 assume !(0 == ~T2_E~0); 6751#L876-1 assume !(0 == ~T3_E~0); 7001#L881-1 assume !(0 == ~T4_E~0); 6760#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6530#L891-1 assume !(0 == ~T6_E~0); 6531#L896-1 assume !(0 == ~T7_E~0); 6753#L901-1 assume !(0 == ~T8_E~0); 6771#L906-1 assume !(0 == ~E_M~0); 6772#L911-1 assume !(0 == ~E_1~0); 6573#L916-1 assume !(0 == ~E_2~0); 6574#L921-1 assume !(0 == ~E_3~0); 6867#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 6966#L931-1 assume !(0 == ~E_5~0); 7006#L936-1 assume !(0 == ~E_6~0); 7013#L941-1 assume !(0 == ~E_7~0); 6579#L946-1 assume !(0 == ~E_8~0); 6580#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6985#L430 assume !(1 == ~m_pc~0); 6438#L430-2 is_master_triggered_~__retres1~0#1 := 0; 6066#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6067#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6680#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6690#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6851#L449 assume 1 == ~t1_pc~0; 6852#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6251#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6025#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6026#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 6786#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6635#L468 assume !(1 == ~t2_pc~0); 6050#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6049#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6538#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6445#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 6068#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6069#L487 assume 1 == ~t3_pc~0; 6998#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6165#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6166#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6840#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 6504#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6505#L506 assume !(1 == ~t4_pc~0); 6631#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6676#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6976#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6977#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 6626#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6456#L525 assume 1 == ~t5_pc~0; 6391#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6110#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6583#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6584#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 6307#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6308#L544 assume !(1 == ~t6_pc~0); 6457#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6458#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6802#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6092#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 6093#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6942#L563 assume 1 == ~t7_pc~0; 6820#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6120#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6121#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6532#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 6252#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6253#L582 assume 1 == ~t8_pc~0; 6176#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6177#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6999#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6493#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 6395#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6396#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 6854#L964-2 assume !(1 == ~T1_E~0); 6309#L969-1 assume !(1 == ~T2_E~0); 6310#L974-1 assume !(1 == ~T3_E~0); 6879#L979-1 assume !(1 == ~T4_E~0); 6880#L984-1 assume !(1 == ~T5_E~0); 6463#L989-1 assume !(1 == ~T6_E~0); 6464#L994-1 assume !(1 == ~T7_E~0); 6349#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6350#L1004-1 assume !(1 == ~E_M~0); 6094#L1009-1 assume !(1 == ~E_1~0); 6095#L1014-1 assume !(1 == ~E_2~0); 6338#L1019-1 assume !(1 == ~E_3~0); 6843#L1024-1 assume !(1 == ~E_4~0); 6271#L1029-1 assume !(1 == ~E_5~0); 6272#L1034-1 assume !(1 == ~E_6~0); 6366#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 6980#L1044-1 assume !(1 == ~E_8~0); 6548#L1049-1 assume { :end_inline_reset_delta_events } true; 6241#L1315-2 [2021-12-06 18:37:50,943 INFO L793 eck$LassoCheckResult]: Loop: 6241#L1315-2 assume !false; 6242#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6028#L841 assume !false; 6367#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6302#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6303#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6143#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 6063#L724 assume !(0 != eval_~tmp~0#1); 6065#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6893#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6074#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6075#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6370#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6371#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6384#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6385#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6608#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6609#L896-3 assume !(0 == ~T7_E~0); 6476#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6477#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6610#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6813#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6416#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6417#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6797#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6483#L936-3 assume !(0 == ~E_6~0); 6484#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6625#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6372#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6373#L430-30 assume 1 == ~m_pc~0; 6397#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6398#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6181#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6182#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6831#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6835#L449-30 assume 1 == ~t1_pc~0; 6400#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6090#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6091#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6462#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6174#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6175#L468-30 assume 1 == ~t2_pc~0; 6266#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6267#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6876#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6599#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6600#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6450#L487-30 assume !(1 == ~t3_pc~0); 6245#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 6246#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6577#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6578#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6850#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6524#L506-30 assume !(1 == ~t4_pc~0); 6525#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 6551#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6552#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6569#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 6451#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6452#L525-30 assume 1 == ~t5_pc~0; 6937#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6938#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6156#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6157#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6455#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6225#L544-30 assume 1 == ~t6_pc~0; 6033#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6034#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7007#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6947#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6948#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6924#L563-30 assume 1 == ~t7_pc~0; 6195#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6196#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6214#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6540#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6541#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6911#L582-30 assume !(1 == ~t8_pc~0); 6292#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 6293#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6528#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6941#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7014#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6099#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6100#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6237#L969-3 assume !(1 == ~T2_E~0); 6228#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6229#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6640#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6641#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6274#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6275#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6784#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6146#L1009-3 assume !(1 == ~E_1~0); 6147#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6621#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6622#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6603#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6570#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6571#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6842#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6264#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6265#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6394#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6731#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 6298#L1334 assume !(0 == start_simulation_~tmp~3#1); 6300#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6318#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6029#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6030#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 6624#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6968#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6803#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 6804#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 6241#L1315-2 [2021-12-06 18:37:50,943 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:37:50,943 INFO L85 PathProgramCache]: Analyzing trace with hash 2129824886, now seen corresponding path program 1 times [2021-12-06 18:37:50,944 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:37:50,944 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1775479719] [2021-12-06 18:37:50,944 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:37:50,944 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:37:50,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:37:50,979 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:37:50,980 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:37:50,980 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1775479719] [2021-12-06 18:37:50,980 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1775479719] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:37:50,981 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:37:50,981 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:37:50,981 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [818637389] [2021-12-06 18:37:50,981 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:37:50,981 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 18:37:50,982 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:37:50,982 INFO L85 PathProgramCache]: Analyzing trace with hash -15808656, now seen corresponding path program 1 times [2021-12-06 18:37:50,982 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:37:50,983 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1951148656] [2021-12-06 18:37:50,983 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:37:50,983 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:37:51,000 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:37:51,066 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:37:51,066 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:37:51,066 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1951148656] [2021-12-06 18:37:51,067 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1951148656] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:37:51,067 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:37:51,067 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:37:51,067 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [50428613] [2021-12-06 18:37:51,067 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:37:51,068 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 18:37:51,068 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:37:51,068 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 18:37:51,069 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 18:37:51,069 INFO L87 Difference]: Start difference. First operand 998 states and 1488 transitions. cyclomatic complexity: 491 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:37:51,095 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:37:51,095 INFO L93 Difference]: Finished difference Result 998 states and 1487 transitions. [2021-12-06 18:37:51,095 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 18:37:51,096 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 998 states and 1487 transitions. [2021-12-06 18:37:51,104 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2021-12-06 18:37:51,112 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 998 states to 998 states and 1487 transitions. [2021-12-06 18:37:51,113 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 998 [2021-12-06 18:37:51,114 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 998 [2021-12-06 18:37:51,114 INFO L73 IsDeterministic]: Start isDeterministic. Operand 998 states and 1487 transitions. [2021-12-06 18:37:51,116 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:37:51,116 INFO L681 BuchiCegarLoop]: Abstraction has 998 states and 1487 transitions. [2021-12-06 18:37:51,118 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 998 states and 1487 transitions. [2021-12-06 18:37:51,135 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 998 to 998. [2021-12-06 18:37:51,137 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 998 states, 998 states have (on average 1.4899799599198398) internal successors, (1487), 997 states have internal predecessors, (1487), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:37:51,141 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 998 states to 998 states and 1487 transitions. [2021-12-06 18:37:51,142 INFO L704 BuchiCegarLoop]: Abstraction has 998 states and 1487 transitions. [2021-12-06 18:37:51,142 INFO L587 BuchiCegarLoop]: Abstraction has 998 states and 1487 transitions. [2021-12-06 18:37:51,142 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-06 18:37:51,142 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 998 states and 1487 transitions. [2021-12-06 18:37:51,148 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2021-12-06 18:37:51,148 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:37:51,149 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:37:51,151 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:37:51,151 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:37:51,151 INFO L791 eck$LassoCheckResult]: Stem: 8798#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 8799#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 8725#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8726#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8578#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 8579#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8164#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8165#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8246#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8957#L629-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8134#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8135#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8542#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8567#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8250#L866 assume !(0 == ~M_E~0); 8251#L866-2 assume !(0 == ~T1_E~0); 8753#L871-1 assume !(0 == ~T2_E~0); 8754#L876-1 assume !(0 == ~T3_E~0); 9004#L881-1 assume !(0 == ~T4_E~0); 8763#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8533#L891-1 assume !(0 == ~T6_E~0); 8534#L896-1 assume !(0 == ~T7_E~0); 8756#L901-1 assume !(0 == ~T8_E~0); 8774#L906-1 assume !(0 == ~E_M~0); 8775#L911-1 assume !(0 == ~E_1~0); 8576#L916-1 assume !(0 == ~E_2~0); 8577#L921-1 assume !(0 == ~E_3~0); 8870#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 8969#L931-1 assume !(0 == ~E_5~0); 9009#L936-1 assume !(0 == ~E_6~0); 9016#L941-1 assume !(0 == ~E_7~0); 8582#L946-1 assume !(0 == ~E_8~0); 8583#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8988#L430 assume !(1 == ~m_pc~0); 8441#L430-2 is_master_triggered_~__retres1~0#1 := 0; 8069#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8070#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8683#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8693#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8854#L449 assume 1 == ~t1_pc~0; 8855#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8254#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8028#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8029#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 8789#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8638#L468 assume !(1 == ~t2_pc~0); 8053#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8052#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8541#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8448#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 8071#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8072#L487 assume 1 == ~t3_pc~0; 9001#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8168#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8169#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8843#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 8507#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8508#L506 assume !(1 == ~t4_pc~0); 8634#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8679#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8979#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8980#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 8629#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8459#L525 assume 1 == ~t5_pc~0; 8394#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8113#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8586#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8587#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 8310#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8311#L544 assume !(1 == ~t6_pc~0); 8460#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 8461#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8805#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8095#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 8096#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8945#L563 assume 1 == ~t7_pc~0; 8823#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8123#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8124#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8535#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 8255#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8256#L582 assume 1 == ~t8_pc~0; 8179#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8180#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9002#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8496#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 8398#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8399#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 8857#L964-2 assume !(1 == ~T1_E~0); 8312#L969-1 assume !(1 == ~T2_E~0); 8313#L974-1 assume !(1 == ~T3_E~0); 8882#L979-1 assume !(1 == ~T4_E~0); 8883#L984-1 assume !(1 == ~T5_E~0); 8466#L989-1 assume !(1 == ~T6_E~0); 8467#L994-1 assume !(1 == ~T7_E~0); 8352#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8353#L1004-1 assume !(1 == ~E_M~0); 8097#L1009-1 assume !(1 == ~E_1~0); 8098#L1014-1 assume !(1 == ~E_2~0); 8341#L1019-1 assume !(1 == ~E_3~0); 8846#L1024-1 assume !(1 == ~E_4~0); 8274#L1029-1 assume !(1 == ~E_5~0); 8275#L1034-1 assume !(1 == ~E_6~0); 8369#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 8983#L1044-1 assume !(1 == ~E_8~0); 8551#L1049-1 assume { :end_inline_reset_delta_events } true; 8244#L1315-2 [2021-12-06 18:37:51,152 INFO L793 eck$LassoCheckResult]: Loop: 8244#L1315-2 assume !false; 8245#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8031#L841 assume !false; 8370#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8305#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8306#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8146#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8066#L724 assume !(0 != eval_~tmp~0#1); 8068#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8896#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8077#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8078#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8373#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8374#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8387#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8388#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8611#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8612#L896-3 assume !(0 == ~T7_E~0); 8479#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8480#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8613#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8816#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8419#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8420#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8800#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8486#L936-3 assume !(0 == ~E_6~0); 8487#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8628#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8375#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8376#L430-30 assume 1 == ~m_pc~0; 8400#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8401#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8184#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8185#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8834#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8838#L449-30 assume 1 == ~t1_pc~0; 8403#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8093#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8094#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8465#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8177#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8178#L468-30 assume 1 == ~t2_pc~0; 8269#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8270#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8879#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8602#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8603#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8453#L487-30 assume 1 == ~t3_pc~0; 8434#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8249#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8580#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8581#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8853#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8527#L506-30 assume !(1 == ~t4_pc~0); 8528#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 8554#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8555#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8572#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 8454#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8455#L525-30 assume 1 == ~t5_pc~0; 8940#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8941#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8159#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8160#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8458#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8228#L544-30 assume 1 == ~t6_pc~0; 8036#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8037#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9010#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8950#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8951#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8927#L563-30 assume 1 == ~t7_pc~0; 8198#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8199#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8217#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8543#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8544#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8914#L582-30 assume !(1 == ~t8_pc~0); 8295#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 8296#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8531#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8944#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9017#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8102#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8103#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8240#L969-3 assume !(1 == ~T2_E~0); 8231#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8232#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8643#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8644#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8277#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8278#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8787#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8149#L1009-3 assume !(1 == ~E_1~0); 8150#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8624#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8625#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8606#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8573#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8574#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8845#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8267#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8268#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8397#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8734#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 8301#L1334 assume !(0 == start_simulation_~tmp~3#1); 8303#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8321#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8032#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8033#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 8627#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8971#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8806#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 8807#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 8244#L1315-2 [2021-12-06 18:37:51,152 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:37:51,152 INFO L85 PathProgramCache]: Analyzing trace with hash -258739144, now seen corresponding path program 1 times [2021-12-06 18:37:51,153 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:37:51,153 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2021141409] [2021-12-06 18:37:51,153 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:37:51,153 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:37:51,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:37:51,187 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:37:51,187 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:37:51,187 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2021141409] [2021-12-06 18:37:51,187 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2021141409] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:37:51,188 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:37:51,188 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:37:51,188 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1109094944] [2021-12-06 18:37:51,188 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:37:51,188 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 18:37:51,189 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:37:51,189 INFO L85 PathProgramCache]: Analyzing trace with hash 2141664367, now seen corresponding path program 1 times [2021-12-06 18:37:51,189 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:37:51,189 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [461160906] [2021-12-06 18:37:51,190 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:37:51,190 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:37:51,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:37:51,239 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:37:51,239 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:37:51,239 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [461160906] [2021-12-06 18:37:51,239 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [461160906] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:37:51,240 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:37:51,240 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:37:51,240 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2113838030] [2021-12-06 18:37:51,240 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:37:51,240 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 18:37:51,241 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:37:51,241 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 18:37:51,241 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 18:37:51,242 INFO L87 Difference]: Start difference. First operand 998 states and 1487 transitions. cyclomatic complexity: 490 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:37:51,267 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:37:51,267 INFO L93 Difference]: Finished difference Result 998 states and 1486 transitions. [2021-12-06 18:37:51,268 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 18:37:51,269 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 998 states and 1486 transitions. [2021-12-06 18:37:51,277 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2021-12-06 18:37:51,285 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 998 states to 998 states and 1486 transitions. [2021-12-06 18:37:51,285 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 998 [2021-12-06 18:37:51,286 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 998 [2021-12-06 18:37:51,286 INFO L73 IsDeterministic]: Start isDeterministic. Operand 998 states and 1486 transitions. [2021-12-06 18:37:51,288 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:37:51,289 INFO L681 BuchiCegarLoop]: Abstraction has 998 states and 1486 transitions. [2021-12-06 18:37:51,291 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 998 states and 1486 transitions. [2021-12-06 18:37:51,307 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 998 to 998. [2021-12-06 18:37:51,309 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 998 states, 998 states have (on average 1.4889779559118237) internal successors, (1486), 997 states have internal predecessors, (1486), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:37:51,314 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 998 states to 998 states and 1486 transitions. [2021-12-06 18:37:51,314 INFO L704 BuchiCegarLoop]: Abstraction has 998 states and 1486 transitions. [2021-12-06 18:37:51,314 INFO L587 BuchiCegarLoop]: Abstraction has 998 states and 1486 transitions. [2021-12-06 18:37:51,314 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-06 18:37:51,314 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 998 states and 1486 transitions. [2021-12-06 18:37:51,321 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2021-12-06 18:37:51,321 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:37:51,321 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:37:51,323 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:37:51,323 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:37:51,324 INFO L791 eck$LassoCheckResult]: Stem: 10801#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 10802#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 10728#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10729#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10581#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 10582#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10167#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10168#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10249#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10960#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10137#L634-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10138#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10545#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10570#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10253#L866 assume !(0 == ~M_E~0); 10254#L866-2 assume !(0 == ~T1_E~0); 10756#L871-1 assume !(0 == ~T2_E~0); 10757#L876-1 assume !(0 == ~T3_E~0); 11007#L881-1 assume !(0 == ~T4_E~0); 10766#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10536#L891-1 assume !(0 == ~T6_E~0); 10537#L896-1 assume !(0 == ~T7_E~0); 10759#L901-1 assume !(0 == ~T8_E~0); 10777#L906-1 assume !(0 == ~E_M~0); 10778#L911-1 assume !(0 == ~E_1~0); 10579#L916-1 assume !(0 == ~E_2~0); 10580#L921-1 assume !(0 == ~E_3~0); 10873#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 10972#L931-1 assume !(0 == ~E_5~0); 11012#L936-1 assume !(0 == ~E_6~0); 11019#L941-1 assume !(0 == ~E_7~0); 10585#L946-1 assume !(0 == ~E_8~0); 10586#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10991#L430 assume !(1 == ~m_pc~0); 10444#L430-2 is_master_triggered_~__retres1~0#1 := 0; 10072#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10073#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10686#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10696#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10857#L449 assume 1 == ~t1_pc~0; 10858#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10257#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10031#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10032#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 10792#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10641#L468 assume !(1 == ~t2_pc~0); 10056#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10055#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10544#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10451#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 10074#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10075#L487 assume 1 == ~t3_pc~0; 11004#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10171#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10172#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10846#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 10510#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10511#L506 assume !(1 == ~t4_pc~0); 10637#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10682#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10982#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10983#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 10632#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10462#L525 assume 1 == ~t5_pc~0; 10397#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10116#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10589#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10590#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 10313#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10314#L544 assume !(1 == ~t6_pc~0); 10463#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10464#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10808#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10098#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 10099#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10948#L563 assume 1 == ~t7_pc~0; 10826#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10126#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10127#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10538#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 10258#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10259#L582 assume 1 == ~t8_pc~0; 10182#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10183#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11005#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10499#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 10401#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10402#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 10860#L964-2 assume !(1 == ~T1_E~0); 10315#L969-1 assume !(1 == ~T2_E~0); 10316#L974-1 assume !(1 == ~T3_E~0); 10885#L979-1 assume !(1 == ~T4_E~0); 10886#L984-1 assume !(1 == ~T5_E~0); 10469#L989-1 assume !(1 == ~T6_E~0); 10470#L994-1 assume !(1 == ~T7_E~0); 10355#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10356#L1004-1 assume !(1 == ~E_M~0); 10100#L1009-1 assume !(1 == ~E_1~0); 10101#L1014-1 assume !(1 == ~E_2~0); 10344#L1019-1 assume !(1 == ~E_3~0); 10849#L1024-1 assume !(1 == ~E_4~0); 10277#L1029-1 assume !(1 == ~E_5~0); 10278#L1034-1 assume !(1 == ~E_6~0); 10372#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 10986#L1044-1 assume !(1 == ~E_8~0); 10554#L1049-1 assume { :end_inline_reset_delta_events } true; 10247#L1315-2 [2021-12-06 18:37:51,324 INFO L793 eck$LassoCheckResult]: Loop: 10247#L1315-2 assume !false; 10248#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10034#L841 assume !false; 10373#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10308#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10309#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10149#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 10069#L724 assume !(0 != eval_~tmp~0#1); 10071#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10899#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10080#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10081#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10376#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10377#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10390#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10391#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10614#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10615#L896-3 assume !(0 == ~T7_E~0); 10482#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10483#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10616#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10819#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10422#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10423#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10803#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10489#L936-3 assume !(0 == ~E_6~0); 10490#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10631#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10378#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10379#L430-30 assume 1 == ~m_pc~0; 10403#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10404#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10187#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10188#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10837#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10841#L449-30 assume 1 == ~t1_pc~0; 10406#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10096#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10097#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10468#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10180#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10181#L468-30 assume 1 == ~t2_pc~0; 10272#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10273#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10882#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10605#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10606#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10456#L487-30 assume 1 == ~t3_pc~0; 10437#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10252#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10583#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10584#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10856#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10530#L506-30 assume !(1 == ~t4_pc~0); 10531#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 10557#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10558#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10575#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 10457#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10458#L525-30 assume !(1 == ~t5_pc~0); 10945#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 10944#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10162#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10163#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10461#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10231#L544-30 assume 1 == ~t6_pc~0; 10039#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10040#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11013#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10953#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10954#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10930#L563-30 assume 1 == ~t7_pc~0; 10201#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10202#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10220#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10546#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10547#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10917#L582-30 assume !(1 == ~t8_pc~0); 10298#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 10299#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10534#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10947#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11020#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10105#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10106#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10243#L969-3 assume !(1 == ~T2_E~0); 10234#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10235#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10646#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10647#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10280#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10281#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10790#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10152#L1009-3 assume !(1 == ~E_1~0); 10153#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10627#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10628#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10609#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10576#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10577#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10848#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10270#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10271#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10400#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10737#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 10304#L1334 assume !(0 == start_simulation_~tmp~3#1); 10306#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10324#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10035#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10036#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 10630#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10974#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10809#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 10810#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 10247#L1315-2 [2021-12-06 18:37:51,325 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:37:51,325 INFO L85 PathProgramCache]: Analyzing trace with hash -1859810250, now seen corresponding path program 1 times [2021-12-06 18:37:51,325 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:37:51,325 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1728984806] [2021-12-06 18:37:51,325 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:37:51,326 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:37:51,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:37:51,356 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:37:51,356 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:37:51,356 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1728984806] [2021-12-06 18:37:51,356 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1728984806] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:37:51,357 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:37:51,357 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:37:51,357 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1954929625] [2021-12-06 18:37:51,357 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:37:51,358 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 18:37:51,358 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:37:51,358 INFO L85 PathProgramCache]: Analyzing trace with hash 1033535728, now seen corresponding path program 1 times [2021-12-06 18:37:51,358 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:37:51,359 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1486238117] [2021-12-06 18:37:51,359 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:37:51,359 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:37:51,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:37:51,400 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:37:51,401 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:37:51,401 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1486238117] [2021-12-06 18:37:51,401 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1486238117] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:37:51,401 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:37:51,401 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:37:51,402 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1251192118] [2021-12-06 18:37:51,402 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:37:51,402 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 18:37:51,402 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:37:51,403 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 18:37:51,403 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 18:37:51,403 INFO L87 Difference]: Start difference. First operand 998 states and 1486 transitions. cyclomatic complexity: 489 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:37:51,428 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:37:51,429 INFO L93 Difference]: Finished difference Result 998 states and 1485 transitions. [2021-12-06 18:37:51,429 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 18:37:51,430 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 998 states and 1485 transitions. [2021-12-06 18:37:51,438 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2021-12-06 18:37:51,446 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 998 states to 998 states and 1485 transitions. [2021-12-06 18:37:51,446 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 998 [2021-12-06 18:37:51,447 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 998 [2021-12-06 18:37:51,448 INFO L73 IsDeterministic]: Start isDeterministic. Operand 998 states and 1485 transitions. [2021-12-06 18:37:51,450 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:37:51,450 INFO L681 BuchiCegarLoop]: Abstraction has 998 states and 1485 transitions. [2021-12-06 18:37:51,452 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 998 states and 1485 transitions. [2021-12-06 18:37:51,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 998 to 998. [2021-12-06 18:37:51,470 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 998 states, 998 states have (on average 1.4879759519038076) internal successors, (1485), 997 states have internal predecessors, (1485), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:37:51,475 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 998 states to 998 states and 1485 transitions. [2021-12-06 18:37:51,475 INFO L704 BuchiCegarLoop]: Abstraction has 998 states and 1485 transitions. [2021-12-06 18:37:51,475 INFO L587 BuchiCegarLoop]: Abstraction has 998 states and 1485 transitions. [2021-12-06 18:37:51,475 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-06 18:37:51,475 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 998 states and 1485 transitions. [2021-12-06 18:37:51,481 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2021-12-06 18:37:51,481 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:37:51,481 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:37:51,484 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:37:51,484 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:37:51,484 INFO L791 eck$LassoCheckResult]: Stem: 12804#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 12805#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 12731#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12732#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12584#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 12585#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12170#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12171#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12252#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12963#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12140#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12141#L639-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12548#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12573#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12256#L866 assume !(0 == ~M_E~0); 12257#L866-2 assume !(0 == ~T1_E~0); 12759#L871-1 assume !(0 == ~T2_E~0); 12760#L876-1 assume !(0 == ~T3_E~0); 13010#L881-1 assume !(0 == ~T4_E~0); 12769#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12539#L891-1 assume !(0 == ~T6_E~0); 12540#L896-1 assume !(0 == ~T7_E~0); 12762#L901-1 assume !(0 == ~T8_E~0); 12780#L906-1 assume !(0 == ~E_M~0); 12781#L911-1 assume !(0 == ~E_1~0); 12582#L916-1 assume !(0 == ~E_2~0); 12583#L921-1 assume !(0 == ~E_3~0); 12876#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 12975#L931-1 assume !(0 == ~E_5~0); 13015#L936-1 assume !(0 == ~E_6~0); 13022#L941-1 assume !(0 == ~E_7~0); 12588#L946-1 assume !(0 == ~E_8~0); 12589#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12994#L430 assume !(1 == ~m_pc~0); 12447#L430-2 is_master_triggered_~__retres1~0#1 := 0; 12075#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12076#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12689#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12699#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12860#L449 assume 1 == ~t1_pc~0; 12861#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12260#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12034#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12035#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 12795#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12644#L468 assume !(1 == ~t2_pc~0); 12059#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12058#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12547#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12454#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 12077#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12078#L487 assume 1 == ~t3_pc~0; 13007#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12174#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12175#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12849#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 12513#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12514#L506 assume !(1 == ~t4_pc~0); 12640#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12685#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12985#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12986#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 12635#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12465#L525 assume 1 == ~t5_pc~0; 12400#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12119#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12592#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12593#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 12316#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12317#L544 assume !(1 == ~t6_pc~0); 12466#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12467#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12811#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12101#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 12102#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12951#L563 assume 1 == ~t7_pc~0; 12829#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12129#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12130#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12541#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 12261#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12262#L582 assume 1 == ~t8_pc~0; 12185#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12186#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13008#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12502#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 12404#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12405#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 12863#L964-2 assume !(1 == ~T1_E~0); 12318#L969-1 assume !(1 == ~T2_E~0); 12319#L974-1 assume !(1 == ~T3_E~0); 12888#L979-1 assume !(1 == ~T4_E~0); 12889#L984-1 assume !(1 == ~T5_E~0); 12472#L989-1 assume !(1 == ~T6_E~0); 12473#L994-1 assume !(1 == ~T7_E~0); 12358#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12359#L1004-1 assume !(1 == ~E_M~0); 12103#L1009-1 assume !(1 == ~E_1~0); 12104#L1014-1 assume !(1 == ~E_2~0); 12347#L1019-1 assume !(1 == ~E_3~0); 12852#L1024-1 assume !(1 == ~E_4~0); 12280#L1029-1 assume !(1 == ~E_5~0); 12281#L1034-1 assume !(1 == ~E_6~0); 12375#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 12989#L1044-1 assume !(1 == ~E_8~0); 12557#L1049-1 assume { :end_inline_reset_delta_events } true; 12250#L1315-2 [2021-12-06 18:37:51,518 INFO L793 eck$LassoCheckResult]: Loop: 12250#L1315-2 assume !false; 12251#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12037#L841 assume !false; 12376#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12311#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12312#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12152#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12072#L724 assume !(0 != eval_~tmp~0#1); 12074#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12902#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12083#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12084#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12379#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12380#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12393#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12394#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12617#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12618#L896-3 assume !(0 == ~T7_E~0); 12485#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12486#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12619#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12822#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12425#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12426#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12806#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12492#L936-3 assume !(0 == ~E_6~0); 12493#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12634#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12381#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12382#L430-30 assume 1 == ~m_pc~0; 12406#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12407#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12190#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12191#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12840#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12844#L449-30 assume 1 == ~t1_pc~0; 12409#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12099#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12100#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12471#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12183#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12184#L468-30 assume 1 == ~t2_pc~0; 12275#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12276#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12885#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12608#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12609#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12459#L487-30 assume 1 == ~t3_pc~0; 12440#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12255#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12586#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12587#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12859#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12533#L506-30 assume !(1 == ~t4_pc~0); 12534#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 12560#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12561#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12578#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 12460#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12461#L525-30 assume 1 == ~t5_pc~0; 12946#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12947#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12165#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12166#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12464#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12234#L544-30 assume 1 == ~t6_pc~0; 12042#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12043#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13016#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12956#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12957#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12933#L563-30 assume 1 == ~t7_pc~0; 12204#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12205#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12223#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12549#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12550#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12920#L582-30 assume 1 == ~t8_pc~0; 12882#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12302#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12537#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12950#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13023#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12108#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12109#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12246#L969-3 assume !(1 == ~T2_E~0); 12237#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12238#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12649#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12650#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12283#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12284#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12793#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12155#L1009-3 assume !(1 == ~E_1~0); 12156#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12630#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12631#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12612#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12579#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12580#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12851#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12273#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12274#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12403#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12740#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 12307#L1334 assume !(0 == start_simulation_~tmp~3#1); 12309#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12327#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12038#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12039#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 12633#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12977#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12812#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 12813#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 12250#L1315-2 [2021-12-06 18:37:51,519 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:37:51,519 INFO L85 PathProgramCache]: Analyzing trace with hash -803079048, now seen corresponding path program 1 times [2021-12-06 18:37:51,519 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:37:51,519 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [165212791] [2021-12-06 18:37:51,520 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:37:51,520 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:37:51,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:37:51,547 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:37:51,547 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:37:51,548 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [165212791] [2021-12-06 18:37:51,548 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [165212791] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:37:51,548 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:37:51,548 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:37:51,548 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [664649456] [2021-12-06 18:37:51,549 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:37:51,549 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 18:37:51,549 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:37:51,550 INFO L85 PathProgramCache]: Analyzing trace with hash 1016404398, now seen corresponding path program 2 times [2021-12-06 18:37:51,550 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:37:51,550 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [308626832] [2021-12-06 18:37:51,550 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:37:51,550 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:37:51,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:37:51,591 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:37:51,591 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:37:51,592 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [308626832] [2021-12-06 18:37:51,592 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [308626832] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:37:51,592 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:37:51,592 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:37:51,592 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [234893749] [2021-12-06 18:37:51,593 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:37:51,593 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 18:37:51,593 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:37:51,594 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 18:37:51,594 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 18:37:51,594 INFO L87 Difference]: Start difference. First operand 998 states and 1485 transitions. cyclomatic complexity: 488 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:37:51,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:37:51,617 INFO L93 Difference]: Finished difference Result 998 states and 1484 transitions. [2021-12-06 18:37:51,617 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 18:37:51,619 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 998 states and 1484 transitions. [2021-12-06 18:37:51,626 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2021-12-06 18:37:51,633 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 998 states to 998 states and 1484 transitions. [2021-12-06 18:37:51,633 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 998 [2021-12-06 18:37:51,635 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 998 [2021-12-06 18:37:51,635 INFO L73 IsDeterministic]: Start isDeterministic. Operand 998 states and 1484 transitions. [2021-12-06 18:37:51,636 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:37:51,636 INFO L681 BuchiCegarLoop]: Abstraction has 998 states and 1484 transitions. [2021-12-06 18:37:51,638 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 998 states and 1484 transitions. [2021-12-06 18:37:51,652 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 998 to 998. [2021-12-06 18:37:51,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 998 states, 998 states have (on average 1.4869739478957915) internal successors, (1484), 997 states have internal predecessors, (1484), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:37:51,658 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 998 states to 998 states and 1484 transitions. [2021-12-06 18:37:51,658 INFO L704 BuchiCegarLoop]: Abstraction has 998 states and 1484 transitions. [2021-12-06 18:37:51,658 INFO L587 BuchiCegarLoop]: Abstraction has 998 states and 1484 transitions. [2021-12-06 18:37:51,658 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-06 18:37:51,658 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 998 states and 1484 transitions. [2021-12-06 18:37:51,663 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2021-12-06 18:37:51,663 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:37:51,663 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:37:51,665 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:37:51,665 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:37:51,665 INFO L791 eck$LassoCheckResult]: Stem: 14807#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 14808#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 14734#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14735#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14587#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 14588#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14173#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14174#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14255#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14966#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14143#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14144#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 14551#L644-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14576#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14259#L866 assume !(0 == ~M_E~0); 14260#L866-2 assume !(0 == ~T1_E~0); 14762#L871-1 assume !(0 == ~T2_E~0); 14763#L876-1 assume !(0 == ~T3_E~0); 15013#L881-1 assume !(0 == ~T4_E~0); 14772#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14542#L891-1 assume !(0 == ~T6_E~0); 14543#L896-1 assume !(0 == ~T7_E~0); 14765#L901-1 assume !(0 == ~T8_E~0); 14783#L906-1 assume !(0 == ~E_M~0); 14784#L911-1 assume !(0 == ~E_1~0); 14585#L916-1 assume !(0 == ~E_2~0); 14586#L921-1 assume !(0 == ~E_3~0); 14879#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 14978#L931-1 assume !(0 == ~E_5~0); 15018#L936-1 assume !(0 == ~E_6~0); 15025#L941-1 assume !(0 == ~E_7~0); 14591#L946-1 assume !(0 == ~E_8~0); 14592#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14997#L430 assume !(1 == ~m_pc~0); 14450#L430-2 is_master_triggered_~__retres1~0#1 := 0; 14078#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14079#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14692#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14702#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14863#L449 assume 1 == ~t1_pc~0; 14864#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14263#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14037#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14038#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 14798#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14647#L468 assume !(1 == ~t2_pc~0); 14062#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14061#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14550#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14457#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 14080#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14081#L487 assume 1 == ~t3_pc~0; 15010#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14177#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14178#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14852#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 14516#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14517#L506 assume !(1 == ~t4_pc~0); 14643#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14688#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14988#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14989#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 14638#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14468#L525 assume 1 == ~t5_pc~0; 14403#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14122#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14595#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14596#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 14319#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14320#L544 assume !(1 == ~t6_pc~0); 14469#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14470#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14814#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14104#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 14105#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14954#L563 assume 1 == ~t7_pc~0; 14832#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14132#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14133#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14544#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 14264#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14265#L582 assume 1 == ~t8_pc~0; 14188#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14189#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15011#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14505#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 14407#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14408#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 14866#L964-2 assume !(1 == ~T1_E~0); 14321#L969-1 assume !(1 == ~T2_E~0); 14322#L974-1 assume !(1 == ~T3_E~0); 14891#L979-1 assume !(1 == ~T4_E~0); 14892#L984-1 assume !(1 == ~T5_E~0); 14475#L989-1 assume !(1 == ~T6_E~0); 14476#L994-1 assume !(1 == ~T7_E~0); 14361#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14362#L1004-1 assume !(1 == ~E_M~0); 14106#L1009-1 assume !(1 == ~E_1~0); 14107#L1014-1 assume !(1 == ~E_2~0); 14350#L1019-1 assume !(1 == ~E_3~0); 14855#L1024-1 assume !(1 == ~E_4~0); 14283#L1029-1 assume !(1 == ~E_5~0); 14284#L1034-1 assume !(1 == ~E_6~0); 14378#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 14992#L1044-1 assume !(1 == ~E_8~0); 14560#L1049-1 assume { :end_inline_reset_delta_events } true; 14253#L1315-2 [2021-12-06 18:37:51,666 INFO L793 eck$LassoCheckResult]: Loop: 14253#L1315-2 assume !false; 14254#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14040#L841 assume !false; 14379#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14314#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14315#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14155#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14075#L724 assume !(0 != eval_~tmp~0#1); 14077#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14905#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14086#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14087#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14382#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14383#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14396#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14397#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14620#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14621#L896-3 assume !(0 == ~T7_E~0); 14488#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14489#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14622#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14825#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14428#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14429#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14809#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14495#L936-3 assume !(0 == ~E_6~0); 14496#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14637#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14384#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14385#L430-30 assume 1 == ~m_pc~0; 14409#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14410#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14193#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14194#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14843#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14847#L449-30 assume 1 == ~t1_pc~0; 14412#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14102#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14103#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14474#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14186#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14187#L468-30 assume 1 == ~t2_pc~0; 14278#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14279#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14888#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14611#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14612#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14462#L487-30 assume !(1 == ~t3_pc~0); 14257#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 14258#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14589#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14590#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14862#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14536#L506-30 assume !(1 == ~t4_pc~0); 14537#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 14563#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14564#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14581#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 14463#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14464#L525-30 assume 1 == ~t5_pc~0; 14949#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14950#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14168#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14169#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14467#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14237#L544-30 assume 1 == ~t6_pc~0; 14045#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14046#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15019#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14959#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14960#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14936#L563-30 assume !(1 == ~t7_pc~0); 14209#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 14208#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14226#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14552#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14553#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14923#L582-30 assume !(1 == ~t8_pc~0); 14304#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 14305#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14540#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14953#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15026#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14111#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14112#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14249#L969-3 assume !(1 == ~T2_E~0); 14240#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14241#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14652#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14653#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14286#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14287#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14796#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14158#L1009-3 assume !(1 == ~E_1~0); 14159#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14633#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14634#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14615#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14582#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14583#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14854#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14276#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14277#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14406#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14743#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 14310#L1334 assume !(0 == start_simulation_~tmp~3#1); 14312#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14330#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14041#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14042#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 14636#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14980#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14815#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 14816#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 14253#L1315-2 [2021-12-06 18:37:51,666 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:37:51,666 INFO L85 PathProgramCache]: Analyzing trace with hash 2140503030, now seen corresponding path program 1 times [2021-12-06 18:37:51,666 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:37:51,666 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [675521841] [2021-12-06 18:37:51,667 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:37:51,667 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:37:51,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:37:51,694 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:37:51,694 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:37:51,694 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [675521841] [2021-12-06 18:37:51,694 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [675521841] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:37:51,695 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:37:51,695 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:37:51,695 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1143935935] [2021-12-06 18:37:51,695 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:37:51,696 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 18:37:51,696 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:37:51,696 INFO L85 PathProgramCache]: Analyzing trace with hash 1882721649, now seen corresponding path program 1 times [2021-12-06 18:37:51,697 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:37:51,697 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [446093259] [2021-12-06 18:37:51,697 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:37:51,697 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:37:51,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:37:51,735 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:37:51,736 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:37:51,736 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [446093259] [2021-12-06 18:37:51,736 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [446093259] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:37:51,736 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:37:51,736 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:37:51,737 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1667648694] [2021-12-06 18:37:51,737 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:37:51,737 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 18:37:51,737 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:37:51,738 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 18:37:51,738 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 18:37:51,738 INFO L87 Difference]: Start difference. First operand 998 states and 1484 transitions. cyclomatic complexity: 487 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:37:51,760 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:37:51,761 INFO L93 Difference]: Finished difference Result 998 states and 1483 transitions. [2021-12-06 18:37:51,761 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 18:37:51,762 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 998 states and 1483 transitions. [2021-12-06 18:37:51,769 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2021-12-06 18:37:51,777 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 998 states to 998 states and 1483 transitions. [2021-12-06 18:37:51,777 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 998 [2021-12-06 18:37:51,779 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 998 [2021-12-06 18:37:51,779 INFO L73 IsDeterministic]: Start isDeterministic. Operand 998 states and 1483 transitions. [2021-12-06 18:37:51,781 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:37:51,781 INFO L681 BuchiCegarLoop]: Abstraction has 998 states and 1483 transitions. [2021-12-06 18:37:51,783 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 998 states and 1483 transitions. [2021-12-06 18:37:51,798 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 998 to 998. [2021-12-06 18:37:51,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 998 states, 998 states have (on average 1.4859719438877756) internal successors, (1483), 997 states have internal predecessors, (1483), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:37:51,804 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 998 states to 998 states and 1483 transitions. [2021-12-06 18:37:51,804 INFO L704 BuchiCegarLoop]: Abstraction has 998 states and 1483 transitions. [2021-12-06 18:37:51,804 INFO L587 BuchiCegarLoop]: Abstraction has 998 states and 1483 transitions. [2021-12-06 18:37:51,805 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-06 18:37:51,805 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 998 states and 1483 transitions. [2021-12-06 18:37:51,810 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 883 [2021-12-06 18:37:51,810 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:37:51,810 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:37:51,812 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:37:51,812 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:37:51,813 INFO L791 eck$LassoCheckResult]: Stem: 16810#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 16811#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 16737#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16738#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16590#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 16591#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16176#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16177#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16258#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16969#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16146#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16147#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16554#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 16579#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16262#L866 assume !(0 == ~M_E~0); 16263#L866-2 assume !(0 == ~T1_E~0); 16765#L871-1 assume !(0 == ~T2_E~0); 16766#L876-1 assume !(0 == ~T3_E~0); 17016#L881-1 assume !(0 == ~T4_E~0); 16775#L886-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16545#L891-1 assume !(0 == ~T6_E~0); 16546#L896-1 assume !(0 == ~T7_E~0); 16768#L901-1 assume !(0 == ~T8_E~0); 16786#L906-1 assume !(0 == ~E_M~0); 16787#L911-1 assume !(0 == ~E_1~0); 16588#L916-1 assume !(0 == ~E_2~0); 16589#L921-1 assume !(0 == ~E_3~0); 16882#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 16981#L931-1 assume !(0 == ~E_5~0); 17021#L936-1 assume !(0 == ~E_6~0); 17028#L941-1 assume !(0 == ~E_7~0); 16594#L946-1 assume !(0 == ~E_8~0); 16595#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17000#L430 assume !(1 == ~m_pc~0); 16453#L430-2 is_master_triggered_~__retres1~0#1 := 0; 16081#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16082#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16695#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16705#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16866#L449 assume 1 == ~t1_pc~0; 16867#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16266#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16040#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16041#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 16801#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16650#L468 assume !(1 == ~t2_pc~0); 16065#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16064#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16553#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16460#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 16083#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16084#L487 assume 1 == ~t3_pc~0; 17013#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16180#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16181#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16855#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 16519#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16520#L506 assume !(1 == ~t4_pc~0); 16646#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16691#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16991#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16992#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 16641#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16471#L525 assume 1 == ~t5_pc~0; 16406#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16125#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16598#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16599#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 16322#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16323#L544 assume !(1 == ~t6_pc~0); 16472#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 16473#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16817#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16107#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 16108#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16957#L563 assume 1 == ~t7_pc~0; 16835#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16135#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16136#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16547#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 16267#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16268#L582 assume 1 == ~t8_pc~0; 16191#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16192#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17014#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16508#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 16410#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16411#L964 assume 1 == ~M_E~0;~M_E~0 := 2; 16869#L964-2 assume !(1 == ~T1_E~0); 16324#L969-1 assume !(1 == ~T2_E~0); 16325#L974-1 assume !(1 == ~T3_E~0); 16894#L979-1 assume !(1 == ~T4_E~0); 16895#L984-1 assume !(1 == ~T5_E~0); 16478#L989-1 assume !(1 == ~T6_E~0); 16479#L994-1 assume !(1 == ~T7_E~0); 16364#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16365#L1004-1 assume !(1 == ~E_M~0); 16109#L1009-1 assume !(1 == ~E_1~0); 16110#L1014-1 assume !(1 == ~E_2~0); 16353#L1019-1 assume !(1 == ~E_3~0); 16858#L1024-1 assume !(1 == ~E_4~0); 16286#L1029-1 assume !(1 == ~E_5~0); 16287#L1034-1 assume !(1 == ~E_6~0); 16381#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 16995#L1044-1 assume !(1 == ~E_8~0); 16563#L1049-1 assume { :end_inline_reset_delta_events } true; 16256#L1315-2 [2021-12-06 18:37:51,813 INFO L793 eck$LassoCheckResult]: Loop: 16256#L1315-2 assume !false; 16257#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16043#L841 assume !false; 16382#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16317#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16318#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16158#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16078#L724 assume !(0 != eval_~tmp~0#1); 16080#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16908#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16089#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16090#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16385#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16386#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16399#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16400#L886-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16623#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16624#L896-3 assume !(0 == ~T7_E~0); 16491#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16492#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16625#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16828#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16431#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16432#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16812#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16498#L936-3 assume !(0 == ~E_6~0); 16499#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 16640#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16387#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16388#L430-30 assume 1 == ~m_pc~0; 16412#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 16413#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16196#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16197#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16846#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16850#L449-30 assume !(1 == ~t1_pc~0); 16416#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 16105#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16106#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16477#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16189#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16190#L468-30 assume 1 == ~t2_pc~0; 16281#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16282#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16891#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16614#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16615#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16465#L487-30 assume !(1 == ~t3_pc~0); 16260#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 16261#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16592#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16593#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16865#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16539#L506-30 assume !(1 == ~t4_pc~0); 16540#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 16566#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16567#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16584#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 16466#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16467#L525-30 assume 1 == ~t5_pc~0; 16952#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16953#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16171#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16172#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 16470#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16240#L544-30 assume 1 == ~t6_pc~0; 16048#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16049#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17022#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16962#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16963#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16939#L563-30 assume 1 == ~t7_pc~0; 16210#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16211#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16229#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16555#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16556#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16926#L582-30 assume !(1 == ~t8_pc~0); 16307#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 16308#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16543#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16956#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17029#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16114#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16115#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16252#L969-3 assume !(1 == ~T2_E~0); 16243#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16244#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16655#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16656#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16289#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16290#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16799#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16161#L1009-3 assume !(1 == ~E_1~0); 16162#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16636#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16637#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16618#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16585#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16586#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16857#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16279#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16280#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16409#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16746#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 16313#L1334 assume !(0 == start_simulation_~tmp~3#1); 16315#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16333#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16044#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16045#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 16639#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16983#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16818#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 16819#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 16256#L1315-2 [2021-12-06 18:37:51,814 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:37:51,814 INFO L85 PathProgramCache]: Analyzing trace with hash -535489352, now seen corresponding path program 1 times [2021-12-06 18:37:51,814 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:37:51,814 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1933440972] [2021-12-06 18:37:51,815 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:37:51,815 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:37:51,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:37:51,856 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:37:51,856 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:37:51,856 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1933440972] [2021-12-06 18:37:51,856 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1933440972] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:37:51,857 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:37:51,857 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:37:51,857 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1277192329] [2021-12-06 18:37:51,857 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:37:51,858 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 18:37:51,858 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:37:51,858 INFO L85 PathProgramCache]: Analyzing trace with hash -952835855, now seen corresponding path program 1 times [2021-12-06 18:37:51,858 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:37:51,859 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [958818600] [2021-12-06 18:37:51,859 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:37:51,859 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:37:51,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:37:51,899 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:37:51,900 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:37:51,900 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [958818600] [2021-12-06 18:37:51,900 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [958818600] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:37:51,900 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:37:51,900 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:37:51,900 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [690258224] [2021-12-06 18:37:51,900 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:37:51,901 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 18:37:51,901 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:37:51,901 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 18:37:51,901 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 18:37:51,902 INFO L87 Difference]: Start difference. First operand 998 states and 1483 transitions. cyclomatic complexity: 486 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:37:52,005 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:37:52,006 INFO L93 Difference]: Finished difference Result 1816 states and 2689 transitions. [2021-12-06 18:37:52,006 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 18:37:52,008 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1816 states and 2689 transitions. [2021-12-06 18:37:52,021 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1683 [2021-12-06 18:37:52,036 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1816 states to 1816 states and 2689 transitions. [2021-12-06 18:37:52,036 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1816 [2021-12-06 18:37:52,039 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1816 [2021-12-06 18:37:52,039 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1816 states and 2689 transitions. [2021-12-06 18:37:52,042 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:37:52,042 INFO L681 BuchiCegarLoop]: Abstraction has 1816 states and 2689 transitions. [2021-12-06 18:37:52,045 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1816 states and 2689 transitions. [2021-12-06 18:37:52,079 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1816 to 1816. [2021-12-06 18:37:52,084 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1816 states, 1816 states have (on average 1.480726872246696) internal successors, (2689), 1815 states have internal predecessors, (2689), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:37:52,090 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1816 states to 1816 states and 2689 transitions. [2021-12-06 18:37:52,091 INFO L704 BuchiCegarLoop]: Abstraction has 1816 states and 2689 transitions. [2021-12-06 18:37:52,091 INFO L587 BuchiCegarLoop]: Abstraction has 1816 states and 2689 transitions. [2021-12-06 18:37:52,091 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-06 18:37:52,091 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1816 states and 2689 transitions. [2021-12-06 18:37:52,098 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1683 [2021-12-06 18:37:52,098 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:37:52,098 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:37:52,100 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:37:52,100 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:37:52,101 INFO L791 eck$LassoCheckResult]: Stem: 19638#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 19639#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 19563#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19564#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19415#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 19416#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19000#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19001#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19082#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19800#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18970#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 18971#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19378#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 19404#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19086#L866 assume !(0 == ~M_E~0); 19087#L866-2 assume !(0 == ~T1_E~0); 19591#L871-1 assume !(0 == ~T2_E~0); 19592#L876-1 assume !(0 == ~T3_E~0); 19848#L881-1 assume !(0 == ~T4_E~0); 19602#L886-1 assume !(0 == ~T5_E~0); 19369#L891-1 assume !(0 == ~T6_E~0); 19370#L896-1 assume !(0 == ~T7_E~0); 19594#L901-1 assume !(0 == ~T8_E~0); 19614#L906-1 assume !(0 == ~E_M~0); 19615#L911-1 assume !(0 == ~E_1~0); 19413#L916-1 assume !(0 == ~E_2~0); 19414#L921-1 assume !(0 == ~E_3~0); 19712#L926-1 assume 0 == ~E_4~0;~E_4~0 := 1; 19812#L931-1 assume !(0 == ~E_5~0); 19853#L936-1 assume !(0 == ~E_6~0); 19861#L941-1 assume !(0 == ~E_7~0); 19419#L946-1 assume !(0 == ~E_8~0); 19420#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19831#L430 assume !(1 == ~m_pc~0); 19277#L430-2 is_master_triggered_~__retres1~0#1 := 0; 18905#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18906#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19520#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19530#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19695#L449 assume 1 == ~t1_pc~0; 19696#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19090#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18864#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18865#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 19629#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19475#L468 assume !(1 == ~t2_pc~0); 18889#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18888#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19377#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19284#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 18907#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18908#L487 assume 1 == ~t3_pc~0; 19844#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19004#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19005#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19684#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 19343#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19344#L506 assume !(1 == ~t4_pc~0); 19471#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 19516#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19822#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19823#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 19466#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19295#L525 assume 1 == ~t5_pc~0; 19230#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18949#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19423#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19424#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 19146#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19147#L544 assume !(1 == ~t6_pc~0); 19296#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19297#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19645#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18931#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 18932#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19788#L563 assume 1 == ~t7_pc~0; 19663#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18959#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18960#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19371#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 19091#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19092#L582 assume 1 == ~t8_pc~0; 19015#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19016#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19845#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19332#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 19234#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19235#L964 assume !(1 == ~M_E~0); 19698#L964-2 assume !(1 == ~T1_E~0); 20095#L969-1 assume !(1 == ~T2_E~0); 20090#L974-1 assume !(1 == ~T3_E~0); 20086#L979-1 assume !(1 == ~T4_E~0); 20082#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19302#L989-1 assume !(1 == ~T6_E~0); 19303#L994-1 assume !(1 == ~T7_E~0); 19188#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19189#L1004-1 assume !(1 == ~E_M~0); 18933#L1009-1 assume !(1 == ~E_1~0); 18934#L1014-1 assume !(1 == ~E_2~0); 19177#L1019-1 assume !(1 == ~E_3~0); 19687#L1024-1 assume !(1 == ~E_4~0); 19110#L1029-1 assume !(1 == ~E_5~0); 19111#L1034-1 assume !(1 == ~E_6~0); 19205#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 19826#L1044-1 assume !(1 == ~E_8~0); 19387#L1049-1 assume { :end_inline_reset_delta_events } true; 19388#L1315-2 [2021-12-06 18:37:52,102 INFO L793 eck$LassoCheckResult]: Loop: 19388#L1315-2 assume !false; 19890#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19889#L841 assume !false; 19888#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 19883#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19878#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 19877#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19875#L724 assume !(0 != eval_~tmp~0#1); 19874#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19873#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19872#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19846#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19209#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19210#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19223#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19224#L886-3 assume !(0 == ~T5_E~0); 19448#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19449#L896-3 assume !(0 == ~T7_E~0); 19315#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19316#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19450#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19656#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19255#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19256#L926-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19640#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19322#L936-3 assume !(0 == ~E_6~0); 19323#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19465#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19211#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19212#L430-30 assume 1 == ~m_pc~0; 19236#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19237#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19020#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19021#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19675#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19679#L449-30 assume 1 == ~t1_pc~0; 19239#L450-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18929#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18930#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19301#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19013#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19014#L468-30 assume 1 == ~t2_pc~0; 19105#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19106#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19721#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19439#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19440#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19289#L487-30 assume 1 == ~t3_pc~0; 19270#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19085#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19417#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19418#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19694#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19363#L506-30 assume !(1 == ~t4_pc~0); 19364#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 19391#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19392#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19409#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 19290#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19291#L525-30 assume 1 == ~t5_pc~0; 19783#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19784#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18995#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18996#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19774#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20401#L544-30 assume !(1 == ~t6_pc~0); 20400#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 20398#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20397#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20396#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19871#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19769#L563-30 assume 1 == ~t7_pc~0; 19034#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19035#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19053#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19379#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19380#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19756#L582-30 assume 1 == ~t8_pc~0; 19718#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19132#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19367#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19787#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19862#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18938#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18939#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19076#L969-3 assume !(1 == ~T2_E~0); 19067#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19068#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19480#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19481#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19113#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19114#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19627#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 18985#L1009-3 assume !(1 == ~E_1~0); 18986#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19461#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19462#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19443#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19410#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19411#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19686#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19103#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 19104#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19233#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 19572#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 19137#L1334 assume !(0 == start_simulation_~tmp~3#1); 19139#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 19157#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 18868#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 18869#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 19464#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19814#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19646#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 19647#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 19388#L1315-2 [2021-12-06 18:37:52,103 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:37:52,103 INFO L85 PathProgramCache]: Analyzing trace with hash -1799592066, now seen corresponding path program 1 times [2021-12-06 18:37:52,103 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:37:52,103 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1267574571] [2021-12-06 18:37:52,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:37:52,104 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:37:52,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:37:52,156 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:37:52,156 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:37:52,156 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1267574571] [2021-12-06 18:37:52,157 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1267574571] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:37:52,157 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:37:52,157 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:37:52,157 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1833659994] [2021-12-06 18:37:52,157 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:37:52,157 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 18:37:52,158 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:37:52,158 INFO L85 PathProgramCache]: Analyzing trace with hash -779318671, now seen corresponding path program 1 times [2021-12-06 18:37:52,158 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:37:52,158 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1023743480] [2021-12-06 18:37:52,158 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:37:52,158 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:37:52,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:37:52,191 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:37:52,191 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:37:52,191 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1023743480] [2021-12-06 18:37:52,191 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1023743480] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:37:52,192 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:37:52,192 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:37:52,192 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [62363311] [2021-12-06 18:37:52,192 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:37:52,192 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 18:37:52,192 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:37:52,193 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 18:37:52,193 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 18:37:52,193 INFO L87 Difference]: Start difference. First operand 1816 states and 2689 transitions. cyclomatic complexity: 875 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:37:52,330 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:37:52,331 INFO L93 Difference]: Finished difference Result 3306 states and 4884 transitions. [2021-12-06 18:37:52,331 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 18:37:52,331 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3306 states and 4884 transitions. [2021-12-06 18:37:52,349 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3153 [2021-12-06 18:37:52,374 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3306 states to 3306 states and 4884 transitions. [2021-12-06 18:37:52,375 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3306 [2021-12-06 18:37:52,378 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3306 [2021-12-06 18:37:52,378 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3306 states and 4884 transitions. [2021-12-06 18:37:52,384 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:37:52,384 INFO L681 BuchiCegarLoop]: Abstraction has 3306 states and 4884 transitions. [2021-12-06 18:37:52,388 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3306 states and 4884 transitions. [2021-12-06 18:37:52,446 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3306 to 3304. [2021-12-06 18:37:52,454 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3304 states, 3304 states have (on average 1.4776029055690072) internal successors, (4882), 3303 states have internal predecessors, (4882), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:37:52,465 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3304 states to 3304 states and 4882 transitions. [2021-12-06 18:37:52,465 INFO L704 BuchiCegarLoop]: Abstraction has 3304 states and 4882 transitions. [2021-12-06 18:37:52,465 INFO L587 BuchiCegarLoop]: Abstraction has 3304 states and 4882 transitions. [2021-12-06 18:37:52,465 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-06 18:37:52,465 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3304 states and 4882 transitions. [2021-12-06 18:37:52,476 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3153 [2021-12-06 18:37:52,477 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:37:52,477 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:37:52,478 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:37:52,478 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:37:52,479 INFO L791 eck$LassoCheckResult]: Stem: 24780#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 24781#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 24702#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24703#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24553#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 24554#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24133#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24134#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24215#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24965#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24103#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 24104#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 24517#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 24542#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24219#L866 assume !(0 == ~M_E~0); 24220#L866-2 assume !(0 == ~T1_E~0); 24732#L871-1 assume !(0 == ~T2_E~0); 24733#L876-1 assume !(0 == ~T3_E~0); 25023#L881-1 assume !(0 == ~T4_E~0); 24744#L886-1 assume !(0 == ~T5_E~0); 24508#L891-1 assume !(0 == ~T6_E~0); 24509#L896-1 assume !(0 == ~T7_E~0); 24736#L901-1 assume !(0 == ~T8_E~0); 24756#L906-1 assume !(0 == ~E_M~0); 24757#L911-1 assume !(0 == ~E_1~0); 24551#L916-1 assume !(0 == ~E_2~0); 24552#L921-1 assume !(0 == ~E_3~0); 24860#L926-1 assume !(0 == ~E_4~0); 24977#L931-1 assume !(0 == ~E_5~0); 25033#L936-1 assume !(0 == ~E_6~0); 25043#L941-1 assume !(0 == ~E_7~0); 24557#L946-1 assume !(0 == ~E_8~0); 24558#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25005#L430 assume !(1 == ~m_pc~0); 24413#L430-2 is_master_triggered_~__retres1~0#1 := 0; 24037#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24038#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24659#L1073 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24669#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24840#L449 assume 1 == ~t1_pc~0; 24841#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24224#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23996#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23997#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 24771#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24613#L468 assume !(1 == ~t2_pc~0); 24021#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 24020#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24516#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24421#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 24039#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24040#L487 assume 1 == ~t3_pc~0; 25020#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 24137#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24138#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24829#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 24482#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24483#L506 assume !(1 == ~t4_pc~0); 24609#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24655#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24991#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24992#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 24604#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24434#L525 assume 1 == ~t5_pc~0; 24366#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24082#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24561#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24562#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 24280#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24281#L544 assume !(1 == ~t6_pc~0); 24435#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 24436#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24788#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24063#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 24064#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24953#L563 assume 1 == ~t7_pc~0; 24807#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24092#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24093#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24510#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 24225#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24226#L582 assume 1 == ~t8_pc~0; 24148#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24149#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25021#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24471#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 24370#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24371#L964 assume !(1 == ~M_E~0); 24843#L964-2 assume !(1 == ~T1_E~0); 25141#L969-1 assume !(1 == ~T2_E~0); 24986#L974-1 assume !(1 == ~T3_E~0); 24987#L979-1 assume !(1 == ~T4_E~0); 25058#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 24441#L989-1 assume !(1 == ~T6_E~0); 24442#L994-1 assume !(1 == ~T7_E~0); 24323#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24324#L1004-1 assume !(1 == ~E_M~0); 24065#L1009-1 assume !(1 == ~E_1~0); 24066#L1014-1 assume !(1 == ~E_2~0); 25131#L1019-1 assume !(1 == ~E_3~0); 25119#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 25117#L1029-1 assume !(1 == ~E_5~0); 25115#L1034-1 assume !(1 == ~E_6~0); 25113#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 25111#L1044-1 assume !(1 == ~E_8~0); 25109#L1049-1 assume { :end_inline_reset_delta_events } true; 25102#L1315-2 [2021-12-06 18:37:52,479 INFO L793 eck$LassoCheckResult]: Loop: 25102#L1315-2 assume !false; 25097#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25096#L841 assume !false; 25095#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25090#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25085#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25084#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 25082#L724 assume !(0 != eval_~tmp~0#1); 25081#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25080#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25078#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25079#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26591#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26590#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26589#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26588#L886-3 assume !(0 == ~T5_E~0); 26586#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 26583#L896-3 assume !(0 == ~T7_E~0); 26581#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 26578#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 26574#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26571#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26568#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26564#L926-3 assume !(0 == ~E_4~0); 26562#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26558#L936-3 assume !(0 == ~E_6~0); 26555#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 26553#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 26551#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26549#L430-30 assume 1 == ~m_pc~0; 26546#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26541#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26503#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26450#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26447#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26445#L449-30 assume !(1 == ~t1_pc~0); 26442#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 26440#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26438#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26436#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26433#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26432#L468-30 assume 1 == ~t2_pc~0; 26429#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26426#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26395#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26392#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26383#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26375#L487-30 assume 1 == ~t3_pc~0; 24406#L488-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 24218#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24555#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24556#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24839#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24502#L506-30 assume !(1 == ~t4_pc~0); 24503#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 24529#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24530#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24547#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 24429#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24430#L525-30 assume 1 == ~t5_pc~0; 24946#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24947#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24128#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24129#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 24433#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24197#L544-30 assume 1 == ~t6_pc~0; 24004#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 24005#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25035#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24958#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 24959#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24928#L563-30 assume 1 == ~t7_pc~0; 24167#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24168#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24186#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24518#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 24519#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24910#L582-30 assume 1 == ~t8_pc~0; 24912#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25319#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25317#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25315#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25294#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25256#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24071#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25242#L969-3 assume !(1 == ~T2_E~0); 25239#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25230#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25217#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25205#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 25198#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25192#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25187#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25181#L1009-3 assume !(1 == ~E_1~0); 25177#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25174#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25166#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25163#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25162#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25161#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25160#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25159#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25148#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25140#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25139#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 25138#L1334 assume !(0 == start_simulation_~tmp~3#1); 24923#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 25128#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25118#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 25116#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 25114#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25112#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25110#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 25108#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 25102#L1315-2 [2021-12-06 18:37:52,479 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:37:52,480 INFO L85 PathProgramCache]: Analyzing trace with hash -1616610622, now seen corresponding path program 1 times [2021-12-06 18:37:52,480 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:37:52,480 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1112287116] [2021-12-06 18:37:52,480 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:37:52,480 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:37:52,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:37:52,526 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:37:52,526 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:37:52,527 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1112287116] [2021-12-06 18:37:52,527 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1112287116] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:37:52,527 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:37:52,527 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 18:37:52,527 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [225725447] [2021-12-06 18:37:52,527 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:37:52,528 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 18:37:52,528 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:37:52,528 INFO L85 PathProgramCache]: Analyzing trace with hash -830163917, now seen corresponding path program 1 times [2021-12-06 18:37:52,528 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:37:52,528 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1037954207] [2021-12-06 18:37:52,528 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:37:52,529 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:37:52,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:37:52,562 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:37:52,562 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:37:52,562 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1037954207] [2021-12-06 18:37:52,562 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1037954207] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:37:52,563 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:37:52,563 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:37:52,563 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [141810738] [2021-12-06 18:37:52,563 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:37:52,563 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 18:37:52,563 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:37:52,564 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-06 18:37:52,564 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-06 18:37:52,564 INFO L87 Difference]: Start difference. First operand 3304 states and 4882 transitions. cyclomatic complexity: 1582 Second operand has 5 states, 5 states have (on average 21.2) internal successors, (106), 5 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:37:52,861 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:37:52,862 INFO L93 Difference]: Finished difference Result 9486 states and 13948 transitions. [2021-12-06 18:37:52,862 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-06 18:37:52,863 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9486 states and 13948 transitions. [2021-12-06 18:37:52,892 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 9108 [2021-12-06 18:37:52,938 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9486 states to 9486 states and 13948 transitions. [2021-12-06 18:37:52,938 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9486 [2021-12-06 18:37:52,945 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9486 [2021-12-06 18:37:52,945 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9486 states and 13948 transitions. [2021-12-06 18:37:52,955 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:37:52,955 INFO L681 BuchiCegarLoop]: Abstraction has 9486 states and 13948 transitions. [2021-12-06 18:37:52,962 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9486 states and 13948 transitions. [2021-12-06 18:37:53,030 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9486 to 3424. [2021-12-06 18:37:53,036 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3424 states, 3424 states have (on average 1.4608644859813085) internal successors, (5002), 3423 states have internal predecessors, (5002), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:37:53,042 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3424 states to 3424 states and 5002 transitions. [2021-12-06 18:37:53,042 INFO L704 BuchiCegarLoop]: Abstraction has 3424 states and 5002 transitions. [2021-12-06 18:37:53,042 INFO L587 BuchiCegarLoop]: Abstraction has 3424 states and 5002 transitions. [2021-12-06 18:37:53,042 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-06 18:37:53,042 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3424 states and 5002 transitions. [2021-12-06 18:37:53,051 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3270 [2021-12-06 18:37:53,051 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:37:53,052 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:37:53,053 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:37:53,053 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:37:53,053 INFO L791 eck$LassoCheckResult]: Stem: 37602#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 37603#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 37524#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37525#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37359#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 37360#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36936#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36937#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37019#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 37795#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36906#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36907#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37325#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37348#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37023#L866 assume !(0 == ~M_E~0); 37024#L866-2 assume !(0 == ~T1_E~0); 37553#L871-1 assume !(0 == ~T2_E~0); 37554#L876-1 assume !(0 == ~T3_E~0); 37865#L881-1 assume !(0 == ~T4_E~0); 37564#L886-1 assume !(0 == ~T5_E~0); 37314#L891-1 assume !(0 == ~T6_E~0); 37315#L896-1 assume !(0 == ~T7_E~0); 37556#L901-1 assume !(0 == ~T8_E~0); 37577#L906-1 assume !(0 == ~E_M~0); 37578#L911-1 assume !(0 == ~E_1~0); 37357#L916-1 assume !(0 == ~E_2~0); 37358#L921-1 assume !(0 == ~E_3~0); 37685#L926-1 assume !(0 == ~E_4~0); 37811#L931-1 assume !(0 == ~E_5~0); 37876#L936-1 assume !(0 == ~E_6~0); 37892#L941-1 assume !(0 == ~E_7~0); 37364#L946-1 assume !(0 == ~E_8~0); 37365#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37840#L430 assume !(1 == ~m_pc~0); 37220#L430-2 is_master_triggered_~__retres1~0#1 := 0; 36842#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36843#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 37483#L1073 assume !(0 != activate_threads_~tmp~1#1); 37484#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37668#L449 assume 1 == ~t1_pc~0; 37669#L450 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37027#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36799#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36800#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 37592#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37423#L468 assume !(1 == ~t2_pc~0); 36826#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 36825#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37322#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 37227#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 36844#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36845#L487 assume 1 == ~t3_pc~0; 37860#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36940#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36941#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 37653#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 37287#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37288#L506 assume !(1 == ~t4_pc~0); 37417#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 37465#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37826#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37827#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 37412#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37236#L525 assume 1 == ~t5_pc~0; 37172#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 36885#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37367#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37368#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 37083#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37084#L544 assume !(1 == ~t6_pc~0); 37237#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 37238#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37609#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36866#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 36867#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37782#L563 assume 1 == ~t7_pc~0; 37628#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36895#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36896#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37321#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 37030#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37031#L582 assume 1 == ~t8_pc~0; 36951#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36952#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37861#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37275#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 37173#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37174#L964 assume !(1 == ~M_E~0); 37672#L964-2 assume !(1 == ~T1_E~0); 37085#L969-1 assume !(1 == ~T2_E~0); 37086#L974-1 assume !(1 == ~T3_E~0); 37703#L979-1 assume !(1 == ~T4_E~0); 37704#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37243#L989-1 assume !(1 == ~T6_E~0); 37244#L994-1 assume !(1 == ~T7_E~0); 37129#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37130#L1004-1 assume !(1 == ~E_M~0); 36868#L1009-1 assume !(1 == ~E_1~0); 36869#L1014-1 assume !(1 == ~E_2~0); 38102#L1019-1 assume !(1 == ~E_3~0); 38078#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 38061#L1029-1 assume !(1 == ~E_5~0); 38040#L1034-1 assume !(1 == ~E_6~0); 38026#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 38015#L1044-1 assume !(1 == ~E_8~0); 38006#L1049-1 assume { :end_inline_reset_delta_events } true; 37999#L1315-2 [2021-12-06 18:37:53,053 INFO L793 eck$LassoCheckResult]: Loop: 37999#L1315-2 assume !false; 37994#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37993#L841 assume !false; 37992#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 37987#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 37982#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 37981#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 37979#L724 assume !(0 != eval_~tmp~0#1); 37978#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37977#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37976#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37863#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37148#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 37149#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 37162#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37163#L886-3 assume !(0 == ~T5_E~0); 37392#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 37393#L896-3 assume !(0 == ~T7_E~0); 37256#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37257#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 37394#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37621#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37194#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 37195#L926-3 assume !(0 == ~E_4~0); 37604#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 40079#L936-3 assume !(0 == ~E_6~0); 40075#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 37695#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37150#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37151#L430-30 assume 1 == ~m_pc~0; 37175#L431-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 37176#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36956#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 36957#L1073-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 40018#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40016#L449-30 assume !(1 == ~t1_pc~0); 40012#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 40010#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40008#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 40006#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40004#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40002#L468-30 assume 1 == ~t2_pc~0; 39998#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39996#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39994#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39992#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 39990#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39988#L487-30 assume !(1 == ~t3_pc~0); 39984#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 39982#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39980#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39978#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 39976#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39974#L506-30 assume 1 == ~t4_pc~0; 39970#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39968#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39966#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39964#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 39963#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39962#L525-30 assume 1 == ~t5_pc~0; 39960#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39959#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39958#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39957#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 39956#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39955#L544-30 assume 1 == ~t6_pc~0; 39953#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 39952#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39951#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37787#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 37788#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37756#L563-30 assume 1 == ~t7_pc~0; 36967#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36968#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36990#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37323#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 37324#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37739#L582-30 assume !(1 == ~t8_pc~0); 37740#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 38459#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38457#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38428#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 38426#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38424#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36871#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38368#L969-3 assume !(1 == ~T2_E~0); 38366#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38364#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 38347#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 38343#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 38332#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38330#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38329#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 38327#L1009-3 assume !(1 == ~E_1~0); 38307#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38306#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38284#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 38280#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38278#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38276#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 38274#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 38273#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 38265#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 38111#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 38109#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 38107#L1334 assume !(0 == start_simulation_~tmp~3#1); 37753#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 38087#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 38077#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 38060#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 38039#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38025#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38014#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 38005#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 37999#L1315-2 [2021-12-06 18:37:53,054 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:37:53,054 INFO L85 PathProgramCache]: Analyzing trace with hash -2109236796, now seen corresponding path program 1 times [2021-12-06 18:37:53,054 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:37:53,054 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [461001126] [2021-12-06 18:37:53,054 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:37:53,054 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:37:53,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:37:53,080 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:37:53,080 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:37:53,080 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [461001126] [2021-12-06 18:37:53,080 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [461001126] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:37:53,080 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:37:53,080 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:37:53,081 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1482102993] [2021-12-06 18:37:53,081 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:37:53,081 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 18:37:53,081 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:37:53,081 INFO L85 PathProgramCache]: Analyzing trace with hash 1404058164, now seen corresponding path program 1 times [2021-12-06 18:37:53,081 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:37:53,082 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1562632721] [2021-12-06 18:37:53,082 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:37:53,082 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:37:53,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:37:53,108 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:37:53,108 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:37:53,108 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1562632721] [2021-12-06 18:37:53,109 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1562632721] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:37:53,109 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:37:53,109 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:37:53,109 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1250704310] [2021-12-06 18:37:53,109 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:37:53,109 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 18:37:53,110 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:37:53,110 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 18:37:53,110 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 18:37:53,110 INFO L87 Difference]: Start difference. First operand 3424 states and 5002 transitions. cyclomatic complexity: 1582 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:37:53,372 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:37:53,372 INFO L93 Difference]: Finished difference Result 9389 states and 13529 transitions. [2021-12-06 18:37:53,373 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 18:37:53,373 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9389 states and 13529 transitions. [2021-12-06 18:37:53,425 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8960 [2021-12-06 18:37:53,470 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9389 states to 9389 states and 13529 transitions. [2021-12-06 18:37:53,470 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9389 [2021-12-06 18:37:53,481 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9389 [2021-12-06 18:37:53,481 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9389 states and 13529 transitions. [2021-12-06 18:37:53,497 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:37:53,498 INFO L681 BuchiCegarLoop]: Abstraction has 9389 states and 13529 transitions. [2021-12-06 18:37:53,507 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9389 states and 13529 transitions. [2021-12-06 18:37:53,646 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9389 to 8901. [2021-12-06 18:37:53,665 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8901 states, 8901 states have (on average 1.4448938321536906) internal successors, (12861), 8900 states have internal predecessors, (12861), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:37:53,692 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8901 states to 8901 states and 12861 transitions. [2021-12-06 18:37:53,693 INFO L704 BuchiCegarLoop]: Abstraction has 8901 states and 12861 transitions. [2021-12-06 18:37:53,693 INFO L587 BuchiCegarLoop]: Abstraction has 8901 states and 12861 transitions. [2021-12-06 18:37:53,693 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-06 18:37:53,693 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8901 states and 12861 transitions. [2021-12-06 18:37:53,729 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8732 [2021-12-06 18:37:53,730 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:37:53,730 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:37:53,732 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:37:53,732 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:37:53,732 INFO L791 eck$LassoCheckResult]: Stem: 50435#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 50436#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 50351#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50352#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50182#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 50183#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49760#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49761#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49842#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50656#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49730#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49731#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50146#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 50171#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49846#L866 assume !(0 == ~M_E~0); 49847#L866-2 assume !(0 == ~T1_E~0); 50381#L871-1 assume !(0 == ~T2_E~0); 50382#L876-1 assume !(0 == ~T3_E~0); 50740#L881-1 assume !(0 == ~T4_E~0); 50394#L886-1 assume !(0 == ~T5_E~0); 50137#L891-1 assume !(0 == ~T6_E~0); 50138#L896-1 assume !(0 == ~T7_E~0); 50385#L901-1 assume !(0 == ~T8_E~0); 50405#L906-1 assume !(0 == ~E_M~0); 50406#L911-1 assume !(0 == ~E_1~0); 50180#L916-1 assume !(0 == ~E_2~0); 50181#L921-1 assume !(0 == ~E_3~0); 50537#L926-1 assume !(0 == ~E_4~0); 50672#L931-1 assume !(0 == ~E_5~0); 50754#L936-1 assume !(0 == ~E_6~0); 50772#L941-1 assume !(0 == ~E_7~0); 50188#L946-1 assume !(0 == ~E_8~0); 50189#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50711#L430 assume !(1 == ~m_pc~0); 50625#L430-2 is_master_triggered_~__retres1~0#1 := 0; 49663#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49664#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 50304#L1073 assume !(0 != activate_threads_~tmp~1#1); 50314#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50515#L449 assume !(1 == ~t1_pc~0); 49849#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 49850#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49622#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 49623#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 50422#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50247#L468 assume !(1 == ~t2_pc~0); 49647#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 49646#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50145#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 50047#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 49665#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49666#L487 assume 1 == ~t3_pc~0; 50735#L488 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49764#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49765#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50499#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 50112#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50113#L506 assume !(1 == ~t4_pc~0); 50243#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 50297#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50692#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50693#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 50235#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50058#L525 assume 1 == ~t5_pc~0; 49997#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49707#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50191#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50192#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 49907#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49908#L544 assume !(1 == ~t6_pc~0); 50059#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 50060#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50442#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49689#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 49690#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50640#L563 assume 1 == ~t7_pc~0; 50461#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49717#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49718#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50139#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 49851#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49852#L582 assume 1 == ~t8_pc~0; 49775#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 49776#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50736#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50099#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 49998#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49999#L964 assume !(1 == ~M_E~0); 50519#L964-2 assume !(1 == ~T1_E~0); 49909#L969-1 assume !(1 == ~T2_E~0); 49910#L974-1 assume !(1 == ~T3_E~0); 50557#L979-1 assume !(1 == ~T4_E~0); 50558#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 53913#L989-1 assume !(1 == ~T6_E~0); 53912#L994-1 assume !(1 == ~T7_E~0); 53911#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 53910#L1004-1 assume !(1 == ~E_M~0); 53909#L1009-1 assume !(1 == ~E_1~0); 53908#L1014-1 assume !(1 == ~E_2~0); 53907#L1019-1 assume !(1 == ~E_3~0); 53906#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 49871#L1029-1 assume !(1 == ~E_5~0); 49872#L1034-1 assume !(1 == ~E_6~0); 49968#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 50702#L1044-1 assume !(1 == ~E_8~0); 50155#L1049-1 assume { :end_inline_reset_delta_events } true; 49840#L1315-2 [2021-12-06 18:37:53,733 INFO L793 eck$LassoCheckResult]: Loop: 49840#L1315-2 assume !false; 49841#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49625#L841 assume !false; 49969#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 49902#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 49903#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 49742#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 49660#L724 assume !(0 != eval_~tmp~0#1); 49662#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50573#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49671#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 49672#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 49972#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 49973#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 49986#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49987#L886-3 assume !(0 == ~T5_E~0); 50215#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50216#L896-3 assume !(0 == ~T7_E~0); 50082#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 50083#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 50217#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 50454#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50020#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50021#L926-3 assume !(0 == ~E_4~0); 50437#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50088#L936-3 assume !(0 == ~E_6~0); 50089#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50234#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 58153#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 58151#L430-30 assume !(1 == ~m_pc~0); 58149#L430-32 is_master_triggered_~__retres1~0#1 := 0; 58147#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58145#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 58143#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 58140#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 58138#L449-30 assume !(1 == ~t1_pc~0); 58136#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 58134#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 58132#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 58130#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 58127#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 58125#L468-30 assume 1 == ~t2_pc~0; 58121#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 58119#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58117#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 58116#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 58113#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 58111#L487-30 assume !(1 == ~t3_pc~0); 58108#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 58106#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58104#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 58102#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 58099#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58097#L506-30 assume 1 == ~t4_pc~0; 58094#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 58092#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58090#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 58088#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 58087#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 58086#L525-30 assume 1 == ~t5_pc~0; 58084#L526-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 57950#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 57949#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 57948#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 57947#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 57946#L544-30 assume 1 == ~t6_pc~0; 57944#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 57943#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 57942#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 57940#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 57939#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 57938#L563-30 assume !(1 == ~t7_pc~0); 57936#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 57933#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 57931#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 57929#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 57925#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 57923#L582-30 assume !(1 == ~t8_pc~0); 57920#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 57918#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 57915#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 57913#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 57911#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57910#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 54657#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 57907#L969-3 assume !(1 == ~T2_E~0); 57905#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 57903#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 57901#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 57392#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 57897#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 57895#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 57893#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 57891#L1009-3 assume !(1 == ~E_1~0); 57889#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 57886#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 57884#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 54427#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 57881#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 57880#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 57879#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 57878#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 57858#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 57854#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 56843#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 50830#L1334 assume !(0 == start_simulation_~tmp~3#1); 50612#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 49918#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 49626#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 49627#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 50233#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50675#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50443#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 50444#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 49840#L1315-2 [2021-12-06 18:37:53,734 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:37:53,734 INFO L85 PathProgramCache]: Analyzing trace with hash 28257477, now seen corresponding path program 1 times [2021-12-06 18:37:53,734 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:37:53,734 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [38779333] [2021-12-06 18:37:53,734 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:37:53,735 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:37:53,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:37:53,770 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:37:53,770 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:37:53,770 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [38779333] [2021-12-06 18:37:53,771 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [38779333] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:37:53,771 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:37:53,771 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:37:53,771 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1060673367] [2021-12-06 18:37:53,771 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:37:53,772 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 18:37:53,772 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:37:53,772 INFO L85 PathProgramCache]: Analyzing trace with hash 1027563768, now seen corresponding path program 1 times [2021-12-06 18:37:53,772 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:37:53,773 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1615736774] [2021-12-06 18:37:53,773 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:37:53,773 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:37:53,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:37:53,807 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:37:53,808 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:37:53,808 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1615736774] [2021-12-06 18:37:53,808 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1615736774] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:37:53,808 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:37:53,808 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:37:53,808 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [464438491] [2021-12-06 18:37:53,809 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:37:53,809 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 18:37:53,809 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:37:53,809 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 18:37:53,810 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 18:37:53,810 INFO L87 Difference]: Start difference. First operand 8901 states and 12861 transitions. cyclomatic complexity: 3968 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:37:54,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:37:54,078 INFO L93 Difference]: Finished difference Result 25288 states and 36118 transitions. [2021-12-06 18:37:54,078 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 18:37:54,079 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25288 states and 36118 transitions. [2021-12-06 18:37:54,226 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24508 [2021-12-06 18:37:54,350 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25288 states to 25288 states and 36118 transitions. [2021-12-06 18:37:54,350 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25288 [2021-12-06 18:37:54,365 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25288 [2021-12-06 18:37:54,365 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25288 states and 36118 transitions. [2021-12-06 18:37:54,385 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:37:54,385 INFO L681 BuchiCegarLoop]: Abstraction has 25288 states and 36118 transitions. [2021-12-06 18:37:54,408 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25288 states and 36118 transitions. [2021-12-06 18:37:54,714 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25288 to 24458. [2021-12-06 18:37:54,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24458 states, 24458 states have (on average 1.4311881592934828) internal successors, (35004), 24457 states have internal predecessors, (35004), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:37:54,808 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24458 states to 24458 states and 35004 transitions. [2021-12-06 18:37:54,809 INFO L704 BuchiCegarLoop]: Abstraction has 24458 states and 35004 transitions. [2021-12-06 18:37:54,809 INFO L587 BuchiCegarLoop]: Abstraction has 24458 states and 35004 transitions. [2021-12-06 18:37:54,809 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-06 18:37:54,809 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24458 states and 35004 transitions. [2021-12-06 18:37:54,931 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24250 [2021-12-06 18:37:54,932 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:37:54,932 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:37:54,934 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:37:54,934 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:37:54,934 INFO L791 eck$LassoCheckResult]: Stem: 84620#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 84621#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 84539#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 84540#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 84381#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 84382#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 83957#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 83958#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 84039#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 84826#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 83928#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 83929#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 84347#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 84370#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 84045#L866 assume !(0 == ~M_E~0); 84046#L866-2 assume !(0 == ~T1_E~0); 84570#L871-1 assume !(0 == ~T2_E~0); 84571#L876-1 assume !(0 == ~T3_E~0); 84892#L881-1 assume !(0 == ~T4_E~0); 84581#L886-1 assume !(0 == ~T5_E~0); 84336#L891-1 assume !(0 == ~T6_E~0); 84337#L896-1 assume !(0 == ~T7_E~0); 84573#L901-1 assume !(0 == ~T8_E~0); 84595#L906-1 assume !(0 == ~E_M~0); 84596#L911-1 assume !(0 == ~E_1~0); 84379#L916-1 assume !(0 == ~E_2~0); 84380#L921-1 assume !(0 == ~E_3~0); 84713#L926-1 assume !(0 == ~E_4~0); 84838#L931-1 assume !(0 == ~E_5~0); 84903#L936-1 assume !(0 == ~E_6~0); 84914#L941-1 assume !(0 == ~E_7~0); 84386#L946-1 assume !(0 == ~E_8~0); 84387#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 84872#L430 assume !(1 == ~m_pc~0); 84801#L430-2 is_master_triggered_~__retres1~0#1 := 0; 83864#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 83865#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 84495#L1073 assume !(0 != activate_threads_~tmp~1#1); 84506#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 84694#L449 assume !(1 == ~t1_pc~0); 84048#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 84049#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 83821#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 83822#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 84610#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 84445#L468 assume !(1 == ~t2_pc~0); 83848#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 83847#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 84344#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 84254#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 83866#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 83867#L487 assume !(1 == ~t3_pc~0); 83985#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 83961#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 83962#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 84678#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 84312#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 84313#L506 assume !(1 == ~t4_pc~0); 84439#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 84491#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 84856#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 84857#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 84434#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 84263#L525 assume 1 == ~t5_pc~0; 84198#L526 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 83906#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 84389#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 84390#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 84106#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 84107#L544 assume !(1 == ~t6_pc~0); 84264#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 84265#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 84627#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 83888#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 83889#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 84813#L563 assume 1 == ~t7_pc~0; 84648#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 83916#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 83917#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 84343#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 84052#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 84053#L582 assume 1 == ~t8_pc~0; 83972#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 83973#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 84889#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 84302#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 84199#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 84200#L964 assume !(1 == ~M_E~0); 84697#L964-2 assume !(1 == ~T1_E~0); 88031#L969-1 assume !(1 == ~T2_E~0); 88030#L974-1 assume !(1 == ~T3_E~0); 84731#L979-1 assume !(1 == ~T4_E~0); 84732#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 88028#L989-1 assume !(1 == ~T6_E~0); 88029#L994-1 assume !(1 == ~T7_E~0); 88027#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 87989#L1004-1 assume !(1 == ~E_M~0); 87990#L1009-1 assume !(1 == ~E_1~0); 84142#L1014-1 assume !(1 == ~E_2~0); 84143#L1019-1 assume !(1 == ~E_3~0); 87966#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 87965#L1029-1 assume !(1 == ~E_5~0); 87964#L1034-1 assume !(1 == ~E_6~0); 87963#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 87962#L1044-1 assume !(1 == ~E_8~0); 87961#L1049-1 assume { :end_inline_reset_delta_events } true; 87950#L1315-2 [2021-12-06 18:37:54,935 INFO L793 eck$LassoCheckResult]: Loop: 87950#L1315-2 assume !false; 87942#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 87939#L841 assume !false; 87933#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 87934#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 107272#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 107271#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 107269#L724 assume !(0 != eval_~tmp~0#1); 107270#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 107712#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 107711#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 107710#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 107709#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 107708#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 107707#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 107706#L886-3 assume !(0 == ~T5_E~0); 107705#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 107704#L896-3 assume !(0 == ~T7_E~0); 107703#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 107702#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 107701#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 107700#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 107699#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 107698#L926-3 assume !(0 == ~E_4~0); 107697#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 107696#L936-3 assume !(0 == ~E_6~0); 107695#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 107694#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 107693#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 107692#L430-30 assume !(1 == ~m_pc~0); 107691#L430-32 is_master_triggered_~__retres1~0#1 := 0; 107690#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 107689#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 107688#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 107687#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 107686#L449-30 assume !(1 == ~t1_pc~0); 107685#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 107684#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 107683#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 107682#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 107681#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 107680#L468-30 assume !(1 == ~t2_pc~0); 107679#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 107677#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 107676#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 107675#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 107674#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 107673#L487-30 assume !(1 == ~t3_pc~0); 107672#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 107671#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 107670#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 107669#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 107668#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 107667#L506-30 assume 1 == ~t4_pc~0; 107665#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 107664#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 107663#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 107662#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 107661#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 107660#L525-30 assume !(1 == ~t5_pc~0); 107659#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 107657#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 107656#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 107655#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 107654#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 107653#L544-30 assume 1 == ~t6_pc~0; 107651#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 107650#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 107649#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 107648#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 107647#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 107646#L563-30 assume !(1 == ~t7_pc~0); 107645#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 107643#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 107642#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 107641#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 107640#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 107639#L582-30 assume !(1 == ~t8_pc~0); 107637#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 107636#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 107635#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 107634#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 107633#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 107632#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 88128#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 107631#L969-3 assume !(1 == ~T2_E~0); 107630#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 88117#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 88118#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 107324#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 107323#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 107322#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 107321#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 107320#L1009-3 assume !(1 == ~E_1~0); 107319#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 107318#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 107317#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 99740#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 107316#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 107315#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 107314#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 107313#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 107306#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 107303#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 107302#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 107301#L1334 assume !(0 == start_simulation_~tmp~3#1); 107300#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 88054#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 88046#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 88045#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 88044#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 88043#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 88019#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 87960#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 87950#L1315-2 [2021-12-06 18:37:54,936 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:37:54,936 INFO L85 PathProgramCache]: Analyzing trace with hash -1079871162, now seen corresponding path program 1 times [2021-12-06 18:37:54,936 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:37:54,936 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [694005591] [2021-12-06 18:37:54,936 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:37:54,937 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:37:54,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:37:54,976 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:37:54,976 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:37:54,976 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [694005591] [2021-12-06 18:37:54,977 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [694005591] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:37:54,977 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:37:54,977 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 18:37:54,977 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1781279006] [2021-12-06 18:37:54,977 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:37:54,977 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 18:37:54,978 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:37:54,978 INFO L85 PathProgramCache]: Analyzing trace with hash 2051423162, now seen corresponding path program 1 times [2021-12-06 18:37:54,978 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:37:54,978 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [528747210] [2021-12-06 18:37:54,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:37:54,979 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:37:54,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:37:55,014 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:37:55,015 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:37:55,015 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [528747210] [2021-12-06 18:37:55,015 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [528747210] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:37:55,015 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:37:55,016 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:37:55,016 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [416233843] [2021-12-06 18:37:55,016 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:37:55,016 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 18:37:55,017 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:37:55,017 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 18:37:55,017 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 18:37:55,018 INFO L87 Difference]: Start difference. First operand 24458 states and 35004 transitions. cyclomatic complexity: 10562 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:37:55,237 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:37:55,237 INFO L93 Difference]: Finished difference Result 46152 states and 65785 transitions. [2021-12-06 18:37:55,237 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 18:37:55,238 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 46152 states and 65785 transitions. [2021-12-06 18:37:55,397 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 45813 [2021-12-06 18:37:55,614 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 46152 states to 46152 states and 65785 transitions. [2021-12-06 18:37:55,627 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 46152 [2021-12-06 18:37:55,647 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 46152 [2021-12-06 18:37:55,648 INFO L73 IsDeterministic]: Start isDeterministic. Operand 46152 states and 65785 transitions. [2021-12-06 18:37:55,671 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:37:55,671 INFO L681 BuchiCegarLoop]: Abstraction has 46152 states and 65785 transitions. [2021-12-06 18:37:55,694 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46152 states and 65785 transitions. [2021-12-06 18:37:56,097 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46152 to 46080. [2021-12-06 18:37:56,132 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46080 states, 46080 states have (on average 1.4260633680555554) internal successors, (65713), 46079 states have internal predecessors, (65713), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:37:56,213 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46080 states to 46080 states and 65713 transitions. [2021-12-06 18:37:56,214 INFO L704 BuchiCegarLoop]: Abstraction has 46080 states and 65713 transitions. [2021-12-06 18:37:56,214 INFO L587 BuchiCegarLoop]: Abstraction has 46080 states and 65713 transitions. [2021-12-06 18:37:56,214 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-06 18:37:56,214 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 46080 states and 65713 transitions. [2021-12-06 18:37:56,329 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 45741 [2021-12-06 18:37:56,329 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:37:56,329 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:37:56,330 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:37:56,330 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:37:56,331 INFO L791 eck$LassoCheckResult]: Stem: 155282#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 155283#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 155192#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 155193#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 155010#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 155011#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 154573#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 154574#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 154658#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 155548#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 154544#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 154545#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 154976#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 154999#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 154664#L866 assume !(0 == ~M_E~0); 154665#L866-2 assume !(0 == ~T1_E~0); 155226#L871-1 assume !(0 == ~T2_E~0); 155227#L876-1 assume !(0 == ~T3_E~0); 155649#L881-1 assume !(0 == ~T4_E~0); 155238#L886-1 assume !(0 == ~T5_E~0); 154965#L891-1 assume !(0 == ~T6_E~0); 154966#L896-1 assume !(0 == ~T7_E~0); 155229#L901-1 assume !(0 == ~T8_E~0); 155252#L906-1 assume !(0 == ~E_M~0); 155253#L911-1 assume !(0 == ~E_1~0); 155008#L916-1 assume !(0 == ~E_2~0); 155009#L921-1 assume !(0 == ~E_3~0); 155393#L926-1 assume !(0 == ~E_4~0); 155566#L931-1 assume !(0 == ~E_5~0); 155677#L936-1 assume !(0 == ~E_6~0); 155696#L941-1 assume !(0 == ~E_7~0); 155016#L946-1 assume !(0 == ~E_8~0); 155017#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 155614#L430 assume !(1 == ~m_pc~0); 155509#L430-2 is_master_triggered_~__retres1~0#1 := 0; 154480#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 154481#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 155136#L1073 assume !(0 != activate_threads_~tmp~1#1); 155153#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 155372#L449 assume !(1 == ~t1_pc~0); 154667#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 154668#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 154438#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 154439#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 155268#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 155077#L468 assume !(1 == ~t2_pc~0); 154464#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 154463#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 154973#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 154873#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 154482#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 154483#L487 assume !(1 == ~t3_pc~0); 154601#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 154577#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 154578#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 155350#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 154938#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 154939#L506 assume !(1 == ~t4_pc~0); 155073#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 155127#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 155587#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 155588#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 155069#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 154883#L525 assume !(1 == ~t5_pc~0); 154521#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 154522#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 155020#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 155021#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 154726#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 154727#L544 assume !(1 == ~t6_pc~0); 154884#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 154885#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 155291#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 154504#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 154505#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 155525#L563 assume 1 == ~t7_pc~0; 155310#L564 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 154532#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 154533#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 154972#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 154671#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 154672#L582 assume 1 == ~t8_pc~0; 154588#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 154589#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 155642#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 154926#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 154820#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 154821#L964 assume !(1 == ~M_E~0); 155376#L964-2 assume !(1 == ~T1_E~0); 154728#L969-1 assume !(1 == ~T2_E~0); 154729#L974-1 assume !(1 == ~T3_E~0); 155413#L979-1 assume !(1 == ~T4_E~0); 155414#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 164107#L989-1 assume !(1 == ~T6_E~0); 164106#L994-1 assume !(1 == ~T7_E~0); 164105#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 164104#L1004-1 assume !(1 == ~E_M~0); 164103#L1009-1 assume !(1 == ~E_1~0); 164102#L1014-1 assume !(1 == ~E_2~0); 164101#L1019-1 assume !(1 == ~E_3~0); 164100#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 155624#L1029-1 assume !(1 == ~E_5~0); 169726#L1034-1 assume !(1 == ~E_6~0); 169724#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 169721#L1044-1 assume !(1 == ~E_8~0); 169719#L1049-1 assume { :end_inline_reset_delta_events } true; 169713#L1315-2 [2021-12-06 18:37:56,331 INFO L793 eck$LassoCheckResult]: Loop: 169713#L1315-2 assume !false; 169708#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 164092#L841 assume !false; 164093#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 164035#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 164031#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 164009#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 164010#L724 assume !(0 != eval_~tmp~0#1); 169688#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 171106#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 171103#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 171101#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 171099#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 171085#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 171079#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 171074#L886-3 assume !(0 == ~T5_E~0); 171069#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 171063#L896-3 assume !(0 == ~T7_E~0); 171059#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 171054#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 171049#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 171044#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 171038#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 171033#L926-3 assume !(0 == ~E_4~0); 171028#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 171021#L936-3 assume !(0 == ~E_6~0); 171017#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 171013#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 171009#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 171005#L430-30 assume !(1 == ~m_pc~0); 171001#L430-32 is_master_triggered_~__retres1~0#1 := 0; 170996#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 170990#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 170986#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 170981#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 170978#L449-30 assume !(1 == ~t1_pc~0); 170975#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 169964#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 169961#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 169959#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 169957#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 169955#L468-30 assume 1 == ~t2_pc~0; 169952#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 169950#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 169948#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 169946#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 169944#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 169942#L487-30 assume !(1 == ~t3_pc~0); 169940#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 169938#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 169935#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 169933#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 169931#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 169929#L506-30 assume 1 == ~t4_pc~0; 169926#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 169924#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 169922#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 169920#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 169918#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 169916#L525-30 assume !(1 == ~t5_pc~0); 169914#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 169912#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 169909#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 169907#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 169905#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 169903#L544-30 assume 1 == ~t6_pc~0; 169900#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 169898#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 169895#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 169893#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 169891#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 169889#L563-30 assume 1 == ~t7_pc~0; 169886#L564-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 169884#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 169881#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 169879#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 169877#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 169875#L582-30 assume !(1 == ~t8_pc~0); 169872#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 169870#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 169868#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 169866#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 169864#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 169862#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 165714#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 169859#L969-3 assume !(1 == ~T2_E~0); 169857#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 169855#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 169853#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 169849#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 169847#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 169845#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 169843#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 169841#L1009-3 assume !(1 == ~E_1~0); 169839#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 169837#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 169835#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 169832#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 169830#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 169828#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 169826#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 169824#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 169781#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 169776#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 169774#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 169772#L1334 assume !(0 == start_simulation_~tmp~3#1); 169769#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 169748#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 169739#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 169737#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 169735#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 169733#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 169731#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 169718#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 169713#L1315-2 [2021-12-06 18:37:56,331 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:37:56,332 INFO L85 PathProgramCache]: Analyzing trace with hash 818659143, now seen corresponding path program 1 times [2021-12-06 18:37:56,332 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:37:56,332 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1650698996] [2021-12-06 18:37:56,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:37:56,332 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:37:56,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:37:56,372 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:37:56,373 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:37:56,373 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1650698996] [2021-12-06 18:37:56,373 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1650698996] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:37:56,373 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:37:56,373 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:37:56,374 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [993099380] [2021-12-06 18:37:56,374 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:37:56,374 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 18:37:56,375 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:37:56,375 INFO L85 PathProgramCache]: Analyzing trace with hash -1979095176, now seen corresponding path program 1 times [2021-12-06 18:37:56,375 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:37:56,375 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1447844567] [2021-12-06 18:37:56,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:37:56,376 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:37:56,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:37:56,412 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:37:56,412 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:37:56,412 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1447844567] [2021-12-06 18:37:56,413 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1447844567] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:37:56,414 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:37:56,414 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:37:56,414 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [502592840] [2021-12-06 18:37:56,414 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:37:56,415 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 18:37:56,415 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:37:56,415 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 18:37:56,415 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 18:37:56,416 INFO L87 Difference]: Start difference. First operand 46080 states and 65713 transitions. cyclomatic complexity: 19665 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:37:57,137 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:37:57,137 INFO L93 Difference]: Finished difference Result 127381 states and 180324 transitions. [2021-12-06 18:37:57,137 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 18:37:57,138 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 127381 states and 180324 transitions. [2021-12-06 18:37:57,561 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 124307 [2021-12-06 18:37:57,774 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 127381 states to 127381 states and 180324 transitions. [2021-12-06 18:37:57,774 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 127381 [2021-12-06 18:37:57,818 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 127381 [2021-12-06 18:37:57,818 INFO L73 IsDeterministic]: Start isDeterministic. Operand 127381 states and 180324 transitions. [2021-12-06 18:37:57,905 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:37:57,905 INFO L681 BuchiCegarLoop]: Abstraction has 127381 states and 180324 transitions. [2021-12-06 18:37:57,952 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127381 states and 180324 transitions. [2021-12-06 18:37:59,135 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127381 to 123869. [2021-12-06 18:37:59,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 123869 states, 123869 states have (on average 1.419209003059684) internal successors, (175796), 123868 states have internal predecessors, (175796), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:37:59,662 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 123869 states to 123869 states and 175796 transitions. [2021-12-06 18:37:59,663 INFO L704 BuchiCegarLoop]: Abstraction has 123869 states and 175796 transitions. [2021-12-06 18:37:59,663 INFO L587 BuchiCegarLoop]: Abstraction has 123869 states and 175796 transitions. [2021-12-06 18:37:59,663 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-06 18:37:59,663 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 123869 states and 175796 transitions. [2021-12-06 18:37:59,896 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 123227 [2021-12-06 18:37:59,896 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:37:59,896 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:37:59,897 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:37:59,897 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:37:59,897 INFO L791 eck$LassoCheckResult]: Stem: 328755#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 328756#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 328655#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 328656#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 328484#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 328485#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 328045#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 328046#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 328129#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 329020#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 328017#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 328018#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 328449#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 328473#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 328135#L866 assume !(0 == ~M_E~0); 328136#L866-2 assume !(0 == ~T1_E~0); 328689#L871-1 assume !(0 == ~T2_E~0); 328690#L876-1 assume !(0 == ~T3_E~0); 329114#L881-1 assume !(0 == ~T4_E~0); 328705#L886-1 assume !(0 == ~T5_E~0); 328438#L891-1 assume !(0 == ~T6_E~0); 328439#L896-1 assume !(0 == ~T7_E~0); 328693#L901-1 assume !(0 == ~T8_E~0); 328722#L906-1 assume !(0 == ~E_M~0); 328723#L911-1 assume !(0 == ~E_1~0); 328482#L916-1 assume !(0 == ~E_2~0); 328483#L921-1 assume !(0 == ~E_3~0); 328861#L926-1 assume !(0 == ~E_4~0); 329035#L931-1 assume !(0 == ~E_5~0); 329139#L936-1 assume !(0 == ~E_6~0); 329166#L941-1 assume !(0 == ~E_7~0); 328490#L946-1 assume !(0 == ~E_8~0); 328491#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 329078#L430 assume !(1 == ~m_pc~0); 328985#L430-2 is_master_triggered_~__retres1~0#1 := 0; 327952#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 327953#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 328607#L1073 assume !(0 != activate_threads_~tmp~1#1); 328619#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 328838#L449 assume !(1 == ~t1_pc~0); 328138#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 328139#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 327909#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 327910#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 328740#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 328552#L468 assume !(1 == ~t2_pc~0); 327936#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 327935#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 328446#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 328348#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 327954#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 327955#L487 assume !(1 == ~t3_pc~0); 328073#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 328049#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 328050#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 328823#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 328414#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 328415#L506 assume !(1 == ~t4_pc~0); 328546#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 328599#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 329056#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 329057#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 328544#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 328357#L525 assume !(1 == ~t5_pc~0); 327993#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 327994#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 328493#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 328494#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 328196#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 328197#L544 assume !(1 == ~t6_pc~0); 328358#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 328359#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 328766#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 327976#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 327977#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 329001#L563 assume !(1 == ~t7_pc~0); 328762#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 328004#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 328005#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 328445#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 328142#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 328143#L582 assume 1 == ~t8_pc~0; 328060#L583 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 328061#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 329111#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 328403#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 328293#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 328294#L964 assume !(1 == ~M_E~0); 328843#L964-2 assume !(1 == ~T1_E~0); 328198#L969-1 assume !(1 == ~T2_E~0); 328199#L974-1 assume !(1 == ~T3_E~0); 328879#L979-1 assume !(1 == ~T4_E~0); 328880#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 344800#L989-1 assume !(1 == ~T6_E~0); 328698#L994-1 assume !(1 == ~T7_E~0); 328699#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 328847#L1004-1 assume !(1 == ~E_M~0); 328848#L1009-1 assume !(1 == ~E_1~0); 328234#L1014-1 assume !(1 == ~E_2~0); 328235#L1019-1 assume !(1 == ~E_3~0); 329088#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 329089#L1029-1 assume !(1 == ~E_5~0); 345354#L1034-1 assume !(1 == ~E_6~0); 345353#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 345352#L1044-1 assume !(1 == ~E_8~0); 345350#L1049-1 assume { :end_inline_reset_delta_events } true; 345351#L1315-2 [2021-12-06 18:37:59,897 INFO L793 eck$LassoCheckResult]: Loop: 345351#L1315-2 assume !false; 398800#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 398799#L841 assume !false; 398798#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 337138#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 337132#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 337130#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 337115#L724 assume !(0 != eval_~tmp~0#1); 337117#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 399156#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 399155#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 399154#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 399153#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 399152#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 399151#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 399150#L886-3 assume !(0 == ~T5_E~0); 399149#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 399148#L896-3 assume !(0 == ~T7_E~0); 399147#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 399146#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 399145#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 399144#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 399143#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 399142#L926-3 assume !(0 == ~E_4~0); 399141#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 399140#L936-3 assume !(0 == ~E_6~0); 399139#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 399138#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 399137#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 399136#L430-30 assume !(1 == ~m_pc~0); 399135#L430-32 is_master_triggered_~__retres1~0#1 := 0; 399134#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 399133#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 399132#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 399131#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 399130#L449-30 assume !(1 == ~t1_pc~0); 399129#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 399128#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 399127#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 399126#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 399125#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 399124#L468-30 assume 1 == ~t2_pc~0; 399122#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 399121#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 399120#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 399119#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 399118#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 399117#L487-30 assume !(1 == ~t3_pc~0); 399116#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 399115#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 399114#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 399113#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 399112#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 399111#L506-30 assume !(1 == ~t4_pc~0); 399110#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 399108#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 399107#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 399106#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 399105#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 399104#L525-30 assume !(1 == ~t5_pc~0); 399103#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 399102#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 399101#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 399100#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 399099#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 399098#L544-30 assume 1 == ~t6_pc~0; 399096#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 399095#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 399094#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 399093#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 399092#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 399091#L563-30 assume !(1 == ~t7_pc~0); 399090#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 399089#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 399088#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 399087#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 399086#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 399085#L582-30 assume 1 == ~t8_pc~0; 399084#L583-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 399082#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 399081#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 399080#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 399079#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 399078#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 393491#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 399075#L969-3 assume !(1 == ~T2_E~0); 399074#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 399073#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 399072#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 393988#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 399071#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 399070#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 399069#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 399068#L1009-3 assume !(1 == ~E_1~0); 399067#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 399066#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 399065#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 399062#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 399061#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 399060#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 399059#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 399058#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 399033#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 399030#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 399029#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 399028#L1334 assume !(0 == start_simulation_~tmp~3#1); 399026#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 399024#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 399016#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 399015#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 399014#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 399013#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 399012#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 399011#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 345351#L1315-2 [2021-12-06 18:37:59,898 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:37:59,898 INFO L85 PathProgramCache]: Analyzing trace with hash -952811832, now seen corresponding path program 1 times [2021-12-06 18:37:59,898 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:37:59,898 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1369599412] [2021-12-06 18:37:59,898 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:37:59,898 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:37:59,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:37:59,932 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:37:59,933 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:37:59,933 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1369599412] [2021-12-06 18:37:59,933 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1369599412] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:37:59,933 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:37:59,933 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 18:37:59,933 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1105877293] [2021-12-06 18:37:59,934 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:37:59,934 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 18:37:59,934 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:37:59,934 INFO L85 PathProgramCache]: Analyzing trace with hash -177292679, now seen corresponding path program 1 times [2021-12-06 18:37:59,934 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:37:59,935 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1277681137] [2021-12-06 18:37:59,935 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:37:59,935 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:37:59,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:37:59,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:37:59,966 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:37:59,966 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1277681137] [2021-12-06 18:37:59,966 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1277681137] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:37:59,966 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:37:59,967 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:37:59,967 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1160540319] [2021-12-06 18:37:59,967 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:37:59,967 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 18:37:59,967 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:37:59,968 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 18:37:59,968 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 18:37:59,968 INFO L87 Difference]: Start difference. First operand 123869 states and 175796 transitions. cyclomatic complexity: 51991 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:38:00,881 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:38:00,882 INFO L93 Difference]: Finished difference Result 232565 states and 329282 transitions. [2021-12-06 18:38:00,882 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 18:38:00,883 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 232565 states and 329282 transitions. [2021-12-06 18:38:01,796 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 230996 [2021-12-06 18:38:02,207 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 232565 states to 232565 states and 329282 transitions. [2021-12-06 18:38:02,207 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 232565 [2021-12-06 18:38:02,290 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 232565 [2021-12-06 18:38:02,290 INFO L73 IsDeterministic]: Start isDeterministic. Operand 232565 states and 329282 transitions. [2021-12-06 18:38:02,358 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:38:02,358 INFO L681 BuchiCegarLoop]: Abstraction has 232565 states and 329282 transitions. [2021-12-06 18:38:02,444 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 232565 states and 329282 transitions. [2021-12-06 18:38:04,064 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 232565 to 232133. [2021-12-06 18:38:04,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 232133 states, 232133 states have (on average 1.416644768300931) internal successors, (328850), 232132 states have internal predecessors, (328850), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:38:05,009 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 232133 states to 232133 states and 328850 transitions. [2021-12-06 18:38:05,009 INFO L704 BuchiCegarLoop]: Abstraction has 232133 states and 328850 transitions. [2021-12-06 18:38:05,009 INFO L587 BuchiCegarLoop]: Abstraction has 232133 states and 328850 transitions. [2021-12-06 18:38:05,009 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-06 18:38:05,023 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 232133 states and 328850 transitions. [2021-12-06 18:38:05,443 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 230564 [2021-12-06 18:38:05,444 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:38:05,444 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:38:05,445 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:38:05,445 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:38:05,445 INFO L791 eck$LassoCheckResult]: Stem: 685166#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 685167#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 685077#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 685078#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 684914#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 684915#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 684482#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 684483#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 684563#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 685425#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 684454#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 684455#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 684881#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 684902#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 684569#L866 assume !(0 == ~M_E~0); 684570#L866-2 assume !(0 == ~T1_E~0); 685112#L871-1 assume !(0 == ~T2_E~0); 685113#L876-1 assume !(0 == ~T3_E~0); 685515#L881-1 assume !(0 == ~T4_E~0); 685124#L886-1 assume !(0 == ~T5_E~0); 684870#L891-1 assume !(0 == ~T6_E~0); 684871#L896-1 assume !(0 == ~T7_E~0); 685115#L901-1 assume !(0 == ~T8_E~0); 685139#L906-1 assume !(0 == ~E_M~0); 685140#L911-1 assume !(0 == ~E_1~0); 684912#L916-1 assume !(0 == ~E_2~0); 684913#L921-1 assume !(0 == ~E_3~0); 685263#L926-1 assume !(0 == ~E_4~0); 685441#L931-1 assume !(0 == ~E_5~0); 685533#L936-1 assume !(0 == ~E_6~0); 685551#L941-1 assume !(0 == ~E_7~0); 684919#L946-1 assume !(0 == ~E_8~0); 684920#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 685479#L430 assume !(1 == ~m_pc~0); 685391#L430-2 is_master_triggered_~__retres1~0#1 := 0; 684392#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 684393#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 685029#L1073 assume !(0 != activate_threads_~tmp~1#1); 685042#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 685244#L449 assume !(1 == ~t1_pc~0); 684572#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 684573#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 684350#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 684351#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 685155#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 684978#L468 assume !(1 == ~t2_pc~0); 684376#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 684375#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 684878#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 684782#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 684394#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 684395#L487 assume !(1 == ~t3_pc~0); 684507#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 684486#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 684487#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 685226#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 684846#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 684847#L506 assume !(1 == ~t4_pc~0); 684971#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 685025#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 685458#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 685459#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 684970#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 684792#L525 assume !(1 == ~t5_pc~0); 684431#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 684432#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 684922#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 684923#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 684634#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 684635#L544 assume !(1 == ~t6_pc~0); 684793#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 684794#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 685175#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 684416#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 684417#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 685405#L563 assume !(1 == ~t7_pc~0); 685171#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 684442#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 684443#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 684877#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 684576#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 684577#L582 assume !(1 == ~t8_pc~0); 685178#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 685510#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 685511#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 684836#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 684724#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 684725#L964 assume !(1 == ~M_E~0); 685247#L964-2 assume !(1 == ~T1_E~0); 737258#L969-1 assume !(1 == ~T2_E~0); 737256#L974-1 assume !(1 == ~T3_E~0); 737254#L979-1 assume !(1 == ~T4_E~0); 737251#L984-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 737249#L989-1 assume !(1 == ~T6_E~0); 737247#L994-1 assume !(1 == ~T7_E~0); 737245#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 737243#L1004-1 assume !(1 == ~E_M~0); 737241#L1009-1 assume !(1 == ~E_1~0); 737239#L1014-1 assume !(1 == ~E_2~0); 737237#L1019-1 assume !(1 == ~E_3~0); 737235#L1024-1 assume 1 == ~E_4~0;~E_4~0 := 2; 684594#L1029-1 assume !(1 == ~E_5~0); 684595#L1034-1 assume !(1 == ~E_6~0); 684693#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 685469#L1044-1 assume !(1 == ~E_8~0); 684889#L1049-1 assume { :end_inline_reset_delta_events } true; 684890#L1315-2 [2021-12-06 18:38:05,445 INFO L793 eck$LassoCheckResult]: Loop: 684890#L1315-2 assume !false; 743259#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 743257#L841 assume !false; 743255#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 743241#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 743235#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 743233#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 743231#L724 assume !(0 != eval_~tmp~0#1); 743232#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 743639#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 743637#L866-3 assume 0 == ~M_E~0;~M_E~0 := 1; 743635#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 743633#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 743631#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 743629#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 743627#L886-3 assume !(0 == ~T5_E~0); 743625#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 743622#L896-3 assume !(0 == ~T7_E~0); 743620#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 743618#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 743616#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 743614#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 743612#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 743610#L926-3 assume !(0 == ~E_4~0); 743608#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 743606#L936-3 assume !(0 == ~E_6~0); 743604#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 743602#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 743600#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 743597#L430-30 assume !(1 == ~m_pc~0); 743595#L430-32 is_master_triggered_~__retres1~0#1 := 0; 743593#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 743591#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 743589#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 743587#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 743585#L449-30 assume !(1 == ~t1_pc~0); 743583#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 743581#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 743579#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 743577#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 743575#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 743572#L468-30 assume !(1 == ~t2_pc~0); 743570#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 743567#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 743565#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 743563#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 743561#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 743559#L487-30 assume !(1 == ~t3_pc~0); 743557#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 743555#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 743553#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 743551#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 743549#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 743547#L506-30 assume !(1 == ~t4_pc~0); 743545#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 743542#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 743540#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 743538#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 743536#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 743534#L525-30 assume !(1 == ~t5_pc~0); 743532#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 743530#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 743528#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 743526#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 743524#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 743522#L544-30 assume 1 == ~t6_pc~0; 743519#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 743517#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 743515#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 743513#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 743511#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 743509#L563-30 assume !(1 == ~t7_pc~0); 743507#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 743505#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 743503#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 743501#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 743500#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 743499#L582-30 assume !(1 == ~t8_pc~0); 743498#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 743497#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 743495#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 743493#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 743491#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 743489#L964-3 assume 1 == ~M_E~0;~M_E~0 := 2; 724551#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 743486#L969-3 assume !(1 == ~T2_E~0); 743484#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 743482#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 743480#L984-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 740979#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 743477#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 743475#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 743473#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 743470#L1009-3 assume !(1 == ~E_1~0); 743468#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 743466#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 743464#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 737308#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 743461#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 743459#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 743457#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 743455#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 743438#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 743434#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 743432#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 743430#L1334 assume !(0 == start_simulation_~tmp~3#1); 743427#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 743419#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 743410#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 743408#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 743406#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 743404#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 743402#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 743400#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 684890#L1315-2 [2021-12-06 18:38:05,445 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:38:05,445 INFO L85 PathProgramCache]: Analyzing trace with hash 1284551433, now seen corresponding path program 1 times [2021-12-06 18:38:05,446 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:38:05,446 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1006465186] [2021-12-06 18:38:05,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:38:05,446 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:38:05,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:38:05,481 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:38:05,482 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:38:05,482 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1006465186] [2021-12-06 18:38:05,482 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1006465186] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:38:05,482 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:38:05,482 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:38:05,482 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [576408561] [2021-12-06 18:38:05,483 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:38:05,483 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 18:38:05,483 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:38:05,484 INFO L85 PathProgramCache]: Analyzing trace with hash -1215011973, now seen corresponding path program 1 times [2021-12-06 18:38:05,484 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:38:05,484 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1507812517] [2021-12-06 18:38:05,484 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:38:05,484 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:38:05,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:38:05,516 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:38:05,516 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:38:05,516 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1507812517] [2021-12-06 18:38:05,516 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1507812517] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:38:05,517 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:38:05,517 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:38:05,517 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1556226228] [2021-12-06 18:38:05,517 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:38:05,517 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 18:38:05,518 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:38:05,518 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 18:38:05,518 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 18:38:05,518 INFO L87 Difference]: Start difference. First operand 232133 states and 328850 transitions. cyclomatic complexity: 96845 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:38:06,269 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:38:06,269 INFO L93 Difference]: Finished difference Result 177412 states and 250686 transitions. [2021-12-06 18:38:06,269 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 18:38:06,269 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 177412 states and 250686 transitions. [2021-12-06 18:38:06,758 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 176230 [2021-12-06 18:38:07,289 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 177412 states to 177412 states and 250686 transitions. [2021-12-06 18:38:07,289 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 177412 [2021-12-06 18:38:07,350 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 177412 [2021-12-06 18:38:07,350 INFO L73 IsDeterministic]: Start isDeterministic. Operand 177412 states and 250686 transitions. [2021-12-06 18:38:07,400 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:38:07,401 INFO L681 BuchiCegarLoop]: Abstraction has 177412 states and 250686 transitions. [2021-12-06 18:38:07,462 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 177412 states and 250686 transitions. [2021-12-06 18:38:08,442 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 177412 to 122717. [2021-12-06 18:38:08,513 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 122717 states, 122717 states have (on average 1.4133249672009582) internal successors, (173439), 122716 states have internal predecessors, (173439), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:38:08,743 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122717 states to 122717 states and 173439 transitions. [2021-12-06 18:38:08,743 INFO L704 BuchiCegarLoop]: Abstraction has 122717 states and 173439 transitions. [2021-12-06 18:38:08,743 INFO L587 BuchiCegarLoop]: Abstraction has 122717 states and 173439 transitions. [2021-12-06 18:38:08,743 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-06 18:38:08,743 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 122717 states and 173439 transitions. [2021-12-06 18:38:09,056 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 121896 [2021-12-06 18:38:09,056 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:38:09,056 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:38:09,058 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:38:09,058 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:38:09,058 INFO L791 eck$LassoCheckResult]: Stem: 1094710#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1094711#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1094625#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1094626#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1094462#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 1094463#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1094039#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1094040#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1094119#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1094939#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1094010#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1094011#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1094430#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1094451#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1094125#L866 assume !(0 == ~M_E~0); 1094126#L866-2 assume !(0 == ~T1_E~0); 1094658#L871-1 assume !(0 == ~T2_E~0); 1094659#L876-1 assume !(0 == ~T3_E~0); 1095026#L881-1 assume !(0 == ~T4_E~0); 1094670#L886-1 assume !(0 == ~T5_E~0); 1094419#L891-1 assume !(0 == ~T6_E~0); 1094420#L896-1 assume !(0 == ~T7_E~0); 1094661#L901-1 assume !(0 == ~T8_E~0); 1094683#L906-1 assume !(0 == ~E_M~0); 1094684#L911-1 assume !(0 == ~E_1~0); 1094460#L916-1 assume !(0 == ~E_2~0); 1094461#L921-1 assume !(0 == ~E_3~0); 1094802#L926-1 assume !(0 == ~E_4~0); 1094956#L931-1 assume !(0 == ~E_5~0); 1095039#L936-1 assume !(0 == ~E_6~0); 1095052#L941-1 assume !(0 == ~E_7~0); 1094466#L946-1 assume !(0 == ~E_8~0); 1094467#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1094996#L430 assume !(1 == ~m_pc~0); 1094909#L430-2 is_master_triggered_~__retres1~0#1 := 0; 1093947#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1093948#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1094580#L1073 assume !(0 != activate_threads_~tmp~1#1); 1094591#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1094785#L449 assume !(1 == ~t1_pc~0); 1094128#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1094129#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1093905#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1093906#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 1094698#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1094528#L468 assume !(1 == ~t2_pc~0); 1093931#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1093930#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1094427#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1094334#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 1093949#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1093950#L487 assume !(1 == ~t3_pc~0); 1094064#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1094043#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1094044#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1094769#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 1094395#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1094396#L506 assume !(1 == ~t4_pc~0); 1094522#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1094575#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1094976#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1094977#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 1094520#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1094343#L525 assume !(1 == ~t5_pc~0); 1093987#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1093988#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1094470#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1094471#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 1094186#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1094187#L544 assume !(1 == ~t6_pc~0); 1094344#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1094345#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1094719#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1093971#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 1093972#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1094923#L563 assume !(1 == ~t7_pc~0); 1094716#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1093998#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1093999#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1094426#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 1094132#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1094133#L582 assume !(1 == ~t8_pc~0); 1094720#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1095020#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1095021#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1094384#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 1094276#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1094277#L964 assume !(1 == ~M_E~0); 1094787#L964-2 assume !(1 == ~T1_E~0); 1094188#L969-1 assume !(1 == ~T2_E~0); 1094189#L974-1 assume !(1 == ~T3_E~0); 1094821#L979-1 assume !(1 == ~T4_E~0); 1094822#L984-1 assume !(1 == ~T5_E~0); 1094350#L989-1 assume !(1 == ~T6_E~0); 1094351#L994-1 assume !(1 == ~T7_E~0); 1094233#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1094234#L1004-1 assume !(1 == ~E_M~0); 1093973#L1009-1 assume !(1 == ~E_1~0); 1093974#L1014-1 assume !(1 == ~E_2~0); 1094220#L1019-1 assume !(1 == ~E_3~0); 1094775#L1024-1 assume !(1 == ~E_4~0); 1094150#L1029-1 assume !(1 == ~E_5~0); 1094151#L1034-1 assume !(1 == ~E_6~0); 1094245#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1094986#L1044-1 assume !(1 == ~E_8~0); 1094438#L1049-1 assume { :end_inline_reset_delta_events } true; 1094117#L1315-2 [2021-12-06 18:38:09,059 INFO L793 eck$LassoCheckResult]: Loop: 1094117#L1315-2 assume !false; 1094118#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1095048#L841 assume !false; 1209931#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1133693#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1133688#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1133687#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1133685#L724 assume !(0 != eval_~tmp~0#1); 1133684#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1133683#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1133682#L866-3 assume !(0 == ~M_E~0); 1133672#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1133670#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1133668#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1133665#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1133662#L886-3 assume !(0 == ~T5_E~0); 1133658#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1133653#L896-3 assume !(0 == ~T7_E~0); 1133651#L901-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1133648#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1133647#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1133646#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1133645#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1133644#L926-3 assume !(0 == ~E_4~0); 1133643#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1133642#L936-3 assume !(0 == ~E_6~0); 1133641#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1133640#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1133639#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1133638#L430-30 assume !(1 == ~m_pc~0); 1133636#L430-32 is_master_triggered_~__retres1~0#1 := 0; 1133634#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1133632#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1133630#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 1133628#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1133626#L449-30 assume !(1 == ~t1_pc~0); 1133624#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1133622#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1133620#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1133618#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1133616#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1133614#L468-30 assume 1 == ~t2_pc~0; 1133611#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1133609#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1133607#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1133604#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1133602#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1133600#L487-30 assume !(1 == ~t3_pc~0); 1133598#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1133596#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1133594#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1133591#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1133589#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1133587#L506-30 assume !(1 == ~t4_pc~0); 1133585#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1133582#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1133580#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1133577#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 1133575#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1133573#L525-30 assume !(1 == ~t5_pc~0); 1133571#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1133569#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1133567#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1133564#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1133562#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1133560#L544-30 assume 1 == ~t6_pc~0; 1133557#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1133555#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1133553#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1133550#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1133548#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1133546#L563-30 assume !(1 == ~t7_pc~0); 1133544#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1133542#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1133540#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1133538#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1133536#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1133534#L582-30 assume !(1 == ~t8_pc~0); 1133532#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1133530#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1133528#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1133526#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1133524#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1133522#L964-3 assume !(1 == ~M_E~0); 1133520#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1133518#L969-3 assume !(1 == ~T2_E~0); 1133517#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1133516#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1133513#L984-3 assume !(1 == ~T5_E~0); 1133511#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1133509#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1133508#L999-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1133507#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1133506#L1009-3 assume !(1 == ~E_1~0); 1133505#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1133504#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1133503#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1133502#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1133501#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1133500#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1133499#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1133498#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1133490#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1133486#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1133484#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1133101#L1334 assume !(0 == start_simulation_~tmp~3#1); 1133102#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1212520#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1212513#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1214559#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1214557#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1212502#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1212500#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1212498#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 1094117#L1315-2 [2021-12-06 18:38:09,059 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:38:09,059 INFO L85 PathProgramCache]: Analyzing trace with hash 330692485, now seen corresponding path program 1 times [2021-12-06 18:38:09,059 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:38:09,060 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1827813422] [2021-12-06 18:38:09,060 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:38:09,060 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:38:09,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:38:09,346 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:38:09,347 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:38:09,347 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1827813422] [2021-12-06 18:38:09,347 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1827813422] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:38:09,347 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:38:09,347 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:38:09,347 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1118232836] [2021-12-06 18:38:09,347 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:38:09,348 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 18:38:09,348 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:38:09,348 INFO L85 PathProgramCache]: Analyzing trace with hash -1194066504, now seen corresponding path program 1 times [2021-12-06 18:38:09,348 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:38:09,348 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1715558105] [2021-12-06 18:38:09,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:38:09,348 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:38:09,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:38:09,393 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:38:09,393 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:38:09,393 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1715558105] [2021-12-06 18:38:09,393 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1715558105] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:38:09,393 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:38:09,394 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:38:09,394 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [187771182] [2021-12-06 18:38:09,394 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:38:09,394 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 18:38:09,394 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:38:09,395 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 18:38:09,395 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 18:38:09,395 INFO L87 Difference]: Start difference. First operand 122717 states and 173439 transitions. cyclomatic complexity: 50786 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:38:09,943 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:38:09,943 INFO L93 Difference]: Finished difference Result 196881 states and 277928 transitions. [2021-12-06 18:38:09,943 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 18:38:09,944 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 196881 states and 277928 transitions. [2021-12-06 18:38:10,821 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 195618 [2021-12-06 18:38:11,173 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 196881 states to 196881 states and 277928 transitions. [2021-12-06 18:38:11,173 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 196881 [2021-12-06 18:38:11,249 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 196881 [2021-12-06 18:38:11,249 INFO L73 IsDeterministic]: Start isDeterministic. Operand 196881 states and 277928 transitions. [2021-12-06 18:38:11,310 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:38:11,310 INFO L681 BuchiCegarLoop]: Abstraction has 196881 states and 277928 transitions. [2021-12-06 18:38:11,382 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 196881 states and 277928 transitions. [2021-12-06 18:38:12,364 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 196881 to 139897. [2021-12-06 18:38:12,441 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 139897 states, 139897 states have (on average 1.4135471096592493) internal successors, (197751), 139896 states have internal predecessors, (197751), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:38:12,893 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139897 states to 139897 states and 197751 transitions. [2021-12-06 18:38:12,893 INFO L704 BuchiCegarLoop]: Abstraction has 139897 states and 197751 transitions. [2021-12-06 18:38:12,893 INFO L587 BuchiCegarLoop]: Abstraction has 139897 states and 197751 transitions. [2021-12-06 18:38:12,893 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-06 18:38:12,894 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 139897 states and 197751 transitions. [2021-12-06 18:38:13,220 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 139000 [2021-12-06 18:38:13,220 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:38:13,221 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:38:13,222 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:38:13,222 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:38:13,222 INFO L791 eck$LassoCheckResult]: Stem: 1414348#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1414349#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1414252#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1414253#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1414077#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 1414078#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1413647#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1413648#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1413728#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1414580#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1413619#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1413620#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1414041#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1414066#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1413734#L866 assume !(0 == ~M_E~0); 1413735#L866-2 assume !(0 == ~T1_E~0); 1414287#L871-1 assume !(0 == ~T2_E~0); 1414288#L876-1 assume !(0 == ~T3_E~0); 1414674#L881-1 assume !(0 == ~T4_E~0); 1414301#L886-1 assume !(0 == ~T5_E~0); 1414030#L891-1 assume !(0 == ~T6_E~0); 1414031#L896-1 assume !(0 == ~T7_E~0); 1414290#L901-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1414318#L906-1 assume !(0 == ~E_M~0); 1414319#L911-1 assume !(0 == ~E_1~0); 1414075#L916-1 assume !(0 == ~E_2~0); 1414076#L921-1 assume !(0 == ~E_3~0); 1414597#L926-1 assume !(0 == ~E_4~0); 1414598#L931-1 assume !(0 == ~E_5~0); 1414703#L936-1 assume !(0 == ~E_6~0); 1414704#L941-1 assume !(0 == ~E_7~0); 1414081#L946-1 assume !(0 == ~E_8~0); 1414082#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1414707#L430 assume !(1 == ~m_pc~0); 1414708#L430-2 is_master_triggered_~__retres1~0#1 := 0; 1413554#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1413555#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1414217#L1073 assume !(0 != activate_threads_~tmp~1#1); 1414218#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1414426#L449 assume !(1 == ~t1_pc~0); 1414427#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1414658#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1414659#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1414710#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 1414711#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1414145#L468 assume !(1 == ~t2_pc~0); 1414146#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1414264#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1414265#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1413940#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 1413941#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1414705#L487 assume !(1 == ~t3_pc~0); 1414706#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1413651#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1413652#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1414504#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 1414005#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1414006#L506 assume !(1 == ~t4_pc~0); 1414200#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1414201#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1414614#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1414615#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 1414132#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1414133#L525 assume !(1 == ~t5_pc~0); 1413596#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1413597#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1414085#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1414086#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 1413797#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1413798#L544 assume !(1 == ~t6_pc~0); 1413954#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1413955#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1414356#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1414746#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 1414643#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1414644#L563 assume !(1 == ~t7_pc~0); 1414352#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1414353#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1414182#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1414183#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 1413739#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1413740#L582 assume !(1 == ~t8_pc~0); 1414357#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1414666#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1414667#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1413991#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 1413992#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1414429#L964 assume !(1 == ~M_E~0); 1414430#L964-2 assume !(1 == ~T1_E~0); 1413799#L969-1 assume !(1 == ~T2_E~0); 1413800#L974-1 assume !(1 == ~T3_E~0); 1414466#L979-1 assume !(1 == ~T4_E~0); 1414467#L984-1 assume !(1 == ~T5_E~0); 1414751#L989-1 assume !(1 == ~T6_E~0); 1414750#L994-1 assume !(1 == ~T7_E~0); 1414749#L999-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1413843#L1004-1 assume !(1 == ~E_M~0); 1413582#L1009-1 assume !(1 == ~E_1~0); 1413583#L1014-1 assume !(1 == ~E_2~0); 1413831#L1019-1 assume !(1 == ~E_3~0); 1414414#L1024-1 assume !(1 == ~E_4~0); 1413758#L1029-1 assume !(1 == ~E_5~0); 1413759#L1034-1 assume !(1 == ~E_6~0); 1413859#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1414624#L1044-1 assume !(1 == ~E_8~0); 1414049#L1049-1 assume { :end_inline_reset_delta_events } true; 1414050#L1315-2 [2021-12-06 18:38:13,222 INFO L793 eck$LassoCheckResult]: Loop: 1414050#L1315-2 assume !false; 1502610#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1502608#L841 assume !false; 1502606#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1502592#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1502586#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1502584#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1502582#L724 assume !(0 != eval_~tmp~0#1); 1502583#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1502940#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1502937#L866-3 assume !(0 == ~M_E~0); 1502935#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1502933#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1502931#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1502929#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1502927#L886-3 assume !(0 == ~T5_E~0); 1502925#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1502923#L896-3 assume !(0 == ~T7_E~0); 1502920#L901-3 assume !(0 == ~T8_E~0); 1502918#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1502916#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1502914#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1502912#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1502910#L926-3 assume !(0 == ~E_4~0); 1502908#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1502906#L936-3 assume !(0 == ~E_6~0); 1502904#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1502902#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1502900#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1502898#L430-30 assume !(1 == ~m_pc~0); 1502896#L430-32 is_master_triggered_~__retres1~0#1 := 0; 1502894#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1502892#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1502890#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 1502888#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1502887#L449-30 assume !(1 == ~t1_pc~0); 1502886#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1502885#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1502884#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1502883#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1502882#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1502881#L468-30 assume !(1 == ~t2_pc~0); 1502880#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1502878#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1502877#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1502875#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1502873#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1502871#L487-30 assume !(1 == ~t3_pc~0); 1502869#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1502867#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1502865#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1502862#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1502859#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1502857#L506-30 assume 1 == ~t4_pc~0; 1502854#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1502852#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1502850#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1502848#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 1502845#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1502843#L525-30 assume !(1 == ~t5_pc~0); 1502841#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1502839#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1502837#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1502835#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1502832#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1502830#L544-30 assume !(1 == ~t6_pc~0); 1502828#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1502825#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1502823#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1502821#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1502818#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1502816#L563-30 assume !(1 == ~t7_pc~0); 1502814#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1502812#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1502810#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1502808#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1502806#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1502804#L582-30 assume !(1 == ~t8_pc~0); 1502802#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1502800#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1502798#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1502796#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1502793#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1502791#L964-3 assume !(1 == ~M_E~0); 1502789#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1502787#L969-3 assume !(1 == ~T2_E~0); 1502785#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1502783#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1502781#L984-3 assume !(1 == ~T5_E~0); 1502779#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1502777#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1502775#L999-3 assume !(1 == ~T8_E~0); 1502772#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1502770#L1009-3 assume !(1 == ~E_1~0); 1502768#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1502766#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1502764#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1502762#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1502760#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1502759#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1502758#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1502757#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1502750#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1502747#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1502746#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1502745#L1334 assume !(0 == start_simulation_~tmp~3#1); 1502744#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1502740#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1502731#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1502729#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1502727#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1502725#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1502723#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1502721#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 1414050#L1315-2 [2021-12-06 18:38:13,223 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:38:13,223 INFO L85 PathProgramCache]: Analyzing trace with hash -2085143865, now seen corresponding path program 1 times [2021-12-06 18:38:13,223 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:38:13,223 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [601519693] [2021-12-06 18:38:13,223 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:38:13,223 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:38:13,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:38:13,248 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:38:13,248 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:38:13,248 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [601519693] [2021-12-06 18:38:13,248 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [601519693] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:38:13,248 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:38:13,248 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:38:13,249 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [73612930] [2021-12-06 18:38:13,249 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:38:13,249 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 18:38:13,249 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:38:13,250 INFO L85 PathProgramCache]: Analyzing trace with hash -1484576839, now seen corresponding path program 1 times [2021-12-06 18:38:13,250 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:38:13,250 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1963263351] [2021-12-06 18:38:13,250 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:38:13,250 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:38:13,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:38:13,273 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:38:13,273 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:38:13,273 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1963263351] [2021-12-06 18:38:13,273 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1963263351] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:38:13,273 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:38:13,273 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:38:13,273 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1980085308] [2021-12-06 18:38:13,274 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:38:13,274 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 18:38:13,274 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:38:13,275 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 18:38:13,275 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 18:38:13,275 INFO L87 Difference]: Start difference. First operand 139897 states and 197751 transitions. cyclomatic complexity: 57918 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:38:13,648 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:38:13,648 INFO L93 Difference]: Finished difference Result 122717 states and 172897 transitions. [2021-12-06 18:38:13,649 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 18:38:13,649 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 122717 states and 172897 transitions. [2021-12-06 18:38:14,084 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 121896 [2021-12-06 18:38:14,610 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 122717 states to 122717 states and 172897 transitions. [2021-12-06 18:38:14,610 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 122717 [2021-12-06 18:38:14,660 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 122717 [2021-12-06 18:38:14,660 INFO L73 IsDeterministic]: Start isDeterministic. Operand 122717 states and 172897 transitions. [2021-12-06 18:38:14,700 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:38:14,700 INFO L681 BuchiCegarLoop]: Abstraction has 122717 states and 172897 transitions. [2021-12-06 18:38:14,750 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122717 states and 172897 transitions. [2021-12-06 18:38:15,591 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122717 to 122717. [2021-12-06 18:38:15,643 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 122717 states, 122717 states have (on average 1.4089083012133607) internal successors, (172897), 122716 states have internal predecessors, (172897), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:38:15,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122717 states to 122717 states and 172897 transitions. [2021-12-06 18:38:15,841 INFO L704 BuchiCegarLoop]: Abstraction has 122717 states and 172897 transitions. [2021-12-06 18:38:15,842 INFO L587 BuchiCegarLoop]: Abstraction has 122717 states and 172897 transitions. [2021-12-06 18:38:15,842 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-06 18:38:15,842 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 122717 states and 172897 transitions. [2021-12-06 18:38:16,100 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 121896 [2021-12-06 18:38:16,100 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:38:16,100 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:38:16,101 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:38:16,101 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:38:16,101 INFO L791 eck$LassoCheckResult]: Stem: 1676943#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1676944#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1676859#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1676860#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1676692#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 1676693#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1676270#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1676271#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1676349#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1677178#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1676242#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1676243#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1676659#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1676681#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1676355#L866 assume !(0 == ~M_E~0); 1676356#L866-2 assume !(0 == ~T1_E~0); 1676891#L871-1 assume !(0 == ~T2_E~0); 1676892#L876-1 assume !(0 == ~T3_E~0); 1677258#L881-1 assume !(0 == ~T4_E~0); 1676901#L886-1 assume !(0 == ~T5_E~0); 1676648#L891-1 assume !(0 == ~T6_E~0); 1676649#L896-1 assume !(0 == ~T7_E~0); 1676894#L901-1 assume !(0 == ~T8_E~0); 1676917#L906-1 assume !(0 == ~E_M~0); 1676918#L911-1 assume !(0 == ~E_1~0); 1676690#L916-1 assume !(0 == ~E_2~0); 1676691#L921-1 assume !(0 == ~E_3~0); 1677039#L926-1 assume !(0 == ~E_4~0); 1677197#L931-1 assume !(0 == ~E_5~0); 1677271#L936-1 assume !(0 == ~E_6~0); 1677285#L941-1 assume !(0 == ~E_7~0); 1676697#L946-1 assume !(0 == ~E_8~0); 1676698#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1677233#L430 assume !(1 == ~m_pc~0); 1677149#L430-2 is_master_triggered_~__retres1~0#1 := 0; 1676182#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1676183#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1676810#L1073 assume !(0 != activate_threads_~tmp~1#1); 1676821#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1677020#L449 assume !(1 == ~t1_pc~0); 1676358#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1676359#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1676137#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1676138#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 1676933#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1676761#L468 assume !(1 == ~t2_pc~0); 1676164#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1676163#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1676656#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1676565#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 1676180#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1676181#L487 assume !(1 == ~t3_pc~0); 1676295#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1676274#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1676275#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1677003#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 1676623#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1676624#L506 assume !(1 == ~t4_pc~0); 1676754#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1676807#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1677213#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1677214#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 1676752#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1676574#L525 assume !(1 == ~t5_pc~0); 1676219#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1676220#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1676701#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1676702#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 1676417#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1676418#L544 assume !(1 == ~t6_pc~0); 1676575#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1676576#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1676951#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1676204#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 1676205#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1677163#L563 assume !(1 == ~t7_pc~0); 1676948#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1676230#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1676231#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1676655#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 1676362#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1676363#L582 assume !(1 == ~t8_pc~0); 1676954#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1677251#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1677252#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1676613#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 1676512#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1676513#L964 assume !(1 == ~M_E~0); 1677023#L964-2 assume !(1 == ~T1_E~0); 1676419#L969-1 assume !(1 == ~T2_E~0); 1676420#L974-1 assume !(1 == ~T3_E~0); 1677059#L979-1 assume !(1 == ~T4_E~0); 1677060#L984-1 assume !(1 == ~T5_E~0); 1676581#L989-1 assume !(1 == ~T6_E~0); 1676582#L994-1 assume !(1 == ~T7_E~0); 1676465#L999-1 assume !(1 == ~T8_E~0); 1676466#L1004-1 assume !(1 == ~E_M~0); 1676206#L1009-1 assume !(1 == ~E_1~0); 1676207#L1014-1 assume !(1 == ~E_2~0); 1676454#L1019-1 assume !(1 == ~E_3~0); 1677007#L1024-1 assume !(1 == ~E_4~0); 1676380#L1029-1 assume !(1 == ~E_5~0); 1676381#L1034-1 assume !(1 == ~E_6~0); 1676478#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1677222#L1044-1 assume !(1 == ~E_8~0); 1676667#L1049-1 assume { :end_inline_reset_delta_events } true; 1676668#L1315-2 [2021-12-06 18:38:16,101 INFO L793 eck$LassoCheckResult]: Loop: 1676668#L1315-2 assume !false; 1731264#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1731262#L841 assume !false; 1731259#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1731248#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1731242#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1731240#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1731237#L724 assume !(0 != eval_~tmp~0#1); 1731238#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1731659#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1731657#L866-3 assume !(0 == ~M_E~0); 1731655#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1731653#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1731651#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1731649#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1731646#L886-3 assume !(0 == ~T5_E~0); 1731644#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1731642#L896-3 assume !(0 == ~T7_E~0); 1731640#L901-3 assume !(0 == ~T8_E~0); 1731638#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1731636#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1731635#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1731633#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1731631#L926-3 assume !(0 == ~E_4~0); 1731629#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1731627#L936-3 assume !(0 == ~E_6~0); 1731625#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1731622#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1731620#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1731618#L430-30 assume !(1 == ~m_pc~0); 1731616#L430-32 is_master_triggered_~__retres1~0#1 := 0; 1731614#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1731612#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1731610#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 1731608#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1731606#L449-30 assume !(1 == ~t1_pc~0); 1731604#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1731602#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1731600#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1731597#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1731595#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1731593#L468-30 assume 1 == ~t2_pc~0; 1731590#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1731588#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1731585#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1731584#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1731581#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1731579#L487-30 assume !(1 == ~t3_pc~0); 1731577#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1731575#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1731573#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1731571#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1731568#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1731566#L506-30 assume 1 == ~t4_pc~0; 1731563#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1731561#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1731559#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1731558#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 1731557#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1731556#L525-30 assume !(1 == ~t5_pc~0); 1731555#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1731554#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1731553#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1731552#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1731551#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1731550#L544-30 assume 1 == ~t6_pc~0; 1731548#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1731547#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1731546#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1731545#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1731544#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1731543#L563-30 assume !(1 == ~t7_pc~0); 1731542#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1731541#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1731539#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1731537#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1731535#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1731533#L582-30 assume !(1 == ~t8_pc~0); 1731531#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1731529#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1731527#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1731525#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1731523#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1731521#L964-3 assume !(1 == ~M_E~0); 1731519#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1731517#L969-3 assume !(1 == ~T2_E~0); 1731515#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1731512#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1731510#L984-3 assume !(1 == ~T5_E~0); 1731508#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1731506#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1731504#L999-3 assume !(1 == ~T8_E~0); 1731502#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1731500#L1009-3 assume !(1 == ~E_1~0); 1731498#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1731496#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1731494#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1731492#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1731490#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1731487#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1731485#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1731483#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1731468#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1731464#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1731461#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1731458#L1334 assume !(0 == start_simulation_~tmp~3#1); 1731456#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1731450#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1731441#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1731439#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1731437#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1731435#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1731433#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1731431#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 1676668#L1315-2 [2021-12-06 18:38:16,102 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:38:16,102 INFO L85 PathProgramCache]: Analyzing trace with hash 1031757063, now seen corresponding path program 1 times [2021-12-06 18:38:16,102 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:38:16,102 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [427845632] [2021-12-06 18:38:16,102 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:38:16,102 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:38:16,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:38:16,130 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:38:16,130 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:38:16,130 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [427845632] [2021-12-06 18:38:16,130 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [427845632] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:38:16,130 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:38:16,131 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:38:16,131 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1146012259] [2021-12-06 18:38:16,131 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:38:16,131 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 18:38:16,131 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:38:16,131 INFO L85 PathProgramCache]: Analyzing trace with hash -789800905, now seen corresponding path program 1 times [2021-12-06 18:38:16,131 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:38:16,131 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1753878142] [2021-12-06 18:38:16,132 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:38:16,132 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:38:16,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:38:16,152 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:38:16,152 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:38:16,152 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1753878142] [2021-12-06 18:38:16,152 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1753878142] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:38:16,152 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:38:16,152 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:38:16,153 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1940497900] [2021-12-06 18:38:16,153 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:38:16,153 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 18:38:16,153 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:38:16,153 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 18:38:16,153 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 18:38:16,153 INFO L87 Difference]: Start difference. First operand 122717 states and 172897 transitions. cyclomatic complexity: 50244 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:38:16,956 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:38:16,956 INFO L93 Difference]: Finished difference Result 191021 states and 268782 transitions. [2021-12-06 18:38:16,956 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 18:38:16,956 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 191021 states and 268782 transitions. [2021-12-06 18:38:17,445 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 189658 [2021-12-06 18:38:17,750 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 191021 states to 191021 states and 268782 transitions. [2021-12-06 18:38:17,751 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 191021 [2021-12-06 18:38:17,815 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 191021 [2021-12-06 18:38:17,815 INFO L73 IsDeterministic]: Start isDeterministic. Operand 191021 states and 268782 transitions. [2021-12-06 18:38:17,869 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:38:17,869 INFO L681 BuchiCegarLoop]: Abstraction has 191021 states and 268782 transitions. [2021-12-06 18:38:17,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 191021 states and 268782 transitions. [2021-12-06 18:38:19,239 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 191021 to 139825. [2021-12-06 18:38:19,317 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 139825 states, 139825 states have (on average 1.4064795279814053) internal successors, (196661), 139824 states have internal predecessors, (196661), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:38:19,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139825 states to 139825 states and 196661 transitions. [2021-12-06 18:38:19,803 INFO L704 BuchiCegarLoop]: Abstraction has 139825 states and 196661 transitions. [2021-12-06 18:38:19,803 INFO L587 BuchiCegarLoop]: Abstraction has 139825 states and 196661 transitions. [2021-12-06 18:38:19,804 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-06 18:38:19,804 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 139825 states and 196661 transitions. [2021-12-06 18:38:20,077 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 138928 [2021-12-06 18:38:20,077 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:38:20,077 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:38:20,078 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:38:20,078 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:38:20,078 INFO L791 eck$LassoCheckResult]: Stem: 1990711#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 1990712#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1990620#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1990621#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1990443#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 1990444#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1990017#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1990018#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1990098#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1990955#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1989989#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1989990#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1990411#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1990432#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1990104#L866 assume !(0 == ~M_E~0); 1990105#L866-2 assume !(0 == ~T1_E~0); 1990655#L871-1 assume !(0 == ~T2_E~0); 1990656#L876-1 assume !(0 == ~T3_E~0); 1991048#L881-1 assume !(0 == ~T4_E~0); 1990668#L886-1 assume !(0 == ~T5_E~0); 1990398#L891-1 assume !(0 == ~T6_E~0); 1990399#L896-1 assume !(0 == ~T7_E~0); 1990658#L901-1 assume !(0 == ~T8_E~0); 1990683#L906-1 assume !(0 == ~E_M~0); 1990684#L911-1 assume !(0 == ~E_1~0); 1990441#L916-1 assume !(0 == ~E_2~0); 1990442#L921-1 assume !(0 == ~E_3~0); 1990812#L926-1 assume !(0 == ~E_4~0); 1990972#L931-1 assume !(0 == ~E_5~0); 1991061#L936-1 assume !(0 == ~E_6~0); 1991074#L941-1 assume 0 == ~E_7~0;~E_7~0 := 1; 1991124#L946-1 assume !(0 == ~E_8~0); 1991007#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1991008#L430 assume !(1 == ~m_pc~0); 1990921#L430-2 is_master_triggered_~__retres1~0#1 := 0; 1990922#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1990571#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1990572#L1073 assume !(0 != activate_threads_~tmp~1#1); 1991037#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1991038#L449 assume !(1 == ~t1_pc~0); 1990107#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1990108#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1989885#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1989886#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 1990698#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1990699#L468 assume !(1 == ~t2_pc~0); 1989911#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1989910#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1990407#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1990408#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 1989929#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1989930#L487 assume !(1 == ~t3_pc~0); 1990041#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1990042#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1990773#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1990774#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 1990373#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1990374#L506 assume !(1 == ~t4_pc~0); 1990566#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1990567#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1990989#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1990990#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 1990504#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1990505#L525 assume !(1 == ~t5_pc~0); 1989966#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1989967#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1990451#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1990452#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 1990168#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1990169#L544 assume !(1 == ~t6_pc~0); 1990321#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1990322#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1990723#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1991132#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 1991020#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1991021#L563 assume !(1 == ~t7_pc~0); 1991140#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1989977#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1989978#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1990405#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 1990406#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1991139#L582 assume !(1 == ~t8_pc~0); 1991095#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1991096#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1991138#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1991137#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 1990256#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1990257#L964 assume !(1 == ~M_E~0); 1991035#L964-2 assume !(1 == ~T1_E~0); 1991036#L969-1 assume !(1 == ~T2_E~0); 1990982#L974-1 assume !(1 == ~T3_E~0); 1990983#L979-1 assume !(1 == ~T4_E~0); 1991112#L984-1 assume !(1 == ~T5_E~0); 1991113#L989-1 assume !(1 == ~T6_E~0); 1990662#L994-1 assume !(1 == ~T7_E~0); 1990663#L999-1 assume !(1 == ~T8_E~0); 1990800#L1004-1 assume !(1 == ~E_M~0); 1989953#L1009-1 assume !(1 == ~E_1~0); 1989954#L1014-1 assume !(1 == ~E_2~0); 1990779#L1019-1 assume !(1 == ~E_3~0); 1990780#L1024-1 assume !(1 == ~E_4~0); 1990129#L1029-1 assume !(1 == ~E_5~0); 1990130#L1034-1 assume !(1 == ~E_6~0); 1991135#L1039-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1990995#L1044-1 assume !(1 == ~E_8~0); 1990419#L1049-1 assume { :end_inline_reset_delta_events } true; 1990420#L1315-2 [2021-12-06 18:38:20,078 INFO L793 eck$LassoCheckResult]: Loop: 1990420#L1315-2 assume !false; 2056506#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2056505#L841 assume !false; 2056504#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2056498#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2056491#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2056489#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2056486#L724 assume !(0 != eval_~tmp~0#1); 2056484#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2056482#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2056480#L866-3 assume !(0 == ~M_E~0); 2056478#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2056476#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2056474#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2056472#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2056470#L886-3 assume !(0 == ~T5_E~0); 2056468#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2056465#L896-3 assume !(0 == ~T7_E~0); 2056463#L901-3 assume !(0 == ~T8_E~0); 2056461#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2056459#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2056457#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2056455#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2056453#L926-3 assume !(0 == ~E_4~0); 2056451#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2056449#L936-3 assume !(0 == ~E_6~0); 2056446#L941-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2056447#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2063076#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2063074#L430-30 assume !(1 == ~m_pc~0); 2063072#L430-32 is_master_triggered_~__retres1~0#1 := 0; 2063070#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2063068#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2063066#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 2063064#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2063062#L449-30 assume !(1 == ~t1_pc~0); 2063059#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 2063057#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2063055#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2063053#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2063051#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2063049#L468-30 assume !(1 == ~t2_pc~0); 2063047#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 2063044#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2063042#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2063040#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2063038#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2063036#L487-30 assume !(1 == ~t3_pc~0); 2063034#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 2063032#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2063030#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2063028#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2063026#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2063024#L506-30 assume !(1 == ~t4_pc~0); 2063022#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2063019#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2063017#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2063015#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 2063013#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2063011#L525-30 assume !(1 == ~t5_pc~0); 2063009#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 2063007#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2063005#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2063003#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2063001#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2062999#L544-30 assume !(1 == ~t6_pc~0); 2062997#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 2062994#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2062992#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2062989#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2062987#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2062985#L563-30 assume !(1 == ~t7_pc~0); 2062984#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 2062983#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2062982#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2062981#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2062980#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2062979#L582-30 assume !(1 == ~t8_pc~0); 2062978#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2062968#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2062966#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2062964#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2062960#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2062958#L964-3 assume !(1 == ~M_E~0); 2062957#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2062956#L969-3 assume !(1 == ~T2_E~0); 2062955#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2062945#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2062943#L984-3 assume !(1 == ~T5_E~0); 2062941#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2062939#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2062937#L999-3 assume !(1 == ~T8_E~0); 2062925#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2062921#L1009-3 assume !(1 == ~E_1~0); 2062917#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2062909#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2062904#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2062903#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2061734#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2056150#L1039-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2056148#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2056146#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2056059#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2056054#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2056052#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2041230#L1334 assume !(0 == start_simulation_~tmp~3#1); 2041231#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2056542#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2056534#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2056530#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 2056528#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2056526#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2056525#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2056520#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 1990420#L1315-2 [2021-12-06 18:38:20,079 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:38:20,079 INFO L85 PathProgramCache]: Analyzing trace with hash -1185873335, now seen corresponding path program 1 times [2021-12-06 18:38:20,079 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:38:20,079 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [395378508] [2021-12-06 18:38:20,079 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:38:20,079 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:38:20,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:38:20,103 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:38:20,103 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:38:20,104 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [395378508] [2021-12-06 18:38:20,104 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [395378508] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:38:20,104 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:38:20,104 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:38:20,104 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1834022742] [2021-12-06 18:38:20,104 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:38:20,105 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 18:38:20,105 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:38:20,105 INFO L85 PathProgramCache]: Analyzing trace with hash -456044678, now seen corresponding path program 1 times [2021-12-06 18:38:20,105 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:38:20,106 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [459376204] [2021-12-06 18:38:20,106 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:38:20,106 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:38:20,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:38:20,132 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:38:20,132 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:38:20,133 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [459376204] [2021-12-06 18:38:20,133 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [459376204] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:38:20,133 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:38:20,133 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:38:20,133 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1511769646] [2021-12-06 18:38:20,133 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:38:20,134 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 18:38:20,134 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:38:20,134 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 18:38:20,134 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 18:38:20,135 INFO L87 Difference]: Start difference. First operand 139825 states and 196661 transitions. cyclomatic complexity: 56900 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:38:20,649 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:38:20,649 INFO L93 Difference]: Finished difference Result 173083 states and 242845 transitions. [2021-12-06 18:38:20,650 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 18:38:20,650 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 173083 states and 242845 transitions. [2021-12-06 18:38:21,455 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 171798 [2021-12-06 18:38:21,708 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 173083 states to 173083 states and 242845 transitions. [2021-12-06 18:38:21,708 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 173083 [2021-12-06 18:38:21,759 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 173083 [2021-12-06 18:38:21,760 INFO L73 IsDeterministic]: Start isDeterministic. Operand 173083 states and 242845 transitions. [2021-12-06 18:38:21,806 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:38:21,806 INFO L681 BuchiCegarLoop]: Abstraction has 173083 states and 242845 transitions. [2021-12-06 18:38:21,862 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 173083 states and 242845 transitions. [2021-12-06 18:38:22,820 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 173083 to 122717. [2021-12-06 18:38:22,889 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 122717 states, 122717 states have (on average 1.4006127920337035) internal successors, (171879), 122716 states have internal predecessors, (171879), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:38:23,076 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122717 states to 122717 states and 171879 transitions. [2021-12-06 18:38:23,077 INFO L704 BuchiCegarLoop]: Abstraction has 122717 states and 171879 transitions. [2021-12-06 18:38:23,077 INFO L587 BuchiCegarLoop]: Abstraction has 122717 states and 171879 transitions. [2021-12-06 18:38:23,077 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-06 18:38:23,077 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 122717 states and 171879 transitions. [2021-12-06 18:38:23,351 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 121896 [2021-12-06 18:38:23,351 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:38:23,351 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:38:23,352 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:38:23,352 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:38:23,352 INFO L791 eck$LassoCheckResult]: Stem: 2303620#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 2303621#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2303533#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2303534#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2303365#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 2303366#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2302936#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2302937#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2303014#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2303862#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2302908#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2302909#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2303328#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2303354#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2303020#L866 assume !(0 == ~M_E~0); 2303021#L866-2 assume !(0 == ~T1_E~0); 2303566#L871-1 assume !(0 == ~T2_E~0); 2303567#L876-1 assume !(0 == ~T3_E~0); 2303950#L881-1 assume !(0 == ~T4_E~0); 2303579#L886-1 assume !(0 == ~T5_E~0); 2303319#L891-1 assume !(0 == ~T6_E~0); 2303320#L896-1 assume !(0 == ~T7_E~0); 2303571#L901-1 assume !(0 == ~T8_E~0); 2303595#L906-1 assume !(0 == ~E_M~0); 2303596#L911-1 assume !(0 == ~E_1~0); 2303363#L916-1 assume !(0 == ~E_2~0); 2303364#L921-1 assume !(0 == ~E_3~0); 2303719#L926-1 assume !(0 == ~E_4~0); 2303883#L931-1 assume !(0 == ~E_5~0); 2303969#L936-1 assume !(0 == ~E_6~0); 2303983#L941-1 assume !(0 == ~E_7~0); 2303369#L946-1 assume !(0 == ~E_8~0); 2303370#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2303921#L430 assume !(1 == ~m_pc~0); 2303831#L430-2 is_master_triggered_~__retres1~0#1 := 0; 2302845#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2302846#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2303485#L1073 assume !(0 != activate_threads_~tmp~1#1); 2303495#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2303700#L449 assume !(1 == ~t1_pc~0); 2303023#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2303024#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2302803#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2302804#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 2303611#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2303432#L468 assume !(1 == ~t2_pc~0); 2302827#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2302826#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2303327#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2303228#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 2302843#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2302844#L487 assume !(1 == ~t3_pc~0); 2302960#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2302940#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2302941#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2303684#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 2303295#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2303296#L506 assume !(1 == ~t4_pc~0); 2303428#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2303481#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2303900#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2303901#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 2303421#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2303240#L525 assume !(1 == ~t5_pc~0); 2302885#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2302886#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2303375#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2303376#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 2303083#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2303084#L544 assume !(1 == ~t6_pc~0); 2303241#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2303242#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2303632#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2302869#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 2302870#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2303845#L563 assume !(1 == ~t7_pc~0); 2303627#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2302896#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2302897#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2303321#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 2303025#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2303026#L582 assume !(1 == ~t8_pc~0); 2303633#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2303944#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2303945#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2303283#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 2303177#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2303178#L964 assume !(1 == ~M_E~0); 2303702#L964-2 assume !(1 == ~T1_E~0); 2303085#L969-1 assume !(1 == ~T2_E~0); 2303086#L974-1 assume !(1 == ~T3_E~0); 2303741#L979-1 assume !(1 == ~T4_E~0); 2303742#L984-1 assume !(1 == ~T5_E~0); 2303247#L989-1 assume !(1 == ~T6_E~0); 2303248#L994-1 assume !(1 == ~T7_E~0); 2303130#L999-1 assume !(1 == ~T8_E~0); 2303131#L1004-1 assume !(1 == ~E_M~0); 2302871#L1009-1 assume !(1 == ~E_1~0); 2302872#L1014-1 assume !(1 == ~E_2~0); 2303117#L1019-1 assume !(1 == ~E_3~0); 2303689#L1024-1 assume !(1 == ~E_4~0); 2303045#L1029-1 assume !(1 == ~E_5~0); 2303046#L1034-1 assume !(1 == ~E_6~0); 2303145#L1039-1 assume !(1 == ~E_7~0); 2303907#L1044-1 assume !(1 == ~E_8~0); 2303336#L1049-1 assume { :end_inline_reset_delta_events } true; 2303337#L1315-2 [2021-12-06 18:38:23,352 INFO L793 eck$LassoCheckResult]: Loop: 2303337#L1315-2 assume !false; 2343263#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2343262#L841 assume !false; 2343261#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2343253#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2343247#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2343245#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2343242#L724 assume !(0 != eval_~tmp~0#1); 2343243#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2343260#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2343259#L866-3 assume !(0 == ~M_E~0); 2343258#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2343248#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2343246#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2343244#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2343241#L886-3 assume !(0 == ~T5_E~0); 2343238#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2343235#L896-3 assume !(0 == ~T7_E~0); 2343230#L901-3 assume !(0 == ~T8_E~0); 2343228#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2343227#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2343226#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2343225#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2343224#L926-3 assume !(0 == ~E_4~0); 2343223#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2343222#L936-3 assume !(0 == ~E_6~0); 2343221#L941-3 assume !(0 == ~E_7~0); 2343220#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2343219#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2343217#L430-30 assume !(1 == ~m_pc~0); 2343215#L430-32 is_master_triggered_~__retres1~0#1 := 0; 2343213#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2343211#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2343209#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 2343207#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2343205#L449-30 assume !(1 == ~t1_pc~0); 2343203#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 2343201#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2343199#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2343197#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2343195#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2343193#L468-30 assume !(1 == ~t2_pc~0); 2343190#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 2343187#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2343185#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2343183#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2343181#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2343179#L487-30 assume !(1 == ~t3_pc~0); 2343177#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 2343175#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2343173#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2343171#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2343169#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2343167#L506-30 assume 1 == ~t4_pc~0; 2343163#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2343161#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2343159#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2343157#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 2343155#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2343153#L525-30 assume !(1 == ~t5_pc~0); 2343151#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 2343149#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2343147#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2343145#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2343143#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2343141#L544-30 assume !(1 == ~t6_pc~0); 2343138#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 2343135#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2343133#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2343131#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2343129#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2343127#L563-30 assume !(1 == ~t7_pc~0); 2343125#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 2343123#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2343121#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2343119#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2343117#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2343115#L582-30 assume !(1 == ~t8_pc~0); 2343113#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2343111#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2343109#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2343107#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2343105#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2343104#L964-3 assume !(1 == ~M_E~0); 2343100#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2343098#L969-3 assume !(1 == ~T2_E~0); 2343096#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2343095#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2343091#L984-3 assume !(1 == ~T5_E~0); 2343089#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2343086#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2343082#L999-3 assume !(1 == ~T8_E~0); 2343079#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2343076#L1009-3 assume !(1 == ~E_1~0); 2343075#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2343074#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2343066#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2343063#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2343060#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2343059#L1039-3 assume !(1 == ~E_7~0); 2343058#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2343055#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2340072#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2340069#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2340068#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2340002#L1334 assume !(0 == start_simulation_~tmp~3#1); 2340003#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2343292#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2343283#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2343282#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 2343278#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2343276#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2343274#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2343273#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 2303337#L1315-2 [2021-12-06 18:38:23,353 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:38:23,353 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 1 times [2021-12-06 18:38:23,353 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:38:23,353 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2080195314] [2021-12-06 18:38:23,353 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:38:23,353 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:38:23,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:38:23,363 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 18:38:23,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:38:23,441 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 18:38:23,442 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:38:23,442 INFO L85 PathProgramCache]: Analyzing trace with hash 535833081, now seen corresponding path program 1 times [2021-12-06 18:38:23,442 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:38:23,442 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [742452381] [2021-12-06 18:38:23,442 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:38:23,443 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:38:23,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:38:23,475 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:38:23,476 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:38:23,476 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [742452381] [2021-12-06 18:38:23,476 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [742452381] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:38:23,476 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:38:23,476 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:38:23,476 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [659680014] [2021-12-06 18:38:23,477 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:38:23,477 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 18:38:23,477 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:38:23,478 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 18:38:23,478 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 18:38:23,478 INFO L87 Difference]: Start difference. First operand 122717 states and 171879 transitions. cyclomatic complexity: 49226 Second operand has 3 states, 3 states have (on average 38.0) internal successors, (114), 3 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:38:24,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:38:24,200 INFO L93 Difference]: Finished difference Result 139897 states and 195793 transitions. [2021-12-06 18:38:24,201 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 18:38:24,201 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 139897 states and 195793 transitions. [2021-12-06 18:38:24,696 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 139000 [2021-12-06 18:38:25,007 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 139897 states to 139897 states and 195793 transitions. [2021-12-06 18:38:25,007 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 139897 [2021-12-06 18:38:25,077 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 139897 [2021-12-06 18:38:25,077 INFO L73 IsDeterministic]: Start isDeterministic. Operand 139897 states and 195793 transitions. [2021-12-06 18:38:25,139 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:38:25,139 INFO L681 BuchiCegarLoop]: Abstraction has 139897 states and 195793 transitions. [2021-12-06 18:38:25,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139897 states and 195793 transitions. [2021-12-06 18:38:26,243 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139897 to 139897. [2021-12-06 18:38:26,318 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 139897 states, 139897 states have (on average 1.3995510983080408) internal successors, (195793), 139896 states have internal predecessors, (195793), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:38:26,826 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139897 states to 139897 states and 195793 transitions. [2021-12-06 18:38:26,826 INFO L704 BuchiCegarLoop]: Abstraction has 139897 states and 195793 transitions. [2021-12-06 18:38:26,827 INFO L587 BuchiCegarLoop]: Abstraction has 139897 states and 195793 transitions. [2021-12-06 18:38:26,827 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-12-06 18:38:26,827 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 139897 states and 195793 transitions. [2021-12-06 18:38:27,080 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 139000 [2021-12-06 18:38:27,080 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:38:27,080 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:38:27,081 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:38:27,081 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:38:27,082 INFO L791 eck$LassoCheckResult]: Stem: 2566246#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 2566247#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2566154#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2566155#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2565986#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 2565987#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2565557#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2565558#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2565636#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2566483#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2565528#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2565529#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2565951#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2565975#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2565642#L866 assume !(0 == ~M_E~0); 2565643#L866-2 assume !(0 == ~T1_E~0); 2566190#L871-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2566191#L876-1 assume !(0 == ~T3_E~0); 2566573#L881-1 assume !(0 == ~T4_E~0); 2566204#L886-1 assume !(0 == ~T5_E~0); 2566205#L891-1 assume !(0 == ~T6_E~0); 2566194#L896-1 assume !(0 == ~T7_E~0); 2566195#L901-1 assume !(0 == ~T8_E~0); 2566220#L906-1 assume !(0 == ~E_M~0); 2566221#L911-1 assume !(0 == ~E_1~0); 2565984#L916-1 assume !(0 == ~E_2~0); 2565985#L921-1 assume !(0 == ~E_3~0); 2566501#L926-1 assume !(0 == ~E_4~0); 2566502#L931-1 assume !(0 == ~E_5~0); 2566599#L936-1 assume !(0 == ~E_6~0); 2566600#L941-1 assume !(0 == ~E_7~0); 2565990#L946-1 assume !(0 == ~E_8~0); 2565991#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2566603#L430 assume !(1 == ~m_pc~0); 2566604#L430-2 is_master_triggered_~__retres1~0#1 := 0; 2565463#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2565464#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2566120#L1073 assume !(0 != activate_threads_~tmp~1#1); 2566121#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2566325#L449 assume !(1 == ~t1_pc~0); 2566326#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2566556#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2566557#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2566606#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 2566607#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2566052#L468 assume !(1 == ~t2_pc~0); 2566053#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2566167#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2566168#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2565852#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 2565853#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2566601#L487 assume !(1 == ~t3_pc~0); 2566602#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2565561#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2565562#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2566406#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 2566407#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2566047#L506 assume !(1 == ~t4_pc~0); 2566048#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2566633#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2566634#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2566560#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 2566561#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2565864#L525 assume !(1 == ~t5_pc~0); 2565865#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2566469#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2566470#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2566629#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 2566630#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2566036#L544 assume !(1 == ~t6_pc~0); 2566037#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2566257#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2566258#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2566642#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 2566541#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2566542#L563 assume !(1 == ~t7_pc~0); 2566252#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2566253#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2566087#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2566088#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 2565648#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2565649#L582 assume !(1 == ~t8_pc~0); 2566259#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2566562#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2566563#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2565902#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 2565799#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2565800#L964 assume !(1 == ~M_E~0); 2566328#L964-2 assume !(1 == ~T1_E~0); 2565706#L969-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2565707#L974-1 assume !(1 == ~T3_E~0); 2566364#L979-1 assume !(1 == ~T4_E~0); 2566365#L984-1 assume !(1 == ~T5_E~0); 2565872#L989-1 assume !(1 == ~T6_E~0); 2565873#L994-1 assume !(1 == ~T7_E~0); 2565749#L999-1 assume !(1 == ~T8_E~0); 2565750#L1004-1 assume !(1 == ~E_M~0); 2565491#L1009-1 assume !(1 == ~E_1~0); 2565492#L1014-1 assume !(1 == ~E_2~0); 2565738#L1019-1 assume !(1 == ~E_3~0); 2566315#L1024-1 assume !(1 == ~E_4~0); 2565667#L1029-1 assume !(1 == ~E_5~0); 2565668#L1034-1 assume !(1 == ~E_6~0); 2565766#L1039-1 assume !(1 == ~E_7~0); 2566523#L1044-1 assume !(1 == ~E_8~0); 2565959#L1049-1 assume { :end_inline_reset_delta_events } true; 2565960#L1315-2 [2021-12-06 18:38:27,082 INFO L793 eck$LassoCheckResult]: Loop: 2565960#L1315-2 assume !false; 2603156#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2603020#L841 assume !false; 2603011#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2603003#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2602998#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2602997#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2602985#L724 assume !(0 != eval_~tmp~0#1); 2602986#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2607295#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2607292#L866-3 assume !(0 == ~M_E~0); 2607290#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2607287#L871-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2607285#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2607283#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2607280#L886-3 assume !(0 == ~T5_E~0); 2607278#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2607276#L896-3 assume !(0 == ~T7_E~0); 2607274#L901-3 assume !(0 == ~T8_E~0); 2607272#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2607270#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2607268#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2607266#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2607264#L926-3 assume !(0 == ~E_4~0); 2607262#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2607260#L936-3 assume !(0 == ~E_6~0); 2607258#L941-3 assume !(0 == ~E_7~0); 2607256#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2607255#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2607254#L430-30 assume !(1 == ~m_pc~0); 2607251#L430-32 is_master_triggered_~__retres1~0#1 := 0; 2607249#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2607247#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2607246#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 2607245#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2607240#L449-30 assume !(1 == ~t1_pc~0); 2607235#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 2607234#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2607233#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2607228#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2607223#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2607221#L468-30 assume !(1 == ~t2_pc~0); 2607218#L468-32 is_transmit2_triggered_~__retres1~2#1 := 0; 2607215#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2607213#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2607211#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2607209#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2607207#L487-30 assume !(1 == ~t3_pc~0); 2607205#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 2607203#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2607201#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2607199#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2607197#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2607195#L506-30 assume !(1 == ~t4_pc~0); 2607193#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2607190#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2607188#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2607186#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 2607184#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2607182#L525-30 assume !(1 == ~t5_pc~0); 2607180#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 2607178#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2607175#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2607172#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2607170#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2607168#L544-30 assume !(1 == ~t6_pc~0); 2607165#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 2607162#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2607159#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2607157#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2607155#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2607153#L563-30 assume !(1 == ~t7_pc~0); 2607151#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 2607149#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2607147#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2607145#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2607144#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2607133#L582-30 assume !(1 == ~t8_pc~0); 2607130#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2607126#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2607121#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2606722#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2606719#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2606717#L964-3 assume !(1 == ~M_E~0); 2606715#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2606713#L969-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2606710#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2606708#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2606705#L984-3 assume !(1 == ~T5_E~0); 2606703#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2606701#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2606699#L999-3 assume !(1 == ~T8_E~0); 2606697#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2606695#L1009-3 assume !(1 == ~E_1~0); 2606693#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2606691#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2606689#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2606687#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2606685#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2606683#L1039-3 assume !(1 == ~E_7~0); 2606680#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2606678#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2606654#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2606647#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2606642#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2606635#L1334 assume !(0 == start_simulation_~tmp~3#1); 2606633#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2606630#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2606622#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2605544#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 2605543#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2605542#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2605541#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2605540#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 2565960#L1315-2 [2021-12-06 18:38:27,082 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:38:27,083 INFO L85 PathProgramCache]: Analyzing trace with hash 743043657, now seen corresponding path program 1 times [2021-12-06 18:38:27,083 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:38:27,083 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [405786284] [2021-12-06 18:38:27,083 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:38:27,083 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:38:27,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:38:27,109 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:38:27,109 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:38:27,109 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [405786284] [2021-12-06 18:38:27,109 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [405786284] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:38:27,109 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:38:27,110 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:38:27,110 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1252866939] [2021-12-06 18:38:27,110 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:38:27,110 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 18:38:27,111 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:38:27,111 INFO L85 PathProgramCache]: Analyzing trace with hash 178161848, now seen corresponding path program 1 times [2021-12-06 18:38:27,111 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:38:27,111 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1179809129] [2021-12-06 18:38:27,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:38:27,111 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:38:27,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:38:27,139 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:38:27,139 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:38:27,139 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1179809129] [2021-12-06 18:38:27,139 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1179809129] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:38:27,139 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:38:27,139 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:38:27,139 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1187965561] [2021-12-06 18:38:27,139 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:38:27,140 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 18:38:27,140 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:38:27,140 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 18:38:27,140 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 18:38:27,140 INFO L87 Difference]: Start difference. First operand 139897 states and 195793 transitions. cyclomatic complexity: 55960 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:38:27,674 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:38:27,674 INFO L93 Difference]: Finished difference Result 179707 states and 251196 transitions. [2021-12-06 18:38:27,674 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 18:38:27,675 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 179707 states and 251196 transitions. [2021-12-06 18:38:28,510 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 178514 [2021-12-06 18:38:28,764 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 179707 states to 179707 states and 251196 transitions. [2021-12-06 18:38:28,765 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 179707 [2021-12-06 18:38:28,821 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 179707 [2021-12-06 18:38:28,821 INFO L73 IsDeterministic]: Start isDeterministic. Operand 179707 states and 251196 transitions. [2021-12-06 18:38:28,869 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:38:28,869 INFO L681 BuchiCegarLoop]: Abstraction has 179707 states and 251196 transitions. [2021-12-06 18:38:28,927 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179707 states and 251196 transitions. [2021-12-06 18:38:29,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179707 to 122717. [2021-12-06 18:38:29,996 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 122717 states, 122717 states have (on average 1.3988444958726174) internal successors, (171662), 122716 states have internal predecessors, (171662), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:38:30,221 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122717 states to 122717 states and 171662 transitions. [2021-12-06 18:38:30,221 INFO L704 BuchiCegarLoop]: Abstraction has 122717 states and 171662 transitions. [2021-12-06 18:38:30,221 INFO L587 BuchiCegarLoop]: Abstraction has 122717 states and 171662 transitions. [2021-12-06 18:38:30,221 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-12-06 18:38:30,221 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 122717 states and 171662 transitions. [2021-12-06 18:38:30,541 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 121896 [2021-12-06 18:38:30,541 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:38:30,541 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:38:30,542 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:38:30,542 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:38:30,542 INFO L791 eck$LassoCheckResult]: Stem: 2885843#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 2885844#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2885759#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2885760#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2885591#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 2885592#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2885171#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2885172#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2885249#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2886063#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2885143#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2885144#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2885556#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2885580#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2885255#L866 assume !(0 == ~M_E~0); 2885256#L866-2 assume !(0 == ~T1_E~0); 2885790#L871-1 assume !(0 == ~T2_E~0); 2885791#L876-1 assume !(0 == ~T3_E~0); 2886143#L881-1 assume !(0 == ~T4_E~0); 2885804#L886-1 assume !(0 == ~T5_E~0); 2885547#L891-1 assume !(0 == ~T6_E~0); 2885548#L896-1 assume !(0 == ~T7_E~0); 2885795#L901-1 assume !(0 == ~T8_E~0); 2885819#L906-1 assume !(0 == ~E_M~0); 2885820#L911-1 assume !(0 == ~E_1~0); 2885589#L916-1 assume !(0 == ~E_2~0); 2885590#L921-1 assume !(0 == ~E_3~0); 2885938#L926-1 assume !(0 == ~E_4~0); 2886080#L931-1 assume !(0 == ~E_5~0); 2886164#L936-1 assume !(0 == ~E_6~0); 2886175#L941-1 assume !(0 == ~E_7~0); 2885595#L946-1 assume !(0 == ~E_8~0); 2885596#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2886110#L430 assume !(1 == ~m_pc~0); 2886029#L430-2 is_master_triggered_~__retres1~0#1 := 0; 2885080#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2885081#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2885709#L1073 assume !(0 != activate_threads_~tmp~1#1); 2885723#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2885919#L449 assume !(1 == ~t1_pc~0); 2885258#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2885259#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2885037#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2885038#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 2885834#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2885655#L468 assume !(1 == ~t2_pc~0); 2885062#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2885061#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2885555#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2885458#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 2885078#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2885079#L487 assume !(1 == ~t3_pc~0); 2885195#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2885175#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2885176#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2885903#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 2885521#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2885522#L506 assume !(1 == ~t4_pc~0); 2885650#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2885703#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2886094#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2886095#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 2885644#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2885470#L525 assume !(1 == ~t5_pc~0); 2885120#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2885121#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2885600#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2885601#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 2885315#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2885316#L544 assume !(1 == ~t6_pc~0); 2885471#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2885472#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2885852#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2885104#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 2885105#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2886049#L563 assume !(1 == ~t7_pc~0); 2885849#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2885131#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2885132#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2885549#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 2885260#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2885261#L582 assume !(1 == ~t8_pc~0); 2885853#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2886138#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2886139#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2885510#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 2885408#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2885409#L964 assume !(1 == ~M_E~0); 2885921#L964-2 assume !(1 == ~T1_E~0); 2885317#L969-1 assume !(1 == ~T2_E~0); 2885318#L974-1 assume !(1 == ~T3_E~0); 2885954#L979-1 assume !(1 == ~T4_E~0); 2885955#L984-1 assume !(1 == ~T5_E~0); 2885477#L989-1 assume !(1 == ~T6_E~0); 2885478#L994-1 assume !(1 == ~T7_E~0); 2885360#L999-1 assume !(1 == ~T8_E~0); 2885361#L1004-1 assume !(1 == ~E_M~0); 2885106#L1009-1 assume !(1 == ~E_1~0); 2885107#L1014-1 assume !(1 == ~E_2~0); 2885349#L1019-1 assume !(1 == ~E_3~0); 2885908#L1024-1 assume !(1 == ~E_4~0); 2885279#L1029-1 assume !(1 == ~E_5~0); 2885280#L1034-1 assume !(1 == ~E_6~0); 2885376#L1039-1 assume !(1 == ~E_7~0); 2886100#L1044-1 assume !(1 == ~E_8~0); 2885564#L1049-1 assume { :end_inline_reset_delta_events } true; 2885565#L1315-2 [2021-12-06 18:38:30,543 INFO L793 eck$LassoCheckResult]: Loop: 2885565#L1315-2 assume !false; 2916730#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2916729#L841 assume !false; 2916719#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2916706#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2916700#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2916698#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2916695#L724 assume !(0 != eval_~tmp~0#1); 2916693#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2916691#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2916689#L866-3 assume !(0 == ~M_E~0); 2916687#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2916685#L871-3 assume !(0 == ~T2_E~0); 2916683#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2916681#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2916679#L886-3 assume !(0 == ~T5_E~0); 2916677#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2916675#L896-3 assume !(0 == ~T7_E~0); 2916673#L901-3 assume !(0 == ~T8_E~0); 2916671#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2916669#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2916667#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2916665#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2916663#L926-3 assume !(0 == ~E_4~0); 2916661#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2916659#L936-3 assume !(0 == ~E_6~0); 2916657#L941-3 assume !(0 == ~E_7~0); 2916655#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2916653#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2916651#L430-30 assume !(1 == ~m_pc~0); 2916649#L430-32 is_master_triggered_~__retres1~0#1 := 0; 2916647#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2916645#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2916643#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 2916641#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2916638#L449-30 assume !(1 == ~t1_pc~0); 2916636#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 2916634#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2916632#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2916630#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2916627#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2916624#L468-30 assume 1 == ~t2_pc~0; 2916621#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2916619#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2916617#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2916615#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2916613#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2916610#L487-30 assume !(1 == ~t3_pc~0); 2916608#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 2916606#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2916604#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2916602#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2916600#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2916598#L506-30 assume !(1 == ~t4_pc~0); 2916596#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2916593#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2916591#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2916589#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 2916587#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2916584#L525-30 assume !(1 == ~t5_pc~0); 2916582#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 2916580#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2916578#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2916576#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2916574#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2916572#L544-30 assume 1 == ~t6_pc~0; 2916569#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2916567#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2916565#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2916563#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2916561#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2916558#L563-30 assume !(1 == ~t7_pc~0); 2916556#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 2916554#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2916552#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2916550#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2916548#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2916546#L582-30 assume !(1 == ~t8_pc~0); 2916544#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2916542#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2916540#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2916538#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2916536#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2916534#L964-3 assume !(1 == ~M_E~0); 2916532#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2916530#L969-3 assume !(1 == ~T2_E~0); 2916528#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2916526#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2916524#L984-3 assume !(1 == ~T5_E~0); 2916522#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2916520#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2916518#L999-3 assume !(1 == ~T8_E~0); 2916516#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2916514#L1009-3 assume !(1 == ~E_1~0); 2916512#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2916511#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2916510#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2916509#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2916508#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2916507#L1039-3 assume !(1 == ~E_7~0); 2916506#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2916505#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2916498#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2916486#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2916484#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2916481#L1334 assume !(0 == start_simulation_~tmp~3#1); 2916482#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2916766#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2916758#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2916754#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 2916752#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2916750#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2916749#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2916744#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 2885565#L1315-2 [2021-12-06 18:38:30,543 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:38:30,543 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 2 times [2021-12-06 18:38:30,543 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:38:30,543 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1533150725] [2021-12-06 18:38:30,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:38:30,543 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:38:30,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:38:30,551 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 18:38:30,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:38:30,584 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 18:38:30,584 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:38:30,584 INFO L85 PathProgramCache]: Analyzing trace with hash 392432502, now seen corresponding path program 1 times [2021-12-06 18:38:30,584 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:38:30,585 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1366313362] [2021-12-06 18:38:30,585 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:38:30,585 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:38:30,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:38:30,607 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:38:30,607 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:38:30,608 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1366313362] [2021-12-06 18:38:30,608 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1366313362] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:38:30,608 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:38:30,608 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:38:30,608 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1939027883] [2021-12-06 18:38:30,608 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:38:30,608 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 18:38:30,608 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:38:30,609 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 18:38:30,609 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 18:38:30,609 INFO L87 Difference]: Start difference. First operand 122717 states and 171662 transitions. cyclomatic complexity: 49009 Second operand has 3 states, 3 states have (on average 38.0) internal successors, (114), 3 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:38:31,415 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:38:31,415 INFO L93 Difference]: Finished difference Result 200421 states and 278496 transitions. [2021-12-06 18:38:31,415 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 18:38:31,416 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 200421 states and 278496 transitions. [2021-12-06 18:38:32,240 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 199044 [2021-12-06 18:38:32,827 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 200421 states to 200421 states and 278496 transitions. [2021-12-06 18:38:32,827 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 200421 [2021-12-06 18:38:32,926 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 200421 [2021-12-06 18:38:32,927 INFO L73 IsDeterministic]: Start isDeterministic. Operand 200421 states and 278496 transitions. [2021-12-06 18:38:33,022 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:38:33,022 INFO L681 BuchiCegarLoop]: Abstraction has 200421 states and 278496 transitions. [2021-12-06 18:38:33,119 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 200421 states and 278496 transitions. [2021-12-06 18:38:34,440 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 200421 to 199589. [2021-12-06 18:38:34,554 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 199589 states, 199589 states have (on average 1.3890144246426406) internal successors, (277232), 199588 states have internal predecessors, (277232), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:38:35,183 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 199589 states to 199589 states and 277232 transitions. [2021-12-06 18:38:35,183 INFO L704 BuchiCegarLoop]: Abstraction has 199589 states and 277232 transitions. [2021-12-06 18:38:35,183 INFO L587 BuchiCegarLoop]: Abstraction has 199589 states and 277232 transitions. [2021-12-06 18:38:35,183 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-12-06 18:38:35,183 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 199589 states and 277232 transitions. [2021-12-06 18:38:35,592 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 198404 [2021-12-06 18:38:35,592 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:38:35,592 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:38:35,593 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:38:35,593 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:38:35,593 INFO L791 eck$LassoCheckResult]: Stem: 3209025#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 3209026#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 3208926#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3208927#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3208748#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 3208749#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3208312#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3208313#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3208392#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3209280#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3208284#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3208285#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3208715#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3208737#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3208398#L866 assume !(0 == ~M_E~0); 3208399#L866-2 assume !(0 == ~T1_E~0); 3208961#L871-1 assume !(0 == ~T2_E~0); 3208962#L876-1 assume !(0 == ~T3_E~0); 3209386#L881-1 assume !(0 == ~T4_E~0); 3208976#L886-1 assume !(0 == ~T5_E~0); 3208702#L891-1 assume !(0 == ~T6_E~0); 3208703#L896-1 assume !(0 == ~T7_E~0); 3208965#L901-1 assume !(0 == ~T8_E~0); 3208992#L906-1 assume !(0 == ~E_M~0); 3208993#L911-1 assume 0 == ~E_1~0;~E_1~0 := 1; 3208746#L916-1 assume !(0 == ~E_2~0); 3208747#L921-1 assume !(0 == ~E_3~0); 3209299#L926-1 assume !(0 == ~E_4~0); 3209300#L931-1 assume !(0 == ~E_5~0); 3209425#L936-1 assume !(0 == ~E_6~0); 3209426#L941-1 assume !(0 == ~E_7~0); 3208752#L946-1 assume !(0 == ~E_8~0); 3208753#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3209430#L430 assume !(1 == ~m_pc~0); 3209431#L430-2 is_master_triggered_~__retres1~0#1 := 0; 3208222#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3208223#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3208889#L1073 assume !(0 != activate_threads_~tmp~1#1); 3208890#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3209110#L449 assume !(1 == ~t1_pc~0); 3209111#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3209370#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3209371#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3209433#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 3209434#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3208821#L468 assume !(1 == ~t2_pc~0); 3208822#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3208939#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3208940#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3208612#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 3208613#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3209428#L487 assume !(1 == ~t3_pc~0); 3209429#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3208316#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3208317#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3209201#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 3208675#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3208676#L506 assume !(1 == ~t4_pc~0); 3208871#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3208872#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3209319#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3209320#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 3208811#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3208812#L525 assume !(1 == ~t5_pc~0); 3208261#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3208262#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3208756#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3208757#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 3208464#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3208465#L544 assume !(1 == ~t6_pc~0); 3208624#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3208625#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3209035#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3209484#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 3209354#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3209355#L563 assume !(1 == ~t7_pc~0); 3209496#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3208272#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3208273#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3208709#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 3208710#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3209495#L582 assume !(1 == ~t8_pc~0); 3209442#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3209443#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3209494#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3209493#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 3208558#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3208559#L964 assume !(1 == ~M_E~0); 3209372#L964-2 assume !(1 == ~T1_E~0); 3209373#L969-1 assume !(1 == ~T2_E~0); 3209310#L974-1 assume !(1 == ~T3_E~0); 3209311#L979-1 assume !(1 == ~T4_E~0); 3209461#L984-1 assume !(1 == ~T5_E~0); 3208630#L989-1 assume !(1 == ~T6_E~0); 3208631#L994-1 assume !(1 == ~T7_E~0); 3208512#L999-1 assume !(1 == ~T8_E~0); 3208513#L1004-1 assume !(1 == ~E_M~0); 3208248#L1009-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3208249#L1014-1 assume !(1 == ~E_2~0); 3208499#L1019-1 assume !(1 == ~E_3~0); 3209098#L1024-1 assume !(1 == ~E_4~0); 3208422#L1029-1 assume !(1 == ~E_5~0); 3208423#L1034-1 assume !(1 == ~E_6~0); 3208525#L1039-1 assume !(1 == ~E_7~0); 3209327#L1044-1 assume !(1 == ~E_8~0); 3208723#L1049-1 assume { :end_inline_reset_delta_events } true; 3208724#L1315-2 [2021-12-06 18:38:35,594 INFO L793 eck$LassoCheckResult]: Loop: 3208724#L1315-2 assume !false; 3300584#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3300583#L841 assume !false; 3300582#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 3300577#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3300572#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 3300571#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3300569#L724 assume !(0 != eval_~tmp~0#1); 3300568#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3300567#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3300566#L866-3 assume !(0 == ~M_E~0); 3300565#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3300564#L871-3 assume !(0 == ~T2_E~0); 3300563#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3300562#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3300561#L886-3 assume !(0 == ~T5_E~0); 3300560#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3300559#L896-3 assume !(0 == ~T7_E~0); 3300558#L901-3 assume !(0 == ~T8_E~0); 3300557#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3300555#L911-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3300554#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3300553#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3300552#L926-3 assume !(0 == ~E_4~0); 3300551#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3300550#L936-3 assume !(0 == ~E_6~0); 3300549#L941-3 assume !(0 == ~E_7~0); 3300548#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3300547#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3300546#L430-30 assume !(1 == ~m_pc~0); 3300545#L430-32 is_master_triggered_~__retres1~0#1 := 0; 3300544#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3300543#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3300542#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 3300541#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3300540#L449-30 assume !(1 == ~t1_pc~0); 3300539#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 3300538#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3300537#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3300536#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3300535#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3300534#L468-30 assume 1 == ~t2_pc~0; 3300532#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3300531#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3300530#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3300529#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3300528#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3300527#L487-30 assume !(1 == ~t3_pc~0); 3300526#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 3300525#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3300524#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3300523#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3300522#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3300521#L506-30 assume 1 == ~t4_pc~0; 3300519#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3300518#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3300517#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3300516#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 3300515#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3300514#L525-30 assume !(1 == ~t5_pc~0); 3300513#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 3300512#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3300511#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3300510#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3300509#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3300508#L544-30 assume 1 == ~t6_pc~0; 3300506#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3300505#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3300504#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3300503#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3300502#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3300501#L563-30 assume !(1 == ~t7_pc~0); 3300500#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 3300499#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3300498#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3300497#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3300496#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3300495#L582-30 assume !(1 == ~t8_pc~0); 3300494#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 3300493#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3300492#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3300491#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3300490#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3300489#L964-3 assume !(1 == ~M_E~0); 3300488#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3300487#L969-3 assume !(1 == ~T2_E~0); 3300486#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3300485#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3300484#L984-3 assume !(1 == ~T5_E~0); 3300483#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3300482#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3300481#L999-3 assume !(1 == ~T8_E~0); 3300480#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3300479#L1009-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3300477#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3300476#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3300475#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3300474#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3300473#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3300472#L1039-3 assume !(1 == ~E_7~0); 3300471#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3300470#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 3300463#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3300460#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 3300459#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 3300457#L1334 assume !(0 == start_simulation_~tmp~3#1); 3300458#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 3300899#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3300891#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 3300890#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 3300889#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3300888#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3300887#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 3300886#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 3208724#L1315-2 [2021-12-06 18:38:35,594 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:38:35,594 INFO L85 PathProgramCache]: Analyzing trace with hash -1215057335, now seen corresponding path program 1 times [2021-12-06 18:38:35,594 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:38:35,594 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1734886404] [2021-12-06 18:38:35,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:38:35,594 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:38:35,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:38:35,616 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:38:35,616 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:38:35,616 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1734886404] [2021-12-06 18:38:35,616 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1734886404] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:38:35,616 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:38:35,617 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:38:35,617 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [254080257] [2021-12-06 18:38:35,617 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:38:35,617 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 18:38:35,618 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:38:35,618 INFO L85 PathProgramCache]: Analyzing trace with hash -1058801485, now seen corresponding path program 1 times [2021-12-06 18:38:35,618 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:38:35,618 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1699608798] [2021-12-06 18:38:35,618 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:38:35,618 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:38:35,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:38:35,652 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:38:35,652 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:38:35,652 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1699608798] [2021-12-06 18:38:35,653 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1699608798] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:38:35,653 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:38:35,653 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 18:38:35,653 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [925871858] [2021-12-06 18:38:35,653 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:38:35,653 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 18:38:35,654 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:38:35,654 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 18:38:35,654 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 18:38:35,654 INFO L87 Difference]: Start difference. First operand 199589 states and 277232 transitions. cyclomatic complexity: 77707 Second operand has 4 states, 4 states have (on average 26.5) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:38:36,307 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:38:36,307 INFO L93 Difference]: Finished difference Result 283287 states and 393073 transitions. [2021-12-06 18:38:36,308 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 18:38:36,308 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 283287 states and 393073 transitions. [2021-12-06 18:38:37,467 INFO L131 ngComponentsAnalysis]: Automaton has 112 accepting balls. 274722 [2021-12-06 18:38:38,312 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 283287 states to 283287 states and 393073 transitions. [2021-12-06 18:38:38,312 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 283287 [2021-12-06 18:38:38,413 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 283287 [2021-12-06 18:38:38,413 INFO L73 IsDeterministic]: Start isDeterministic. Operand 283287 states and 393073 transitions. [2021-12-06 18:38:38,532 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:38:38,532 INFO L681 BuchiCegarLoop]: Abstraction has 283287 states and 393073 transitions. [2021-12-06 18:38:38,646 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 283287 states and 393073 transitions. [2021-12-06 18:38:39,917 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 283287 to 193921. [2021-12-06 18:38:40,020 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 193921 states, 193921 states have (on average 1.3881786913227552) internal successors, (269197), 193920 states have internal predecessors, (269197), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:38:40,300 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 193921 states to 193921 states and 269197 transitions. [2021-12-06 18:38:40,300 INFO L704 BuchiCegarLoop]: Abstraction has 193921 states and 269197 transitions. [2021-12-06 18:38:40,300 INFO L587 BuchiCegarLoop]: Abstraction has 193921 states and 269197 transitions. [2021-12-06 18:38:40,300 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-12-06 18:38:40,300 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 193921 states and 269197 transitions. [2021-12-06 18:38:40,717 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 192812 [2021-12-06 18:38:40,717 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:38:40,717 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:38:40,718 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:38:40,718 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:38:40,719 INFO L791 eck$LassoCheckResult]: Stem: 3691874#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 3691875#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 3691793#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3691794#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3691627#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 3691628#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3691202#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3691203#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3691280#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3692097#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3691174#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3691175#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3691594#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3691616#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3691286#L866 assume !(0 == ~M_E~0); 3691287#L866-2 assume !(0 == ~T1_E~0); 3691822#L871-1 assume !(0 == ~T2_E~0); 3691823#L876-1 assume !(0 == ~T3_E~0); 3692189#L881-1 assume !(0 == ~T4_E~0); 3691834#L886-1 assume !(0 == ~T5_E~0); 3691583#L891-1 assume !(0 == ~T6_E~0); 3691584#L896-1 assume !(0 == ~T7_E~0); 3691825#L901-1 assume !(0 == ~T8_E~0); 3691849#L906-1 assume !(0 == ~E_M~0); 3691850#L911-1 assume !(0 == ~E_1~0); 3691625#L916-1 assume !(0 == ~E_2~0); 3691626#L921-1 assume !(0 == ~E_3~0); 3691961#L926-1 assume !(0 == ~E_4~0); 3692111#L931-1 assume !(0 == ~E_5~0); 3692199#L936-1 assume !(0 == ~E_6~0); 3692214#L941-1 assume !(0 == ~E_7~0); 3691631#L946-1 assume !(0 == ~E_8~0); 3691632#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3692155#L430 assume !(1 == ~m_pc~0); 3692064#L430-2 is_master_triggered_~__retres1~0#1 := 0; 3691113#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3691114#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3691745#L1073 assume !(0 != activate_threads_~tmp~1#1); 3691756#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3691942#L449 assume !(1 == ~t1_pc~0); 3691289#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3691290#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3691069#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3691070#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 3691865#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3691695#L468 assume !(1 == ~t2_pc~0); 3691094#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3691093#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3691591#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3691495#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 3691111#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3691112#L487 assume !(1 == ~t3_pc~0); 3691226#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3691206#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3691207#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3691929#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 3691557#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3691558#L506 assume !(1 == ~t4_pc~0); 3691688#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3691741#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3692129#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3692130#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 3691686#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3691504#L525 assume !(1 == ~t5_pc~0); 3691150#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3691151#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3691635#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3691636#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 3691350#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3691351#L544 assume !(1 == ~t6_pc~0); 3691505#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3691506#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3691884#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3691135#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 3691136#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3692083#L563 assume !(1 == ~t7_pc~0); 3691880#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3691161#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3691162#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3691590#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 3691293#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3691294#L582 assume !(1 == ~t8_pc~0); 3691885#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3692179#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3692180#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3691546#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 3691441#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3691442#L964 assume !(1 == ~M_E~0); 3691944#L964-2 assume !(1 == ~T1_E~0); 3691352#L969-1 assume !(1 == ~T2_E~0); 3691353#L974-1 assume !(1 == ~T3_E~0); 3691979#L979-1 assume !(1 == ~T4_E~0); 3691980#L984-1 assume !(1 == ~T5_E~0); 3691511#L989-1 assume !(1 == ~T6_E~0); 3691512#L994-1 assume !(1 == ~T7_E~0); 3691396#L999-1 assume !(1 == ~T8_E~0); 3691397#L1004-1 assume !(1 == ~E_M~0); 3691137#L1009-1 assume !(1 == ~E_1~0); 3691138#L1014-1 assume !(1 == ~E_2~0); 3691385#L1019-1 assume !(1 == ~E_3~0); 3691932#L1024-1 assume !(1 == ~E_4~0); 3691310#L1029-1 assume !(1 == ~E_5~0); 3691311#L1034-1 assume !(1 == ~E_6~0); 3691410#L1039-1 assume !(1 == ~E_7~0); 3692138#L1044-1 assume !(1 == ~E_8~0); 3691602#L1049-1 assume { :end_inline_reset_delta_events } true; 3691603#L1315-2 [2021-12-06 18:38:40,719 INFO L793 eck$LassoCheckResult]: Loop: 3691603#L1315-2 assume !false; 3794721#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3794635#L841 assume !false; 3794710#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 3794699#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3794694#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 3794693#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3794690#L724 assume !(0 != eval_~tmp~0#1); 3794691#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3798392#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3798390#L866-3 assume !(0 == ~M_E~0); 3798388#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3798386#L871-3 assume !(0 == ~T2_E~0); 3798384#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3798382#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3798380#L886-3 assume !(0 == ~T5_E~0); 3798378#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3798376#L896-3 assume !(0 == ~T7_E~0); 3798374#L901-3 assume !(0 == ~T8_E~0); 3798372#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3798369#L911-3 assume !(0 == ~E_1~0); 3798367#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3798365#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3798363#L926-3 assume !(0 == ~E_4~0); 3798361#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3798360#L936-3 assume !(0 == ~E_6~0); 3798359#L941-3 assume !(0 == ~E_7~0); 3798355#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3798353#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3798351#L430-30 assume !(1 == ~m_pc~0); 3798350#L430-32 is_master_triggered_~__retres1~0#1 := 0; 3798349#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3798348#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3798347#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 3798345#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3798344#L449-30 assume !(1 == ~t1_pc~0); 3798343#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 3798342#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3798340#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3798338#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3798336#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3798334#L468-30 assume 1 == ~t2_pc~0; 3798331#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3798329#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3798327#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3798096#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3798093#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3798091#L487-30 assume !(1 == ~t3_pc~0); 3798089#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 3798087#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3798085#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3798083#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3797463#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3797075#L506-30 assume 1 == ~t4_pc~0; 3797071#L507-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3797069#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3797067#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3797065#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 3797063#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3797061#L525-30 assume !(1 == ~t5_pc~0); 3797057#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 3797055#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3797053#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3797051#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3797049#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3797047#L544-30 assume !(1 == ~t6_pc~0); 3797045#L544-32 is_transmit6_triggered_~__retres1~6#1 := 0; 3797043#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3797042#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3797041#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3797039#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3797037#L563-30 assume !(1 == ~t7_pc~0); 3797035#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 3797033#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3797031#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3797029#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3797027#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3797026#L582-30 assume !(1 == ~t8_pc~0); 3797024#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 3797022#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3797020#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3797018#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3797016#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3797013#L964-3 assume !(1 == ~M_E~0); 3797011#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3797009#L969-3 assume !(1 == ~T2_E~0); 3795764#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3795763#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3795758#L984-3 assume !(1 == ~T5_E~0); 3795745#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3795664#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3795652#L999-3 assume !(1 == ~T8_E~0); 3795643#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3795640#L1009-3 assume !(1 == ~E_1~0); 3795638#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3795636#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3795634#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3795632#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3795630#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3795572#L1039-3 assume !(1 == ~E_7~0); 3795565#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3795561#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 3795404#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3795397#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 3795388#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 3794913#L1334 assume !(0 == start_simulation_~tmp~3#1); 3794797#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 3794768#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3794759#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 3794757#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 3794755#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3794753#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3794752#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 3794722#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 3691603#L1315-2 [2021-12-06 18:38:40,719 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:38:40,719 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 3 times [2021-12-06 18:38:40,720 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:38:40,720 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1068054000] [2021-12-06 18:38:40,720 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:38:40,720 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:38:40,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:38:40,726 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 18:38:40,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:38:40,752 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 18:38:40,752 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:38:40,752 INFO L85 PathProgramCache]: Analyzing trace with hash -786871244, now seen corresponding path program 1 times [2021-12-06 18:38:40,753 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:38:40,753 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [142517451] [2021-12-06 18:38:40,753 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:38:40,753 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:38:40,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:38:40,778 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:38:40,778 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:38:40,779 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [142517451] [2021-12-06 18:38:40,779 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [142517451] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:38:40,779 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:38:40,779 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 18:38:40,779 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [397992753] [2021-12-06 18:38:40,779 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:38:40,779 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 18:38:40,779 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:38:40,780 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-06 18:38:40,780 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-06 18:38:40,780 INFO L87 Difference]: Start difference. First operand 193921 states and 269197 transitions. cyclomatic complexity: 75340 Second operand has 5 states, 5 states have (on average 22.8) internal successors, (114), 5 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:38:42,070 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:38:42,070 INFO L93 Difference]: Finished difference Result 350765 states and 481957 transitions. [2021-12-06 18:38:42,070 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-06 18:38:42,071 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 350765 states and 481957 transitions. [2021-12-06 18:38:43,607 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 348656 [2021-12-06 18:38:44,228 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 350765 states to 350765 states and 481957 transitions. [2021-12-06 18:38:44,228 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 350765 [2021-12-06 18:38:44,382 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 350765 [2021-12-06 18:38:44,382 INFO L73 IsDeterministic]: Start isDeterministic. Operand 350765 states and 481957 transitions. [2021-12-06 18:38:44,806 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:38:44,806 INFO L681 BuchiCegarLoop]: Abstraction has 350765 states and 481957 transitions. [2021-12-06 18:38:44,914 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 350765 states and 481957 transitions. [2021-12-06 18:38:46,473 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 350765 to 195001. [2021-12-06 18:38:46,579 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 195001 states, 195001 states have (on average 1.3860287895959509) internal successors, (270277), 195000 states have internal predecessors, (270277), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:38:46,858 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195001 states to 195001 states and 270277 transitions. [2021-12-06 18:38:46,858 INFO L704 BuchiCegarLoop]: Abstraction has 195001 states and 270277 transitions. [2021-12-06 18:38:46,859 INFO L587 BuchiCegarLoop]: Abstraction has 195001 states and 270277 transitions. [2021-12-06 18:38:46,859 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-12-06 18:38:46,859 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 195001 states and 270277 transitions. [2021-12-06 18:38:47,609 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 193892 [2021-12-06 18:38:47,609 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:38:47,609 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:38:47,610 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:38:47,611 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:38:47,611 INFO L791 eck$LassoCheckResult]: Stem: 4236586#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 4236587#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 4236500#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4236501#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4236333#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 4236334#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4235903#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4235904#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4235983#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4236824#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4235874#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4235875#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4236298#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4236321#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4235989#L866 assume !(0 == ~M_E~0); 4235990#L866-2 assume !(0 == ~T1_E~0); 4236529#L871-1 assume !(0 == ~T2_E~0); 4236530#L876-1 assume !(0 == ~T3_E~0); 4236900#L881-1 assume !(0 == ~T4_E~0); 4236543#L886-1 assume !(0 == ~T5_E~0); 4236287#L891-1 assume !(0 == ~T6_E~0); 4236288#L896-1 assume !(0 == ~T7_E~0); 4236532#L901-1 assume !(0 == ~T8_E~0); 4236558#L906-1 assume !(0 == ~E_M~0); 4236559#L911-1 assume !(0 == ~E_1~0); 4236331#L916-1 assume !(0 == ~E_2~0); 4236332#L921-1 assume !(0 == ~E_3~0); 4236681#L926-1 assume !(0 == ~E_4~0); 4236838#L931-1 assume !(0 == ~E_5~0); 4236918#L936-1 assume !(0 == ~E_6~0); 4236933#L941-1 assume !(0 == ~E_7~0); 4236337#L946-1 assume !(0 == ~E_8~0); 4236338#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4236872#L430 assume !(1 == ~m_pc~0); 4236792#L430-2 is_master_triggered_~__retres1~0#1 := 0; 4235814#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4235815#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4236449#L1073 assume !(0 != activate_threads_~tmp~1#1); 4236464#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4236660#L449 assume !(1 == ~t1_pc~0); 4235992#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4235993#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4235771#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4235772#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 4236573#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4236399#L468 assume !(1 == ~t2_pc~0); 4235796#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4235795#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4236295#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4236202#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 4235812#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4235813#L487 assume !(1 == ~t3_pc~0); 4235927#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4235907#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4235908#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4236644#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 4236263#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4236264#L506 assume !(1 == ~t4_pc~0); 4236393#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4236443#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4236851#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4236852#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 4236391#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4236213#L525 assume !(1 == ~t5_pc~0); 4235851#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4235852#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4236342#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4236343#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 4236056#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4236057#L544 assume !(1 == ~t6_pc~0); 4236214#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4236215#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4236595#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4235836#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 4235837#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4236809#L563 assume !(1 == ~t7_pc~0); 4236592#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4235862#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4235863#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4236294#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 4235996#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4235997#L582 assume !(1 == ~t8_pc~0); 4236596#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4236892#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4236893#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4236253#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 4236144#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4236145#L964 assume !(1 == ~M_E~0); 4236662#L964-2 assume !(1 == ~T1_E~0); 4236054#L969-1 assume !(1 == ~T2_E~0); 4236055#L974-1 assume !(1 == ~T3_E~0); 4236701#L979-1 assume !(1 == ~T4_E~0); 4236702#L984-1 assume !(1 == ~T5_E~0); 4236220#L989-1 assume !(1 == ~T6_E~0); 4236221#L994-1 assume !(1 == ~T7_E~0); 4236099#L999-1 assume !(1 == ~T8_E~0); 4236100#L1004-1 assume !(1 == ~E_M~0); 4235838#L1009-1 assume !(1 == ~E_1~0); 4235839#L1014-1 assume !(1 == ~E_2~0); 4236088#L1019-1 assume !(1 == ~E_3~0); 4236650#L1024-1 assume !(1 == ~E_4~0); 4236013#L1029-1 assume !(1 == ~E_5~0); 4236014#L1034-1 assume !(1 == ~E_6~0); 4236113#L1039-1 assume !(1 == ~E_7~0); 4236857#L1044-1 assume !(1 == ~E_8~0); 4236306#L1049-1 assume { :end_inline_reset_delta_events } true; 4236307#L1315-2 [2021-12-06 18:38:47,611 INFO L793 eck$LassoCheckResult]: Loop: 4236307#L1315-2 assume !false; 4270233#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4270231#L841 assume !false; 4270232#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4331451#L662 assume !(0 == ~m_st~0); 4331450#L666 assume !(0 == ~t1_st~0); 4331449#L670 assume !(0 == ~t2_st~0); 4331448#L674 assume !(0 == ~t3_st~0); 4331447#L678 assume !(0 == ~t4_st~0); 4331446#L682 assume !(0 == ~t5_st~0); 4331445#L686 assume !(0 == ~t6_st~0); 4331444#L690 assume !(0 == ~t7_st~0); 4331443#L694 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 4331442#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4331441#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4285269#L724 assume !(0 != eval_~tmp~0#1); 4285270#L856 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4337646#L602-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4337645#L866-3 assume !(0 == ~M_E~0); 4337644#L866-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4337643#L871-3 assume !(0 == ~T2_E~0); 4337642#L876-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4337641#L881-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4337640#L886-3 assume !(0 == ~T5_E~0); 4337639#L891-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4337638#L896-3 assume !(0 == ~T7_E~0); 4337637#L901-3 assume !(0 == ~T8_E~0); 4337636#L906-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4337635#L911-3 assume !(0 == ~E_1~0); 4337634#L916-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4337633#L921-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4337632#L926-3 assume !(0 == ~E_4~0); 4337631#L931-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4337630#L936-3 assume !(0 == ~E_6~0); 4337629#L941-3 assume !(0 == ~E_7~0); 4337628#L946-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4337627#L951-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4337626#L430-30 assume !(1 == ~m_pc~0); 4337625#L430-32 is_master_triggered_~__retres1~0#1 := 0; 4337624#L441-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4337623#L442-10 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4337622#L1073-30 assume !(0 != activate_threads_~tmp~1#1); 4337621#L1073-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4337620#L449-30 assume !(1 == ~t1_pc~0); 4337619#L449-32 is_transmit1_triggered_~__retres1~1#1 := 0; 4337618#L460-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4337617#L461-10 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4337616#L1081-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4337615#L1081-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4337614#L468-30 assume 1 == ~t2_pc~0; 4337612#L469-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4337611#L479-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4337610#L480-10 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4337609#L1089-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4337608#L1089-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4337607#L487-30 assume !(1 == ~t3_pc~0); 4337606#L487-32 is_transmit3_triggered_~__retres1~3#1 := 0; 4337605#L498-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4337604#L499-10 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4337603#L1097-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4337602#L1097-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4337601#L506-30 assume !(1 == ~t4_pc~0); 4337600#L506-32 is_transmit4_triggered_~__retres1~4#1 := 0; 4337598#L517-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4337597#L518-10 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4337596#L1105-30 assume !(0 != activate_threads_~tmp___3~0#1); 4337595#L1105-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4337594#L525-30 assume !(1 == ~t5_pc~0); 4337593#L525-32 is_transmit5_triggered_~__retres1~5#1 := 0; 4337592#L536-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4337591#L537-10 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4337590#L1113-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4337589#L1113-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4337588#L544-30 assume 1 == ~t6_pc~0; 4337586#L545-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4337585#L555-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4337584#L556-10 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4337583#L1121-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4337582#L1121-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4337581#L563-30 assume !(1 == ~t7_pc~0); 4337580#L563-32 is_transmit7_triggered_~__retres1~7#1 := 0; 4337579#L574-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4337578#L575-10 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4337577#L1129-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4337576#L1129-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4337575#L582-30 assume !(1 == ~t8_pc~0); 4337574#L582-32 is_transmit8_triggered_~__retres1~8#1 := 0; 4337573#L593-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4337572#L594-10 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4337571#L1137-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4337570#L1137-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4337569#L964-3 assume !(1 == ~M_E~0); 4337568#L964-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4337567#L969-3 assume !(1 == ~T2_E~0); 4337566#L974-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4337565#L979-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4337564#L984-3 assume !(1 == ~T5_E~0); 4337563#L989-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4337562#L994-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4337561#L999-3 assume !(1 == ~T8_E~0); 4337560#L1004-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4337559#L1009-3 assume !(1 == ~E_1~0); 4337558#L1014-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4337557#L1019-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4337556#L1024-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4337555#L1029-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4337554#L1034-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4337553#L1039-3 assume !(1 == ~E_7~0); 4337552#L1044-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4337551#L1049-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4269927#L662-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4269925#L709-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4291955#L710-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 4291951#L1334 assume !(0 == start_simulation_~tmp~3#1); 4291953#L1334-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4296604#L662-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4270284#L709-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4270285#L710-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 4296590#L1289 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4296591#L1296 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4337430#L1297 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 4296583#L1347 assume !(0 != start_simulation_~tmp___0~1#1); 4236307#L1315-2 [2021-12-06 18:38:47,612 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:38:47,612 INFO L85 PathProgramCache]: Analyzing trace with hash 1031758985, now seen corresponding path program 4 times [2021-12-06 18:38:47,612 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:38:47,612 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [159631428] [2021-12-06 18:38:47,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:38:47,612 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:38:47,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:38:47,622 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 18:38:47,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:38:47,653 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 18:38:47,654 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:38:47,654 INFO L85 PathProgramCache]: Analyzing trace with hash 887837022, now seen corresponding path program 1 times [2021-12-06 18:38:47,654 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:38:47,654 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [763629360] [2021-12-06 18:38:47,654 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:38:47,655 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:38:47,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:38:47,688 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:38:47,688 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:38:47,688 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [763629360] [2021-12-06 18:38:47,688 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [763629360] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:38:47,688 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:38:47,689 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:38:47,689 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [455009612] [2021-12-06 18:38:47,689 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:38:47,689 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 18:38:47,689 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:38:47,690 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 18:38:47,690 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 18:38:47,690 INFO L87 Difference]: Start difference. First operand 195001 states and 270277 transitions. cyclomatic complexity: 75340 Second operand has 3 states, 3 states have (on average 40.666666666666664) internal successors, (122), 3 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:38:48,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:38:48,411 INFO L93 Difference]: Finished difference Result 304889 states and 418229 transitions. [2021-12-06 18:38:48,411 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 18:38:48,412 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 304889 states and 418229 transitions. [2021-12-06 18:38:49,703 INFO L131 ngComponentsAnalysis]: Automaton has 104 accepting balls. 303430 [2021-12-06 18:38:50,236 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 304889 states to 304889 states and 418229 transitions. [2021-12-06 18:38:50,236 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 304889 [2021-12-06 18:38:50,360 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 304889 [2021-12-06 18:38:50,360 INFO L73 IsDeterministic]: Start isDeterministic. Operand 304889 states and 418229 transitions. [2021-12-06 18:38:50,459 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:38:50,459 INFO L681 BuchiCegarLoop]: Abstraction has 304889 states and 418229 transitions. [2021-12-06 18:38:50,584 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 304889 states and 418229 transitions. [2021-12-06 18:38:52,578 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 304889 to 301369. [2021-12-06 18:38:52,745 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 301369 states, 301369 states have (on average 1.372261247839028) internal successors, (413557), 301368 states have internal predecessors, (413557), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:38:53,663 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 301369 states to 301369 states and 413557 transitions. [2021-12-06 18:38:53,663 INFO L704 BuchiCegarLoop]: Abstraction has 301369 states and 413557 transitions. [2021-12-06 18:38:53,663 INFO L587 BuchiCegarLoop]: Abstraction has 301369 states and 413557 transitions. [2021-12-06 18:38:53,663 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-12-06 18:38:53,663 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 301369 states and 413557 transitions. [2021-12-06 18:38:54,244 INFO L131 ngComponentsAnalysis]: Automaton has 104 accepting balls. 299910 [2021-12-06 18:38:54,244 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:38:54,244 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:38:54,245 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:38:54,245 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:38:54,245 INFO L791 eck$LassoCheckResult]: Stem: 4736494#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 4736495#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 4736403#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4736404#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4736226#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 4736227#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4735800#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4735801#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4735880#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4736750#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4735771#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4735772#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4736194#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4736215#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4735886#L866 assume !(0 == ~M_E~0); 4735887#L866-2 assume !(0 == ~T1_E~0); 4736434#L871-1 assume !(0 == ~T2_E~0); 4736435#L876-1 assume !(0 == ~T3_E~0); 4736849#L881-1 assume !(0 == ~T4_E~0); 4736450#L886-1 assume !(0 == ~T5_E~0); 4736183#L891-1 assume !(0 == ~T6_E~0); 4736184#L896-1 assume !(0 == ~T7_E~0); 4736438#L901-1 assume !(0 == ~T8_E~0); 4736464#L906-1 assume !(0 == ~E_M~0); 4736465#L911-1 assume !(0 == ~E_1~0); 4736224#L916-1 assume !(0 == ~E_2~0); 4736225#L921-1 assume !(0 == ~E_3~0); 4736597#L926-1 assume !(0 == ~E_4~0); 4736769#L931-1 assume !(0 == ~E_5~0); 4736870#L936-1 assume !(0 == ~E_6~0); 4736894#L941-1 assume !(0 == ~E_7~0); 4736230#L946-1 assume !(0 == ~E_8~0); 4736231#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4736808#L430 assume !(1 == ~m_pc~0); 4736717#L430-2 is_master_triggered_~__retres1~0#1 := 0; 4735708#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4735709#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4736351#L1073 assume !(0 != activate_threads_~tmp~1#1); 4736362#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4736575#L449 assume !(1 == ~t1_pc~0); 4735889#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4735890#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4735667#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4735668#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 4736479#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4736295#L468 assume !(1 == ~t2_pc~0); 4735692#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4735691#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4736191#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4736093#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 4735710#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4735711#L487 assume !(1 == ~t3_pc~0); 4735824#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4735804#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4735805#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4736557#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 4736157#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4736158#L506 assume !(1 == ~t4_pc~0); 4736288#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4736345#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4736788#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4736789#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 4736282#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4736102#L525 assume !(1 == ~t5_pc~0); 4735747#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4735748#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4736234#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4736235#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 4735949#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4735950#L544 assume !(1 == ~t6_pc~0); 4736103#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4736104#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4736504#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4735732#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 4735733#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4736734#L563 assume !(1 == ~t7_pc~0); 4736500#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4735758#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4735759#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4736190#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 4735893#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4735894#L582 assume !(1 == ~t8_pc~0); 4736505#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4736839#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4736840#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4736146#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 4736036#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4736037#L964 assume !(1 == ~M_E~0); 4736578#L964-2 assume !(1 == ~T1_E~0); 4735951#L969-1 assume !(1 == ~T2_E~0); 4735952#L974-1 assume !(1 == ~T3_E~0); 4736618#L979-1 assume !(1 == ~T4_E~0); 4736619#L984-1 assume !(1 == ~T5_E~0); 4736109#L989-1 assume !(1 == ~T6_E~0); 4736110#L994-1 assume !(1 == ~T7_E~0); 4735992#L999-1 assume !(1 == ~T8_E~0); 4735993#L1004-1 assume !(1 == ~E_M~0); 4735734#L1009-1 assume !(1 == ~E_1~0); 4735735#L1014-1 assume !(1 == ~E_2~0); 4735982#L1019-1 assume !(1 == ~E_3~0); 4736564#L1024-1 assume !(1 == ~E_4~0); 4735910#L1029-1 assume !(1 == ~E_5~0); 4735911#L1034-1 assume !(1 == ~E_6~0); 4736006#L1039-1 assume !(1 == ~E_7~0); 4736794#L1044-1 assume !(1 == ~E_8~0); 4736200#L1049-1 assume { :end_inline_reset_delta_events } true; 4736201#L1315-2 assume !false; 4769997#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4769998#L841 [2021-12-06 18:38:54,245 INFO L793 eck$LassoCheckResult]: Loop: 4769998#L841 assume !false; 4849570#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4849569#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4849568#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4849567#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4849566#L724 assume 0 != eval_~tmp~0#1; 4849565#L724-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 4849564#L732 assume !(0 != eval_~tmp_ndt_1~0#1); 4849563#L729 assume !(0 == ~t1_st~0); 4849561#L743 assume !(0 == ~t2_st~0); 4849559#L757 assume !(0 == ~t3_st~0); 4849411#L771 assume !(0 == ~t4_st~0); 4849582#L785 assume !(0 == ~t5_st~0); 4849579#L799 assume !(0 == ~t6_st~0); 4849573#L813 assume !(0 == ~t7_st~0); 4849572#L827 assume !(0 == ~t8_st~0); 4769998#L841 [2021-12-06 18:38:54,246 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:38:54,246 INFO L85 PathProgramCache]: Analyzing trace with hash -617044821, now seen corresponding path program 1 times [2021-12-06 18:38:54,246 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:38:54,246 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2012700690] [2021-12-06 18:38:54,246 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:38:54,246 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:38:54,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:38:54,252 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 18:38:54,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:38:54,276 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 18:38:54,277 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:38:54,277 INFO L85 PathProgramCache]: Analyzing trace with hash -208281481, now seen corresponding path program 1 times [2021-12-06 18:38:54,277 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:38:54,277 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1905280265] [2021-12-06 18:38:54,277 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:38:54,277 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:38:54,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:38:54,280 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 18:38:54,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:38:54,283 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 18:38:54,284 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:38:54,284 INFO L85 PathProgramCache]: Analyzing trace with hash -1043074783, now seen corresponding path program 1 times [2021-12-06 18:38:54,284 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:38:54,284 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1535163681] [2021-12-06 18:38:54,284 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:38:54,284 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:38:54,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:38:54,304 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:38:54,305 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:38:54,305 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1535163681] [2021-12-06 18:38:54,305 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1535163681] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:38:54,305 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:38:54,305 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:38:54,305 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1209258647] [2021-12-06 18:38:54,306 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:38:54,414 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:38:54,415 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 18:38:54,415 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 18:38:54,415 INFO L87 Difference]: Start difference. First operand 301369 states and 413557 transitions. cyclomatic complexity: 112292 Second operand has 3 states, 3 states have (on average 41.333333333333336) internal successors, (124), 3 states have internal predecessors, (124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:38:55,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:38:55,975 INFO L93 Difference]: Finished difference Result 577624 states and 787023 transitions. [2021-12-06 18:38:55,975 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 18:38:55,976 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 577624 states and 787023 transitions. [2021-12-06 18:38:58,288 INFO L131 ngComponentsAnalysis]: Automaton has 152 accepting balls. 565928 [2021-12-06 18:38:59,179 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 577624 states to 577624 states and 787023 transitions. [2021-12-06 18:38:59,179 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 577624 [2021-12-06 18:38:59,364 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 577624 [2021-12-06 18:38:59,364 INFO L73 IsDeterministic]: Start isDeterministic. Operand 577624 states and 787023 transitions. [2021-12-06 18:38:59,517 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:38:59,518 INFO L681 BuchiCegarLoop]: Abstraction has 577624 states and 787023 transitions. [2021-12-06 18:38:59,974 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 577624 states and 787023 transitions. [2021-12-06 18:39:03,588 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 577624 to 565048. [2021-12-06 18:39:03,886 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 565048 states, 565048 states have (on average 1.3635354872506407) internal successors, (770463), 565047 states have internal predecessors, (770463), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:39:05,535 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 565048 states to 565048 states and 770463 transitions. [2021-12-06 18:39:05,535 INFO L704 BuchiCegarLoop]: Abstraction has 565048 states and 770463 transitions. [2021-12-06 18:39:05,535 INFO L587 BuchiCegarLoop]: Abstraction has 565048 states and 770463 transitions. [2021-12-06 18:39:05,535 INFO L425 BuchiCegarLoop]: ======== Iteration 29============ [2021-12-06 18:39:05,535 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 565048 states and 770463 transitions. [2021-12-06 18:39:07,277 INFO L131 ngComponentsAnalysis]: Automaton has 152 accepting balls. 553352 [2021-12-06 18:39:07,277 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:39:07,277 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:39:07,278 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:39:07,278 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:39:07,279 INFO L791 eck$LassoCheckResult]: Stem: 5615502#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 5615503#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 5615411#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5615412#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5615236#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 5615237#L609-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 5614799#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5614800#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5615747#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5615748#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5614771#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 5614772#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 5615861#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 5615862#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5614885#L866 assume !(0 == ~M_E~0); 5614886#L866-2 assume !(0 == ~T1_E~0); 5615442#L871-1 assume !(0 == ~T2_E~0); 5615443#L876-1 assume !(0 == ~T3_E~0); 5615842#L881-1 assume !(0 == ~T4_E~0); 5615843#L886-1 assume !(0 == ~T5_E~0); 5615187#L891-1 assume !(0 == ~T6_E~0); 5615188#L896-1 assume !(0 == ~T7_E~0); 5615600#L901-1 assume !(0 == ~T8_E~0); 5615601#L906-1 assume !(0 == ~E_M~0); 5615858#L911-1 assume !(0 == ~E_1~0); 5615859#L916-1 assume !(0 == ~E_2~0); 5615603#L921-1 assume !(0 == ~E_3~0); 5615604#L926-1 assume !(0 == ~E_4~0); 5615867#L931-1 assume !(0 == ~E_5~0); 5615868#L936-1 assume !(0 == ~E_6~0); 5615926#L941-1 assume !(0 == ~E_7~0); 5615927#L946-1 assume !(0 == ~E_8~0); 5615800#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5615801#L430 assume !(1 == ~m_pc~0); 5615714#L430-2 is_master_triggered_~__retres1~0#1 := 0; 5615715#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5615363#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5615364#L1073 assume !(0 != activate_threads_~tmp~1#1); 5615833#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5615834#L449 assume !(1 == ~t1_pc~0); 5614888#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5614889#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5614668#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5614669#L1081 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5615893#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5615308#L468 assume !(1 == ~t2_pc~0); 5615309#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5615423#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5615424#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5615094#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 5615095#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5615888#L487 assume !(1 == ~t3_pc~0); 5615889#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5614803#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5614804#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5615669#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 5615670#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5615300#L506 assume !(1 == ~t4_pc~0); 5615301#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5615924#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5615925#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5615835#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 5615836#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5615106#L525 assume !(1 == ~t5_pc~0); 5615107#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5615735#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5615736#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5615916#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 5615917#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5615288#L544 assume !(1 == ~t6_pc~0); 5615289#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5615513#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5615514#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5614733#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 5614734#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5615729#L563 assume !(1 == ~t7_pc~0); 5615730#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5614759#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5614760#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5615194#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 5615195#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5615517#L582 assume !(1 == ~t8_pc~0); 5615518#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5615837#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5615838#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5615151#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 5615152#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5615583#L964 assume !(1 == ~M_E~0); 5615584#L964-2 assume !(1 == ~T1_E~0); 5614950#L969-1 assume !(1 == ~T2_E~0); 5614951#L974-1 assume !(1 == ~T3_E~0); 5615623#L979-1 assume !(1 == ~T4_E~0); 5615624#L984-1 assume !(1 == ~T5_E~0); 5615116#L989-1 assume !(1 == ~T6_E~0); 5615117#L994-1 assume !(1 == ~T7_E~0); 5614996#L999-1 assume !(1 == ~T8_E~0); 5614997#L1004-1 assume !(1 == ~E_M~0); 5614735#L1009-1 assume !(1 == ~E_1~0); 5614736#L1014-1 assume !(1 == ~E_2~0); 5615567#L1019-1 assume !(1 == ~E_3~0); 5615568#L1024-1 assume !(1 == ~E_4~0); 5614909#L1029-1 assume !(1 == ~E_5~0); 5614910#L1034-1 assume !(1 == ~E_6~0); 5615931#L1039-1 assume !(1 == ~E_7~0); 5615932#L1044-1 assume !(1 == ~E_8~0); 5615209#L1049-1 assume { :end_inline_reset_delta_events } true; 5615210#L1315-2 assume !false; 5625993#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5625994#L841 [2021-12-06 18:39:07,279 INFO L793 eck$LassoCheckResult]: Loop: 5625994#L841 assume !false; 5693942#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 5693939#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5693937#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 5693935#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5693933#L724 assume 0 != eval_~tmp~0#1; 5693929#L724-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 5693927#L732 assume !(0 != eval_~tmp_ndt_1~0#1); 5693925#L729 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 5693920#L746 assume !(0 != eval_~tmp_ndt_2~0#1); 5693921#L743 assume !(0 == ~t2_st~0); 5694163#L757 assume !(0 == ~t3_st~0); 5693962#L771 assume !(0 == ~t4_st~0); 5693960#L785 assume !(0 == ~t5_st~0); 5693957#L799 assume !(0 == ~t6_st~0); 5693949#L813 assume !(0 == ~t7_st~0); 5693947#L827 assume !(0 == ~t8_st~0); 5625994#L841 [2021-12-06 18:39:07,279 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:39:07,279 INFO L85 PathProgramCache]: Analyzing trace with hash -964259029, now seen corresponding path program 1 times [2021-12-06 18:39:07,280 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:39:07,280 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1049479341] [2021-12-06 18:39:07,280 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:39:07,280 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:39:07,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:39:07,307 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:39:07,308 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:39:07,308 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1049479341] [2021-12-06 18:39:07,308 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1049479341] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:39:07,308 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:39:07,308 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:39:07,309 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [79857774] [2021-12-06 18:39:07,309 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:39:07,309 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 18:39:07,309 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:39:07,310 INFO L85 PathProgramCache]: Analyzing trace with hash -97489926, now seen corresponding path program 1 times [2021-12-06 18:39:07,310 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:39:07,310 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1179199804] [2021-12-06 18:39:07,310 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:39:07,310 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:39:07,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:39:07,314 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 18:39:07,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:39:07,318 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 18:39:07,460 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:39:07,460 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 18:39:07,460 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 18:39:07,461 INFO L87 Difference]: Start difference. First operand 565048 states and 770463 transitions. cyclomatic complexity: 205567 Second operand has 3 states, 3 states have (on average 36.0) internal successors, (108), 3 states have internal predecessors, (108), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:39:08,844 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:39:08,844 INFO L93 Difference]: Finished difference Result 495231 states and 675354 transitions. [2021-12-06 18:39:08,844 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 18:39:08,845 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 495231 states and 675354 transitions. [2021-12-06 18:39:10,757 INFO L131 ngComponentsAnalysis]: Automaton has 88 accepting balls. 492732 [2021-12-06 18:39:11,973 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 495231 states to 495231 states and 675354 transitions. [2021-12-06 18:39:11,973 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 495231 [2021-12-06 18:39:12,132 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 495231 [2021-12-06 18:39:12,132 INFO L73 IsDeterministic]: Start isDeterministic. Operand 495231 states and 675354 transitions. [2021-12-06 18:39:12,264 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:39:12,264 INFO L681 BuchiCegarLoop]: Abstraction has 495231 states and 675354 transitions. [2021-12-06 18:39:12,433 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 495231 states and 675354 transitions. [2021-12-06 18:39:15,597 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 495231 to 495231. [2021-12-06 18:39:15,833 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 495231 states, 495231 states have (on average 1.363715114764625) internal successors, (675354), 495230 states have internal predecessors, (675354), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:39:17,275 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 495231 states to 495231 states and 675354 transitions. [2021-12-06 18:39:17,276 INFO L704 BuchiCegarLoop]: Abstraction has 495231 states and 675354 transitions. [2021-12-06 18:39:17,276 INFO L587 BuchiCegarLoop]: Abstraction has 495231 states and 675354 transitions. [2021-12-06 18:39:17,276 INFO L425 BuchiCegarLoop]: ======== Iteration 30============ [2021-12-06 18:39:17,276 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 495231 states and 675354 transitions. [2021-12-06 18:39:18,156 INFO L131 ngComponentsAnalysis]: Automaton has 88 accepting balls. 492732 [2021-12-06 18:39:18,156 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:39:18,156 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:39:18,157 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:39:18,157 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:39:18,157 INFO L791 eck$LassoCheckResult]: Stem: 6675773#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 6675774#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 6675683#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6675684#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6675514#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 6675515#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6675085#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6675086#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6675163#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6676011#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6675056#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 6675057#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 6675481#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 6675503#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6675169#L866 assume !(0 == ~M_E~0); 6675170#L866-2 assume !(0 == ~T1_E~0); 6675713#L871-1 assume !(0 == ~T2_E~0); 6675714#L876-1 assume !(0 == ~T3_E~0); 6676097#L881-1 assume !(0 == ~T4_E~0); 6675730#L886-1 assume !(0 == ~T5_E~0); 6675470#L891-1 assume !(0 == ~T6_E~0); 6675471#L896-1 assume !(0 == ~T7_E~0); 6675717#L901-1 assume !(0 == ~T8_E~0); 6675748#L906-1 assume !(0 == ~E_M~0); 6675749#L911-1 assume !(0 == ~E_1~0); 6675512#L916-1 assume !(0 == ~E_2~0); 6675513#L921-1 assume !(0 == ~E_3~0); 6675871#L926-1 assume !(0 == ~E_4~0); 6676026#L931-1 assume !(0 == ~E_5~0); 6676116#L936-1 assume !(0 == ~E_6~0); 6676133#L941-1 assume !(0 == ~E_7~0); 6675519#L946-1 assume !(0 == ~E_8~0); 6675520#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6676070#L430 assume !(1 == ~m_pc~0); 6675982#L430-2 is_master_triggered_~__retres1~0#1 := 0; 6674996#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6674997#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6675634#L1073 assume !(0 != activate_threads_~tmp~1#1); 6675647#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6675851#L449 assume !(1 == ~t1_pc~0); 6675172#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6675173#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6674953#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6674954#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 6675764#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6675583#L468 assume !(1 == ~t2_pc~0); 6674980#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6674979#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6675478#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6675379#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 6674994#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6674995#L487 assume !(1 == ~t3_pc~0); 6675109#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6675089#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6675090#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6675839#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 6675445#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6675446#L506 assume !(1 == ~t4_pc~0); 6675576#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6675631#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6676045#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6676046#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 6675573#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6675388#L525 assume !(1 == ~t5_pc~0); 6675033#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 6675034#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6675522#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6675523#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 6675232#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6675233#L544 assume !(1 == ~t6_pc~0); 6675389#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6675390#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6675784#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6675018#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 6675019#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6675996#L563 assume !(1 == ~t7_pc~0); 6675779#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 6675044#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6675045#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6675477#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 6675176#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6675177#L582 assume !(1 == ~t8_pc~0); 6675787#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 6676089#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6676090#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6675433#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 6675323#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6675324#L964 assume !(1 == ~M_E~0); 6675854#L964-2 assume !(1 == ~T1_E~0); 6675234#L969-1 assume !(1 == ~T2_E~0); 6675235#L974-1 assume !(1 == ~T3_E~0); 6675892#L979-1 assume !(1 == ~T4_E~0); 6675893#L984-1 assume !(1 == ~T5_E~0); 6675397#L989-1 assume !(1 == ~T6_E~0); 6675398#L994-1 assume !(1 == ~T7_E~0); 6675279#L999-1 assume !(1 == ~T8_E~0); 6675280#L1004-1 assume !(1 == ~E_M~0); 6675020#L1009-1 assume !(1 == ~E_1~0); 6675021#L1014-1 assume !(1 == ~E_2~0); 6675269#L1019-1 assume !(1 == ~E_3~0); 6675844#L1024-1 assume !(1 == ~E_4~0); 6675193#L1029-1 assume !(1 == ~E_5~0); 6675194#L1034-1 assume !(1 == ~E_6~0); 6675292#L1039-1 assume !(1 == ~E_7~0); 6676053#L1044-1 assume !(1 == ~E_8~0); 6675489#L1049-1 assume { :end_inline_reset_delta_events } true; 6675490#L1315-2 assume !false; 6681255#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6681256#L841 [2021-12-06 18:39:18,157 INFO L793 eck$LassoCheckResult]: Loop: 6681256#L841 assume !false; 6756755#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6756751#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6756749#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6756747#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 6756745#L724 assume 0 != eval_~tmp~0#1; 6756742#L724-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 6756740#L732 assume !(0 != eval_~tmp_ndt_1~0#1); 6756738#L729 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 6756736#L746 assume !(0 != eval_~tmp_ndt_2~0#1); 6756734#L743 assume !(0 == ~t2_st~0); 6756729#L757 assume !(0 == ~t3_st~0); 6756699#L771 assume !(0 == ~t4_st~0); 6756698#L785 assume !(0 == ~t5_st~0); 6756692#L799 assume !(0 == ~t6_st~0); 6756689#L813 assume !(0 == ~t7_st~0); 6753944#L827 assume !(0 == ~t8_st~0); 6681256#L841 [2021-12-06 18:39:18,158 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:39:18,158 INFO L85 PathProgramCache]: Analyzing trace with hash -617044821, now seen corresponding path program 2 times [2021-12-06 18:39:18,158 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:39:18,158 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [482066006] [2021-12-06 18:39:18,158 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:39:18,158 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:39:18,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:39:18,165 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 18:39:18,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:39:18,196 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 18:39:18,196 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:39:18,196 INFO L85 PathProgramCache]: Analyzing trace with hash -97489926, now seen corresponding path program 2 times [2021-12-06 18:39:18,196 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:39:18,196 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1354026485] [2021-12-06 18:39:18,197 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:39:18,197 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:39:18,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:39:18,199 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 18:39:18,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:39:18,203 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 18:39:18,203 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:39:18,203 INFO L85 PathProgramCache]: Analyzing trace with hash -206278512, now seen corresponding path program 1 times [2021-12-06 18:39:18,203 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:39:18,204 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1169382441] [2021-12-06 18:39:18,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:39:18,204 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:39:18,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:39:18,235 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:39:18,236 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:39:18,236 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1169382441] [2021-12-06 18:39:18,236 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1169382441] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:39:18,236 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:39:18,236 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:39:18,237 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1903729411] [2021-12-06 18:39:18,237 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:39:18,374 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:39:18,375 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 18:39:18,375 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 18:39:18,375 INFO L87 Difference]: Start difference. First operand 495231 states and 675354 transitions. cyclomatic complexity: 180211 Second operand has 3 states, 3 states have (on average 41.666666666666664) internal successors, (125), 3 states have internal predecessors, (125), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:39:21,139 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:39:21,139 INFO L93 Difference]: Finished difference Result 942839 states and 1281014 transitions. [2021-12-06 18:39:21,139 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 18:39:21,139 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 942839 states and 1281014 transitions. [2021-12-06 18:39:24,887 INFO L131 ngComponentsAnalysis]: Automaton has 88 accepting balls. 937952 [2021-12-06 18:39:26,774 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 942839 states to 942839 states and 1281014 transitions. [2021-12-06 18:39:26,774 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 942839 [2021-12-06 18:39:27,138 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 942839 [2021-12-06 18:39:27,138 INFO L73 IsDeterministic]: Start isDeterministic. Operand 942839 states and 1281014 transitions. [2021-12-06 18:39:27,663 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:39:27,663 INFO L681 BuchiCegarLoop]: Abstraction has 942839 states and 1281014 transitions. [2021-12-06 18:39:27,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 942839 states and 1281014 transitions. [2021-12-06 18:39:34,183 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 942839 to 896335. [2021-12-06 18:39:34,578 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 896335 states, 896335 states have (on average 1.3617832618384866) internal successors, (1220614), 896334 states have internal predecessors, (1220614), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:39:37,180 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 896335 states to 896335 states and 1220614 transitions. [2021-12-06 18:39:37,181 INFO L704 BuchiCegarLoop]: Abstraction has 896335 states and 1220614 transitions. [2021-12-06 18:39:37,181 INFO L587 BuchiCegarLoop]: Abstraction has 896335 states and 1220614 transitions. [2021-12-06 18:39:37,181 INFO L425 BuchiCegarLoop]: ======== Iteration 31============ [2021-12-06 18:39:37,181 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 896335 states and 1220614 transitions. [2021-12-06 18:39:40,209 INFO L131 ngComponentsAnalysis]: Automaton has 88 accepting balls. 891448 [2021-12-06 18:39:40,210 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:39:40,210 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:39:40,211 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:39:40,211 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:39:40,211 INFO L791 eck$LassoCheckResult]: Stem: 8113850#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 8113851#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 8113759#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8113760#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8113587#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 8113588#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8113162#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8113163#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8113241#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8114104#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8113134#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 8113135#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 8113551#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 8113576#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8113247#L866 assume !(0 == ~M_E~0); 8113248#L866-2 assume !(0 == ~T1_E~0); 8113791#L871-1 assume !(0 == ~T2_E~0); 8113792#L876-1 assume !(0 == ~T3_E~0); 8114196#L881-1 assume !(0 == ~T4_E~0); 8113805#L886-1 assume !(0 == ~T5_E~0); 8113542#L891-1 assume !(0 == ~T6_E~0); 8113543#L896-1 assume !(0 == ~T7_E~0); 8113795#L901-1 assume !(0 == ~T8_E~0); 8113822#L906-1 assume !(0 == ~E_M~0); 8113823#L911-1 assume !(0 == ~E_1~0); 8113585#L916-1 assume !(0 == ~E_2~0); 8113586#L921-1 assume !(0 == ~E_3~0); 8113951#L926-1 assume !(0 == ~E_4~0); 8114122#L931-1 assume !(0 == ~E_5~0); 8114221#L936-1 assume !(0 == ~E_6~0); 8114239#L941-1 assume !(0 == ~E_7~0); 8113591#L946-1 assume !(0 == ~E_8~0); 8113592#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8114155#L430 assume !(1 == ~m_pc~0); 8114066#L430-2 is_master_triggered_~__retres1~0#1 := 0; 8113072#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8113073#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8113710#L1073 assume !(0 != activate_threads_~tmp~1#1); 8113722#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8113928#L449 assume !(1 == ~t1_pc~0); 8113250#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8113251#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8113031#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8113032#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 8113838#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8113655#L468 assume !(1 == ~t2_pc~0); 8113056#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8113055#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8113550#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8113451#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 8113070#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8113071#L487 assume !(1 == ~t3_pc~0); 8113186#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8113166#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8113167#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8113914#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 8113517#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8113518#L506 assume !(1 == ~t4_pc~0); 8113650#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8113704#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8114137#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8114138#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 8113643#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8113463#L525 assume !(1 == ~t5_pc~0); 8113111#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8113112#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8113596#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8113597#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 8113311#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8113312#L544 assume !(1 == ~t6_pc~0); 8113464#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 8113465#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8113860#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8113096#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 8113097#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8114088#L563 assume !(1 == ~t7_pc~0); 8113855#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8113122#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8113123#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8113544#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 8113252#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8113253#L582 assume !(1 == ~t8_pc~0); 8113861#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8114184#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8114185#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8113504#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 8113400#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8113401#L964 assume !(1 == ~M_E~0); 8113930#L964-2 assume !(1 == ~T1_E~0); 8113309#L969-1 assume !(1 == ~T2_E~0); 8113310#L974-1 assume !(1 == ~T3_E~0); 8113973#L979-1 assume !(1 == ~T4_E~0); 8113974#L984-1 assume !(1 == ~T5_E~0); 8113471#L989-1 assume !(1 == ~T6_E~0); 8113472#L994-1 assume !(1 == ~T7_E~0); 8113351#L999-1 assume !(1 == ~T8_E~0); 8113352#L1004-1 assume !(1 == ~E_M~0); 8113098#L1009-1 assume !(1 == ~E_1~0); 8113099#L1014-1 assume !(1 == ~E_2~0); 8113341#L1019-1 assume !(1 == ~E_3~0); 8113918#L1024-1 assume !(1 == ~E_4~0); 8113271#L1029-1 assume !(1 == ~E_5~0); 8113272#L1034-1 assume !(1 == ~E_6~0); 8113368#L1039-1 assume !(1 == ~E_7~0); 8114142#L1044-1 assume !(1 == ~E_8~0); 8113561#L1049-1 assume { :end_inline_reset_delta_events } true; 8113562#L1315-2 assume !false; 8152497#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8152498#L841 [2021-12-06 18:39:40,211 INFO L793 eck$LassoCheckResult]: Loop: 8152498#L841 assume !false; 8283026#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8283024#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 8283023#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8283022#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8283021#L724 assume 0 != eval_~tmp~0#1; 8283019#L724-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 8283018#L732 assume !(0 != eval_~tmp_ndt_1~0#1); 8283017#L729 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 8283015#L746 assume !(0 != eval_~tmp_ndt_2~0#1); 8283016#L743 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 8161353#L760 assume !(0 != eval_~tmp_ndt_3~0#1); 8283104#L757 assume !(0 == ~t3_st~0); 8283038#L771 assume !(0 == ~t4_st~0); 8283037#L785 assume !(0 == ~t5_st~0); 8283035#L799 assume !(0 == ~t6_st~0); 8283030#L813 assume !(0 == ~t7_st~0); 8283029#L827 assume !(0 == ~t8_st~0); 8152498#L841 [2021-12-06 18:39:40,211 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:39:40,212 INFO L85 PathProgramCache]: Analyzing trace with hash -617044821, now seen corresponding path program 3 times [2021-12-06 18:39:40,212 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:39:40,212 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1921168829] [2021-12-06 18:39:40,212 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:39:40,212 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:39:40,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:39:40,221 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 18:39:40,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:39:40,255 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 18:39:40,255 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:39:40,255 INFO L85 PathProgramCache]: Analyzing trace with hash 2032108579, now seen corresponding path program 1 times [2021-12-06 18:39:40,256 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:39:40,256 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1972777714] [2021-12-06 18:39:40,256 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:39:40,257 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:39:40,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:39:40,267 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 18:39:40,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:39:40,273 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 18:39:40,274 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:39:40,274 INFO L85 PathProgramCache]: Analyzing trace with hash -1340337587, now seen corresponding path program 1 times [2021-12-06 18:39:40,274 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:39:40,275 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [636818827] [2021-12-06 18:39:40,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:39:40,275 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:39:40,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:39:40,402 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:39:40,402 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:39:40,402 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [636818827] [2021-12-06 18:39:40,402 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [636818827] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:39:40,403 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:39:40,403 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:39:40,403 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [128325585] [2021-12-06 18:39:40,403 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:39:40,578 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:39:40,582 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 18:39:40,582 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 18:39:40,583 INFO L87 Difference]: Start difference. First operand 896335 states and 1220614 transitions. cyclomatic complexity: 324367 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:39:46,098 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:39:46,115 INFO L93 Difference]: Finished difference Result 1420775 states and 1933702 transitions. [2021-12-06 18:39:46,119 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 18:39:46,119 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1420775 states and 1933702 transitions. [2021-12-06 18:39:52,127 INFO L131 ngComponentsAnalysis]: Automaton has 88 accepting balls. 1412864 [2021-12-06 18:39:55,802 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1420775 states to 1420775 states and 1933702 transitions. [2021-12-06 18:39:55,802 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1420775 [2021-12-06 18:39:56,543 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1420775 [2021-12-06 18:39:56,543 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1420775 states and 1933702 transitions. [2021-12-06 18:39:57,173 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:39:57,173 INFO L681 BuchiCegarLoop]: Abstraction has 1420775 states and 1933702 transitions. [2021-12-06 18:39:58,008 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1420775 states and 1933702 transitions. [2021-12-06 18:40:08,778 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1420775 to 1392679. [2021-12-06 18:40:10,165 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1392679 states, 1392679 states have (on average 1.362167448493156) internal successors, (1897062), 1392678 states have internal predecessors, (1897062), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:40:14,301 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1392679 states to 1392679 states and 1897062 transitions. [2021-12-06 18:40:14,301 INFO L704 BuchiCegarLoop]: Abstraction has 1392679 states and 1897062 transitions. [2021-12-06 18:40:14,301 INFO L587 BuchiCegarLoop]: Abstraction has 1392679 states and 1897062 transitions. [2021-12-06 18:40:14,301 INFO L425 BuchiCegarLoop]: ======== Iteration 32============ [2021-12-06 18:40:14,302 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1392679 states and 1897062 transitions. [2021-12-06 18:40:19,522 INFO L131 ngComponentsAnalysis]: Automaton has 88 accepting balls. 1384768 [2021-12-06 18:40:19,522 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 18:40:19,522 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 18:40:19,523 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:40:19,523 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:40:19,523 INFO L791 eck$LassoCheckResult]: Stem: 10430984#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~token~0 := 0;~local~0 := 0; 10430985#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 10430895#L1278 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10430896#L602 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10430718#L609 assume 1 == ~m_i~0;~m_st~0 := 0; 10430719#L609-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10430280#L614-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10430281#L619-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10430358#L624-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10431238#L629-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10430251#L634-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10430252#L639-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 10430682#L644-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 10430707#L649-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10430364#L866 assume !(0 == ~M_E~0); 10430365#L866-2 assume !(0 == ~T1_E~0); 10430929#L871-1 assume !(0 == ~T2_E~0); 10430930#L876-1 assume !(0 == ~T3_E~0); 10431340#L881-1 assume !(0 == ~T4_E~0); 10430940#L886-1 assume !(0 == ~T5_E~0); 10430673#L891-1 assume !(0 == ~T6_E~0); 10430674#L896-1 assume !(0 == ~T7_E~0); 10430932#L901-1 assume !(0 == ~T8_E~0); 10430955#L906-1 assume !(0 == ~E_M~0); 10430956#L911-1 assume !(0 == ~E_1~0); 10430716#L916-1 assume !(0 == ~E_2~0); 10430717#L921-1 assume !(0 == ~E_3~0); 10431087#L926-1 assume !(0 == ~E_4~0); 10431259#L931-1 assume !(0 == ~E_5~0); 10431368#L936-1 assume !(0 == ~E_6~0); 10431386#L941-1 assume !(0 == ~E_7~0); 10430722#L946-1 assume !(0 == ~E_8~0); 10430723#L951-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10431299#L430 assume !(1 == ~m_pc~0); 10431200#L430-2 is_master_triggered_~__retres1~0#1 := 0; 10430188#L441 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10430189#L442 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10430844#L1073 assume !(0 != activate_threads_~tmp~1#1); 10430857#L1073-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10431065#L449 assume !(1 == ~t1_pc~0); 10430367#L449-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10430368#L460 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10430149#L461 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10430150#L1081 assume !(0 != activate_threads_~tmp___0~0#1); 10430973#L1081-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10430787#L468 assume !(1 == ~t2_pc~0); 10430174#L468-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10430173#L479 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10430681#L480 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10430581#L1089 assume !(0 != activate_threads_~tmp___1~0#1); 10430190#L1089-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10430191#L487 assume !(1 == ~t3_pc~0); 10430304#L487-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10430284#L498 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10430285#L499 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10431049#L1097 assume !(0 != activate_threads_~tmp___2~0#1); 10430648#L1097-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10430649#L506 assume !(1 == ~t4_pc~0); 10430782#L506-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10430839#L517 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10431280#L518 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10431281#L1105 assume !(0 != activate_threads_~tmp___3~0#1); 10430774#L1105-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10430594#L525 assume !(1 == ~t5_pc~0); 10430229#L525-2 is_transmit5_triggered_~__retres1~5#1 := 0; 10430230#L536 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10430726#L537 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10430727#L1113 assume !(0 != activate_threads_~tmp___4~0#1); 10430429#L1113-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10430430#L544 assume !(1 == ~t6_pc~0); 10430595#L544-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10430596#L555 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10430994#L556 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10430214#L1121 assume !(0 != activate_threads_~tmp___5~0#1); 10430215#L1121-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10431222#L563 assume !(1 == ~t7_pc~0); 10430991#L563-2 is_transmit7_triggered_~__retres1~7#1 := 0; 10430240#L574 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10430241#L575 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10430675#L1129 assume !(0 != activate_threads_~tmp___6~0#1); 10430369#L1129-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10430370#L582 assume !(1 == ~t8_pc~0); 10430995#L582-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10431329#L593 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10431330#L594 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10430636#L1137 assume !(0 != activate_threads_~tmp___7~0#1); 10430525#L1137-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10430526#L964 assume !(1 == ~M_E~0); 10431067#L964-2 assume !(1 == ~T1_E~0); 10430431#L969-1 assume !(1 == ~T2_E~0); 10430432#L974-1 assume !(1 == ~T3_E~0); 10431107#L979-1 assume !(1 == ~T4_E~0); 10431108#L984-1 assume !(1 == ~T5_E~0); 10430603#L989-1 assume !(1 == ~T6_E~0); 10430604#L994-1 assume !(1 == ~T7_E~0); 10430474#L999-1 assume !(1 == ~T8_E~0); 10430475#L1004-1 assume !(1 == ~E_M~0); 10430216#L1009-1 assume !(1 == ~E_1~0); 10430217#L1014-1 assume !(1 == ~E_2~0); 10430463#L1019-1 assume !(1 == ~E_3~0); 10431054#L1024-1 assume !(1 == ~E_4~0); 10430388#L1029-1 assume !(1 == ~E_5~0); 10430389#L1034-1 assume !(1 == ~E_6~0); 10430490#L1039-1 assume !(1 == ~E_7~0); 10431286#L1044-1 assume !(1 == ~E_8~0); 10430691#L1049-1 assume { :end_inline_reset_delta_events } true; 10430692#L1315-2 assume !false; 10698866#L1316 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10698864#L841 [2021-12-06 18:40:19,524 INFO L793 eck$LassoCheckResult]: Loop: 10698864#L841 assume !false; 10698862#L720 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10698859#L662 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 10698857#L709 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 10698855#L710 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 10698853#L724 assume 0 != eval_~tmp~0#1; 10698851#L724-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 10698808#L732 assume !(0 != eval_~tmp_ndt_1~0#1); 10698774#L729 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 10688041#L746 assume !(0 != eval_~tmp_ndt_2~0#1); 10688042#L743 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 10699062#L760 assume !(0 != eval_~tmp_ndt_3~0#1); 10699058#L757 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 10699055#L774 assume !(0 != eval_~tmp_ndt_4~0#1); 10699050#L771 assume !(0 == ~t4_st~0); 10699049#L785 assume !(0 == ~t5_st~0); 10698876#L799 assume !(0 == ~t6_st~0); 10698870#L813 assume !(0 == ~t7_st~0); 10698869#L827 assume !(0 == ~t8_st~0); 10698864#L841 [2021-12-06 18:40:19,524 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:40:19,524 INFO L85 PathProgramCache]: Analyzing trace with hash -617044821, now seen corresponding path program 4 times [2021-12-06 18:40:19,524 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:40:19,524 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1447765394] [2021-12-06 18:40:19,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:40:19,525 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:40:19,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:40:19,533 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 18:40:19,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:40:19,563 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 18:40:19,563 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:40:19,564 INFO L85 PathProgramCache]: Analyzing trace with hash 396469326, now seen corresponding path program 1 times [2021-12-06 18:40:19,564 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:40:19,564 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [4424718] [2021-12-06 18:40:19,564 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:40:19,564 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:40:19,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:40:19,568 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 18:40:19,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 18:40:19,572 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 18:40:19,572 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:40:19,573 INFO L85 PathProgramCache]: Analyzing trace with hash -1070146716, now seen corresponding path program 1 times [2021-12-06 18:40:19,573 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:40:19,573 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1125230426] [2021-12-06 18:40:19,573 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:40:19,573 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:40:19,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:40:19,604 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:40:19,604 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:40:19,604 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1125230426] [2021-12-06 18:40:19,604 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1125230426] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:40:19,605 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:40:19,605 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:40:19,605 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [70589368] [2021-12-06 18:40:19,605 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:40:19,786 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:40:19,786 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 18:40:19,786 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 18:40:19,787 INFO L87 Difference]: Start difference. First operand 1392679 states and 1897062 transitions. cyclomatic complexity: 504471 Second operand has 3 states, 3 states have (on average 42.333333333333336) internal successors, (127), 3 states have internal predecessors, (127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)