./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.09.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 839c364b Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7665f81f-dec0-4c14-9b31-703379b68a01/bin/uautomizer-DrprNOufMa/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7665f81f-dec0-4c14-9b31-703379b68a01/bin/uautomizer-DrprNOufMa/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7665f81f-dec0-4c14-9b31-703379b68a01/bin/uautomizer-DrprNOufMa/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7665f81f-dec0-4c14-9b31-703379b68a01/bin/uautomizer-DrprNOufMa/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.09.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7665f81f-dec0-4c14-9b31-703379b68a01/bin/uautomizer-DrprNOufMa/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7665f81f-dec0-4c14-9b31-703379b68a01/bin/uautomizer-DrprNOufMa --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 834ccc2d6e5ce947bfece9c1e11f57131346eaac8927553a9495d7568350ac6e --- Real Ultimate output --- This is Ultimate 0.2.2-hotfix-svcomp22-839c364 [2021-12-06 17:16:47,178 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-06 17:16:47,180 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-06 17:16:47,201 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-06 17:16:47,202 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-06 17:16:47,203 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-06 17:16:47,204 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-06 17:16:47,205 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-06 17:16:47,207 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-06 17:16:47,208 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-06 17:16:47,209 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-06 17:16:47,210 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-06 17:16:47,210 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-06 17:16:47,211 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-06 17:16:47,212 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-06 17:16:47,213 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-06 17:16:47,214 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-06 17:16:47,215 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-06 17:16:47,216 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-06 17:16:47,218 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-06 17:16:47,220 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-06 17:16:47,221 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-06 17:16:47,222 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-06 17:16:47,222 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-06 17:16:47,225 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-06 17:16:47,226 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-06 17:16:47,226 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-06 17:16:47,227 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-06 17:16:47,227 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-06 17:16:47,228 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-06 17:16:47,228 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-06 17:16:47,229 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-06 17:16:47,229 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-06 17:16:47,230 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-06 17:16:47,231 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-06 17:16:47,231 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-06 17:16:47,231 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-06 17:16:47,231 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-06 17:16:47,231 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-06 17:16:47,232 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-06 17:16:47,233 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-06 17:16:47,233 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7665f81f-dec0-4c14-9b31-703379b68a01/bin/uautomizer-DrprNOufMa/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-06 17:16:47,250 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-06 17:16:47,250 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-06 17:16:47,251 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-06 17:16:47,251 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-06 17:16:47,252 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-06 17:16:47,252 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-06 17:16:47,252 INFO L138 SettingsManager]: * Use SBE=true [2021-12-06 17:16:47,252 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-06 17:16:47,252 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-06 17:16:47,252 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-06 17:16:47,252 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-06 17:16:47,252 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-06 17:16:47,253 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-06 17:16:47,253 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-06 17:16:47,253 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-06 17:16:47,253 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-06 17:16:47,253 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-06 17:16:47,253 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-06 17:16:47,253 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-06 17:16:47,253 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-06 17:16:47,254 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-06 17:16:47,254 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-06 17:16:47,254 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-06 17:16:47,254 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-06 17:16:47,254 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-06 17:16:47,254 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-06 17:16:47,254 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-06 17:16:47,254 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-06 17:16:47,255 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-06 17:16:47,255 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-06 17:16:47,255 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-06 17:16:47,255 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-06 17:16:47,256 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-06 17:16:47,256 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7665f81f-dec0-4c14-9b31-703379b68a01/bin/uautomizer-DrprNOufMa/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7665f81f-dec0-4c14-9b31-703379b68a01/bin/uautomizer-DrprNOufMa Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 834ccc2d6e5ce947bfece9c1e11f57131346eaac8927553a9495d7568350ac6e [2021-12-06 17:16:47,429 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-06 17:16:47,445 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-06 17:16:47,448 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-06 17:16:47,449 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-06 17:16:47,450 INFO L275 PluginConnector]: CDTParser initialized [2021-12-06 17:16:47,451 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7665f81f-dec0-4c14-9b31-703379b68a01/bin/uautomizer-DrprNOufMa/../../sv-benchmarks/c/systemc/token_ring.09.cil-1.c [2021-12-06 17:16:47,493 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7665f81f-dec0-4c14-9b31-703379b68a01/bin/uautomizer-DrprNOufMa/data/6b8a29c85/17e74e7ce4e1420a9f21a9e8fde31ec8/FLAG7750652aa [2021-12-06 17:16:47,905 INFO L306 CDTParser]: Found 1 translation units. [2021-12-06 17:16:47,906 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7665f81f-dec0-4c14-9b31-703379b68a01/sv-benchmarks/c/systemc/token_ring.09.cil-1.c [2021-12-06 17:16:47,915 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7665f81f-dec0-4c14-9b31-703379b68a01/bin/uautomizer-DrprNOufMa/data/6b8a29c85/17e74e7ce4e1420a9f21a9e8fde31ec8/FLAG7750652aa [2021-12-06 17:16:47,926 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7665f81f-dec0-4c14-9b31-703379b68a01/bin/uautomizer-DrprNOufMa/data/6b8a29c85/17e74e7ce4e1420a9f21a9e8fde31ec8 [2021-12-06 17:16:47,928 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-06 17:16:47,929 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-06 17:16:47,931 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-06 17:16:47,931 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-06 17:16:47,933 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-06 17:16:47,934 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 05:16:47" (1/1) ... [2021-12-06 17:16:47,935 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2562737 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:47, skipping insertion in model container [2021-12-06 17:16:47,935 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 05:16:47" (1/1) ... [2021-12-06 17:16:47,940 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-06 17:16:47,967 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-06 17:16:48,070 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7665f81f-dec0-4c14-9b31-703379b68a01/sv-benchmarks/c/systemc/token_ring.09.cil-1.c[671,684] [2021-12-06 17:16:48,139 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-06 17:16:48,146 INFO L203 MainTranslator]: Completed pre-run [2021-12-06 17:16:48,155 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7665f81f-dec0-4c14-9b31-703379b68a01/sv-benchmarks/c/systemc/token_ring.09.cil-1.c[671,684] [2021-12-06 17:16:48,193 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-06 17:16:48,207 INFO L208 MainTranslator]: Completed translation [2021-12-06 17:16:48,207 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:48 WrapperNode [2021-12-06 17:16:48,207 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-06 17:16:48,208 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-06 17:16:48,208 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-06 17:16:48,208 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-06 17:16:48,214 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:48" (1/1) ... [2021-12-06 17:16:48,223 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:48" (1/1) ... [2021-12-06 17:16:48,278 INFO L137 Inliner]: procedures = 46, calls = 58, calls flagged for inlining = 53, calls inlined = 182, statements flattened = 2757 [2021-12-06 17:16:48,279 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-06 17:16:48,279 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-06 17:16:48,279 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-06 17:16:48,279 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-06 17:16:48,286 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:48" (1/1) ... [2021-12-06 17:16:48,286 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:48" (1/1) ... [2021-12-06 17:16:48,294 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:48" (1/1) ... [2021-12-06 17:16:48,294 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:48" (1/1) ... [2021-12-06 17:16:48,321 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:48" (1/1) ... [2021-12-06 17:16:48,342 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:48" (1/1) ... [2021-12-06 17:16:48,346 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:48" (1/1) ... [2021-12-06 17:16:48,356 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-06 17:16:48,357 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-06 17:16:48,357 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-06 17:16:48,357 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-06 17:16:48,358 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:48" (1/1) ... [2021-12-06 17:16:48,364 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 17:16:48,373 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7665f81f-dec0-4c14-9b31-703379b68a01/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 17:16:48,382 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7665f81f-dec0-4c14-9b31-703379b68a01/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 17:16:48,384 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7665f81f-dec0-4c14-9b31-703379b68a01/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-06 17:16:48,411 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-06 17:16:48,411 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-06 17:16:48,411 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-06 17:16:48,412 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-06 17:16:48,486 INFO L236 CfgBuilder]: Building ICFG [2021-12-06 17:16:48,487 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-06 17:16:49,455 INFO L277 CfgBuilder]: Performing block encoding [2021-12-06 17:16:49,473 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-06 17:16:49,473 INFO L301 CfgBuilder]: Removed 12 assume(true) statements. [2021-12-06 17:16:49,476 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 05:16:49 BoogieIcfgContainer [2021-12-06 17:16:49,476 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-06 17:16:49,477 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-06 17:16:49,477 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-06 17:16:49,480 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-06 17:16:49,480 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 17:16:49,480 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.12 05:16:47" (1/3) ... [2021-12-06 17:16:49,481 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@20d00c7d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.12 05:16:49, skipping insertion in model container [2021-12-06 17:16:49,481 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 17:16:49,481 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:16:48" (2/3) ... [2021-12-06 17:16:49,481 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@20d00c7d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.12 05:16:49, skipping insertion in model container [2021-12-06 17:16:49,481 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 17:16:49,481 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 05:16:49" (3/3) ... [2021-12-06 17:16:49,482 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.09.cil-1.c [2021-12-06 17:16:49,523 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-06 17:16:49,524 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-06 17:16:49,524 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-06 17:16:49,524 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-06 17:16:49,524 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-06 17:16:49,524 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-06 17:16:49,524 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-06 17:16:49,524 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-06 17:16:49,563 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1176 states, 1175 states have (on average 1.509787234042553) internal successors, (1774), 1175 states have internal predecessors, (1774), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:49,617 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1045 [2021-12-06 17:16:49,617 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:49,617 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:49,629 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:49,629 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:49,629 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-06 17:16:49,631 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1176 states, 1175 states have (on average 1.509787234042553) internal successors, (1774), 1175 states have internal predecessors, (1774), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:49,641 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1045 [2021-12-06 17:16:49,642 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:49,642 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:49,645 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:49,645 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:49,652 INFO L791 eck$LassoCheckResult]: Stem: 548#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1061#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 500#L1391true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 867#L651true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 751#L658true assume !(1 == ~m_i~0);~m_st~0 := 2; 400#L658-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 772#L663-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 716#L668-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 275#L673-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 811#L678-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 623#L683-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1030#L688-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10#L693-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 106#L698-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 335#L703-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1020#L939true assume !(0 == ~M_E~0); 531#L939-2true assume !(0 == ~T1_E~0); 745#L944-1true assume !(0 == ~T2_E~0); 356#L949-1true assume !(0 == ~T3_E~0); 354#L954-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1069#L959-1true assume !(0 == ~T5_E~0); 773#L964-1true assume !(0 == ~T6_E~0); 187#L969-1true assume !(0 == ~T7_E~0); 888#L974-1true assume !(0 == ~T8_E~0); 703#L979-1true assume !(0 == ~T9_E~0); 1096#L984-1true assume !(0 == ~E_M~0); 282#L989-1true assume !(0 == ~E_1~0); 510#L994-1true assume 0 == ~E_2~0;~E_2~0 := 1; 214#L999-1true assume !(0 == ~E_3~0); 670#L1004-1true assume !(0 == ~E_4~0); 40#L1009-1true assume !(0 == ~E_5~0); 209#L1014-1true assume !(0 == ~E_6~0); 630#L1019-1true assume !(0 == ~E_7~0); 938#L1024-1true assume !(0 == ~E_8~0); 170#L1029-1true assume !(0 == ~E_9~0); 222#L1034-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 953#L460true assume 1 == ~m_pc~0; 3#L461true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 596#L471true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1051#L472true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1024#L1167true assume !(0 != activate_threads_~tmp~1#1); 346#L1167-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 493#L479true assume 1 == ~t1_pc~0; 336#L480true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1040#L490true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 891#L491true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 177#L1175true assume !(0 != activate_threads_~tmp___0~0#1); 388#L1175-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 98#L498true assume !(1 == ~t2_pc~0); 639#L498-2true is_transmit2_triggered_~__retres1~2#1 := 0; 334#L509true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 831#L510true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 671#L1183true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 587#L1183-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1120#L517true assume 1 == ~t3_pc~0; 899#L518true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1063#L528true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 383#L529true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 195#L1191true assume !(0 != activate_threads_~tmp___2~0#1); 641#L1191-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 812#L536true assume !(1 == ~t4_pc~0); 1098#L536-2true is_transmit4_triggered_~__retres1~4#1 := 0; 762#L547true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1087#L548true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 373#L1199true assume !(0 != activate_threads_~tmp___3~0#1); 1085#L1199-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 559#L555true assume 1 == ~t5_pc~0; 1165#L556true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 700#L566true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55#L567true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 171#L1207true assume !(0 != activate_threads_~tmp___4~0#1); 109#L1207-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 59#L574true assume !(1 == ~t6_pc~0); 632#L574-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1102#L585true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 112#L586true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 665#L1215true assume !(0 != activate_threads_~tmp___5~0#1); 1093#L1215-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 968#L593true assume 1 == ~t7_pc~0; 1138#L594true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 778#L604true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1084#L605true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1078#L1223true assume !(0 != activate_threads_~tmp___6~0#1); 902#L1223-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 280#L612true assume !(1 == ~t8_pc~0); 1017#L612-2true is_transmit8_triggered_~__retres1~8#1 := 0; 892#L623true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 474#L624true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 807#L1231true assume !(0 != activate_threads_~tmp___7~0#1); 444#L1231-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 499#L631true assume 1 == ~t9_pc~0; 456#L632true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 54#L642true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39#L643true activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 337#L1239true assume !(0 != activate_threads_~tmp___8~0#1); 1050#L1239-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 643#L1047true assume !(1 == ~M_E~0); 26#L1047-2true assume 1 == ~T1_E~0;~T1_E~0 := 2; 438#L1052-1true assume !(1 == ~T2_E~0); 18#L1057-1true assume !(1 == ~T3_E~0); 161#L1062-1true assume !(1 == ~T4_E~0); 774#L1067-1true assume !(1 == ~T5_E~0); 348#L1072-1true assume !(1 == ~T6_E~0); 611#L1077-1true assume !(1 == ~T7_E~0); 104#L1082-1true assume !(1 == ~T8_E~0); 419#L1087-1true assume 1 == ~T9_E~0;~T9_E~0 := 2; 6#L1092-1true assume !(1 == ~E_M~0); 19#L1097-1true assume !(1 == ~E_1~0); 942#L1102-1true assume !(1 == ~E_2~0); 495#L1107-1true assume !(1 == ~E_3~0); 440#L1112-1true assume !(1 == ~E_4~0); 475#L1117-1true assume !(1 == ~E_5~0); 1153#L1122-1true assume !(1 == ~E_6~0); 384#L1127-1true assume 1 == ~E_7~0;~E_7~0 := 2; 224#L1132-1true assume !(1 == ~E_8~0); 946#L1137-1true assume !(1 == ~E_9~0); 160#L1142-1true assume { :end_inline_reset_delta_events } true; 90#L1428-2true [2021-12-06 17:16:49,654 INFO L793 eck$LassoCheckResult]: Loop: 90#L1428-2true assume !false; 437#L1429true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 971#L914true assume false; 216#L929true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 494#L651-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 759#L939-3true assume !(0 == ~M_E~0); 117#L939-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 144#L944-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 5#L949-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 719#L954-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 360#L959-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 41#L964-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 268#L969-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 143#L974-3true assume !(0 == ~T8_E~0); 1055#L979-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 414#L984-3true assume 0 == ~E_M~0;~E_M~0 := 1; 1142#L989-3true assume 0 == ~E_1~0;~E_1~0 := 1; 174#L994-3true assume 0 == ~E_2~0;~E_2~0 := 1; 969#L999-3true assume 0 == ~E_3~0;~E_3~0 := 1; 538#L1004-3true assume 0 == ~E_4~0;~E_4~0 := 1; 82#L1009-3true assume 0 == ~E_5~0;~E_5~0 := 1; 617#L1014-3true assume !(0 == ~E_6~0); 401#L1019-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1113#L1024-3true assume 0 == ~E_8~0;~E_8~0 := 1; 391#L1029-3true assume 0 == ~E_9~0;~E_9~0 := 1; 362#L1034-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 922#L460-33true assume !(1 == ~m_pc~0); 571#L460-35true is_master_triggered_~__retres1~0#1 := 0; 550#L471-11true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 226#L472-11true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9#L1167-33true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 501#L1167-35true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 190#L479-33true assume 1 == ~t1_pc~0; 934#L480-11true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 172#L490-11true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 605#L491-11true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 870#L1175-33true assume !(0 != activate_threads_~tmp___0~0#1); 992#L1175-35true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 194#L498-33true assume !(1 == ~t2_pc~0); 61#L498-35true is_transmit2_triggered_~__retres1~2#1 := 0; 321#L509-11true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 130#L510-11true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 429#L1183-33true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 118#L1183-35true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1000#L517-33true assume !(1 == ~t3_pc~0); 1111#L517-35true is_transmit3_triggered_~__retres1~3#1 := 0; 737#L528-11true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1091#L529-11true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 525#L1191-33true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 666#L1191-35true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 250#L536-33true assume 1 == ~t4_pc~0; 598#L537-11true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 290#L547-11true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 418#L548-11true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 709#L1199-33true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 813#L1199-35true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30#L555-33true assume !(1 == ~t5_pc~0); 800#L555-35true is_transmit5_triggered_~__retres1~5#1 := 0; 470#L566-11true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 166#L567-11true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 490#L1207-33true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1034#L1207-35true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17#L574-33true assume 1 == ~t6_pc~0; 722#L575-11true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 846#L585-11true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 175#L586-11true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 572#L1215-33true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 332#L1215-35true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51#L593-33true assume 1 == ~t7_pc~0; 399#L594-11true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 954#L604-11true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 103#L605-11true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 549#L1223-33true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 695#L1223-35true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1119#L612-33true assume 1 == ~t8_pc~0; 919#L613-11true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 853#L623-11true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1088#L624-11true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 610#L1231-33true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 102#L1231-35true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1162#L631-33true assume !(1 == ~t9_pc~0); 497#L631-35true is_transmit9_triggered_~__retres1~9#1 := 0; 73#L642-11true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 404#L643-11true activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 208#L1239-33true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 131#L1239-35true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 227#L1047-3true assume !(1 == ~M_E~0); 771#L1047-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1173#L1052-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 677#L1057-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1167#L1062-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 79#L1067-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1025#L1072-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 295#L1077-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 199#L1082-3true assume !(1 == ~T8_E~0); 248#L1087-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 434#L1092-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1178#L1097-3true assume 1 == ~E_1~0;~E_1~0 := 2; 382#L1102-3true assume 1 == ~E_2~0;~E_2~0 := 2; 952#L1107-3true assume 1 == ~E_3~0;~E_3~0 := 2; 728#L1112-3true assume 1 == ~E_4~0;~E_4~0 := 2; 196#L1117-3true assume 1 == ~E_5~0;~E_5~0 := 2; 735#L1122-3true assume !(1 == ~E_6~0); 228#L1127-3true assume 1 == ~E_7~0;~E_7~0 := 2; 509#L1132-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1080#L1137-3true assume 1 == ~E_9~0;~E_9~0 := 2; 486#L1142-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 133#L716-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 492#L768-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 487#L769-1true start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 307#L1447true assume !(0 == start_simulation_~tmp~3#1); 702#L1447-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1140#L716-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 732#L768-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 511#L769-2true stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 213#L1402true assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 85#L1409true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 533#L1410true start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 349#L1460true assume !(0 != start_simulation_~tmp___0~1#1); 90#L1428-2true [2021-12-06 17:16:49,659 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:49,659 INFO L85 PathProgramCache]: Analyzing trace with hash -986421749, now seen corresponding path program 1 times [2021-12-06 17:16:49,666 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:49,666 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1825432289] [2021-12-06 17:16:49,667 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:49,667 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:49,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:49,825 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:49,826 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:49,826 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1825432289] [2021-12-06 17:16:49,826 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1825432289] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:49,826 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:49,827 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:49,828 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1249281457] [2021-12-06 17:16:49,828 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:49,833 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:49,834 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:49,834 INFO L85 PathProgramCache]: Analyzing trace with hash -1744542878, now seen corresponding path program 1 times [2021-12-06 17:16:49,835 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:49,835 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1643526389] [2021-12-06 17:16:49,835 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:49,835 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:49,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:49,881 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:49,881 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:49,882 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1643526389] [2021-12-06 17:16:49,882 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1643526389] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:49,882 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:49,882 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 17:16:49,882 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [429241279] [2021-12-06 17:16:49,882 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:49,883 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:49,884 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:49,907 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:16:49,908 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:16:49,912 INFO L87 Difference]: Start difference. First operand has 1176 states, 1175 states have (on average 1.509787234042553) internal successors, (1774), 1175 states have internal predecessors, (1774), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:49,983 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:49,983 INFO L93 Difference]: Finished difference Result 1175 states and 1747 transitions. [2021-12-06 17:16:49,984 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:16:49,988 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1747 transitions. [2021-12-06 17:16:49,997 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2021-12-06 17:16:50,008 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1170 states and 1742 transitions. [2021-12-06 17:16:50,009 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2021-12-06 17:16:50,010 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2021-12-06 17:16:50,011 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1742 transitions. [2021-12-06 17:16:50,016 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:50,016 INFO L681 BuchiCegarLoop]: Abstraction has 1170 states and 1742 transitions. [2021-12-06 17:16:50,030 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1742 transitions. [2021-12-06 17:16:50,083 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1170. [2021-12-06 17:16:50,086 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1170 states, 1170 states have (on average 1.488888888888889) internal successors, (1742), 1169 states have internal predecessors, (1742), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:50,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 1170 states and 1742 transitions. [2021-12-06 17:16:50,093 INFO L704 BuchiCegarLoop]: Abstraction has 1170 states and 1742 transitions. [2021-12-06 17:16:50,093 INFO L587 BuchiCegarLoop]: Abstraction has 1170 states and 1742 transitions. [2021-12-06 17:16:50,093 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-06 17:16:50,093 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1170 states and 1742 transitions. [2021-12-06 17:16:50,101 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2021-12-06 17:16:50,101 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:50,101 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:50,105 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:50,105 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:50,106 INFO L791 eck$LassoCheckResult]: Stem: 3232#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 3233#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 3182#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3183#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3401#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 3068#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3069#L663-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3378#L668-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2877#L673-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2878#L678-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3306#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3307#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2376#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2377#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2580#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2968#L939 assume !(0 == ~M_E~0); 3212#L939-2 assume !(0 == ~T1_E~0); 3213#L944-1 assume !(0 == ~T2_E~0); 2997#L949-1 assume !(0 == ~T3_E~0); 2995#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2996#L959-1 assume !(0 == ~T5_E~0); 3415#L964-1 assume !(0 == ~T6_E~0); 2728#L969-1 assume !(0 == ~T7_E~0); 2729#L974-1 assume !(0 == ~T8_E~0); 3366#L979-1 assume !(0 == ~T9_E~0); 3367#L984-1 assume !(0 == ~E_M~0); 2889#L989-1 assume !(0 == ~E_1~0); 2890#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 2778#L999-1 assume !(0 == ~E_3~0); 2779#L1004-1 assume !(0 == ~E_4~0); 2444#L1009-1 assume !(0 == ~E_5~0); 2445#L1014-1 assume !(0 == ~E_6~0); 2772#L1019-1 assume !(0 == ~E_7~0); 3311#L1024-1 assume !(0 == ~E_8~0); 2701#L1029-1 assume !(0 == ~E_9~0); 2702#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2792#L460 assume 1 == ~m_pc~0; 2360#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2361#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3277#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3516#L1167 assume !(0 != activate_threads_~tmp~1#1); 2985#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2986#L479 assume 1 == ~t1_pc~0; 2969#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2970#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3473#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2713#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 2714#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2562#L498 assume !(1 == ~t2_pc~0); 2563#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2966#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2967#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3344#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3268#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3269#L517 assume 1 == ~t3_pc~0; 3477#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3478#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3040#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2746#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 2747#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3322#L536 assume !(1 == ~t4_pc~0); 3030#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3029#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3406#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3022#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 3023#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3242#L555 assume 1 == ~t5_pc~0; 3243#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3312#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2475#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2476#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 2583#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2483#L574 assume !(1 == ~t6_pc~0); 2484#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3115#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2588#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2589#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 3340#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3500#L593 assume 1 == ~t7_pc~0; 3501#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2720#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3418#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3521#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 3481#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2884#L612 assume !(1 == ~t8_pc~0); 2885#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3294#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3152#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3153#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 3117#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3118#L631 assume 1 == ~t9_pc~0; 3136#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2474#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2442#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2443#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 2972#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3323#L1047 assume !(1 == ~M_E~0); 2412#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2413#L1052-1 assume !(1 == ~T2_E~0); 2395#L1057-1 assume !(1 == ~T3_E~0); 2396#L1062-1 assume !(1 == ~T4_E~0); 2685#L1067-1 assume !(1 == ~T5_E~0); 2988#L1072-1 assume !(1 == ~T6_E~0); 2989#L1077-1 assume !(1 == ~T7_E~0); 2576#L1082-1 assume !(1 == ~T8_E~0); 2577#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2370#L1092-1 assume !(1 == ~E_M~0); 2371#L1097-1 assume !(1 == ~E_1~0); 2397#L1102-1 assume !(1 == ~E_2~0); 3178#L1107-1 assume !(1 == ~E_3~0); 3113#L1112-1 assume !(1 == ~E_4~0); 3114#L1117-1 assume !(1 == ~E_5~0); 3154#L1122-1 assume !(1 == ~E_6~0); 3041#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 2797#L1132-1 assume !(1 == ~E_8~0); 2798#L1137-1 assume !(1 == ~E_9~0); 2684#L1142-1 assume { :end_inline_reset_delta_events } true; 2544#L1428-2 [2021-12-06 17:16:50,107 INFO L793 eck$LassoCheckResult]: Loop: 2544#L1428-2 assume !false; 2545#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2619#L914 assume !false; 3109#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3110#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2381#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2382#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3341#L783 assume !(0 != eval_~tmp~0#1); 2781#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2782#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3177#L939-3 assume !(0 == ~M_E~0); 2600#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2601#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2366#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2367#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3003#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2446#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2447#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2653#L974-3 assume !(0 == ~T8_E~0); 2654#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3084#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3085#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2707#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2708#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3219#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2530#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2531#L1014-3 assume !(0 == ~E_6~0); 3070#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3071#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3052#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3004#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3005#L460-33 assume 1 == ~m_pc~0; 3042#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3043#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2799#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2374#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2375#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2736#L479-33 assume !(1 == ~t1_pc~0); 2737#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 2703#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2704#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3288#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 3461#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2744#L498-33 assume 1 == ~t2_pc~0; 2745#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2490#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2626#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2627#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2602#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2603#L517-33 assume !(1 == ~t3_pc~0); 3509#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 3392#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3393#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3205#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3206#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2831#L536-33 assume 1 == ~t4_pc~0; 2832#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2901#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2902#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3092#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3371#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2421#L555-33 assume !(1 == ~t5_pc~0); 2422#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 3147#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2694#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2695#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3174#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2387#L574-33 assume 1 == ~t6_pc~0; 2388#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3383#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2709#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2710#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2963#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2463#L593-33 assume !(1 == ~t7_pc~0); 2464#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 2919#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2574#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2575#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3234#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3361#L612-33 assume 1 == ~t8_pc~0; 3488#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3452#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3453#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3295#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2570#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2571#L631-33 assume 1 == ~t9_pc~0; 3413#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2512#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2513#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2767#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2624#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2625#L1047-3 assume !(1 == ~M_E~0); 2800#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3414#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3346#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3347#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2525#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2526#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2908#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2753#L1082-3 assume !(1 == ~T8_E~0); 2754#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2827#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3108#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3038#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3039#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3384#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2748#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2749#L1122-3 assume !(1 == ~E_6~0); 2801#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2802#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3191#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3168#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2628#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2506#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3169#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2926#L1447 assume !(0 == start_simulation_~tmp~3#1); 2927#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3365#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2667#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3192#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 2777#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 2534#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2535#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 2990#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 2544#L1428-2 [2021-12-06 17:16:50,108 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:50,108 INFO L85 PathProgramCache]: Analyzing trace with hash 1581400585, now seen corresponding path program 1 times [2021-12-06 17:16:50,108 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:50,108 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [621389091] [2021-12-06 17:16:50,109 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:50,109 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:50,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:50,181 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:50,181 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:50,181 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [621389091] [2021-12-06 17:16:50,181 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [621389091] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:50,181 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:50,181 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:50,182 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1780089862] [2021-12-06 17:16:50,182 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:50,182 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:50,183 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:50,183 INFO L85 PathProgramCache]: Analyzing trace with hash 250029902, now seen corresponding path program 1 times [2021-12-06 17:16:50,183 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:50,184 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [869235681] [2021-12-06 17:16:50,184 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:50,184 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:50,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:50,264 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:50,264 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:50,264 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [869235681] [2021-12-06 17:16:50,265 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [869235681] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:50,265 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:50,265 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:50,265 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [775996471] [2021-12-06 17:16:50,265 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:50,266 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:50,266 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:50,267 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:16:50,267 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:16:50,267 INFO L87 Difference]: Start difference. First operand 1170 states and 1742 transitions. cyclomatic complexity: 573 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:50,298 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:50,298 INFO L93 Difference]: Finished difference Result 1170 states and 1741 transitions. [2021-12-06 17:16:50,298 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:16:50,299 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1170 states and 1741 transitions. [2021-12-06 17:16:50,309 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2021-12-06 17:16:50,319 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1170 states to 1170 states and 1741 transitions. [2021-12-06 17:16:50,319 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2021-12-06 17:16:50,320 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2021-12-06 17:16:50,321 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1741 transitions. [2021-12-06 17:16:50,323 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:50,323 INFO L681 BuchiCegarLoop]: Abstraction has 1170 states and 1741 transitions. [2021-12-06 17:16:50,325 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1741 transitions. [2021-12-06 17:16:50,342 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1170. [2021-12-06 17:16:50,344 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1170 states, 1170 states have (on average 1.488034188034188) internal successors, (1741), 1169 states have internal predecessors, (1741), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:50,349 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 1170 states and 1741 transitions. [2021-12-06 17:16:50,349 INFO L704 BuchiCegarLoop]: Abstraction has 1170 states and 1741 transitions. [2021-12-06 17:16:50,349 INFO L587 BuchiCegarLoop]: Abstraction has 1170 states and 1741 transitions. [2021-12-06 17:16:50,350 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-06 17:16:50,350 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1170 states and 1741 transitions. [2021-12-06 17:16:50,354 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2021-12-06 17:16:50,354 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:50,354 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:50,356 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:50,356 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:50,357 INFO L791 eck$LassoCheckResult]: Stem: 5579#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 5580#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 5529#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5530#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5748#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 5415#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5416#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5725#L668-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5224#L673-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5225#L678-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5653#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5654#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4723#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4724#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4927#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5315#L939 assume !(0 == ~M_E~0); 5559#L939-2 assume !(0 == ~T1_E~0); 5560#L944-1 assume !(0 == ~T2_E~0); 5344#L949-1 assume !(0 == ~T3_E~0); 5342#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5343#L959-1 assume !(0 == ~T5_E~0); 5762#L964-1 assume !(0 == ~T6_E~0); 5075#L969-1 assume !(0 == ~T7_E~0); 5076#L974-1 assume !(0 == ~T8_E~0); 5715#L979-1 assume !(0 == ~T9_E~0); 5716#L984-1 assume !(0 == ~E_M~0); 5236#L989-1 assume !(0 == ~E_1~0); 5237#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5125#L999-1 assume !(0 == ~E_3~0); 5126#L1004-1 assume !(0 == ~E_4~0); 4791#L1009-1 assume !(0 == ~E_5~0); 4792#L1014-1 assume !(0 == ~E_6~0); 5121#L1019-1 assume !(0 == ~E_7~0); 5658#L1024-1 assume !(0 == ~E_8~0); 5048#L1029-1 assume !(0 == ~E_9~0); 5049#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5139#L460 assume 1 == ~m_pc~0; 4710#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4711#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5624#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5863#L1167 assume !(0 != activate_threads_~tmp~1#1); 5332#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5333#L479 assume 1 == ~t1_pc~0; 5316#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5317#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5820#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5060#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 5061#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4909#L498 assume !(1 == ~t2_pc~0); 4910#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5313#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5314#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5691#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5615#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5616#L517 assume 1 == ~t3_pc~0; 5824#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5825#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5387#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5093#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 5094#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5669#L536 assume !(1 == ~t4_pc~0); 5377#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5376#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5753#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5369#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 5370#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5589#L555 assume 1 == ~t5_pc~0; 5590#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5659#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4822#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4823#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 4930#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4830#L574 assume !(1 == ~t6_pc~0); 4831#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5462#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4935#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4936#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 5687#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5847#L593 assume 1 == ~t7_pc~0; 5848#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5067#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5765#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5868#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 5828#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5231#L612 assume !(1 == ~t8_pc~0); 5232#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5641#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5500#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5501#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 5466#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5467#L631 assume 1 == ~t9_pc~0; 5483#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4821#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4789#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4790#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 5319#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5670#L1047 assume !(1 == ~M_E~0); 4759#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4760#L1052-1 assume !(1 == ~T2_E~0); 4742#L1057-1 assume !(1 == ~T3_E~0); 4743#L1062-1 assume !(1 == ~T4_E~0); 5032#L1067-1 assume !(1 == ~T5_E~0); 5335#L1072-1 assume !(1 == ~T6_E~0); 5336#L1077-1 assume !(1 == ~T7_E~0); 4923#L1082-1 assume !(1 == ~T8_E~0); 4924#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4719#L1092-1 assume !(1 == ~E_M~0); 4720#L1097-1 assume !(1 == ~E_1~0); 4744#L1102-1 assume !(1 == ~E_2~0); 5525#L1107-1 assume !(1 == ~E_3~0); 5460#L1112-1 assume !(1 == ~E_4~0); 5461#L1117-1 assume !(1 == ~E_5~0); 5502#L1122-1 assume !(1 == ~E_6~0); 5388#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 5144#L1132-1 assume !(1 == ~E_8~0); 5145#L1137-1 assume !(1 == ~E_9~0); 5031#L1142-1 assume { :end_inline_reset_delta_events } true; 4894#L1428-2 [2021-12-06 17:16:50,357 INFO L793 eck$LassoCheckResult]: Loop: 4894#L1428-2 assume !false; 4895#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4966#L914 assume !false; 5456#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5457#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4728#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4729#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5688#L783 assume !(0 != eval_~tmp~0#1); 5128#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5129#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5524#L939-3 assume !(0 == ~M_E~0); 4949#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4950#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4713#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4714#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5350#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4793#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4794#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5000#L974-3 assume !(0 == ~T8_E~0); 5001#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5431#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5432#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5054#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5055#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5566#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4877#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4878#L1014-3 assume !(0 == ~E_6~0); 5417#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5418#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5399#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 5351#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5352#L460-33 assume !(1 == ~m_pc~0); 5392#L460-35 is_master_triggered_~__retres1~0#1 := 0; 5391#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5146#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4721#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4722#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5083#L479-33 assume !(1 == ~t1_pc~0); 5084#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 5050#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5051#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5635#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 5808#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5088#L498-33 assume 1 == ~t2_pc~0; 5089#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4834#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4971#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4972#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4947#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4948#L517-33 assume !(1 == ~t3_pc~0); 5856#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 5739#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5740#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5552#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5553#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5175#L536-33 assume 1 == ~t4_pc~0; 5176#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5248#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5249#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5439#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5718#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4768#L555-33 assume !(1 == ~t5_pc~0); 4769#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 5494#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5041#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5042#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5521#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4737#L574-33 assume 1 == ~t6_pc~0; 4738#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5730#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5056#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5057#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5310#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4813#L593-33 assume !(1 == ~t7_pc~0); 4814#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 5267#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4921#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4922#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5581#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5708#L612-33 assume 1 == ~t8_pc~0; 5835#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5799#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5800#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5642#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4917#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4918#L631-33 assume 1 == ~t9_pc~0; 5760#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4861#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4862#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5114#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4973#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4974#L1047-3 assume !(1 == ~M_E~0); 5147#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5761#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5693#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5694#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4872#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4873#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5255#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5100#L1082-3 assume !(1 == ~T8_E~0); 5101#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5174#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5455#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5385#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5386#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5731#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5095#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5096#L1122-3 assume !(1 == ~E_6~0); 5148#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5149#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5538#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5515#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 4975#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4853#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 5516#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 5273#L1447 assume !(0 == start_simulation_~tmp~3#1); 5274#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5712#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 5014#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 5539#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 5124#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 4881#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4882#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 5337#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 4894#L1428-2 [2021-12-06 17:16:50,357 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:50,358 INFO L85 PathProgramCache]: Analyzing trace with hash -1066203769, now seen corresponding path program 1 times [2021-12-06 17:16:50,358 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:50,358 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2056960326] [2021-12-06 17:16:50,358 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:50,358 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:50,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:50,391 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:50,391 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:50,391 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2056960326] [2021-12-06 17:16:50,391 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2056960326] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:50,391 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:50,391 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:50,392 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1481918075] [2021-12-06 17:16:50,392 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:50,392 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:50,392 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:50,392 INFO L85 PathProgramCache]: Analyzing trace with hash 1367214863, now seen corresponding path program 1 times [2021-12-06 17:16:50,392 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:50,393 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [263215960] [2021-12-06 17:16:50,393 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:50,393 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:50,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:50,437 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:50,437 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:50,437 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [263215960] [2021-12-06 17:16:50,438 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [263215960] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:50,438 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:50,438 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:50,438 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [364257336] [2021-12-06 17:16:50,438 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:50,438 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:50,438 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:50,439 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:16:50,439 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:16:50,439 INFO L87 Difference]: Start difference. First operand 1170 states and 1741 transitions. cyclomatic complexity: 572 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:50,471 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:50,472 INFO L93 Difference]: Finished difference Result 1170 states and 1740 transitions. [2021-12-06 17:16:50,472 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:16:50,473 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1170 states and 1740 transitions. [2021-12-06 17:16:50,481 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2021-12-06 17:16:50,490 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1170 states to 1170 states and 1740 transitions. [2021-12-06 17:16:50,490 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2021-12-06 17:16:50,492 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2021-12-06 17:16:50,492 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1740 transitions. [2021-12-06 17:16:50,494 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:50,494 INFO L681 BuchiCegarLoop]: Abstraction has 1170 states and 1740 transitions. [2021-12-06 17:16:50,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1740 transitions. [2021-12-06 17:16:50,507 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1170. [2021-12-06 17:16:50,509 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1170 states, 1170 states have (on average 1.4871794871794872) internal successors, (1740), 1169 states have internal predecessors, (1740), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:50,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 1170 states and 1740 transitions. [2021-12-06 17:16:50,512 INFO L704 BuchiCegarLoop]: Abstraction has 1170 states and 1740 transitions. [2021-12-06 17:16:50,512 INFO L587 BuchiCegarLoop]: Abstraction has 1170 states and 1740 transitions. [2021-12-06 17:16:50,512 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-06 17:16:50,512 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1170 states and 1740 transitions. [2021-12-06 17:16:50,517 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2021-12-06 17:16:50,517 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:50,517 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:50,519 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:50,519 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:50,519 INFO L791 eck$LassoCheckResult]: Stem: 7926#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 7927#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 7876#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7877#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8095#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 7764#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7765#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8072#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7571#L673-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7572#L678-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8000#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8001#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7070#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7071#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7274#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7662#L939 assume !(0 == ~M_E~0); 7906#L939-2 assume !(0 == ~T1_E~0); 7907#L944-1 assume !(0 == ~T2_E~0); 7691#L949-1 assume !(0 == ~T3_E~0); 7689#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7690#L959-1 assume !(0 == ~T5_E~0); 8109#L964-1 assume !(0 == ~T6_E~0); 7422#L969-1 assume !(0 == ~T7_E~0); 7423#L974-1 assume !(0 == ~T8_E~0); 8062#L979-1 assume !(0 == ~T9_E~0); 8063#L984-1 assume !(0 == ~E_M~0); 7585#L989-1 assume !(0 == ~E_1~0); 7586#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 7472#L999-1 assume !(0 == ~E_3~0); 7473#L1004-1 assume !(0 == ~E_4~0); 7138#L1009-1 assume !(0 == ~E_5~0); 7139#L1014-1 assume !(0 == ~E_6~0); 7468#L1019-1 assume !(0 == ~E_7~0); 8005#L1024-1 assume !(0 == ~E_8~0); 7395#L1029-1 assume !(0 == ~E_9~0); 7396#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7488#L460 assume 1 == ~m_pc~0; 7057#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7058#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7971#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8210#L1167 assume !(0 != activate_threads_~tmp~1#1); 7679#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7680#L479 assume 1 == ~t1_pc~0; 7663#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7664#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8167#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7408#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 7409#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7256#L498 assume !(1 == ~t2_pc~0); 7257#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7660#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7661#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8038#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7962#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7963#L517 assume 1 == ~t3_pc~0; 8172#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8173#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7734#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7440#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 7441#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8016#L536 assume !(1 == ~t4_pc~0); 7724#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7723#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8100#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7716#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 7717#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7938#L555 assume 1 == ~t5_pc~0; 7939#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8006#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7171#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7172#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 7279#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7177#L574 assume !(1 == ~t6_pc~0); 7178#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7809#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7282#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7283#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 8034#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8194#L593 assume 1 == ~t7_pc~0; 8195#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7414#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8114#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8215#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 8175#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7578#L612 assume !(1 == ~t8_pc~0); 7579#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7988#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7847#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7848#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 7813#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7814#L631 assume 1 == ~t9_pc~0; 7830#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7168#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7136#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7137#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 7666#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8017#L1047 assume !(1 == ~M_E~0); 7108#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7109#L1052-1 assume !(1 == ~T2_E~0); 7089#L1057-1 assume !(1 == ~T3_E~0); 7090#L1062-1 assume !(1 == ~T4_E~0); 7379#L1067-1 assume !(1 == ~T5_E~0); 7682#L1072-1 assume !(1 == ~T6_E~0); 7683#L1077-1 assume !(1 == ~T7_E~0); 7270#L1082-1 assume !(1 == ~T8_E~0); 7271#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7066#L1092-1 assume !(1 == ~E_M~0); 7067#L1097-1 assume !(1 == ~E_1~0); 7091#L1102-1 assume !(1 == ~E_2~0); 7872#L1107-1 assume !(1 == ~E_3~0); 7807#L1112-1 assume !(1 == ~E_4~0); 7808#L1117-1 assume !(1 == ~E_5~0); 7849#L1122-1 assume !(1 == ~E_6~0); 7735#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7491#L1132-1 assume !(1 == ~E_8~0); 7492#L1137-1 assume !(1 == ~E_9~0); 7378#L1142-1 assume { :end_inline_reset_delta_events } true; 7241#L1428-2 [2021-12-06 17:16:50,520 INFO L793 eck$LassoCheckResult]: Loop: 7241#L1428-2 assume !false; 7242#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7313#L914 assume !false; 7803#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7804#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7077#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7078#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8035#L783 assume !(0 != eval_~tmp~0#1); 7475#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7476#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7871#L939-3 assume !(0 == ~M_E~0); 7296#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7297#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7060#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7061#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7697#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7142#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7143#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7347#L974-3 assume !(0 == ~T8_E~0); 7348#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7778#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7779#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7401#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7402#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7913#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7224#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7225#L1014-3 assume !(0 == ~E_6~0); 7762#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7763#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7744#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 7698#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7699#L460-33 assume 1 == ~m_pc~0; 7736#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7737#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7493#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7068#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7069#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7429#L479-33 assume !(1 == ~t1_pc~0); 7430#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 7397#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7398#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7980#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 8155#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7438#L498-33 assume 1 == ~t2_pc~0; 7439#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7184#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7318#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7319#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7294#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7295#L517-33 assume !(1 == ~t3_pc~0); 8203#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 8086#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8087#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7899#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7900#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7525#L536-33 assume 1 == ~t4_pc~0; 7526#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7595#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7596#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7786#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8065#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7115#L555-33 assume !(1 == ~t5_pc~0); 7116#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 7841#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7388#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7389#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7868#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7086#L574-33 assume !(1 == ~t6_pc~0); 7088#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 8077#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7403#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7404#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7657#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7162#L593-33 assume !(1 == ~t7_pc~0); 7163#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 7618#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7268#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7269#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7928#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8055#L612-33 assume 1 == ~t8_pc~0; 8182#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8146#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8147#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7989#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7264#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7265#L631-33 assume !(1 == ~t9_pc~0); 7875#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 7208#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7209#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7461#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7320#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7321#L1047-3 assume !(1 == ~M_E~0); 7494#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8108#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8040#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8041#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7219#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7220#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7602#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7447#L1082-3 assume !(1 == ~T8_E~0); 7448#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7521#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7802#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7732#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7733#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8078#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7442#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7443#L1122-3 assume !(1 == ~E_6~0); 7495#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7496#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7885#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 7862#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7325#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7200#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7863#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 7620#L1447 assume !(0 == start_simulation_~tmp~3#1); 7621#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 8059#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7361#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7886#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 7471#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 7228#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7229#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 7684#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 7241#L1428-2 [2021-12-06 17:16:50,521 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:50,521 INFO L85 PathProgramCache]: Analyzing trace with hash 1065146953, now seen corresponding path program 1 times [2021-12-06 17:16:50,521 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:50,521 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1640985958] [2021-12-06 17:16:50,522 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:50,522 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:50,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:50,559 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:50,560 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:50,560 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1640985958] [2021-12-06 17:16:50,560 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1640985958] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:50,560 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:50,560 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:50,561 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1473806027] [2021-12-06 17:16:50,561 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:50,561 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:50,562 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:50,562 INFO L85 PathProgramCache]: Analyzing trace with hash -466631152, now seen corresponding path program 1 times [2021-12-06 17:16:50,562 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:50,562 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2032563076] [2021-12-06 17:16:50,562 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:50,563 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:50,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:50,617 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:50,617 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:50,618 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2032563076] [2021-12-06 17:16:50,618 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2032563076] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:50,618 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:50,618 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 17:16:50,618 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1947076120] [2021-12-06 17:16:50,618 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:50,619 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:50,619 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:50,619 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:16:50,620 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:16:50,620 INFO L87 Difference]: Start difference. First operand 1170 states and 1740 transitions. cyclomatic complexity: 571 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:50,637 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:50,637 INFO L93 Difference]: Finished difference Result 1170 states and 1739 transitions. [2021-12-06 17:16:50,637 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:16:50,638 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1170 states and 1739 transitions. [2021-12-06 17:16:50,644 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2021-12-06 17:16:50,650 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1170 states to 1170 states and 1739 transitions. [2021-12-06 17:16:50,650 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2021-12-06 17:16:50,651 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2021-12-06 17:16:50,651 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1739 transitions. [2021-12-06 17:16:50,652 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:50,653 INFO L681 BuchiCegarLoop]: Abstraction has 1170 states and 1739 transitions. [2021-12-06 17:16:50,654 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1739 transitions. [2021-12-06 17:16:50,664 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1170. [2021-12-06 17:16:50,666 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1170 states, 1170 states have (on average 1.4863247863247864) internal successors, (1739), 1169 states have internal predecessors, (1739), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:50,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 1170 states and 1739 transitions. [2021-12-06 17:16:50,669 INFO L704 BuchiCegarLoop]: Abstraction has 1170 states and 1739 transitions. [2021-12-06 17:16:50,669 INFO L587 BuchiCegarLoop]: Abstraction has 1170 states and 1739 transitions. [2021-12-06 17:16:50,669 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-06 17:16:50,669 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1170 states and 1739 transitions. [2021-12-06 17:16:50,673 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2021-12-06 17:16:50,674 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:50,674 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:50,675 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:50,675 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:50,675 INFO L791 eck$LassoCheckResult]: Stem: 10275#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 10276#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 10225#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10226#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10444#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 10111#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10112#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10421#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9920#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9921#L678-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10347#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10348#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9419#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9420#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9623#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10011#L939 assume !(0 == ~M_E~0); 10255#L939-2 assume !(0 == ~T1_E~0); 10256#L944-1 assume !(0 == ~T2_E~0); 10040#L949-1 assume !(0 == ~T3_E~0); 10038#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10039#L959-1 assume !(0 == ~T5_E~0); 10458#L964-1 assume !(0 == ~T6_E~0); 9771#L969-1 assume !(0 == ~T7_E~0); 9772#L974-1 assume !(0 == ~T8_E~0); 10409#L979-1 assume !(0 == ~T9_E~0); 10410#L984-1 assume !(0 == ~E_M~0); 9932#L989-1 assume !(0 == ~E_1~0); 9933#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 9821#L999-1 assume !(0 == ~E_3~0); 9822#L1004-1 assume !(0 == ~E_4~0); 9487#L1009-1 assume !(0 == ~E_5~0); 9488#L1014-1 assume !(0 == ~E_6~0); 9813#L1019-1 assume !(0 == ~E_7~0); 10354#L1024-1 assume !(0 == ~E_8~0); 9744#L1029-1 assume !(0 == ~E_9~0); 9745#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9835#L460 assume 1 == ~m_pc~0; 9403#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9404#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10320#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10559#L1167 assume !(0 != activate_threads_~tmp~1#1); 10028#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10029#L479 assume 1 == ~t1_pc~0; 10012#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10013#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10516#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9756#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 9757#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9605#L498 assume !(1 == ~t2_pc~0); 9606#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10009#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10010#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10387#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10310#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10311#L517 assume 1 == ~t3_pc~0; 10518#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10519#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10083#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9789#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 9790#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10363#L536 assume !(1 == ~t4_pc~0); 10073#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10072#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10449#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10065#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 10066#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10283#L555 assume 1 == ~t5_pc~0; 10284#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10355#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9518#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9519#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 9626#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9526#L574 assume !(1 == ~t6_pc~0); 9527#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10158#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9631#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9632#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 10381#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10543#L593 assume 1 == ~t7_pc~0; 10544#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9763#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10461#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10564#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 10524#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9927#L612 assume !(1 == ~t8_pc~0); 9928#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10337#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10195#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10196#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 10160#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10161#L631 assume 1 == ~t9_pc~0; 10179#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9517#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9485#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9486#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 10015#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10366#L1047 assume !(1 == ~M_E~0); 9455#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9456#L1052-1 assume !(1 == ~T2_E~0); 9438#L1057-1 assume !(1 == ~T3_E~0); 9439#L1062-1 assume !(1 == ~T4_E~0); 9728#L1067-1 assume !(1 == ~T5_E~0); 10031#L1072-1 assume !(1 == ~T6_E~0); 10032#L1077-1 assume !(1 == ~T7_E~0); 9619#L1082-1 assume !(1 == ~T8_E~0); 9620#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9411#L1092-1 assume !(1 == ~E_M~0); 9412#L1097-1 assume !(1 == ~E_1~0); 9440#L1102-1 assume !(1 == ~E_2~0); 10221#L1107-1 assume !(1 == ~E_3~0); 10156#L1112-1 assume !(1 == ~E_4~0); 10157#L1117-1 assume !(1 == ~E_5~0); 10197#L1122-1 assume !(1 == ~E_6~0); 10084#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 9838#L1132-1 assume !(1 == ~E_8~0); 9839#L1137-1 assume !(1 == ~E_9~0); 9727#L1142-1 assume { :end_inline_reset_delta_events } true; 9587#L1428-2 [2021-12-06 17:16:50,676 INFO L793 eck$LassoCheckResult]: Loop: 9587#L1428-2 assume !false; 9588#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9662#L914 assume !false; 10152#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10153#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9424#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 9425#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10384#L783 assume !(0 != eval_~tmp~0#1); 9824#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9825#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10220#L939-3 assume !(0 == ~M_E~0); 9643#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9644#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9409#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9410#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10046#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9489#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9490#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9696#L974-3 assume !(0 == ~T8_E~0); 9697#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10127#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10128#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9750#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9751#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10262#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9573#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9574#L1014-3 assume !(0 == ~E_6~0); 10113#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10114#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10095#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 10047#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10048#L460-33 assume 1 == ~m_pc~0; 10085#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10086#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9842#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9417#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9418#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9778#L479-33 assume !(1 == ~t1_pc~0); 9779#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 9746#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9747#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10331#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 10504#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9787#L498-33 assume 1 == ~t2_pc~0; 9788#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9533#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9667#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9668#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9645#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9646#L517-33 assume !(1 == ~t3_pc~0); 10552#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 10435#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10436#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10248#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10249#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9874#L536-33 assume 1 == ~t4_pc~0; 9875#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9944#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9945#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10135#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10414#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9464#L555-33 assume !(1 == ~t5_pc~0); 9465#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 10190#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9737#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9738#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10217#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9435#L574-33 assume 1 == ~t6_pc~0; 9436#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10426#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9752#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9753#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10006#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9511#L593-33 assume !(1 == ~t7_pc~0); 9512#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 9967#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9617#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9618#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10277#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10404#L612-33 assume 1 == ~t8_pc~0; 10531#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10495#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10496#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10338#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9615#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9616#L631-33 assume !(1 == ~t9_pc~0); 10224#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 9557#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9558#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9812#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9669#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9670#L1047-3 assume !(1 == ~M_E~0); 9843#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10457#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10389#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10390#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9568#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9569#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9951#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9796#L1082-3 assume !(1 == ~T8_E~0); 9797#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9870#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10151#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10081#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10082#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10427#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9791#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9792#L1122-3 assume !(1 == ~E_6~0); 9844#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9845#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10234#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 10211#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 9674#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9552#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 10212#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 9969#L1447 assume !(0 == start_simulation_~tmp~3#1); 9970#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10408#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9710#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 10235#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 9820#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 9577#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9578#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 10033#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 9587#L1428-2 [2021-12-06 17:16:50,676 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:50,676 INFO L85 PathProgramCache]: Analyzing trace with hash 2103731527, now seen corresponding path program 1 times [2021-12-06 17:16:50,676 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:50,676 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1918556575] [2021-12-06 17:16:50,676 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:50,676 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:50,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:50,705 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:50,705 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:50,706 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1918556575] [2021-12-06 17:16:50,706 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1918556575] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:50,706 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:50,706 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:50,706 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1307595040] [2021-12-06 17:16:50,706 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:50,707 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:50,707 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:50,707 INFO L85 PathProgramCache]: Analyzing trace with hash -706898481, now seen corresponding path program 1 times [2021-12-06 17:16:50,708 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:50,708 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [610569019] [2021-12-06 17:16:50,708 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:50,708 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:50,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:50,761 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:50,761 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:50,761 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [610569019] [2021-12-06 17:16:50,761 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [610569019] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:50,762 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:50,762 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:50,762 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1060328641] [2021-12-06 17:16:50,762 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:50,762 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:50,762 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:50,763 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:16:50,763 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:16:50,763 INFO L87 Difference]: Start difference. First operand 1170 states and 1739 transitions. cyclomatic complexity: 570 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:50,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:50,781 INFO L93 Difference]: Finished difference Result 1170 states and 1738 transitions. [2021-12-06 17:16:50,781 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:16:50,782 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1170 states and 1738 transitions. [2021-12-06 17:16:50,788 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2021-12-06 17:16:50,795 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1170 states to 1170 states and 1738 transitions. [2021-12-06 17:16:50,795 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2021-12-06 17:16:50,796 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2021-12-06 17:16:50,796 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1738 transitions. [2021-12-06 17:16:50,798 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:50,798 INFO L681 BuchiCegarLoop]: Abstraction has 1170 states and 1738 transitions. [2021-12-06 17:16:50,800 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1738 transitions. [2021-12-06 17:16:50,812 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1170. [2021-12-06 17:16:50,814 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1170 states, 1170 states have (on average 1.4854700854700855) internal successors, (1738), 1169 states have internal predecessors, (1738), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:50,817 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 1170 states and 1738 transitions. [2021-12-06 17:16:50,818 INFO L704 BuchiCegarLoop]: Abstraction has 1170 states and 1738 transitions. [2021-12-06 17:16:50,818 INFO L587 BuchiCegarLoop]: Abstraction has 1170 states and 1738 transitions. [2021-12-06 17:16:50,818 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-06 17:16:50,818 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1170 states and 1738 transitions. [2021-12-06 17:16:50,823 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2021-12-06 17:16:50,823 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:50,823 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:50,824 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:50,824 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:50,825 INFO L791 eck$LassoCheckResult]: Stem: 12622#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 12623#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 12572#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12573#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12791#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 12458#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12459#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12768#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12267#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12268#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12694#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12695#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11766#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11767#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11970#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12358#L939 assume !(0 == ~M_E~0); 12602#L939-2 assume !(0 == ~T1_E~0); 12603#L944-1 assume !(0 == ~T2_E~0); 12387#L949-1 assume !(0 == ~T3_E~0); 12385#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12386#L959-1 assume !(0 == ~T5_E~0); 12805#L964-1 assume !(0 == ~T6_E~0); 12118#L969-1 assume !(0 == ~T7_E~0); 12119#L974-1 assume !(0 == ~T8_E~0); 12756#L979-1 assume !(0 == ~T9_E~0); 12757#L984-1 assume !(0 == ~E_M~0); 12279#L989-1 assume !(0 == ~E_1~0); 12280#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 12168#L999-1 assume !(0 == ~E_3~0); 12169#L1004-1 assume !(0 == ~E_4~0); 11834#L1009-1 assume !(0 == ~E_5~0); 11835#L1014-1 assume !(0 == ~E_6~0); 12160#L1019-1 assume !(0 == ~E_7~0); 12701#L1024-1 assume !(0 == ~E_8~0); 12091#L1029-1 assume !(0 == ~E_9~0); 12092#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12182#L460 assume 1 == ~m_pc~0; 11750#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11751#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12667#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12906#L1167 assume !(0 != activate_threads_~tmp~1#1); 12375#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12376#L479 assume 1 == ~t1_pc~0; 12359#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12360#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12863#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12103#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 12104#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11952#L498 assume !(1 == ~t2_pc~0); 11953#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12356#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12357#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12734#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12657#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12658#L517 assume 1 == ~t3_pc~0; 12865#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12866#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12430#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12136#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 12137#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12710#L536 assume !(1 == ~t4_pc~0); 12420#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12419#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12796#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12412#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 12413#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12630#L555 assume 1 == ~t5_pc~0; 12631#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12702#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11865#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11866#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 11973#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11873#L574 assume !(1 == ~t6_pc~0); 11874#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12505#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11978#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11979#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 12728#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12890#L593 assume 1 == ~t7_pc~0; 12891#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12110#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12808#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12911#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 12871#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12274#L612 assume !(1 == ~t8_pc~0); 12275#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12684#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12542#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12543#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 12507#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12508#L631 assume 1 == ~t9_pc~0; 12526#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11864#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11832#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11833#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 12362#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12713#L1047 assume !(1 == ~M_E~0); 11802#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11803#L1052-1 assume !(1 == ~T2_E~0); 11785#L1057-1 assume !(1 == ~T3_E~0); 11786#L1062-1 assume !(1 == ~T4_E~0); 12075#L1067-1 assume !(1 == ~T5_E~0); 12378#L1072-1 assume !(1 == ~T6_E~0); 12379#L1077-1 assume !(1 == ~T7_E~0); 11966#L1082-1 assume !(1 == ~T8_E~0); 11967#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11758#L1092-1 assume !(1 == ~E_M~0); 11759#L1097-1 assume !(1 == ~E_1~0); 11787#L1102-1 assume !(1 == ~E_2~0); 12568#L1107-1 assume !(1 == ~E_3~0); 12503#L1112-1 assume !(1 == ~E_4~0); 12504#L1117-1 assume !(1 == ~E_5~0); 12544#L1122-1 assume !(1 == ~E_6~0); 12431#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 12185#L1132-1 assume !(1 == ~E_8~0); 12186#L1137-1 assume !(1 == ~E_9~0); 12074#L1142-1 assume { :end_inline_reset_delta_events } true; 11934#L1428-2 [2021-12-06 17:16:50,825 INFO L793 eck$LassoCheckResult]: Loop: 11934#L1428-2 assume !false; 11935#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12009#L914 assume !false; 12499#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12500#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11771#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11772#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12731#L783 assume !(0 != eval_~tmp~0#1); 12171#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12172#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12567#L939-3 assume !(0 == ~M_E~0); 11990#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11991#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11756#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11757#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12393#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11836#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11837#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12043#L974-3 assume !(0 == ~T8_E~0); 12044#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 12474#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12475#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12097#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12098#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12609#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11920#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11921#L1014-3 assume !(0 == ~E_6~0); 12460#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12461#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12442#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12394#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12395#L460-33 assume 1 == ~m_pc~0; 12432#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12433#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12189#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11764#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11765#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12125#L479-33 assume !(1 == ~t1_pc~0); 12126#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 12093#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12094#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12678#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 12851#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12134#L498-33 assume 1 == ~t2_pc~0; 12135#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11880#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12014#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12015#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11992#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11993#L517-33 assume !(1 == ~t3_pc~0); 12899#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 12782#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12783#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12595#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12596#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12221#L536-33 assume 1 == ~t4_pc~0; 12222#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12291#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12292#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12482#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12761#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11811#L555-33 assume !(1 == ~t5_pc~0); 11812#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 12537#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12084#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12085#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12564#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11782#L574-33 assume 1 == ~t6_pc~0; 11783#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12773#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12099#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12100#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12353#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11858#L593-33 assume !(1 == ~t7_pc~0); 11859#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 12314#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11964#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11965#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12624#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12751#L612-33 assume 1 == ~t8_pc~0; 12878#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12842#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12843#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12685#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11962#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11963#L631-33 assume 1 == ~t9_pc~0; 12803#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11904#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11905#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12159#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12016#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12017#L1047-3 assume !(1 == ~M_E~0); 12190#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12804#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12736#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12737#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11915#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11916#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12298#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12143#L1082-3 assume !(1 == ~T8_E~0); 12144#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12217#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12498#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12428#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12429#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12774#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12138#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12139#L1122-3 assume !(1 == ~E_6~0); 12191#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12192#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12581#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12558#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12021#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11899#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 12559#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 12316#L1447 assume !(0 == start_simulation_~tmp~3#1); 12317#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12755#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 12057#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 12582#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 12167#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 11924#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11925#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 12380#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 11934#L1428-2 [2021-12-06 17:16:50,825 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:50,826 INFO L85 PathProgramCache]: Analyzing trace with hash -218070391, now seen corresponding path program 1 times [2021-12-06 17:16:50,826 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:50,826 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1463526274] [2021-12-06 17:16:50,826 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:50,826 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:50,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:50,850 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:50,850 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:50,850 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1463526274] [2021-12-06 17:16:50,850 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1463526274] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:50,850 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:50,850 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:50,851 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1557988639] [2021-12-06 17:16:50,851 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:50,851 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:50,851 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:50,851 INFO L85 PathProgramCache]: Analyzing trace with hash 250029902, now seen corresponding path program 2 times [2021-12-06 17:16:50,852 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:50,852 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1075168180] [2021-12-06 17:16:50,852 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:50,852 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:50,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:50,883 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:50,883 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:50,883 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1075168180] [2021-12-06 17:16:50,883 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1075168180] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:50,884 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:50,884 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:50,884 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2020685602] [2021-12-06 17:16:50,884 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:50,884 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:50,884 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:50,885 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:16:50,885 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:16:50,885 INFO L87 Difference]: Start difference. First operand 1170 states and 1738 transitions. cyclomatic complexity: 569 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:50,903 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:50,903 INFO L93 Difference]: Finished difference Result 1170 states and 1737 transitions. [2021-12-06 17:16:50,903 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:16:50,904 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1170 states and 1737 transitions. [2021-12-06 17:16:50,910 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2021-12-06 17:16:50,917 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1170 states to 1170 states and 1737 transitions. [2021-12-06 17:16:50,917 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2021-12-06 17:16:50,918 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2021-12-06 17:16:50,918 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1737 transitions. [2021-12-06 17:16:50,920 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:50,920 INFO L681 BuchiCegarLoop]: Abstraction has 1170 states and 1737 transitions. [2021-12-06 17:16:50,922 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1737 transitions. [2021-12-06 17:16:50,934 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1170. [2021-12-06 17:16:50,935 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1170 states, 1170 states have (on average 1.4846153846153847) internal successors, (1737), 1169 states have internal predecessors, (1737), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:50,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 1170 states and 1737 transitions. [2021-12-06 17:16:50,939 INFO L704 BuchiCegarLoop]: Abstraction has 1170 states and 1737 transitions. [2021-12-06 17:16:50,939 INFO L587 BuchiCegarLoop]: Abstraction has 1170 states and 1737 transitions. [2021-12-06 17:16:50,939 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-06 17:16:50,939 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1170 states and 1737 transitions. [2021-12-06 17:16:50,944 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2021-12-06 17:16:50,944 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:50,944 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:50,946 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:50,946 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:50,946 INFO L791 eck$LassoCheckResult]: Stem: 14969#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 14970#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 14919#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14920#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15138#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 14805#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14806#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15115#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14614#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14615#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15041#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 15042#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14113#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14114#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14317#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14705#L939 assume !(0 == ~M_E~0); 14949#L939-2 assume !(0 == ~T1_E~0); 14950#L944-1 assume !(0 == ~T2_E~0); 14734#L949-1 assume !(0 == ~T3_E~0); 14732#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14733#L959-1 assume !(0 == ~T5_E~0); 15152#L964-1 assume !(0 == ~T6_E~0); 14465#L969-1 assume !(0 == ~T7_E~0); 14466#L974-1 assume !(0 == ~T8_E~0); 15103#L979-1 assume !(0 == ~T9_E~0); 15104#L984-1 assume !(0 == ~E_M~0); 14626#L989-1 assume !(0 == ~E_1~0); 14627#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 14515#L999-1 assume !(0 == ~E_3~0); 14516#L1004-1 assume !(0 == ~E_4~0); 14181#L1009-1 assume !(0 == ~E_5~0); 14182#L1014-1 assume !(0 == ~E_6~0); 14507#L1019-1 assume !(0 == ~E_7~0); 15048#L1024-1 assume !(0 == ~E_8~0); 14438#L1029-1 assume !(0 == ~E_9~0); 14439#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14529#L460 assume 1 == ~m_pc~0; 14097#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14098#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15014#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15253#L1167 assume !(0 != activate_threads_~tmp~1#1); 14722#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14723#L479 assume 1 == ~t1_pc~0; 14706#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14707#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15210#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14450#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 14451#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14299#L498 assume !(1 == ~t2_pc~0); 14300#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14703#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14704#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15081#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15004#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15005#L517 assume 1 == ~t3_pc~0; 15212#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15213#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14777#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14483#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 14484#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15057#L536 assume !(1 == ~t4_pc~0); 14767#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14766#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15143#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14759#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 14760#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14977#L555 assume 1 == ~t5_pc~0; 14978#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15049#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14212#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14213#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 14320#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14220#L574 assume !(1 == ~t6_pc~0); 14221#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14852#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14325#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14326#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 15075#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15237#L593 assume 1 == ~t7_pc~0; 15238#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14457#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15155#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15258#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 15218#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14621#L612 assume !(1 == ~t8_pc~0); 14622#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 15031#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14889#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14890#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 14854#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14855#L631 assume 1 == ~t9_pc~0; 14873#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14211#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14179#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14180#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 14709#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15060#L1047 assume !(1 == ~M_E~0); 14149#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14150#L1052-1 assume !(1 == ~T2_E~0); 14132#L1057-1 assume !(1 == ~T3_E~0); 14133#L1062-1 assume !(1 == ~T4_E~0); 14422#L1067-1 assume !(1 == ~T5_E~0); 14725#L1072-1 assume !(1 == ~T6_E~0); 14726#L1077-1 assume !(1 == ~T7_E~0); 14313#L1082-1 assume !(1 == ~T8_E~0); 14314#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14105#L1092-1 assume !(1 == ~E_M~0); 14106#L1097-1 assume !(1 == ~E_1~0); 14134#L1102-1 assume !(1 == ~E_2~0); 14915#L1107-1 assume !(1 == ~E_3~0); 14850#L1112-1 assume !(1 == ~E_4~0); 14851#L1117-1 assume !(1 == ~E_5~0); 14891#L1122-1 assume !(1 == ~E_6~0); 14778#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 14532#L1132-1 assume !(1 == ~E_8~0); 14533#L1137-1 assume !(1 == ~E_9~0); 14421#L1142-1 assume { :end_inline_reset_delta_events } true; 14281#L1428-2 [2021-12-06 17:16:50,947 INFO L793 eck$LassoCheckResult]: Loop: 14281#L1428-2 assume !false; 14282#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14356#L914 assume !false; 14846#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14847#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14118#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14119#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 15078#L783 assume !(0 != eval_~tmp~0#1); 14518#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14519#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14914#L939-3 assume !(0 == ~M_E~0); 14337#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14338#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14103#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14104#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14740#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14183#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14184#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14390#L974-3 assume !(0 == ~T8_E~0); 14391#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14821#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14822#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14444#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14445#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14956#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14267#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14268#L1014-3 assume !(0 == ~E_6~0); 14807#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14808#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14789#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 14741#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14742#L460-33 assume 1 == ~m_pc~0; 14779#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14780#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14536#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14111#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14112#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14472#L479-33 assume !(1 == ~t1_pc~0); 14473#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 14440#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14441#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15025#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 15198#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14481#L498-33 assume 1 == ~t2_pc~0; 14482#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14227#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14361#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14362#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14339#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14340#L517-33 assume !(1 == ~t3_pc~0); 15246#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 15129#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15130#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14942#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14943#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14568#L536-33 assume 1 == ~t4_pc~0; 14569#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14638#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14639#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14829#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15108#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14158#L555-33 assume 1 == ~t5_pc~0; 14160#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14884#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14431#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14432#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14911#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14129#L574-33 assume 1 == ~t6_pc~0; 14130#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15120#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14446#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14447#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14700#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14205#L593-33 assume !(1 == ~t7_pc~0); 14206#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 14661#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14311#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14312#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14971#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15098#L612-33 assume 1 == ~t8_pc~0; 15225#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15189#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15190#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15032#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14309#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14310#L631-33 assume !(1 == ~t9_pc~0); 14918#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 14251#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14252#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14506#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 14363#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14364#L1047-3 assume !(1 == ~M_E~0); 14537#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15151#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15083#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15084#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14262#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14263#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14645#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14490#L1082-3 assume !(1 == ~T8_E~0); 14491#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14564#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14845#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14775#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14776#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15121#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14485#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14486#L1122-3 assume !(1 == ~E_6~0); 14538#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14539#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14928#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 14905#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14368#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14246#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14906#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 14663#L1447 assume !(0 == start_simulation_~tmp~3#1); 14664#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 15102#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14404#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14929#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 14514#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 14271#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14272#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 14727#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 14281#L1428-2 [2021-12-06 17:16:50,947 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:50,947 INFO L85 PathProgramCache]: Analyzing trace with hash 1923790087, now seen corresponding path program 1 times [2021-12-06 17:16:50,947 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:50,947 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [914755549] [2021-12-06 17:16:50,947 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:50,947 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:50,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:50,970 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:50,970 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:50,970 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [914755549] [2021-12-06 17:16:50,970 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [914755549] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:50,970 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:50,970 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:50,970 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [789485976] [2021-12-06 17:16:50,970 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:50,971 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:50,971 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:50,971 INFO L85 PathProgramCache]: Analyzing trace with hash -1283827122, now seen corresponding path program 1 times [2021-12-06 17:16:50,971 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:50,971 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [622049811] [2021-12-06 17:16:50,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:50,972 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:50,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:51,001 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:51,002 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:51,002 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [622049811] [2021-12-06 17:16:51,002 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [622049811] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:51,002 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:51,002 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:51,002 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [69396449] [2021-12-06 17:16:51,002 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:51,003 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:51,003 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:51,003 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:16:51,003 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:16:51,003 INFO L87 Difference]: Start difference. First operand 1170 states and 1737 transitions. cyclomatic complexity: 568 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:51,018 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:51,019 INFO L93 Difference]: Finished difference Result 1170 states and 1736 transitions. [2021-12-06 17:16:51,019 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:16:51,019 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1170 states and 1736 transitions. [2021-12-06 17:16:51,025 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2021-12-06 17:16:51,031 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1170 states to 1170 states and 1736 transitions. [2021-12-06 17:16:51,031 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2021-12-06 17:16:51,032 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2021-12-06 17:16:51,032 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1736 transitions. [2021-12-06 17:16:51,033 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:51,033 INFO L681 BuchiCegarLoop]: Abstraction has 1170 states and 1736 transitions. [2021-12-06 17:16:51,035 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1736 transitions. [2021-12-06 17:16:51,045 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1170. [2021-12-06 17:16:51,046 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1170 states, 1170 states have (on average 1.4837606837606838) internal successors, (1736), 1169 states have internal predecessors, (1736), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:51,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 1170 states and 1736 transitions. [2021-12-06 17:16:51,049 INFO L704 BuchiCegarLoop]: Abstraction has 1170 states and 1736 transitions. [2021-12-06 17:16:51,049 INFO L587 BuchiCegarLoop]: Abstraction has 1170 states and 1736 transitions. [2021-12-06 17:16:51,049 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-06 17:16:51,050 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1170 states and 1736 transitions. [2021-12-06 17:16:51,053 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2021-12-06 17:16:51,054 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:51,054 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:51,055 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:51,055 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:51,055 INFO L791 eck$LassoCheckResult]: Stem: 17316#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 17317#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 17266#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17267#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17485#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 17152#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17153#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17462#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16961#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16962#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17390#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17391#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16460#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16461#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16664#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17052#L939 assume !(0 == ~M_E~0); 17296#L939-2 assume !(0 == ~T1_E~0); 17297#L944-1 assume !(0 == ~T2_E~0); 17081#L949-1 assume !(0 == ~T3_E~0); 17079#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17080#L959-1 assume !(0 == ~T5_E~0); 17499#L964-1 assume !(0 == ~T6_E~0); 16812#L969-1 assume !(0 == ~T7_E~0); 16813#L974-1 assume !(0 == ~T8_E~0); 17450#L979-1 assume !(0 == ~T9_E~0); 17451#L984-1 assume !(0 == ~E_M~0); 16973#L989-1 assume !(0 == ~E_1~0); 16974#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 16862#L999-1 assume !(0 == ~E_3~0); 16863#L1004-1 assume !(0 == ~E_4~0); 16528#L1009-1 assume !(0 == ~E_5~0); 16529#L1014-1 assume !(0 == ~E_6~0); 16854#L1019-1 assume !(0 == ~E_7~0); 17395#L1024-1 assume !(0 == ~E_8~0); 16785#L1029-1 assume !(0 == ~E_9~0); 16786#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16876#L460 assume 1 == ~m_pc~0; 16444#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 16445#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17361#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17600#L1167 assume !(0 != activate_threads_~tmp~1#1); 17069#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17070#L479 assume 1 == ~t1_pc~0; 17053#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17054#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17557#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16797#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 16798#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16646#L498 assume !(1 == ~t2_pc~0); 16647#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 17050#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17051#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17428#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17352#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17353#L517 assume 1 == ~t3_pc~0; 17559#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17560#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17124#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16830#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 16831#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17404#L536 assume !(1 == ~t4_pc~0); 17114#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 17113#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17490#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17106#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 17107#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17324#L555 assume 1 == ~t5_pc~0; 17325#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17396#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16559#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16560#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 16667#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16567#L574 assume !(1 == ~t6_pc~0); 16568#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17199#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16672#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16673#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 17422#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17584#L593 assume 1 == ~t7_pc~0; 17585#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16804#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17502#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17605#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 17565#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16968#L612 assume !(1 == ~t8_pc~0); 16969#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 17378#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17236#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17237#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 17201#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17202#L631 assume 1 == ~t9_pc~0; 17220#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16558#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16526#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16527#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 17056#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17407#L1047 assume !(1 == ~M_E~0); 16496#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16497#L1052-1 assume !(1 == ~T2_E~0); 16479#L1057-1 assume !(1 == ~T3_E~0); 16480#L1062-1 assume !(1 == ~T4_E~0); 16769#L1067-1 assume !(1 == ~T5_E~0); 17072#L1072-1 assume !(1 == ~T6_E~0); 17073#L1077-1 assume !(1 == ~T7_E~0); 16660#L1082-1 assume !(1 == ~T8_E~0); 16661#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16452#L1092-1 assume !(1 == ~E_M~0); 16453#L1097-1 assume !(1 == ~E_1~0); 16481#L1102-1 assume !(1 == ~E_2~0); 17262#L1107-1 assume !(1 == ~E_3~0); 17197#L1112-1 assume !(1 == ~E_4~0); 17198#L1117-1 assume !(1 == ~E_5~0); 17238#L1122-1 assume !(1 == ~E_6~0); 17125#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 16879#L1132-1 assume !(1 == ~E_8~0); 16880#L1137-1 assume !(1 == ~E_9~0); 16768#L1142-1 assume { :end_inline_reset_delta_events } true; 16628#L1428-2 [2021-12-06 17:16:51,056 INFO L793 eck$LassoCheckResult]: Loop: 16628#L1428-2 assume !false; 16629#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16703#L914 assume !false; 17193#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17194#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16465#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 16466#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 17425#L783 assume !(0 != eval_~tmp~0#1); 16865#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16866#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17261#L939-3 assume !(0 == ~M_E~0); 16684#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16685#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16450#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16451#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17087#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16530#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16531#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16737#L974-3 assume !(0 == ~T8_E~0); 16738#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17168#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17169#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16791#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16792#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17303#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16614#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16615#L1014-3 assume !(0 == ~E_6~0); 17154#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17155#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17136#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 17088#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17089#L460-33 assume 1 == ~m_pc~0; 17126#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17127#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16883#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16458#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16459#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16820#L479-33 assume !(1 == ~t1_pc~0); 16821#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 16787#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16788#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17372#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 17545#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16828#L498-33 assume 1 == ~t2_pc~0; 16829#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16574#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16708#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16709#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16686#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16687#L517-33 assume !(1 == ~t3_pc~0); 17593#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 17476#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17477#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17289#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17290#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16915#L536-33 assume 1 == ~t4_pc~0; 16916#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16985#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16986#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17176#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17455#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16505#L555-33 assume !(1 == ~t5_pc~0); 16506#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 17231#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16778#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16779#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17258#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16476#L574-33 assume 1 == ~t6_pc~0; 16477#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17467#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16793#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16794#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17047#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16552#L593-33 assume !(1 == ~t7_pc~0); 16553#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 17009#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16658#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16659#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17318#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17445#L612-33 assume 1 == ~t8_pc~0; 17572#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 17536#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17537#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17379#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16656#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16657#L631-33 assume !(1 == ~t9_pc~0); 17265#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 16598#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16599#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16853#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16710#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16711#L1047-3 assume !(1 == ~M_E~0); 16884#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17498#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17430#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17431#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16609#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16610#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16992#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16837#L1082-3 assume !(1 == ~T8_E~0); 16838#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16911#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17192#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17122#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17123#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17468#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16832#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16833#L1122-3 assume !(1 == ~E_6~0); 16885#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16886#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17275#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17252#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 16715#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16593#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17253#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 17010#L1447 assume !(0 == start_simulation_~tmp~3#1); 17011#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17449#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16751#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17276#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 16861#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 16618#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16619#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 17074#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 16628#L1428-2 [2021-12-06 17:16:51,056 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:51,056 INFO L85 PathProgramCache]: Analyzing trace with hash -1747895607, now seen corresponding path program 1 times [2021-12-06 17:16:51,056 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:51,056 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1661328596] [2021-12-06 17:16:51,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:51,056 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:51,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:51,074 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:51,075 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:51,075 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1661328596] [2021-12-06 17:16:51,075 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1661328596] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:51,075 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:51,075 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:51,075 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [550553664] [2021-12-06 17:16:51,075 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:51,075 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:51,076 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:51,076 INFO L85 PathProgramCache]: Analyzing trace with hash -706898481, now seen corresponding path program 2 times [2021-12-06 17:16:51,076 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:51,076 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [179488979] [2021-12-06 17:16:51,076 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:51,076 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:51,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:51,112 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:51,112 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:51,112 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [179488979] [2021-12-06 17:16:51,112 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [179488979] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:51,112 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:51,112 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:51,113 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [309092807] [2021-12-06 17:16:51,113 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:51,113 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:51,113 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:51,113 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:16:51,113 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:16:51,113 INFO L87 Difference]: Start difference. First operand 1170 states and 1736 transitions. cyclomatic complexity: 567 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:51,128 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:51,128 INFO L93 Difference]: Finished difference Result 1170 states and 1735 transitions. [2021-12-06 17:16:51,128 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:16:51,129 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1170 states and 1735 transitions. [2021-12-06 17:16:51,133 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2021-12-06 17:16:51,139 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1170 states to 1170 states and 1735 transitions. [2021-12-06 17:16:51,139 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1170 [2021-12-06 17:16:51,140 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1170 [2021-12-06 17:16:51,140 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1170 states and 1735 transitions. [2021-12-06 17:16:51,141 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:51,141 INFO L681 BuchiCegarLoop]: Abstraction has 1170 states and 1735 transitions. [2021-12-06 17:16:51,143 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1170 states and 1735 transitions. [2021-12-06 17:16:51,152 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1170 to 1170. [2021-12-06 17:16:51,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1170 states, 1170 states have (on average 1.482905982905983) internal successors, (1735), 1169 states have internal predecessors, (1735), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:51,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 1170 states and 1735 transitions. [2021-12-06 17:16:51,157 INFO L704 BuchiCegarLoop]: Abstraction has 1170 states and 1735 transitions. [2021-12-06 17:16:51,157 INFO L587 BuchiCegarLoop]: Abstraction has 1170 states and 1735 transitions. [2021-12-06 17:16:51,157 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-06 17:16:51,157 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1170 states and 1735 transitions. [2021-12-06 17:16:51,160 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1043 [2021-12-06 17:16:51,160 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:51,160 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:51,161 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:51,161 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:51,161 INFO L791 eck$LassoCheckResult]: Stem: 19663#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 19664#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 19613#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19614#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19832#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 19499#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19500#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19809#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19308#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19309#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19737#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19738#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 18807#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 18808#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19011#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19399#L939 assume !(0 == ~M_E~0); 19643#L939-2 assume !(0 == ~T1_E~0); 19644#L944-1 assume !(0 == ~T2_E~0); 19428#L949-1 assume !(0 == ~T3_E~0); 19426#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19427#L959-1 assume !(0 == ~T5_E~0); 19846#L964-1 assume !(0 == ~T6_E~0); 19159#L969-1 assume !(0 == ~T7_E~0); 19160#L974-1 assume !(0 == ~T8_E~0); 19797#L979-1 assume !(0 == ~T9_E~0); 19798#L984-1 assume !(0 == ~E_M~0); 19320#L989-1 assume !(0 == ~E_1~0); 19321#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 19209#L999-1 assume !(0 == ~E_3~0); 19210#L1004-1 assume !(0 == ~E_4~0); 18875#L1009-1 assume !(0 == ~E_5~0); 18876#L1014-1 assume !(0 == ~E_6~0); 19203#L1019-1 assume !(0 == ~E_7~0); 19742#L1024-1 assume !(0 == ~E_8~0); 19132#L1029-1 assume !(0 == ~E_9~0); 19133#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19223#L460 assume 1 == ~m_pc~0; 18791#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18792#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19708#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19947#L1167 assume !(0 != activate_threads_~tmp~1#1); 19416#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19417#L479 assume 1 == ~t1_pc~0; 19400#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19401#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19904#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19144#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 19145#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18993#L498 assume !(1 == ~t2_pc~0); 18994#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19397#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19398#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19775#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19699#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19700#L517 assume 1 == ~t3_pc~0; 19908#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19909#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19471#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19177#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 19178#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19753#L536 assume !(1 == ~t4_pc~0); 19461#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 19460#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19837#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19453#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 19454#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19673#L555 assume 1 == ~t5_pc~0; 19674#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19743#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18906#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18907#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 19014#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18914#L574 assume !(1 == ~t6_pc~0); 18915#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19546#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19019#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19020#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 19771#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19931#L593 assume 1 == ~t7_pc~0; 19932#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19151#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19849#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19952#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 19912#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19315#L612 assume !(1 == ~t8_pc~0); 19316#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19725#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19583#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19584#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 19550#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19551#L631 assume 1 == ~t9_pc~0; 19567#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18905#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18873#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18874#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 19403#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19754#L1047 assume !(1 == ~M_E~0); 18843#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18844#L1052-1 assume !(1 == ~T2_E~0); 18826#L1057-1 assume !(1 == ~T3_E~0); 18827#L1062-1 assume !(1 == ~T4_E~0); 19116#L1067-1 assume !(1 == ~T5_E~0); 19419#L1072-1 assume !(1 == ~T6_E~0); 19420#L1077-1 assume !(1 == ~T7_E~0); 19007#L1082-1 assume !(1 == ~T8_E~0); 19008#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18801#L1092-1 assume !(1 == ~E_M~0); 18802#L1097-1 assume !(1 == ~E_1~0); 18828#L1102-1 assume !(1 == ~E_2~0); 19609#L1107-1 assume !(1 == ~E_3~0); 19544#L1112-1 assume !(1 == ~E_4~0); 19545#L1117-1 assume !(1 == ~E_5~0); 19585#L1122-1 assume !(1 == ~E_6~0); 19472#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 19228#L1132-1 assume !(1 == ~E_8~0); 19229#L1137-1 assume !(1 == ~E_9~0); 19115#L1142-1 assume { :end_inline_reset_delta_events } true; 18975#L1428-2 [2021-12-06 17:16:51,161 INFO L793 eck$LassoCheckResult]: Loop: 18975#L1428-2 assume !false; 18976#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19050#L914 assume !false; 19540#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 19541#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 18812#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 18813#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 19772#L783 assume !(0 != eval_~tmp~0#1); 19212#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19213#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19608#L939-3 assume !(0 == ~M_E~0); 19031#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19032#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18797#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18798#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19434#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18877#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18878#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19084#L974-3 assume !(0 == ~T8_E~0); 19085#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19515#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19516#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19138#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19139#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19650#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18961#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18962#L1014-3 assume !(0 == ~E_6~0); 19501#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19502#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19483#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19435#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19436#L460-33 assume 1 == ~m_pc~0; 19473#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19474#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19230#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18805#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18806#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19167#L479-33 assume !(1 == ~t1_pc~0); 19168#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 19134#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19135#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19719#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 19892#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19175#L498-33 assume 1 == ~t2_pc~0; 19176#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18921#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19057#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19058#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19033#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19034#L517-33 assume !(1 == ~t3_pc~0); 19940#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 19823#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19824#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19636#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19637#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19262#L536-33 assume !(1 == ~t4_pc~0); 19264#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 19332#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19333#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19523#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19802#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18852#L555-33 assume !(1 == ~t5_pc~0); 18853#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 19578#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19125#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19126#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19605#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18818#L574-33 assume 1 == ~t6_pc~0; 18819#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19814#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19140#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19141#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19394#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18894#L593-33 assume 1 == ~t7_pc~0; 18896#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19350#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19005#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19006#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19665#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19792#L612-33 assume !(1 == ~t8_pc~0); 19920#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 19883#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19884#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19726#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19001#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19002#L631-33 assume 1 == ~t9_pc~0; 19844#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18945#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18946#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19198#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 19055#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19056#L1047-3 assume !(1 == ~M_E~0); 19231#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19845#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19777#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19778#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18956#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18957#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19339#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19184#L1082-3 assume !(1 == ~T8_E~0); 19185#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19258#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19539#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19469#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19470#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19815#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19179#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19180#L1122-3 assume !(1 == ~E_6~0); 19232#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19233#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19622#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 19599#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 19059#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 18937#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 19600#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 19357#L1447 assume !(0 == start_simulation_~tmp~3#1); 19358#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 19796#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19098#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 19623#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 19208#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 18965#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18966#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 19421#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 18975#L1428-2 [2021-12-06 17:16:51,162 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:51,162 INFO L85 PathProgramCache]: Analyzing trace with hash -1866337081, now seen corresponding path program 1 times [2021-12-06 17:16:51,162 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:51,162 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1214695413] [2021-12-06 17:16:51,162 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:51,162 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:51,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:51,189 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:51,189 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:51,189 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1214695413] [2021-12-06 17:16:51,189 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1214695413] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:51,189 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:51,189 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:51,190 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1247585839] [2021-12-06 17:16:51,190 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:51,190 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:51,190 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:51,190 INFO L85 PathProgramCache]: Analyzing trace with hash -1679945009, now seen corresponding path program 1 times [2021-12-06 17:16:51,190 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:51,190 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1577753037] [2021-12-06 17:16:51,190 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:51,191 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:51,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:51,214 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:51,214 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:51,214 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1577753037] [2021-12-06 17:16:51,214 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1577753037] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:51,214 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:51,214 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:51,215 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1270238405] [2021-12-06 17:16:51,215 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:51,215 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:51,215 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:51,215 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 17:16:51,215 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 17:16:51,215 INFO L87 Difference]: Start difference. First operand 1170 states and 1735 transitions. cyclomatic complexity: 566 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:51,298 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:51,298 INFO L93 Difference]: Finished difference Result 2141 states and 3163 transitions. [2021-12-06 17:16:51,299 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 17:16:51,299 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2141 states and 3163 transitions. [2021-12-06 17:16:51,307 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1994 [2021-12-06 17:16:51,318 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2141 states to 2141 states and 3163 transitions. [2021-12-06 17:16:51,318 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2141 [2021-12-06 17:16:51,320 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2141 [2021-12-06 17:16:51,320 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2141 states and 3163 transitions. [2021-12-06 17:16:51,322 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:51,322 INFO L681 BuchiCegarLoop]: Abstraction has 2141 states and 3163 transitions. [2021-12-06 17:16:51,324 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2141 states and 3163 transitions. [2021-12-06 17:16:51,350 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2141 to 2141. [2021-12-06 17:16:51,353 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2141 states, 2141 states have (on average 1.4773470340962167) internal successors, (3163), 2140 states have internal predecessors, (3163), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:51,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2141 states to 2141 states and 3163 transitions. [2021-12-06 17:16:51,359 INFO L704 BuchiCegarLoop]: Abstraction has 2141 states and 3163 transitions. [2021-12-06 17:16:51,359 INFO L587 BuchiCegarLoop]: Abstraction has 2141 states and 3163 transitions. [2021-12-06 17:16:51,359 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-06 17:16:51,359 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2141 states and 3163 transitions. [2021-12-06 17:16:51,364 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1994 [2021-12-06 17:16:51,364 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:51,364 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:51,365 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:51,365 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:51,365 INFO L791 eck$LassoCheckResult]: Stem: 22999#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 23000#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 22947#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22948#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23188#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 22828#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22829#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23164#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22634#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22635#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23082#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23083#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 22128#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 22129#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22332#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22725#L939 assume !(0 == ~M_E~0); 22977#L939-2 assume !(0 == ~T1_E~0); 22978#L944-1 assume !(0 == ~T2_E~0); 22754#L949-1 assume !(0 == ~T3_E~0); 22752#L954-1 assume !(0 == ~T4_E~0); 22753#L959-1 assume !(0 == ~T5_E~0); 23206#L964-1 assume !(0 == ~T6_E~0); 22481#L969-1 assume !(0 == ~T7_E~0); 22482#L974-1 assume !(0 == ~T8_E~0); 23152#L979-1 assume !(0 == ~T9_E~0); 23153#L984-1 assume !(0 == ~E_M~0); 22648#L989-1 assume !(0 == ~E_1~0); 22649#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 22531#L999-1 assume !(0 == ~E_3~0); 22532#L1004-1 assume !(0 == ~E_4~0); 22196#L1009-1 assume !(0 == ~E_5~0); 22197#L1014-1 assume !(0 == ~E_6~0); 22527#L1019-1 assume !(0 == ~E_7~0); 23087#L1024-1 assume !(0 == ~E_8~0); 22454#L1029-1 assume !(0 == ~E_9~0); 22455#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22547#L460 assume 1 == ~m_pc~0; 22115#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22116#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23052#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 23334#L1167 assume !(0 != activate_threads_~tmp~1#1); 22742#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22743#L479 assume 1 == ~t1_pc~0; 22726#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22727#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23276#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22467#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 22468#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22314#L498 assume !(1 == ~t2_pc~0); 22315#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 22723#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22724#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23125#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23042#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23043#L517 assume 1 == ~t3_pc~0; 23281#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23282#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22798#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22499#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 22500#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23099#L536 assume !(1 == ~t4_pc~0); 22788#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22787#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23195#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22780#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 22781#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23011#L555 assume 1 == ~t5_pc~0; 23012#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23088#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22229#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22230#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 22335#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22235#L574 assume !(1 == ~t6_pc~0); 22236#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22878#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22340#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22341#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 23120#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23314#L593 assume 1 == ~t7_pc~0; 23315#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22473#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23210#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23343#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 23284#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22641#L612 assume !(1 == ~t8_pc~0); 22642#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 23069#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22916#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22917#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 22882#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22883#L631 assume 1 == ~t9_pc~0; 22899#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22226#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22194#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22195#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 22729#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23100#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 22166#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22167#L1052-1 assume !(1 == ~T2_E~0); 23558#L1057-1 assume !(1 == ~T3_E~0); 23557#L1062-1 assume !(1 == ~T4_E~0); 22437#L1067-1 assume !(1 == ~T5_E~0); 22745#L1072-1 assume !(1 == ~T6_E~0); 22746#L1077-1 assume !(1 == ~T7_E~0); 22328#L1082-1 assume !(1 == ~T8_E~0); 22329#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22124#L1092-1 assume !(1 == ~E_M~0); 22125#L1097-1 assume !(1 == ~E_1~0); 22149#L1102-1 assume !(1 == ~E_2~0); 22943#L1107-1 assume !(1 == ~E_3~0); 22876#L1112-1 assume !(1 == ~E_4~0); 22877#L1117-1 assume !(1 == ~E_5~0); 22918#L1122-1 assume !(1 == ~E_6~0); 22799#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 22550#L1132-1 assume !(1 == ~E_8~0); 22551#L1137-1 assume !(1 == ~E_9~0); 22436#L1142-1 assume { :end_inline_reset_delta_events } true; 22299#L1428-2 [2021-12-06 17:16:51,365 INFO L793 eck$LassoCheckResult]: Loop: 22299#L1428-2 assume !false; 22300#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23317#L914 assume !false; 23318#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 23073#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 22135#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 22136#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 23121#L783 assume !(0 != eval_~tmp~0#1); 23122#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22941#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22942#L939-3 assume !(0 == ~M_E~0); 22354#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22355#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22118#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22119#L954-3 assume !(0 == ~T4_E~0); 22760#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22200#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22201#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22405#L974-3 assume !(0 == ~T8_E~0); 22406#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22842#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22843#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22460#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22461#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22986#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22282#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22283#L1014-3 assume !(0 == ~E_6~0); 22826#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 22827#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22808#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22761#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22762#L460-33 assume 1 == ~m_pc~0; 22800#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22801#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22552#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22126#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22127#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22485#L479-33 assume !(1 == ~t1_pc~0); 22486#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 23663#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23662#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23661#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 23660#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23659#L498-33 assume 1 == ~t2_pc~0; 23657#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23656#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23655#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23654#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23653#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23652#L517-33 assume 1 == ~t3_pc~0; 23650#L518-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23649#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23648#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23647#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23646#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23645#L536-33 assume 1 == ~t4_pc~0; 23643#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 23642#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23641#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23640#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23639#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23638#L555-33 assume !(1 == ~t5_pc~0); 23636#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 23635#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23634#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23633#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 23632#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23631#L574-33 assume 1 == ~t6_pc~0; 23629#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23628#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23627#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23626#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23625#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23624#L593-33 assume !(1 == ~t7_pc~0); 23622#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 23621#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23620#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23619#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 23618#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23617#L612-33 assume !(1 == ~t8_pc~0); 23616#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 23614#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23613#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23612#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 23611#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 23360#L631-33 assume !(1 == ~t9_pc~0); 22946#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 22266#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22267#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22520#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 22378#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22379#L1047-3 assume !(1 == ~M_E~0); 22553#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23205#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23362#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23361#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22277#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22278#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 22665#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22506#L1082-3 assume !(1 == ~T8_E~0); 22507#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22581#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22869#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22796#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22797#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23171#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22501#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22502#L1122-3 assume !(1 == ~E_6~0); 22554#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22555#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 22956#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 22932#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 22383#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 22258#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 22933#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 22683#L1447 assume !(0 == start_simulation_~tmp~3#1); 22684#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 23489#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 23480#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 23479#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 23478#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 23477#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23476#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 22747#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 22299#L1428-2 [2021-12-06 17:16:51,366 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:51,366 INFO L85 PathProgramCache]: Analyzing trace with hash 99525123, now seen corresponding path program 1 times [2021-12-06 17:16:51,366 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:51,366 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1142629202] [2021-12-06 17:16:51,366 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:51,366 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:51,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:51,387 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:51,387 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:51,387 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1142629202] [2021-12-06 17:16:51,387 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1142629202] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:51,387 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:51,388 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 17:16:51,388 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1407417551] [2021-12-06 17:16:51,388 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:51,388 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:51,388 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:51,388 INFO L85 PathProgramCache]: Analyzing trace with hash 442140877, now seen corresponding path program 1 times [2021-12-06 17:16:51,388 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:51,388 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1147864018] [2021-12-06 17:16:51,389 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:51,389 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:51,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:51,412 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:51,412 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:51,412 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1147864018] [2021-12-06 17:16:51,412 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1147864018] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:51,412 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:51,412 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:51,412 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2034556426] [2021-12-06 17:16:51,413 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:51,413 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:51,413 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:51,413 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:16:51,413 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:16:51,413 INFO L87 Difference]: Start difference. First operand 2141 states and 3163 transitions. cyclomatic complexity: 1024 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:51,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:51,465 INFO L93 Difference]: Finished difference Result 2141 states and 3133 transitions. [2021-12-06 17:16:51,465 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:16:51,466 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2141 states and 3133 transitions. [2021-12-06 17:16:51,476 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1994 [2021-12-06 17:16:51,492 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2141 states to 2141 states and 3133 transitions. [2021-12-06 17:16:51,492 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2141 [2021-12-06 17:16:51,494 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2141 [2021-12-06 17:16:51,494 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2141 states and 3133 transitions. [2021-12-06 17:16:51,497 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:51,497 INFO L681 BuchiCegarLoop]: Abstraction has 2141 states and 3133 transitions. [2021-12-06 17:16:51,500 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2141 states and 3133 transitions. [2021-12-06 17:16:51,554 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2141 to 2141. [2021-12-06 17:16:51,557 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2141 states, 2141 states have (on average 1.4633348902382064) internal successors, (3133), 2140 states have internal predecessors, (3133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:51,562 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2141 states to 2141 states and 3133 transitions. [2021-12-06 17:16:51,562 INFO L704 BuchiCegarLoop]: Abstraction has 2141 states and 3133 transitions. [2021-12-06 17:16:51,563 INFO L587 BuchiCegarLoop]: Abstraction has 2141 states and 3133 transitions. [2021-12-06 17:16:51,563 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-06 17:16:51,563 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2141 states and 3133 transitions. [2021-12-06 17:16:51,567 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1994 [2021-12-06 17:16:51,567 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:51,567 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:51,568 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:51,568 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:51,569 INFO L791 eck$LassoCheckResult]: Stem: 27318#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 27319#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 27263#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27264#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27534#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 27132#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27133#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27496#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26931#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26932#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27407#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27408#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26417#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 26418#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 26621#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27027#L939 assume !(0 == ~M_E~0); 27297#L939-2 assume !(0 == ~T1_E~0); 27298#L944-1 assume !(0 == ~T2_E~0); 27056#L949-1 assume !(0 == ~T3_E~0); 27054#L954-1 assume !(0 == ~T4_E~0); 27055#L959-1 assume !(0 == ~T5_E~0); 27551#L964-1 assume !(0 == ~T6_E~0); 26770#L969-1 assume !(0 == ~T7_E~0); 26771#L974-1 assume !(0 == ~T8_E~0); 27484#L979-1 assume !(0 == ~T9_E~0); 27485#L984-1 assume !(0 == ~E_M~0); 26943#L989-1 assume !(0 == ~E_1~0); 26944#L994-1 assume !(0 == ~E_2~0); 26822#L999-1 assume !(0 == ~E_3~0); 26823#L1004-1 assume !(0 == ~E_4~0); 26485#L1009-1 assume !(0 == ~E_5~0); 26486#L1014-1 assume !(0 == ~E_6~0); 26818#L1019-1 assume !(0 == ~E_7~0); 27412#L1024-1 assume !(0 == ~E_8~0); 26743#L1029-1 assume !(0 == ~E_9~0); 26744#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26839#L460 assume 1 == ~m_pc~0; 26404#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26405#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27371#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 27694#L1167 assume !(0 != activate_threads_~tmp~1#1); 27044#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27045#L479 assume 1 == ~t1_pc~0; 27028#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27029#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27626#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26756#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 26757#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26603#L498 assume !(1 == ~t2_pc~0); 26604#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 27025#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27026#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27454#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27361#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27362#L517 assume 1 == ~t3_pc~0; 27631#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27632#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27100#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26788#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 26789#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27423#L536 assume !(1 == ~t4_pc~0); 27090#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 27089#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27541#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27082#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 27083#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27332#L555 assume 1 == ~t5_pc~0; 27333#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27413#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26518#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26519#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 26626#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26524#L574 assume !(1 == ~t6_pc~0); 26525#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 27188#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26629#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26630#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 27449#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27672#L593 assume 1 == ~t7_pc~0; 27673#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26762#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27558#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27706#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 27634#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26936#L612 assume !(1 == ~t8_pc~0); 26937#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 27391#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27229#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27230#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 27192#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27193#L631 assume 1 == ~t9_pc~0; 27209#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26515#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26483#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26484#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 27031#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27424#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 26455#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26456#L1052-1 assume !(1 == ~T2_E~0); 26436#L1057-1 assume !(1 == ~T3_E~0); 26437#L1062-1 assume !(1 == ~T4_E~0); 26727#L1067-1 assume !(1 == ~T5_E~0); 27047#L1072-1 assume !(1 == ~T6_E~0); 27048#L1077-1 assume !(1 == ~T7_E~0); 26617#L1082-1 assume !(1 == ~T8_E~0); 26618#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 27797#L1092-1 assume !(1 == ~E_M~0); 27796#L1097-1 assume !(1 == ~E_1~0); 27658#L1102-1 assume !(1 == ~E_2~0); 27256#L1107-1 assume !(1 == ~E_3~0); 27257#L1112-1 assume !(1 == ~E_4~0); 27752#L1117-1 assume !(1 == ~E_5~0); 27751#L1122-1 assume !(1 == ~E_6~0); 27750#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 27749#L1132-1 assume !(1 == ~E_8~0); 27661#L1137-1 assume !(1 == ~E_9~0); 26726#L1142-1 assume { :end_inline_reset_delta_events } true; 26588#L1428-2 [2021-12-06 17:16:51,569 INFO L793 eck$LassoCheckResult]: Loop: 26588#L1428-2 assume !false; 26589#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27675#L914 assume !false; 27676#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 27398#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 26424#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 26425#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 27450#L783 assume !(0 != eval_~tmp~0#1); 27451#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27254#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27255#L939-3 assume !(0 == ~M_E~0); 26643#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26644#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26407#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26408#L954-3 assume !(0 == ~T4_E~0); 27063#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26489#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 26490#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 26694#L974-3 assume !(0 == ~T8_E~0); 26695#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 27148#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 27149#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26749#L994-3 assume !(0 == ~E_2~0); 26750#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27306#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26571#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26572#L1014-3 assume !(0 == ~E_6~0); 27130#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 27131#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27110#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 27064#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27065#L460-33 assume !(1 == ~m_pc~0); 27104#L460-35 is_master_triggered_~__retres1~0#1 := 0; 27103#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26844#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26415#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26416#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26777#L479-33 assume !(1 == ~t1_pc~0); 26778#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 26745#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26746#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27893#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 27891#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27889#L498-33 assume !(1 == ~t2_pc~0); 27885#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 27007#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26665#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26666#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26641#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26642#L517-33 assume !(1 == ~t3_pc~0); 27685#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 27520#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27521#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27290#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27291#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26880#L536-33 assume 1 == ~t4_pc~0; 26881#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27869#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27868#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27867#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 27866#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27865#L555-33 assume !(1 == ~t5_pc~0); 27863#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 27862#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27861#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27860#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 27859#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27858#L574-33 assume 1 == ~t6_pc~0; 27856#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27855#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27854#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27851#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27022#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26509#L593-33 assume !(1 == ~t7_pc~0); 26510#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 27665#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26615#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26616#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 27320#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27714#L612-33 assume 1 == ~t8_pc~0; 27715#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 27600#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27601#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27392#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 27393#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27826#L631-33 assume 1 == ~t9_pc~0; 27549#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27262#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27135#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27136#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 26667#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26668#L1047-3 assume !(1 == ~M_E~0); 26847#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27819#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27457#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27458#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27728#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27805#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26961#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26795#L1082-3 assume !(1 == ~T8_E~0); 26796#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 27176#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 27177#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 27730#L1102-3 assume !(1 == ~E_2~0); 27664#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27506#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27507#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27516#L1122-3 assume !(1 == ~E_6~0); 27517#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 27788#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 27785#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 27245#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 26672#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 26546#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 27246#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 26981#L1447 assume !(0 == start_simulation_~tmp~3#1); 26982#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 27481#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 26709#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 27275#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 27276#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 27760#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27758#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 27049#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 26588#L1428-2 [2021-12-06 17:16:51,569 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:51,569 INFO L85 PathProgramCache]: Analyzing trace with hash 1976588353, now seen corresponding path program 1 times [2021-12-06 17:16:51,569 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:51,569 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1573760871] [2021-12-06 17:16:51,570 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:51,570 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:51,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:51,590 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:51,590 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:51,590 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1573760871] [2021-12-06 17:16:51,590 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1573760871] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:51,590 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:51,591 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 17:16:51,591 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1913588869] [2021-12-06 17:16:51,591 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:51,591 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:51,591 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:51,591 INFO L85 PathProgramCache]: Analyzing trace with hash -748148786, now seen corresponding path program 1 times [2021-12-06 17:16:51,591 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:51,591 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [58000306] [2021-12-06 17:16:51,592 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:51,592 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:51,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:51,615 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:51,615 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:51,615 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [58000306] [2021-12-06 17:16:51,615 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [58000306] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:51,615 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:51,615 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:51,615 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2125963189] [2021-12-06 17:16:51,615 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:51,616 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:51,616 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:51,616 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:16:51,616 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:16:51,616 INFO L87 Difference]: Start difference. First operand 2141 states and 3133 transitions. cyclomatic complexity: 994 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:51,698 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:51,699 INFO L93 Difference]: Finished difference Result 4105 states and 5952 transitions. [2021-12-06 17:16:51,699 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:16:51,699 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4105 states and 5952 transitions. [2021-12-06 17:16:51,713 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3957 [2021-12-06 17:16:51,733 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4105 states to 4105 states and 5952 transitions. [2021-12-06 17:16:51,734 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4105 [2021-12-06 17:16:51,736 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4105 [2021-12-06 17:16:51,737 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4105 states and 5952 transitions. [2021-12-06 17:16:51,741 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:51,741 INFO L681 BuchiCegarLoop]: Abstraction has 4105 states and 5952 transitions. [2021-12-06 17:16:51,745 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4105 states and 5952 transitions. [2021-12-06 17:16:51,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4105 to 3967. [2021-12-06 17:16:51,795 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3967 states, 3967 states have (on average 1.4519788253087975) internal successors, (5760), 3966 states have internal predecessors, (5760), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:51,802 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3967 states to 3967 states and 5760 transitions. [2021-12-06 17:16:51,802 INFO L704 BuchiCegarLoop]: Abstraction has 3967 states and 5760 transitions. [2021-12-06 17:16:51,802 INFO L587 BuchiCegarLoop]: Abstraction has 3967 states and 5760 transitions. [2021-12-06 17:16:51,802 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-06 17:16:51,802 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3967 states and 5760 transitions. [2021-12-06 17:16:51,811 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3819 [2021-12-06 17:16:51,811 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:51,811 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:51,813 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:51,813 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:51,813 INFO L791 eck$LassoCheckResult]: Stem: 33525#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 33526#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 33476#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33477#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33706#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 33360#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33361#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33682#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33169#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33170#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33605#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33606#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32667#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 32668#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 32870#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33261#L939 assume !(0 == ~M_E~0); 33506#L939-2 assume !(0 == ~T1_E~0); 33507#L944-1 assume !(0 == ~T2_E~0); 33290#L949-1 assume !(0 == ~T3_E~0); 33288#L954-1 assume !(0 == ~T4_E~0); 33289#L959-1 assume !(0 == ~T5_E~0); 33722#L964-1 assume !(0 == ~T6_E~0); 33019#L969-1 assume !(0 == ~T7_E~0); 33020#L974-1 assume !(0 == ~T8_E~0); 33669#L979-1 assume !(0 == ~T9_E~0); 33670#L984-1 assume !(0 == ~E_M~0); 33181#L989-1 assume !(0 == ~E_1~0); 33182#L994-1 assume !(0 == ~E_2~0); 33068#L999-1 assume !(0 == ~E_3~0); 33069#L1004-1 assume !(0 == ~E_4~0); 32735#L1009-1 assume !(0 == ~E_5~0); 32736#L1014-1 assume !(0 == ~E_6~0); 33060#L1019-1 assume !(0 == ~E_7~0); 33612#L1024-1 assume !(0 == ~E_8~0); 32992#L1029-1 assume !(0 == ~E_9~0); 32993#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33082#L460 assume !(1 == ~m_pc~0); 33820#L460-2 is_master_triggered_~__retres1~0#1 := 0; 33577#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33578#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 33844#L1167 assume !(0 != activate_threads_~tmp~1#1); 33277#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33278#L479 assume 1 == ~t1_pc~0; 33262#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33263#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33789#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33004#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 33005#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32852#L498 assume !(1 == ~t2_pc~0); 32853#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 33259#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33260#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 33646#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33565#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33566#L517 assume 1 == ~t3_pc~0; 33794#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33795#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33332#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33037#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 33038#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33621#L536 assume !(1 == ~t4_pc~0); 33322#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 33321#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33712#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33314#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 33315#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33534#L555 assume 1 == ~t5_pc~0; 33535#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33613#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32766#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32767#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 32873#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32774#L574 assume !(1 == ~t6_pc~0); 32775#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 33408#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32878#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32879#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 33640#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33825#L593 assume 1 == ~t7_pc~0; 33826#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33011#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33725#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33849#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 33800#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33176#L612 assume !(1 == ~t8_pc~0); 33177#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 33595#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33445#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33446#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 33410#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33411#L631 assume 1 == ~t9_pc~0; 33429#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32765#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32733#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32734#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 33265#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33624#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 33625#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35728#L1052-1 assume !(1 == ~T2_E~0); 35727#L1057-1 assume !(1 == ~T3_E~0); 35726#L1062-1 assume !(1 == ~T4_E~0); 32975#L1067-1 assume !(1 == ~T5_E~0); 35725#L1072-1 assume !(1 == ~T6_E~0); 35723#L1077-1 assume !(1 == ~T7_E~0); 35722#L1082-1 assume !(1 == ~T8_E~0); 35721#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 35719#L1092-1 assume !(1 == ~E_M~0); 35708#L1097-1 assume !(1 == ~E_1~0); 35706#L1102-1 assume !(1 == ~E_2~0); 35704#L1107-1 assume !(1 == ~E_3~0); 35702#L1112-1 assume !(1 == ~E_4~0); 35700#L1117-1 assume !(1 == ~E_5~0); 35698#L1122-1 assume !(1 == ~E_6~0); 35697#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 35696#L1132-1 assume !(1 == ~E_8~0); 33815#L1137-1 assume !(1 == ~E_9~0); 32974#L1142-1 assume { :end_inline_reset_delta_events } true; 32834#L1428-2 [2021-12-06 17:16:51,813 INFO L793 eck$LassoCheckResult]: Loop: 32834#L1428-2 assume !false; 32835#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32909#L914 assume !false; 33401#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 33402#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 32672#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 32673#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 33643#L783 assume !(0 != eval_~tmp~0#1); 33071#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33072#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35724#L939-3 assume !(0 == ~M_E~0); 32890#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 32891#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32657#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32658#L954-3 assume !(0 == ~T4_E~0); 33296#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32737#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32738#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 32943#L974-3 assume !(0 == ~T8_E~0); 32944#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33376#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 33377#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32998#L994-3 assume !(0 == ~E_2~0); 32999#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33513#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 32820#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32821#L1014-3 assume !(0 == ~E_6~0); 33362#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 33363#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 33344#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 33297#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33298#L460-33 assume !(1 == ~m_pc~0); 33549#L460-35 is_master_triggered_~__retres1~0#1 := 0; 33528#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33089#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 32665#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 32666#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33026#L479-33 assume !(1 == ~t1_pc~0); 33027#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 32994#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32995#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33589#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 33773#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33035#L498-33 assume !(1 == ~t2_pc~0); 32779#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 32780#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32914#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 32915#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 32892#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32893#L517-33 assume !(1 == ~t3_pc~0); 33837#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 33697#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33698#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33499#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33500#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33124#L536-33 assume 1 == ~t4_pc~0; 33125#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33193#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33194#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33384#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33675#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32712#L555-33 assume !(1 == ~t5_pc~0); 32713#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 33440#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32985#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32986#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33467#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32683#L574-33 assume 1 == ~t6_pc~0; 32684#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33687#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33000#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33001#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33256#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32759#L593-33 assume !(1 == ~t7_pc~0); 32760#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 33216#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32864#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32865#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33527#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33664#L612-33 assume 1 == ~t8_pc~0; 33808#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33763#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33764#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33596#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32862#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32863#L631-33 assume !(1 == ~t9_pc~0); 33475#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 32803#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32804#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33059#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 32916#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32917#L1047-3 assume !(1 == ~M_E~0); 33090#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33721#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33648#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33649#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32814#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 32815#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33200#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33044#L1082-3 assume !(1 == ~T8_E~0); 33045#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 33120#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33400#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33330#L1102-3 assume !(1 == ~E_2~0); 33331#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33689#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33039#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33040#L1122-3 assume !(1 == ~E_6~0); 33091#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 33092#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 33485#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 33461#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 32921#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 32798#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 33462#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 33218#L1447 assume !(0 == start_simulation_~tmp~3#1); 33219#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 33668#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 32957#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 33486#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 33067#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 32824#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 32825#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 33283#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 32834#L1428-2 [2021-12-06 17:16:51,813 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:51,813 INFO L85 PathProgramCache]: Analyzing trace with hash -858385022, now seen corresponding path program 1 times [2021-12-06 17:16:51,813 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:51,814 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1237144071] [2021-12-06 17:16:51,814 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:51,814 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:51,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:51,837 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:51,837 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:51,837 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1237144071] [2021-12-06 17:16:51,837 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1237144071] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:51,837 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:51,838 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:51,838 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [501436948] [2021-12-06 17:16:51,838 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:51,838 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:51,838 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:51,839 INFO L85 PathProgramCache]: Analyzing trace with hash -1705077169, now seen corresponding path program 1 times [2021-12-06 17:16:51,839 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:51,839 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [773503953] [2021-12-06 17:16:51,839 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:51,839 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:51,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:51,871 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:51,871 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:51,871 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [773503953] [2021-12-06 17:16:51,871 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [773503953] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:51,871 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:51,871 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:51,872 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [244725745] [2021-12-06 17:16:51,872 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:51,872 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:51,872 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:51,873 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 17:16:51,873 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 17:16:51,873 INFO L87 Difference]: Start difference. First operand 3967 states and 5760 transitions. cyclomatic complexity: 1797 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:52,049 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:52,049 INFO L93 Difference]: Finished difference Result 9505 states and 13663 transitions. [2021-12-06 17:16:52,049 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 17:16:52,050 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9505 states and 13663 transitions. [2021-12-06 17:16:52,081 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 9204 [2021-12-06 17:16:52,128 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9505 states to 9505 states and 13663 transitions. [2021-12-06 17:16:52,128 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9505 [2021-12-06 17:16:52,135 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9505 [2021-12-06 17:16:52,135 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9505 states and 13663 transitions. [2021-12-06 17:16:52,145 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:52,145 INFO L681 BuchiCegarLoop]: Abstraction has 9505 states and 13663 transitions. [2021-12-06 17:16:52,152 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9505 states and 13663 transitions. [2021-12-06 17:16:52,231 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9505 to 7449. [2021-12-06 17:16:52,242 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7449 states, 7449 states have (on average 1.4431467311048463) internal successors, (10750), 7448 states have internal predecessors, (10750), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:52,257 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7449 states to 7449 states and 10750 transitions. [2021-12-06 17:16:52,257 INFO L704 BuchiCegarLoop]: Abstraction has 7449 states and 10750 transitions. [2021-12-06 17:16:52,257 INFO L587 BuchiCegarLoop]: Abstraction has 7449 states and 10750 transitions. [2021-12-06 17:16:52,257 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-06 17:16:52,257 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7449 states and 10750 transitions. [2021-12-06 17:16:52,274 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7300 [2021-12-06 17:16:52,275 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:52,275 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:52,276 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:52,276 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:52,276 INFO L791 eck$LassoCheckResult]: Stem: 47019#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 47020#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 46966#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46967#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 47204#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 46837#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46838#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47180#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46651#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46652#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 47102#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 47103#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 46149#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 46150#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 46352#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46742#L939 assume !(0 == ~M_E~0); 46998#L939-2 assume !(0 == ~T1_E~0); 46999#L944-1 assume !(0 == ~T2_E~0); 46768#L949-1 assume !(0 == ~T3_E~0); 46766#L954-1 assume !(0 == ~T4_E~0); 46767#L959-1 assume !(0 == ~T5_E~0); 47221#L964-1 assume !(0 == ~T6_E~0); 46503#L969-1 assume !(0 == ~T7_E~0); 46504#L974-1 assume !(0 == ~T8_E~0); 47165#L979-1 assume !(0 == ~T9_E~0); 47166#L984-1 assume !(0 == ~E_M~0); 46663#L989-1 assume !(0 == ~E_1~0); 46664#L994-1 assume !(0 == ~E_2~0); 46550#L999-1 assume !(0 == ~E_3~0); 46551#L1004-1 assume !(0 == ~E_4~0); 46218#L1009-1 assume !(0 == ~E_5~0); 46219#L1014-1 assume !(0 == ~E_6~0); 46542#L1019-1 assume !(0 == ~E_7~0); 47109#L1024-1 assume !(0 == ~E_8~0); 46475#L1029-1 assume !(0 == ~E_9~0); 46476#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46564#L460 assume !(1 == ~m_pc~0); 47339#L460-2 is_master_triggered_~__retres1~0#1 := 0; 47072#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47073#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 47364#L1167 assume !(0 != activate_threads_~tmp~1#1); 46755#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46756#L479 assume !(1 == ~t1_pc~0); 46913#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46914#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47296#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 46487#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 46488#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46334#L498 assume !(1 == ~t2_pc~0); 46335#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 46740#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46741#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 47143#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 47059#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47060#L517 assume 1 == ~t3_pc~0; 47301#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 47302#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46810#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46520#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 46521#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47118#L536 assume !(1 == ~t4_pc~0); 46800#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 46799#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47209#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46792#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 46793#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47028#L555 assume 1 == ~t5_pc~0; 47029#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47110#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46249#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46250#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 46355#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46257#L574 assume !(1 == ~t6_pc~0); 46258#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 46890#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46360#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46361#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 47137#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47346#L593 assume 1 == ~t7_pc~0; 47347#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46495#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47226#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47380#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 47307#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46658#L612 assume !(1 == ~t8_pc~0); 46659#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 47090#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46933#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46934#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 46892#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 46893#L631 assume 1 == ~t9_pc~0; 46911#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46248#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46216#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46217#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 46743#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47121#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 46186#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46187#L1052-1 assume !(1 == ~T2_E~0); 46168#L1057-1 assume !(1 == ~T3_E~0); 46169#L1062-1 assume !(1 == ~T4_E~0); 46458#L1067-1 assume !(1 == ~T5_E~0); 47222#L1072-1 assume !(1 == ~T6_E~0); 47092#L1077-1 assume !(1 == ~T7_E~0); 47093#L1082-1 assume !(1 == ~T8_E~0); 46864#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46865#L1092-1 assume !(1 == ~E_M~0); 46170#L1097-1 assume !(1 == ~E_1~0); 46171#L1102-1 assume !(1 == ~E_2~0); 46961#L1107-1 assume !(1 == ~E_3~0); 46962#L1112-1 assume !(1 == ~E_4~0); 46935#L1117-1 assume !(1 == ~E_5~0); 46936#L1122-1 assume !(1 == ~E_6~0); 46811#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 46812#L1132-1 assume !(1 == ~E_8~0); 47333#L1137-1 assume !(1 == ~E_9~0); 47334#L1142-1 assume { :end_inline_reset_delta_events } true; 52797#L1428-2 [2021-12-06 17:16:52,276 INFO L793 eck$LassoCheckResult]: Loop: 52797#L1428-2 assume !false; 52791#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 52787#L914 assume !false; 52786#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 52784#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 52775#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 52774#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 52772#L783 assume !(0 != eval_~tmp~0#1); 52773#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 53584#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 53583#L939-3 assume !(0 == ~M_E~0); 53582#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 53581#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 53580#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 53579#L954-3 assume !(0 == ~T4_E~0); 53578#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 53577#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 53576#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53575#L974-3 assume !(0 == ~T8_E~0); 53574#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 53573#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 53572#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 53571#L994-3 assume !(0 == ~E_2~0); 53570#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 53569#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 53568#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 53567#L1014-3 assume !(0 == ~E_6~0); 53566#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 53565#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 53564#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 53563#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53562#L460-33 assume !(1 == ~m_pc~0); 53561#L460-35 is_master_triggered_~__retres1~0#1 := 0; 53560#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53559#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 53558#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 53557#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53556#L479-33 assume !(1 == ~t1_pc~0); 52724#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 53555#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53554#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 53553#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 53552#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53516#L498-33 assume !(1 == ~t2_pc~0); 53513#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 53511#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53509#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 53506#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 53504#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53503#L517-33 assume 1 == ~t3_pc~0; 47368#L518-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 47195#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47196#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46991#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46992#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46603#L536-33 assume 1 == ~t4_pc~0; 46604#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46675#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46676#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53434#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 53433#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53432#L555-33 assume !(1 == ~t5_pc~0); 53430#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 53429#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53428#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53427#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 53426#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53425#L574-33 assume !(1 == ~t6_pc~0); 53424#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 53422#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53421#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53420#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 53419#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53418#L593-33 assume !(1 == ~t7_pc~0); 53416#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 53415#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53414#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53413#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 53412#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53411#L612-33 assume 1 == ~t8_pc~0; 53409#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 53408#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53407#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53406#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 53405#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53404#L631-33 assume !(1 == ~t9_pc~0); 53402#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 53401#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53400#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53398#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 53396#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53394#L1047-3 assume !(1 == ~M_E~0); 46573#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 53391#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 53388#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53386#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47399#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 53383#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 53381#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 53379#L1082-3 assume !(1 == ~T8_E~0); 53376#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 53374#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 53053#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 53052#L1102-3 assume !(1 == ~E_2~0); 53051#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 53050#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53049#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 53048#L1122-3 assume !(1 == ~E_6~0); 53047#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 53046#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 53045#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 53044#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 53042#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 53033#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 53032#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 53031#L1447 assume !(0 == start_simulation_~tmp~3#1); 46851#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 53027#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 53017#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 53015#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 53013#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 52833#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 52812#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 52804#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 52797#L1428-2 [2021-12-06 17:16:52,276 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:52,277 INFO L85 PathProgramCache]: Analyzing trace with hash -717285501, now seen corresponding path program 1 times [2021-12-06 17:16:52,277 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:52,277 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1070846833] [2021-12-06 17:16:52,277 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:52,277 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:52,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:52,317 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:52,317 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:52,317 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1070846833] [2021-12-06 17:16:52,317 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1070846833] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:52,317 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:52,317 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 17:16:52,317 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [381011243] [2021-12-06 17:16:52,317 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:52,318 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:52,318 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:52,318 INFO L85 PathProgramCache]: Analyzing trace with hash -1605909361, now seen corresponding path program 1 times [2021-12-06 17:16:52,318 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:52,318 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [789362435] [2021-12-06 17:16:52,319 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:52,319 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:52,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:52,347 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:52,348 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:52,348 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [789362435] [2021-12-06 17:16:52,348 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [789362435] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:52,348 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:52,348 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 17:16:52,348 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1372228482] [2021-12-06 17:16:52,348 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:52,348 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:52,349 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:52,349 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-06 17:16:52,349 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-06 17:16:52,349 INFO L87 Difference]: Start difference. First operand 7449 states and 10750 transitions. cyclomatic complexity: 3305 Second operand has 5 states, 5 states have (on average 23.4) internal successors, (117), 5 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:52,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:52,482 INFO L93 Difference]: Finished difference Result 9557 states and 13735 transitions. [2021-12-06 17:16:52,482 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-06 17:16:52,483 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9557 states and 13735 transitions. [2021-12-06 17:16:52,517 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 9404 [2021-12-06 17:16:52,543 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9557 states to 9557 states and 13735 transitions. [2021-12-06 17:16:52,543 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9557 [2021-12-06 17:16:52,550 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9557 [2021-12-06 17:16:52,550 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9557 states and 13735 transitions. [2021-12-06 17:16:52,558 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:52,558 INFO L681 BuchiCegarLoop]: Abstraction has 9557 states and 13735 transitions. [2021-12-06 17:16:52,566 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9557 states and 13735 transitions. [2021-12-06 17:16:52,633 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9557 to 7461. [2021-12-06 17:16:52,640 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7461 states, 7461 states have (on average 1.4315775365232541) internal successors, (10681), 7460 states have internal predecessors, (10681), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:52,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7461 states to 7461 states and 10681 transitions. [2021-12-06 17:16:52,654 INFO L704 BuchiCegarLoop]: Abstraction has 7461 states and 10681 transitions. [2021-12-06 17:16:52,654 INFO L587 BuchiCegarLoop]: Abstraction has 7461 states and 10681 transitions. [2021-12-06 17:16:52,654 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-06 17:16:52,654 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7461 states and 10681 transitions. [2021-12-06 17:16:52,670 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7312 [2021-12-06 17:16:52,670 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:52,670 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:52,671 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:52,671 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:52,672 INFO L791 eck$LassoCheckResult]: Stem: 64127#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 64128#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 64054#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 64055#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 64386#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 63911#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 63912#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 64343#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 63697#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 63698#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 64239#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 64240#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 63170#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 63171#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 63374#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 63799#L939 assume !(0 == ~M_E~0); 64097#L939-2 assume !(0 == ~T1_E~0); 64098#L944-1 assume !(0 == ~T2_E~0); 63831#L949-1 assume !(0 == ~T3_E~0); 63829#L954-1 assume !(0 == ~T4_E~0); 63830#L959-1 assume !(0 == ~T5_E~0); 64407#L964-1 assume !(0 == ~T6_E~0); 63531#L969-1 assume !(0 == ~T7_E~0); 63532#L974-1 assume !(0 == ~T8_E~0); 64328#L979-1 assume !(0 == ~T9_E~0); 64329#L984-1 assume !(0 == ~E_M~0); 63709#L989-1 assume !(0 == ~E_1~0); 63710#L994-1 assume !(0 == ~E_2~0); 63585#L999-1 assume !(0 == ~E_3~0); 63586#L1004-1 assume !(0 == ~E_4~0); 63238#L1009-1 assume !(0 == ~E_5~0); 63239#L1014-1 assume !(0 == ~E_6~0); 63576#L1019-1 assume !(0 == ~E_7~0); 64247#L1024-1 assume !(0 == ~E_8~0); 63504#L1029-1 assume !(0 == ~E_9~0); 63505#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 63600#L460 assume !(1 == ~m_pc~0); 64609#L460-2 is_master_triggered_~__retres1~0#1 := 0; 64204#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64205#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 64670#L1167 assume !(0 != activate_threads_~tmp~1#1); 63815#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63816#L479 assume !(1 == ~t1_pc~0); 63998#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 63999#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 64542#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 63516#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 63517#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63355#L498 assume !(1 == ~t2_pc~0); 63356#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 63797#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 63798#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 64295#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 64190#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 64191#L517 assume 1 == ~t3_pc~0; 64549#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 64550#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 63879#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 63550#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 63551#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64260#L536 assume !(1 == ~t4_pc~0); 63869#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 63868#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64394#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 63860#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 63861#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 64148#L555 assume 1 == ~t5_pc~0; 64149#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 64248#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63270#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 63271#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 63377#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 63278#L574 assume !(1 == ~t6_pc~0); 63279#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 63972#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 63382#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 63383#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 64288#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64620#L593 assume 1 == ~t7_pc~0; 64621#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 63523#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 64410#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 64711#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 64556#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 63704#L612 assume !(1 == ~t8_pc~0); 63705#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 64226#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 64019#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64020#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 63975#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 63976#L631 assume 1 == ~t9_pc~0; 63996#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 63269#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 63236#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 63237#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 63800#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64264#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 64265#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 67062#L1052-1 assume !(1 == ~T2_E~0); 67061#L1057-1 assume !(1 == ~T3_E~0); 67060#L1062-1 assume !(1 == ~T4_E~0); 63486#L1067-1 assume !(1 == ~T5_E~0); 67059#L1072-1 assume !(1 == ~T6_E~0); 67058#L1077-1 assume !(1 == ~T7_E~0); 67057#L1082-1 assume !(1 == ~T8_E~0); 67056#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 67055#L1092-1 assume !(1 == ~E_M~0); 67054#L1097-1 assume !(1 == ~E_1~0); 67053#L1102-1 assume !(1 == ~E_2~0); 67052#L1107-1 assume !(1 == ~E_3~0); 67051#L1112-1 assume !(1 == ~E_4~0); 67050#L1117-1 assume !(1 == ~E_5~0); 67049#L1122-1 assume !(1 == ~E_6~0); 67048#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 67047#L1132-1 assume !(1 == ~E_8~0); 67046#L1137-1 assume !(1 == ~E_9~0); 63484#L1142-1 assume { :end_inline_reset_delta_events } true; 63485#L1428-2 [2021-12-06 17:16:52,672 INFO L793 eck$LassoCheckResult]: Loop: 63485#L1428-2 assume !false; 65386#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 65383#L914 assume !false; 65359#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 65360#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 65319#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 65320#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 65309#L783 assume !(0 != eval_~tmp~0#1); 65310#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 66982#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 66980#L939-3 assume !(0 == ~M_E~0); 66976#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 66977#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 66972#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 66973#L954-3 assume !(0 == ~T4_E~0); 66968#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 66969#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 66964#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 66965#L974-3 assume !(0 == ~T8_E~0); 66960#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 66961#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 66956#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 66957#L994-3 assume !(0 == ~E_2~0); 66952#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 66953#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 66948#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 66949#L1014-3 assume !(0 == ~E_6~0); 66944#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 66945#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 66940#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 66941#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 66936#L460-33 assume !(1 == ~m_pc~0); 66937#L460-35 is_master_triggered_~__retres1~0#1 := 0; 66932#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 66933#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 66928#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 66929#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65251#L479-33 assume !(1 == ~t1_pc~0); 65252#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 65247#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65248#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 65244#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 65243#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65242#L498-33 assume !(1 == ~t2_pc~0); 65240#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 63777#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 63420#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 63421#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 63396#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63397#L517-33 assume !(1 == ~t3_pc~0); 64652#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 64369#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64370#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 64089#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 64090#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64289#L536-33 assume 1 == ~t4_pc~0; 64208#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 63722#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 63723#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 63943#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 64334#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 63212#L555-33 assume !(1 == ~t5_pc~0); 63213#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 64012#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63496#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 63497#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 64044#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 63183#L574-33 assume 1 == ~t6_pc~0; 63184#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 64351#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 63512#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 63513#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 63794#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 63259#L593-33 assume !(1 == ~t7_pc~0); 63260#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 65175#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 65174#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 65173#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 65172#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 64745#L612-33 assume !(1 == ~t8_pc~0); 64576#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 64486#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 64487#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64227#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 63365#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 63366#L631-33 assume 1 == ~t9_pc~0; 64405#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 63307#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 63308#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 63574#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 63575#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 65145#L1047-3 assume !(1 == ~M_E~0); 65144#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 65143#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 65142#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 65141#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 63318#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 63319#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 63729#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 63559#L1082-3 assume !(1 == ~T8_E~0); 63560#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 63644#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 63962#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 63877#L1102-3 assume !(1 == ~E_2~0); 63878#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 64358#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 63552#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 63553#L1122-3 assume !(1 == ~E_6~0); 63611#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 63612#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 65114#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 65113#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 63427#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 63302#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 64039#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 63751#L1447 assume !(0 == start_simulation_~tmp~3#1); 63752#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 65930#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 67036#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 67035#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 67034#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 67033#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 67032#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 65438#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 63485#L1428-2 [2021-12-06 17:16:52,672 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:52,672 INFO L85 PathProgramCache]: Analyzing trace with hash 1891501957, now seen corresponding path program 1 times [2021-12-06 17:16:52,672 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:52,672 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [976428164] [2021-12-06 17:16:52,672 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:52,673 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:52,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:52,696 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:52,696 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:52,696 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [976428164] [2021-12-06 17:16:52,696 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [976428164] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:52,696 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:52,696 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:52,696 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1750968953] [2021-12-06 17:16:52,696 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:52,697 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:52,697 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:52,697 INFO L85 PathProgramCache]: Analyzing trace with hash -1594560879, now seen corresponding path program 1 times [2021-12-06 17:16:52,697 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:52,697 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1479468010] [2021-12-06 17:16:52,698 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:52,698 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:52,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:52,728 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:52,728 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:52,728 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1479468010] [2021-12-06 17:16:52,728 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1479468010] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:52,728 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:52,729 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:52,729 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [699936383] [2021-12-06 17:16:52,729 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:52,729 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:52,729 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:52,730 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 17:16:52,730 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 17:16:52,730 INFO L87 Difference]: Start difference. First operand 7461 states and 10681 transitions. cyclomatic complexity: 3224 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:52,940 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:52,940 INFO L93 Difference]: Finished difference Result 17949 states and 25479 transitions. [2021-12-06 17:16:52,941 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 17:16:52,941 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17949 states and 25479 transitions. [2021-12-06 17:16:52,996 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 17495 [2021-12-06 17:16:53,043 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17949 states to 17949 states and 25479 transitions. [2021-12-06 17:16:53,043 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17949 [2021-12-06 17:16:53,052 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17949 [2021-12-06 17:16:53,052 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17949 states and 25479 transitions. [2021-12-06 17:16:53,062 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:53,062 INFO L681 BuchiCegarLoop]: Abstraction has 17949 states and 25479 transitions. [2021-12-06 17:16:53,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17949 states and 25479 transitions. [2021-12-06 17:16:53,171 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17949 to 14108. [2021-12-06 17:16:53,186 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14108 states, 14108 states have (on average 1.424581797561667) internal successors, (20098), 14107 states have internal predecessors, (20098), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:53,241 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14108 states to 14108 states and 20098 transitions. [2021-12-06 17:16:53,241 INFO L704 BuchiCegarLoop]: Abstraction has 14108 states and 20098 transitions. [2021-12-06 17:16:53,241 INFO L587 BuchiCegarLoop]: Abstraction has 14108 states and 20098 transitions. [2021-12-06 17:16:53,241 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-06 17:16:53,241 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14108 states and 20098 transitions. [2021-12-06 17:16:53,264 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13956 [2021-12-06 17:16:53,264 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:53,264 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:53,265 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:53,265 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:53,265 INFO L791 eck$LassoCheckResult]: Stem: 89472#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 89473#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 89416#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 89417#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 89670#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 89288#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 89289#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 89645#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 89097#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 89098#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 89559#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 89560#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 88590#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 88591#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 88795#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 89188#L939 assume !(0 == ~M_E~0); 89451#L939-2 assume !(0 == ~T1_E~0); 89452#L944-1 assume !(0 == ~T2_E~0); 89218#L949-1 assume !(0 == ~T3_E~0); 89216#L954-1 assume !(0 == ~T4_E~0); 89217#L959-1 assume !(0 == ~T5_E~0); 89688#L964-1 assume !(0 == ~T6_E~0); 88949#L969-1 assume !(0 == ~T7_E~0); 88950#L974-1 assume !(0 == ~T8_E~0); 89631#L979-1 assume !(0 == ~T9_E~0); 89632#L984-1 assume !(0 == ~E_M~0); 89109#L989-1 assume !(0 == ~E_1~0); 89110#L994-1 assume !(0 == ~E_2~0); 88996#L999-1 assume !(0 == ~E_3~0); 88997#L1004-1 assume !(0 == ~E_4~0); 88659#L1009-1 assume !(0 == ~E_5~0); 88660#L1014-1 assume !(0 == ~E_6~0); 88988#L1019-1 assume !(0 == ~E_7~0); 89567#L1024-1 assume !(0 == ~E_8~0); 88920#L1029-1 assume !(0 == ~E_9~0); 88921#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 89011#L460 assume !(1 == ~m_pc~0); 89805#L460-2 is_master_triggered_~__retres1~0#1 := 0; 89526#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 89527#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 89834#L1167 assume !(0 != activate_threads_~tmp~1#1); 89203#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 89204#L479 assume !(1 == ~t1_pc~0); 89363#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 89364#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 89765#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 88932#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 88933#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88777#L498 assume !(1 == ~t2_pc~0); 88778#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 89186#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 89187#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 89607#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 89513#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 89514#L517 assume !(1 == ~t3_pc~0); 89855#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 89856#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 89261#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 88966#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 88967#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 89577#L536 assume !(1 == ~t4_pc~0); 89251#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 89250#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 89679#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 89243#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 89244#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 89482#L555 assume 1 == ~t5_pc~0; 89483#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 89568#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 88690#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 88691#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 88800#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 88698#L574 assume !(1 == ~t6_pc~0); 88699#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 89340#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 88805#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 88806#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 89600#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 89813#L593 assume 1 == ~t7_pc~0; 89814#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 88939#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 89693#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 89858#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 89773#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 89104#L612 assume !(1 == ~t8_pc~0); 89105#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 89544#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 89383#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 89384#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 89342#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 89343#L631 assume 1 == ~t9_pc~0; 89361#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 88689#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 88657#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 88658#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 89189#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 89580#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 88627#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 88628#L1052-1 assume !(1 == ~T2_E~0); 88609#L1057-1 assume !(1 == ~T3_E~0); 88610#L1062-1 assume !(1 == ~T4_E~0); 88903#L1067-1 assume !(1 == ~T5_E~0); 89689#L1072-1 assume !(1 == ~T6_E~0); 89546#L1077-1 assume !(1 == ~T7_E~0); 89547#L1082-1 assume !(1 == ~T8_E~0); 89315#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 89316#L1092-1 assume !(1 == ~E_M~0); 88611#L1097-1 assume !(1 == ~E_1~0); 88612#L1102-1 assume !(1 == ~E_2~0); 89411#L1107-1 assume !(1 == ~E_3~0); 89412#L1112-1 assume !(1 == ~E_4~0); 89385#L1117-1 assume !(1 == ~E_5~0); 89386#L1122-1 assume !(1 == ~E_6~0); 89262#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 89263#L1132-1 assume !(1 == ~E_8~0); 89798#L1137-1 assume !(1 == ~E_9~0); 89799#L1142-1 assume { :end_inline_reset_delta_events } true; 101106#L1428-2 [2021-12-06 17:16:53,266 INFO L793 eck$LassoCheckResult]: Loop: 101106#L1428-2 assume !false; 100946#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 100940#L914 assume !false; 100938#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 100932#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 100921#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 100919#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 100916#L783 assume !(0 != eval_~tmp~0#1); 100917#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 102621#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 102620#L939-3 assume !(0 == ~M_E~0); 102617#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 102616#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 102533#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 102532#L954-3 assume !(0 == ~T4_E~0); 102531#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 102530#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 102529#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 102527#L974-3 assume !(0 == ~T8_E~0); 102525#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 102523#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 102521#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 102519#L994-3 assume !(0 == ~E_2~0); 102517#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 102515#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 102514#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 102513#L1014-3 assume !(0 == ~E_6~0); 89290#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 89291#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 89274#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 89226#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 89227#L460-33 assume !(1 == ~m_pc~0); 89497#L460-35 is_master_triggered_~__retres1~0#1 := 0; 89475#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 89018#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 88588#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 88589#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88953#L479-33 assume !(1 == ~t1_pc~0); 88954#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 101419#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 101418#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 101415#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 101413#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 101411#L498-33 assume !(1 == ~t2_pc~0); 101408#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 101406#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 101404#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 101401#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 101399#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 101397#L517-33 assume !(1 == ~t3_pc~0); 95445#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 101394#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 101392#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 101389#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 101387#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 101385#L536-33 assume !(1 == ~t4_pc~0); 101383#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 101380#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 101378#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 101375#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 101373#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 101371#L555-33 assume 1 == ~t5_pc~0; 101369#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 101366#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 101364#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 101361#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 101359#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 101357#L574-33 assume !(1 == ~t6_pc~0); 101355#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 101352#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 101350#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 101348#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 101346#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 101344#L593-33 assume !(1 == ~t7_pc~0); 101341#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 101339#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 101337#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 101335#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 101333#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 101331#L612-33 assume !(1 == ~t8_pc~0); 101329#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 101326#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 101324#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 101322#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 101320#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 101318#L631-33 assume !(1 == ~t9_pc~0); 101315#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 101313#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 101311#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 101309#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 101307#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 101197#L1047-3 assume !(1 == ~M_E~0); 101195#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 101192#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 101190#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 101188#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 101184#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 101182#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 101180#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 101178#L1082-3 assume !(1 == ~T8_E~0); 101176#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 101174#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 101172#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 101170#L1102-3 assume !(1 == ~E_2~0); 101168#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 101166#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 101164#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 101162#L1122-3 assume !(1 == ~E_6~0); 101160#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 101158#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 101156#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 101154#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 101148#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 101138#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 101136#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 101135#L1447 assume !(0 == start_simulation_~tmp~3#1); 101133#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 101131#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 101119#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 101117#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 101115#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 101114#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 101109#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 101108#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 101106#L1428-2 [2021-12-06 17:16:53,266 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:53,266 INFO L85 PathProgramCache]: Analyzing trace with hash -1826536698, now seen corresponding path program 1 times [2021-12-06 17:16:53,266 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:53,266 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1427160386] [2021-12-06 17:16:53,266 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:53,266 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:53,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:53,294 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:53,294 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:53,294 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1427160386] [2021-12-06 17:16:53,294 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1427160386] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:53,294 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:53,294 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 17:16:53,294 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1014661646] [2021-12-06 17:16:53,294 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:53,295 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:53,295 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:53,295 INFO L85 PathProgramCache]: Analyzing trace with hash -1750521709, now seen corresponding path program 1 times [2021-12-06 17:16:53,295 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:53,295 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [611671382] [2021-12-06 17:16:53,295 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:53,295 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:53,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:53,320 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:53,320 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:53,320 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [611671382] [2021-12-06 17:16:53,320 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [611671382] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:53,320 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:53,320 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 17:16:53,320 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [325867498] [2021-12-06 17:16:53,320 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:53,320 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:53,321 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:53,321 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:16:53,321 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:16:53,321 INFO L87 Difference]: Start difference. First operand 14108 states and 20098 transitions. cyclomatic complexity: 5994 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:53,461 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:53,461 INFO L93 Difference]: Finished difference Result 26783 states and 37979 transitions. [2021-12-06 17:16:53,465 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:16:53,465 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26783 states and 37979 transitions. [2021-12-06 17:16:53,544 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 26592 [2021-12-06 17:16:53,628 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26783 states to 26783 states and 37979 transitions. [2021-12-06 17:16:53,628 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26783 [2021-12-06 17:16:53,638 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26783 [2021-12-06 17:16:53,638 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26783 states and 37979 transitions. [2021-12-06 17:16:53,652 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:53,652 INFO L681 BuchiCegarLoop]: Abstraction has 26783 states and 37979 transitions. [2021-12-06 17:16:53,662 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26783 states and 37979 transitions. [2021-12-06 17:16:53,870 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26783 to 26751. [2021-12-06 17:16:53,891 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26751 states, 26751 states have (on average 1.4185264102276551) internal successors, (37947), 26750 states have internal predecessors, (37947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:53,935 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26751 states to 26751 states and 37947 transitions. [2021-12-06 17:16:53,936 INFO L704 BuchiCegarLoop]: Abstraction has 26751 states and 37947 transitions. [2021-12-06 17:16:53,936 INFO L587 BuchiCegarLoop]: Abstraction has 26751 states and 37947 transitions. [2021-12-06 17:16:53,936 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-06 17:16:53,936 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26751 states and 37947 transitions. [2021-12-06 17:16:53,990 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 26560 [2021-12-06 17:16:53,990 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:53,990 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:53,992 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:53,992 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:53,992 INFO L791 eck$LassoCheckResult]: Stem: 130377#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 130378#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 130323#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 130324#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 130574#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 130193#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 130194#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 130547#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 130001#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 130002#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 130455#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 130456#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 129490#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 129491#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 129694#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 130095#L939 assume !(0 == ~M_E~0); 130356#L939-2 assume !(0 == ~T1_E~0); 130357#L944-1 assume !(0 == ~T2_E~0); 130124#L949-1 assume !(0 == ~T3_E~0); 130122#L954-1 assume !(0 == ~T4_E~0); 130123#L959-1 assume !(0 == ~T5_E~0); 130597#L964-1 assume !(0 == ~T6_E~0); 129846#L969-1 assume !(0 == ~T7_E~0); 129847#L974-1 assume !(0 == ~T8_E~0); 130530#L979-1 assume !(0 == ~T9_E~0); 130531#L984-1 assume !(0 == ~E_M~0); 130013#L989-1 assume !(0 == ~E_1~0); 130014#L994-1 assume !(0 == ~E_2~0); 129896#L999-1 assume !(0 == ~E_3~0); 129897#L1004-1 assume !(0 == ~E_4~0); 129557#L1009-1 assume !(0 == ~E_5~0); 129558#L1014-1 assume !(0 == ~E_6~0); 129888#L1019-1 assume !(0 == ~E_7~0); 130463#L1024-1 assume !(0 == ~E_8~0); 129816#L1029-1 assume !(0 == ~E_9~0); 129817#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 129910#L460 assume !(1 == ~m_pc~0); 130719#L460-2 is_master_triggered_~__retres1~0#1 := 0; 130427#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 130428#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 130751#L1167 assume !(0 != activate_threads_~tmp~1#1); 130111#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 130112#L479 assume !(1 == ~t1_pc~0); 130269#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 130270#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 130683#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 129828#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 129829#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 129676#L498 assume !(1 == ~t2_pc~0); 129677#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 130093#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 130094#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 130504#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 130415#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 130416#L517 assume !(1 == ~t3_pc~0); 130769#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 130770#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 130166#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 129863#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 129864#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 130472#L536 assume !(1 == ~t4_pc~0); 130156#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 130155#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 130586#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 130148#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 130149#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 130385#L555 assume !(1 == ~t5_pc~0); 130386#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 130464#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 129588#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 129589#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 129697#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 129597#L574 assume !(1 == ~t6_pc~0); 129598#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 130245#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 129702#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 129703#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 130497#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 130726#L593 assume 1 == ~t7_pc~0; 130727#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 129836#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 130602#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 130773#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 130692#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 130008#L612 assume !(1 == ~t8_pc~0); 130009#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 130445#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 130291#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 130292#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 130248#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 130249#L631 assume 1 == ~t9_pc~0; 130267#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 129587#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 129555#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 129556#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 130096#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 130475#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 130476#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 153125#L1052-1 assume !(1 == ~T2_E~0); 153124#L1057-1 assume !(1 == ~T3_E~0); 153123#L1062-1 assume !(1 == ~T4_E~0); 129799#L1067-1 assume !(1 == ~T5_E~0); 153122#L1072-1 assume !(1 == ~T6_E~0); 153121#L1077-1 assume !(1 == ~T7_E~0); 153120#L1082-1 assume !(1 == ~T8_E~0); 153119#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 153118#L1092-1 assume !(1 == ~E_M~0); 153117#L1097-1 assume !(1 == ~E_1~0); 153116#L1102-1 assume !(1 == ~E_2~0); 153115#L1107-1 assume !(1 == ~E_3~0); 130243#L1112-1 assume !(1 == ~E_4~0); 130244#L1117-1 assume !(1 == ~E_5~0); 130293#L1122-1 assume !(1 == ~E_6~0); 130167#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 129913#L1132-1 assume !(1 == ~E_8~0); 129914#L1137-1 assume !(1 == ~E_9~0); 129798#L1142-1 assume { :end_inline_reset_delta_events } true; 129659#L1428-2 [2021-12-06 17:16:53,992 INFO L793 eck$LassoCheckResult]: Loop: 129659#L1428-2 assume !false; 129660#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 129733#L914 assume !false; 130239#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 130240#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 129495#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 129496#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 130500#L783 assume !(0 != eval_~tmp~0#1); 130501#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 155705#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 155703#L939-3 assume !(0 == ~M_E~0); 155700#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 155698#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 155696#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 155694#L954-3 assume !(0 == ~T4_E~0); 155692#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 155691#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 155690#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 155689#L974-3 assume !(0 == ~T8_E~0); 155688#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 155687#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 155686#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 155685#L994-3 assume !(0 == ~E_2~0); 155684#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 155683#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 155682#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 155681#L1014-3 assume !(0 == ~E_6~0); 155680#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 155679#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 155678#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 155676#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 155674#L460-33 assume !(1 == ~m_pc~0); 155672#L460-35 is_master_triggered_~__retres1~0#1 := 0; 155670#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 155668#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 154696#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 154695#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 154694#L479-33 assume !(1 == ~t1_pc~0); 150985#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 155535#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 155534#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 155533#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 155532#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 155531#L498-33 assume !(1 == ~t2_pc~0); 155529#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 155528#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 155527#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 155526#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 155525#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 155524#L517-33 assume !(1 == ~t3_pc~0); 152537#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 155523#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 155522#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 155520#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 155518#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 155516#L536-33 assume !(1 == ~t4_pc~0); 155514#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 155511#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 155509#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 155507#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 155504#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 155502#L555-33 assume !(1 == ~t5_pc~0); 155500#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 155498#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 155496#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 155494#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 155491#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 155489#L574-33 assume 1 == ~t6_pc~0; 155486#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 155484#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 155482#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 155480#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 155477#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 155475#L593-33 assume !(1 == ~t7_pc~0); 155472#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 155470#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 155468#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 155466#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 155463#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 155461#L612-33 assume 1 == ~t8_pc~0; 155458#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 155456#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 155454#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 155452#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 155449#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 155447#L631-33 assume !(1 == ~t9_pc~0); 155444#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 155442#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 155440#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 155438#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 155435#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 155433#L1047-3 assume !(1 == ~M_E~0); 153587#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 155430#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 155428#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 155427#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 153582#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 155426#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 155425#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 155424#L1082-3 assume !(1 == ~T8_E~0); 155423#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 155422#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 155421#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 155420#L1102-3 assume !(1 == ~E_2~0); 155419#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 155418#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 155417#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 155416#L1122-3 assume !(1 == ~E_6~0); 155415#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 155414#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 154491#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 130308#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 129745#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 129621#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 130309#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 130052#L1447 assume !(0 == start_simulation_~tmp~3#1); 130053#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 130529#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 129781#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 130332#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 129895#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 129649#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 129650#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 130117#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 129659#L1428-2 [2021-12-06 17:16:53,993 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:53,993 INFO L85 PathProgramCache]: Analyzing trace with hash 367589383, now seen corresponding path program 1 times [2021-12-06 17:16:53,993 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:53,993 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1312901819] [2021-12-06 17:16:53,993 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:53,993 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:54,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:54,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:54,017 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:54,017 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1312901819] [2021-12-06 17:16:54,017 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1312901819] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:54,017 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:54,018 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:54,018 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [567946954] [2021-12-06 17:16:54,018 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:54,018 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:54,018 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:54,018 INFO L85 PathProgramCache]: Analyzing trace with hash -540382702, now seen corresponding path program 1 times [2021-12-06 17:16:54,018 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:54,018 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1129957574] [2021-12-06 17:16:54,018 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:54,019 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:54,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:54,038 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:54,038 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:54,038 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1129957574] [2021-12-06 17:16:54,039 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1129957574] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:54,039 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:54,039 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:54,039 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1239848545] [2021-12-06 17:16:54,039 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:54,039 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:54,039 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:54,039 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 17:16:54,039 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 17:16:54,040 INFO L87 Difference]: Start difference. First operand 26751 states and 37947 transitions. cyclomatic complexity: 11204 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:54,383 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:54,383 INFO L93 Difference]: Finished difference Result 63922 states and 90012 transitions. [2021-12-06 17:16:54,383 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 17:16:54,383 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63922 states and 90012 transitions. [2021-12-06 17:16:54,625 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 62476 [2021-12-06 17:16:54,771 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63922 states to 63922 states and 90012 transitions. [2021-12-06 17:16:54,771 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 63922 [2021-12-06 17:16:54,797 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63922 [2021-12-06 17:16:54,798 INFO L73 IsDeterministic]: Start isDeterministic. Operand 63922 states and 90012 transitions. [2021-12-06 17:16:54,827 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:54,827 INFO L681 BuchiCegarLoop]: Abstraction has 63922 states and 90012 transitions. [2021-12-06 17:16:54,852 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63922 states and 90012 transitions. [2021-12-06 17:16:55,204 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63922 to 50750. [2021-12-06 17:16:55,244 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50750 states, 50750 states have (on average 1.4132019704433498) internal successors, (71720), 50749 states have internal predecessors, (71720), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:55,330 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50750 states to 50750 states and 71720 transitions. [2021-12-06 17:16:55,331 INFO L704 BuchiCegarLoop]: Abstraction has 50750 states and 71720 transitions. [2021-12-06 17:16:55,331 INFO L587 BuchiCegarLoop]: Abstraction has 50750 states and 71720 transitions. [2021-12-06 17:16:55,331 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-06 17:16:55,331 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50750 states and 71720 transitions. [2021-12-06 17:16:55,508 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 50512 [2021-12-06 17:16:55,508 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:55,508 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:55,510 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:55,511 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:55,511 INFO L791 eck$LassoCheckResult]: Stem: 221057#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 221058#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 221006#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 221007#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 221272#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 220879#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 220880#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 221241#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 220681#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 220682#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 221149#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 221150#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 220172#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 220173#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 220374#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 220778#L939 assume !(0 == ~M_E~0); 221037#L939-2 assume !(0 == ~T1_E~0); 221038#L944-1 assume !(0 == ~T2_E~0); 220806#L949-1 assume !(0 == ~T3_E~0); 220804#L954-1 assume !(0 == ~T4_E~0); 220805#L959-1 assume !(0 == ~T5_E~0); 221296#L964-1 assume !(0 == ~T6_E~0); 220528#L969-1 assume !(0 == ~T7_E~0); 220529#L974-1 assume !(0 == ~T8_E~0); 221223#L979-1 assume !(0 == ~T9_E~0); 221224#L984-1 assume !(0 == ~E_M~0); 220693#L989-1 assume !(0 == ~E_1~0); 220694#L994-1 assume !(0 == ~E_2~0); 220577#L999-1 assume !(0 == ~E_3~0); 220578#L1004-1 assume !(0 == ~E_4~0); 220239#L1009-1 assume !(0 == ~E_5~0); 220240#L1014-1 assume !(0 == ~E_6~0); 220569#L1019-1 assume !(0 == ~E_7~0); 221157#L1024-1 assume !(0 == ~E_8~0); 220499#L1029-1 assume !(0 == ~E_9~0); 220500#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 220592#L460 assume !(1 == ~m_pc~0); 221431#L460-2 is_master_triggered_~__retres1~0#1 := 0; 221118#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 221119#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 221461#L1167 assume !(0 != activate_threads_~tmp~1#1); 220793#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 220794#L479 assume !(1 == ~t1_pc~0); 220954#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 220955#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 221388#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 220511#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 220512#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 220356#L498 assume !(1 == ~t2_pc~0); 220357#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 220776#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 220777#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 221195#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 221105#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 221106#L517 assume !(1 == ~t3_pc~0); 221483#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 221484#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 220849#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 220545#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 220546#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 221168#L536 assume !(1 == ~t4_pc~0); 220839#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 220838#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 221284#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 220830#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 220831#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 221071#L555 assume !(1 == ~t5_pc~0); 221072#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 221158#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 220270#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 220271#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 220379#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 220279#L574 assume !(1 == ~t6_pc~0); 220280#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 220930#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 220384#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 220385#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 221187#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 221439#L593 assume !(1 == ~t7_pc~0); 220517#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 220518#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 221301#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 221491#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 221397#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 220688#L612 assume !(1 == ~t8_pc~0); 220689#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 221139#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 220973#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 220974#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 220932#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 220933#L631 assume 1 == ~t9_pc~0; 220952#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 220269#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 220237#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 220238#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 220779#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 221171#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 221172#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 269186#L1052-1 assume !(1 == ~T2_E~0); 269185#L1057-1 assume !(1 == ~T3_E~0); 269184#L1062-1 assume !(1 == ~T4_E~0); 220482#L1067-1 assume !(1 == ~T5_E~0); 269183#L1072-1 assume !(1 == ~T6_E~0); 269182#L1077-1 assume !(1 == ~T7_E~0); 269181#L1082-1 assume !(1 == ~T8_E~0); 269180#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 269179#L1092-1 assume !(1 == ~E_M~0); 269178#L1097-1 assume !(1 == ~E_1~0); 269177#L1102-1 assume !(1 == ~E_2~0); 269176#L1107-1 assume !(1 == ~E_3~0); 269175#L1112-1 assume !(1 == ~E_4~0); 269174#L1117-1 assume !(1 == ~E_5~0); 269173#L1122-1 assume !(1 == ~E_6~0); 269172#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 269171#L1132-1 assume !(1 == ~E_8~0); 269169#L1137-1 assume !(1 == ~E_9~0); 269167#L1142-1 assume { :end_inline_reset_delta_events } true; 269164#L1428-2 [2021-12-06 17:16:55,511 INFO L793 eck$LassoCheckResult]: Loop: 269164#L1428-2 assume !false; 269047#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 269041#L914 assume !false; 269039#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 269031#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 269021#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 269019#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 269018#L783 assume !(0 != eval_~tmp~0#1); 220580#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 220581#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 221279#L939-3 assume !(0 == ~M_E~0); 221280#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 220450#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 220162#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 220163#L954-3 assume !(0 == ~T4_E~0); 220812#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 220241#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 220242#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 220448#L974-3 assume !(0 == ~T8_E~0); 220449#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 220897#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 220898#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 220505#L994-3 assume !(0 == ~E_2~0); 220506#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 221045#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 220324#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 220325#L1014-3 assume !(0 == ~E_6~0); 220881#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 220882#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 220861#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 220813#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 220814#L460-33 assume !(1 == ~m_pc~0); 221087#L460-35 is_master_triggered_~__retres1~0#1 := 0; 221060#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 221061#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 270475#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 221008#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 221009#L479-33 assume !(1 == ~t1_pc~0); 269455#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 269454#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 269453#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 269450#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 269448#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 269446#L498-33 assume !(1 == ~t2_pc~0); 269444#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 269443#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 269442#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 269441#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 269440#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 269439#L517-33 assume !(1 == ~t3_pc~0); 261921#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 269438#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 269437#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 269436#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 269435#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 269434#L536-33 assume 1 == ~t4_pc~0; 269432#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 269431#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 269429#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 269427#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 269426#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 269425#L555-33 assume !(1 == ~t5_pc~0); 269424#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 269423#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 269422#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 269421#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 269419#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 269417#L574-33 assume 1 == ~t6_pc~0; 269414#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 269412#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 269410#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 269408#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 269406#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 269404#L593-33 assume !(1 == ~t7_pc~0); 237072#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 269401#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 269399#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 269397#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 269395#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 269393#L612-33 assume 1 == ~t8_pc~0; 269390#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 269388#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 269386#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 269384#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 269382#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 269380#L631-33 assume !(1 == ~t9_pc~0); 269377#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 269375#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 269373#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 269371#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 269369#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 269260#L1047-3 assume !(1 == ~M_E~0); 269258#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 269256#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 269253#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 269251#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 269247#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 269245#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 269243#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 269241#L1082-3 assume !(1 == ~T8_E~0); 269238#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 269236#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 269234#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 269232#L1102-3 assume !(1 == ~E_2~0); 269230#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 269229#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 269228#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 269227#L1122-3 assume !(1 == ~E_6~0); 269226#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 269225#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 269224#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 269223#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 269221#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 269212#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 269211#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 269210#L1447 assume !(0 == start_simulation_~tmp~3#1); 220894#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 269208#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 269196#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 269194#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 269192#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 269191#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 269187#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 269166#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 269164#L1428-2 [2021-12-06 17:16:55,511 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:55,512 INFO L85 PathProgramCache]: Analyzing trace with hash -589339000, now seen corresponding path program 1 times [2021-12-06 17:16:55,512 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:55,512 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1513512414] [2021-12-06 17:16:55,512 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:55,512 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:55,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:55,541 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:55,541 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:55,541 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1513512414] [2021-12-06 17:16:55,541 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1513512414] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:55,541 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:55,541 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:55,542 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [732433991] [2021-12-06 17:16:55,542 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:55,542 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:55,542 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:55,542 INFO L85 PathProgramCache]: Analyzing trace with hash -1678011567, now seen corresponding path program 1 times [2021-12-06 17:16:55,542 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:55,542 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2046854843] [2021-12-06 17:16:55,542 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:55,543 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:55,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:55,561 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:55,561 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:55,561 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2046854843] [2021-12-06 17:16:55,561 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2046854843] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:55,561 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:55,561 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:16:55,561 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1517903436] [2021-12-06 17:16:55,561 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:55,562 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:55,562 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:55,562 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 17:16:55,562 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 17:16:55,562 INFO L87 Difference]: Start difference. First operand 50750 states and 71720 transitions. cyclomatic complexity: 20978 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:56,038 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:56,038 INFO L93 Difference]: Finished difference Result 120381 states and 168933 transitions. [2021-12-06 17:16:56,039 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 17:16:56,039 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 120381 states and 168933 transitions. [2021-12-06 17:16:56,501 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 117648 [2021-12-06 17:16:56,743 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 120381 states to 120381 states and 168933 transitions. [2021-12-06 17:16:56,743 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 120381 [2021-12-06 17:16:56,789 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 120381 [2021-12-06 17:16:56,789 INFO L73 IsDeterministic]: Start isDeterministic. Operand 120381 states and 168933 transitions. [2021-12-06 17:16:56,832 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:56,832 INFO L681 BuchiCegarLoop]: Abstraction has 120381 states and 168933 transitions. [2021-12-06 17:16:56,875 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120381 states and 168933 transitions. [2021-12-06 17:16:57,518 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120381 to 96205. [2021-12-06 17:16:57,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 96205 states, 96205 states have (on average 1.4085442544566291) internal successors, (135509), 96204 states have internal predecessors, (135509), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:57,726 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 96205 states to 96205 states and 135509 transitions. [2021-12-06 17:16:57,726 INFO L704 BuchiCegarLoop]: Abstraction has 96205 states and 135509 transitions. [2021-12-06 17:16:57,726 INFO L587 BuchiCegarLoop]: Abstraction has 96205 states and 135509 transitions. [2021-12-06 17:16:57,727 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-06 17:16:57,727 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 96205 states and 135509 transitions. [2021-12-06 17:16:57,953 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 95872 [2021-12-06 17:16:57,953 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:16:57,953 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:16:57,956 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:57,956 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:16:57,956 INFO L791 eck$LassoCheckResult]: Stem: 392215#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 392216#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 392159#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 392160#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 392432#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 392025#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 392026#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 392402#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 391821#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 391822#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 392307#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 392308#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 391313#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 391314#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 391515#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 391920#L939 assume !(0 == ~M_E~0); 392193#L939-2 assume !(0 == ~T1_E~0); 392194#L944-1 assume !(0 == ~T2_E~0); 391951#L949-1 assume !(0 == ~T3_E~0); 391947#L954-1 assume !(0 == ~T4_E~0); 391948#L959-1 assume !(0 == ~T5_E~0); 392453#L964-1 assume !(0 == ~T6_E~0); 391669#L969-1 assume !(0 == ~T7_E~0); 391670#L974-1 assume !(0 == ~T8_E~0); 392388#L979-1 assume !(0 == ~T9_E~0); 392389#L984-1 assume !(0 == ~E_M~0); 391833#L989-1 assume !(0 == ~E_1~0); 391834#L994-1 assume !(0 == ~E_2~0); 391718#L999-1 assume !(0 == ~E_3~0); 391719#L1004-1 assume !(0 == ~E_4~0); 391382#L1009-1 assume !(0 == ~E_5~0); 391383#L1014-1 assume !(0 == ~E_6~0); 391710#L1019-1 assume !(0 == ~E_7~0); 392315#L1024-1 assume !(0 == ~E_8~0); 391639#L1029-1 assume !(0 == ~E_9~0); 391640#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 391733#L460 assume !(1 == ~m_pc~0); 392590#L460-2 is_master_triggered_~__retres1~0#1 := 0; 392274#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 392275#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 392625#L1167 assume !(0 != activate_threads_~tmp~1#1); 391936#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 391937#L479 assume !(1 == ~t1_pc~0); 392103#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 392104#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 392540#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 391651#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 391652#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 391497#L498 assume !(1 == ~t2_pc~0); 391498#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 391918#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 391919#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 392358#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 392261#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 392262#L517 assume !(1 == ~t3_pc~0); 392643#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 392644#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 391996#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 391686#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 391687#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 392326#L536 assume !(1 == ~t4_pc~0); 391986#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 391985#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 392440#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 391977#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 391978#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 392230#L555 assume !(1 == ~t5_pc~0); 392231#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 392316#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 391412#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 391413#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 391518#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 391421#L574 assume !(1 == ~t6_pc~0); 391422#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 392082#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 391523#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 391524#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 392351#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 392596#L593 assume !(1 == ~t7_pc~0); 391658#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 391659#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 392459#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 392650#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 392548#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 391828#L612 assume !(1 == ~t8_pc~0); 391829#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 392293#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 392121#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 392122#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 392084#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 392085#L631 assume !(1 == ~t9_pc~0); 392158#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 391411#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 391380#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 391381#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 391921#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 392330#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 392331#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 392077#L1052-1 assume !(1 == ~T2_E~0); 392078#L1057-1 assume !(1 == ~T3_E~0); 391622#L1062-1 assume !(1 == ~T4_E~0); 391623#L1067-1 assume !(1 == ~T5_E~0); 391940#L1072-1 assume !(1 == ~T6_E~0); 391941#L1077-1 assume !(1 == ~T7_E~0); 391511#L1082-1 assume !(1 == ~T8_E~0); 391512#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 391305#L1092-1 assume !(1 == ~E_M~0); 391306#L1097-1 assume !(1 == ~E_1~0); 392581#L1102-1 assume !(1 == ~E_2~0); 392582#L1107-1 assume !(1 == ~E_3~0); 392080#L1112-1 assume !(1 == ~E_4~0); 392081#L1117-1 assume !(1 == ~E_5~0); 392680#L1122-1 assume !(1 == ~E_6~0); 392681#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 391736#L1132-1 assume !(1 == ~E_8~0); 391737#L1137-1 assume !(1 == ~E_9~0); 391620#L1142-1 assume { :end_inline_reset_delta_events } true; 391621#L1428-2 [2021-12-06 17:16:57,957 INFO L793 eck$LassoCheckResult]: Loop: 391621#L1428-2 assume !false; 473361#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 473352#L914 assume !false; 473349#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 473242#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 473163#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 473160#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 473154#L783 assume !(0 != eval_~tmp~0#1); 473155#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 486428#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 486426#L939-3 assume !(0 == ~M_E~0); 486424#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 486422#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 486420#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 486419#L954-3 assume !(0 == ~T4_E~0); 486418#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 486417#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 486416#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 486415#L974-3 assume !(0 == ~T8_E~0); 486414#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 486413#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 486412#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 486411#L994-3 assume !(0 == ~E_2~0); 486410#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 486409#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 486408#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 486407#L1014-3 assume !(0 == ~E_6~0); 486406#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 486405#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 486404#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 486403#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 486402#L460-33 assume !(1 == ~m_pc~0); 486400#L460-35 is_master_triggered_~__retres1~0#1 := 0; 486398#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 486396#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 486394#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 486392#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 486390#L479-33 assume !(1 == ~t1_pc~0); 484583#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 486385#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 486383#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 486381#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 486379#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 486377#L498-33 assume !(1 == ~t2_pc~0); 486373#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 486371#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 486369#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 486367#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 486365#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 486363#L517-33 assume !(1 == ~t3_pc~0); 473898#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 486361#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 486359#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 486357#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 486355#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 486353#L536-33 assume !(1 == ~t4_pc~0); 486351#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 486347#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 486345#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 486343#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 486341#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 486339#L555-33 assume !(1 == ~t5_pc~0); 486337#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 486334#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 486332#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 486330#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 486328#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 486326#L574-33 assume !(1 == ~t6_pc~0); 486324#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 486320#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 486318#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 486316#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 486314#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 473656#L593-33 assume !(1 == ~t7_pc~0); 473651#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 473650#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 473649#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 473648#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 473647#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 473646#L612-33 assume !(1 == ~t8_pc~0); 473644#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 473641#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 473639#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 473637#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 473635#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 473633#L631-33 assume !(1 == ~t9_pc~0); 434345#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 473629#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 473627#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 473625#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 473623#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 473621#L1047-3 assume !(1 == ~M_E~0); 470274#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 473619#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 473617#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 473615#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 470257#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 473612#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 473610#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 473608#L1082-3 assume !(1 == ~T8_E~0); 473606#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 473604#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 473602#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 473600#L1102-3 assume !(1 == ~E_2~0); 473597#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 473595#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 473593#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 473591#L1122-3 assume !(1 == ~E_6~0); 473589#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 473587#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 473586#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 473584#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 473515#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 473505#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 473503#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 473501#L1447 assume !(0 == start_simulation_~tmp~3#1); 473498#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 473490#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 473480#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 473477#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 473475#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 473473#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 473462#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 473451#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 391621#L1428-2 [2021-12-06 17:16:57,957 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:57,957 INFO L85 PathProgramCache]: Analyzing trace with hash 2033110665, now seen corresponding path program 1 times [2021-12-06 17:16:57,957 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:57,957 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1750788570] [2021-12-06 17:16:57,957 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:57,957 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:57,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:57,983 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:57,983 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:57,983 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1750788570] [2021-12-06 17:16:57,983 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1750788570] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:57,983 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:57,983 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 17:16:57,983 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [217231750] [2021-12-06 17:16:57,983 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:57,983 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:16:57,984 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:16:57,984 INFO L85 PathProgramCache]: Analyzing trace with hash -1173593068, now seen corresponding path program 1 times [2021-12-06 17:16:57,984 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:16:57,984 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1193456404] [2021-12-06 17:16:57,984 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:16:57,984 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:16:57,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:16:58,007 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:16:58,007 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:16:58,007 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1193456404] [2021-12-06 17:16:58,007 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1193456404] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:16:58,007 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:16:58,007 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 17:16:58,007 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2126221184] [2021-12-06 17:16:58,007 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:16:58,008 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:16:58,008 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:16:58,008 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:16:58,008 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:16:58,008 INFO L87 Difference]: Start difference. First operand 96205 states and 135509 transitions. cyclomatic complexity: 39312 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:16:58,505 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:16:58,505 INFO L93 Difference]: Finished difference Result 142665 states and 201260 transitions. [2021-12-06 17:16:58,505 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:16:58,506 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 142665 states and 201260 transitions. [2021-12-06 17:16:59,081 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 142240 [2021-12-06 17:16:59,326 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 142665 states to 142665 states and 201260 transitions. [2021-12-06 17:16:59,326 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 142665 [2021-12-06 17:16:59,371 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 142665 [2021-12-06 17:16:59,371 INFO L73 IsDeterministic]: Start isDeterministic. Operand 142665 states and 201260 transitions. [2021-12-06 17:16:59,412 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:16:59,412 INFO L681 BuchiCegarLoop]: Abstraction has 142665 states and 201260 transitions. [2021-12-06 17:16:59,548 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142665 states and 201260 transitions. [2021-12-06 17:17:00,248 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142665 to 97465. [2021-12-06 17:17:00,310 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97465 states, 97465 states have (on average 1.4142307494998205) internal successors, (137838), 97464 states have internal predecessors, (137838), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:17:00,568 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97465 states to 97465 states and 137838 transitions. [2021-12-06 17:17:00,568 INFO L704 BuchiCegarLoop]: Abstraction has 97465 states and 137838 transitions. [2021-12-06 17:17:00,568 INFO L587 BuchiCegarLoop]: Abstraction has 97465 states and 137838 transitions. [2021-12-06 17:17:00,568 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-06 17:17:00,568 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97465 states and 137838 transitions. [2021-12-06 17:17:00,771 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 97152 [2021-12-06 17:17:00,771 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:17:00,771 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:17:00,775 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:17:00,775 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:17:00,775 INFO L791 eck$LassoCheckResult]: Stem: 631096#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 631097#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 631038#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 631039#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 631315#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 630907#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 630908#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 631284#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 630701#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 630702#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 631185#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 631186#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 630192#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 630193#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 630393#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 630799#L939 assume !(0 == ~M_E~0); 631071#L939-2 assume !(0 == ~T1_E~0); 631072#L944-1 assume !(0 == ~T2_E~0); 630833#L949-1 assume !(0 == ~T3_E~0); 630829#L954-1 assume !(0 == ~T4_E~0); 630830#L959-1 assume !(0 == ~T5_E~0); 631339#L964-1 assume !(0 == ~T6_E~0); 630543#L969-1 assume !(0 == ~T7_E~0); 630544#L974-1 assume !(0 == ~T8_E~0); 631270#L979-1 assume !(0 == ~T9_E~0); 631271#L984-1 assume !(0 == ~E_M~0); 630714#L989-1 assume !(0 == ~E_1~0); 630715#L994-1 assume !(0 == ~E_2~0); 630593#L999-1 assume !(0 == ~E_3~0); 630594#L1004-1 assume !(0 == ~E_4~0); 630259#L1009-1 assume !(0 == ~E_5~0); 630260#L1014-1 assume !(0 == ~E_6~0); 630589#L1019-1 assume !(0 == ~E_7~0); 631191#L1024-1 assume !(0 == ~E_8~0); 630513#L1029-1 assume !(0 == ~E_9~0); 630514#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 630609#L460 assume !(1 == ~m_pc~0); 631479#L460-2 is_master_triggered_~__retres1~0#1 := 0; 631154#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 631155#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 631520#L1167 assume !(0 != activate_threads_~tmp~1#1); 630818#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 630819#L479 assume !(1 == ~t1_pc~0); 630982#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 630983#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 631437#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 630528#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 630529#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 630374#L498 assume !(1 == ~t2_pc~0); 630375#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 630797#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 630798#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 631230#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 631144#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 631145#L517 assume !(1 == ~t3_pc~0); 631549#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 631550#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 630877#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 630560#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 630561#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 631202#L536 assume !(1 == ~t4_pc~0); 630867#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 630866#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 631325#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 630859#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 630860#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 631117#L555 assume !(1 == ~t5_pc~0); 631118#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 631192#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 630291#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 630292#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 630398#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 630297#L574 assume !(1 == ~t6_pc~0); 630298#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 630957#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 630401#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 630402#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 631225#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 631489#L593 assume !(1 == ~t7_pc~0); 630532#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 630533#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 631345#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 631559#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 631446#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 630707#L612 assume !(1 == ~t8_pc~0); 630708#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 631172#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 631003#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 631004#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 630961#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 630962#L631 assume !(1 == ~t9_pc~0); 631037#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 630288#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 630257#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 630258#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 630800#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 631203#L1047 assume !(1 == ~M_E~0); 630230#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 630231#L1052-1 assume !(1 == ~T2_E~0); 630211#L1057-1 assume !(1 == ~T3_E~0); 630212#L1062-1 assume !(1 == ~T4_E~0); 630497#L1067-1 assume !(1 == ~T5_E~0); 630822#L1072-1 assume !(1 == ~T6_E~0); 630823#L1077-1 assume !(1 == ~T7_E~0); 630388#L1082-1 assume !(1 == ~T8_E~0); 630389#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 630188#L1092-1 assume !(1 == ~E_M~0); 630189#L1097-1 assume !(1 == ~E_1~0); 630213#L1102-1 assume !(1 == ~E_2~0); 631032#L1107-1 assume !(1 == ~E_3~0); 630955#L1112-1 assume !(1 == ~E_4~0); 630956#L1117-1 assume !(1 == ~E_5~0); 631005#L1122-1 assume !(1 == ~E_6~0); 630878#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 630612#L1132-1 assume !(1 == ~E_8~0); 630613#L1137-1 assume !(1 == ~E_9~0); 630496#L1142-1 assume { :end_inline_reset_delta_events } true; 630360#L1428-2 [2021-12-06 17:17:00,775 INFO L793 eck$LassoCheckResult]: Loop: 630360#L1428-2 assume !false; 630361#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 630432#L914 assume !false; 630952#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 630953#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 630197#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 630198#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 631226#L783 assume !(0 != eval_~tmp~0#1); 631227#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 727548#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 727546#L939-3 assume !(0 == ~M_E~0); 727544#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 727542#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 727540#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 727538#L954-3 assume !(0 == ~T4_E~0); 727536#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 727534#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 727532#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 727530#L974-3 assume !(0 == ~T8_E~0); 727528#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 727526#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 727512#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 727511#L994-3 assume !(0 == ~E_2~0); 727509#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 727507#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 727506#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 727504#L1014-3 assume !(0 == ~E_6~0); 727498#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 727497#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 630886#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 630841#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 630842#L460-33 assume !(1 == ~m_pc~0); 631129#L460-35 is_master_triggered_~__retres1~0#1 := 0; 631100#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 630614#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 630190#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 630191#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 630549#L479-33 assume !(1 == ~t1_pc~0); 630550#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 727623#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 727622#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 727621#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 727620#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 630557#L498-33 assume !(1 == ~t2_pc~0); 630559#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 727572#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 727571#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 727570#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 727257#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 723434#L517-33 assume !(1 == ~t3_pc~0); 723433#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 723432#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 723431#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 723430#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 723428#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 723426#L536-33 assume !(1 == ~t4_pc~0); 723424#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 723421#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 723418#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 723416#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 723414#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 723412#L555-33 assume !(1 == ~t5_pc~0); 723410#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 723408#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 723407#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 723406#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 723403#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 723404#L574-33 assume !(1 == ~t6_pc~0); 724153#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 724150#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 723392#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 723390#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 723388#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 723383#L593-33 assume !(1 == ~t7_pc~0); 723381#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 723379#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 723377#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 723375#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 723373#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 723227#L612-33 assume !(1 == ~t8_pc~0); 723199#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 723192#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 723187#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 723182#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 722386#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 710532#L631-33 assume !(1 == ~t9_pc~0); 710530#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 710527#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 710525#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 710523#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 710521#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 710519#L1047-3 assume !(1 == ~M_E~0); 678798#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 710515#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 710513#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 710511#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 710509#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 710507#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 710505#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 710503#L1082-3 assume !(1 == ~T8_E~0); 710501#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 710499#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 710497#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 710495#L1102-3 assume !(1 == ~E_2~0); 710493#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 710490#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 710488#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 710486#L1122-3 assume !(1 == ~E_6~0); 710484#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 710482#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 710480#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 710478#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 710472#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 710406#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 710398#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 710397#L1447 assume !(0 == start_simulation_~tmp~3#1); 631264#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 631265#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 630479#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 631050#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 630592#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 630347#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 630348#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 630824#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 630360#L1428-2 [2021-12-06 17:17:00,776 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:17:00,776 INFO L85 PathProgramCache]: Analyzing trace with hash -1839154805, now seen corresponding path program 1 times [2021-12-06 17:17:00,776 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:17:00,776 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1093888221] [2021-12-06 17:17:00,776 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:17:00,776 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:17:00,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:17:00,803 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:17:00,803 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:17:00,803 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1093888221] [2021-12-06 17:17:00,803 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1093888221] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:17:00,803 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:17:00,803 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:17:00,803 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1883147492] [2021-12-06 17:17:00,803 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:17:00,803 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:17:00,804 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:17:00,804 INFO L85 PathProgramCache]: Analyzing trace with hash -1173593068, now seen corresponding path program 2 times [2021-12-06 17:17:00,804 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:17:00,804 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1727381535] [2021-12-06 17:17:00,804 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:17:00,804 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:17:00,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:17:00,826 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:17:00,826 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:17:00,826 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1727381535] [2021-12-06 17:17:00,827 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1727381535] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:17:00,827 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:17:00,827 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 17:17:00,827 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [885730085] [2021-12-06 17:17:00,827 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:17:00,827 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:17:00,827 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:17:00,828 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 17:17:00,828 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 17:17:00,828 INFO L87 Difference]: Start difference. First operand 97465 states and 137838 transitions. cyclomatic complexity: 40377 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:17:01,195 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:17:01,196 INFO L93 Difference]: Finished difference Result 154017 states and 217383 transitions. [2021-12-06 17:17:01,196 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 17:17:01,196 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 154017 states and 217383 transitions. [2021-12-06 17:17:01,790 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 153504 [2021-12-06 17:17:02,135 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 154017 states to 154017 states and 217383 transitions. [2021-12-06 17:17:02,135 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 154017 [2021-12-06 17:17:02,167 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 154017 [2021-12-06 17:17:02,168 INFO L73 IsDeterministic]: Start isDeterministic. Operand 154017 states and 217383 transitions. [2021-12-06 17:17:02,198 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:17:02,198 INFO L681 BuchiCegarLoop]: Abstraction has 154017 states and 217383 transitions. [2021-12-06 17:17:02,235 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 154017 states and 217383 transitions. [2021-12-06 17:17:02,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 154017 to 108814. [2021-12-06 17:17:03,018 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108814 states, 108814 states have (on average 1.415433675813774) internal successors, (154019), 108813 states have internal predecessors, (154019), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:17:03,235 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108814 states to 108814 states and 154019 transitions. [2021-12-06 17:17:03,236 INFO L704 BuchiCegarLoop]: Abstraction has 108814 states and 154019 transitions. [2021-12-06 17:17:03,236 INFO L587 BuchiCegarLoop]: Abstraction has 108814 states and 154019 transitions. [2021-12-06 17:17:03,236 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-06 17:17:03,236 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108814 states and 154019 transitions. [2021-12-06 17:17:03,543 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 108416 [2021-12-06 17:17:03,543 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:17:03,543 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:17:03,549 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:17:03,549 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:17:03,550 INFO L791 eck$LassoCheckResult]: Stem: 882596#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 882597#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 882541#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 882542#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 882826#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 882415#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 882416#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 882794#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 882206#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 882207#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 882690#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 882691#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 881686#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 881687#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 881889#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 882302#L939 assume !(0 == ~M_E~0); 882575#L939-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 882576#L944-1 assume !(0 == ~T2_E~0); 882818#L949-1 assume !(0 == ~T3_E~0); 882334#L954-1 assume !(0 == ~T4_E~0); 882335#L959-1 assume !(0 == ~T5_E~0); 882847#L964-1 assume !(0 == ~T6_E~0); 882848#L969-1 assume !(0 == ~T7_E~0); 883110#L974-1 assume !(0 == ~T8_E~0); 882781#L979-1 assume !(0 == ~T9_E~0); 882782#L984-1 assume !(0 == ~E_M~0); 882218#L989-1 assume !(0 == ~E_1~0); 882219#L994-1 assume !(0 == ~E_2~0); 882553#L999-1 assume !(0 == ~E_3~0); 882743#L1004-1 assume !(0 == ~E_4~0); 882744#L1009-1 assume !(0 == ~E_5~0); 882093#L1014-1 assume !(0 == ~E_6~0); 882094#L1019-1 assume !(0 == ~E_7~0); 883108#L1024-1 assume !(0 == ~E_8~0); 882017#L1029-1 assume !(0 == ~E_9~0); 882018#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 883107#L460 assume !(1 == ~m_pc~0); 883027#L460-2 is_master_triggered_~__retres1~0#1 := 0; 883028#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 883035#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 883014#L1167 assume !(0 != activate_threads_~tmp~1#1); 883015#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 883105#L479 assume !(1 == ~t1_pc~0); 883104#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 883029#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 882942#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 882943#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 882392#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 882393#L498 assume !(1 == ~t2_pc~0); 882710#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 882711#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 882896#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 882897#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 882647#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 882648#L517 assume !(1 == ~t3_pc~0); 883039#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 883040#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 882382#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 882383#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 882714#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 882715#L536 assume !(1 == ~t4_pc~0); 882372#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 882371#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 883058#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 883059#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 883056#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 883057#L555 assume !(1 == ~t5_pc~0); 882699#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 882700#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 881787#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 881788#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 881896#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 881793#L574 assume !(1 == ~t6_pc~0); 881794#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 883064#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 883065#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 882737#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 882738#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 883100#L593 assume !(1 == ~t7_pc~0); 882038#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 882039#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 883054#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 883055#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 883099#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 882211#L612 assume !(1 == ~t8_pc~0); 882212#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 882676#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 882508#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 882509#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 883094#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 883093#L631 assume !(1 == ~t9_pc~0); 883092#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 881783#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 881784#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 882303#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 882304#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 882716#L1047 assume !(1 == ~M_E~0); 882717#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 881725#L1052-1 assume !(1 == ~T2_E~0); 881705#L1057-1 assume !(1 == ~T3_E~0); 881706#L1062-1 assume !(1 == ~T4_E~0); 882001#L1067-1 assume !(1 == ~T5_E~0); 882326#L1072-1 assume !(1 == ~T6_E~0); 882327#L1077-1 assume !(1 == ~T7_E~0); 881885#L1082-1 assume !(1 == ~T8_E~0); 881886#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 881682#L1092-1 assume !(1 == ~E_M~0); 881683#L1097-1 assume !(1 == ~E_1~0); 881707#L1102-1 assume !(1 == ~E_2~0); 882535#L1107-1 assume !(1 == ~E_3~0); 882462#L1112-1 assume !(1 == ~E_4~0); 882463#L1117-1 assume !(1 == ~E_5~0); 882510#L1122-1 assume !(1 == ~E_6~0); 882384#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 882120#L1132-1 assume !(1 == ~E_8~0); 882121#L1137-1 assume !(1 == ~E_9~0); 881999#L1142-1 assume { :end_inline_reset_delta_events } true; 882000#L1428-2 [2021-12-06 17:17:03,550 INFO L793 eck$LassoCheckResult]: Loop: 882000#L1428-2 assume !false; 924082#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 923791#L914 assume !false; 924080#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 924072#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 924062#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 924060#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 924058#L783 assume !(0 != eval_~tmp~0#1); 924059#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 987454#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 986689#L939-3 assume !(0 == ~M_E~0); 925771#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 925772#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 925758#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 925759#L954-3 assume !(0 == ~T4_E~0); 925747#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 925748#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 925648#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 925649#L974-3 assume !(0 == ~T8_E~0); 925644#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 925645#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 925640#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 925641#L994-3 assume !(0 == ~E_2~0); 925636#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 925637#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 925631#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 925632#L1014-3 assume !(0 == ~E_6~0); 925625#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 925626#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 925619#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 925620#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 925613#L460-33 assume !(1 == ~m_pc~0); 925614#L460-35 is_master_triggered_~__retres1~0#1 := 0; 925606#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 925607#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 925600#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 925601#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 922156#L479-33 assume !(1 == ~t1_pc~0); 922157#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 922146#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 922147#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 922133#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 922134#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 922116#L498-33 assume !(1 == ~t2_pc~0); 922115#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 922101#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 922102#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 922084#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 922085#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 921053#L517-33 assume !(1 == ~t3_pc~0); 921054#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 921042#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 921043#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 921031#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 921032#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 921021#L536-33 assume 1 == ~t4_pc~0; 921022#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 921010#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 921011#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 921000#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 921001#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 920990#L555-33 assume !(1 == ~t5_pc~0); 920991#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 920980#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 920981#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 920643#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 920644#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 920633#L574-33 assume 1 == ~t6_pc~0; 920634#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 920624#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 920625#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 920616#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 920617#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 920608#L593-33 assume !(1 == ~t7_pc~0); 911411#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 920601#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 920602#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 920592#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 920593#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 920584#L612-33 assume !(1 == ~t8_pc~0); 920586#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 920575#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 920576#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 919964#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 919965#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 912500#L631-33 assume !(1 == ~t9_pc~0); 912497#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 912495#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 912493#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 910706#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 910705#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 898389#L1047-3 assume !(1 == ~M_E~0); 898358#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 898355#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 898353#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 898350#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 898347#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 898344#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 898341#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 898338#L1082-3 assume !(1 == ~T8_E~0); 898336#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 898332#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 898329#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 898326#L1102-3 assume !(1 == ~E_2~0); 898323#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 898320#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 898314#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 898312#L1122-3 assume !(1 == ~E_6~0); 898310#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 898309#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 898308#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 898307#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 898291#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 898279#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 898277#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 898271#L1447 assume !(0 == start_simulation_~tmp~3#1); 898272#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 924106#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 924096#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 924094#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 924091#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 924089#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 924087#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 924085#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 882000#L1428-2 [2021-12-06 17:17:03,550 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:17:03,551 INFO L85 PathProgramCache]: Analyzing trace with hash -532012407, now seen corresponding path program 1 times [2021-12-06 17:17:03,551 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:17:03,551 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [117258695] [2021-12-06 17:17:03,551 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:17:03,551 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:17:03,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:17:03,580 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:17:03,581 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:17:03,581 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [117258695] [2021-12-06 17:17:03,581 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [117258695] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:17:03,581 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:17:03,581 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:17:03,581 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [79160835] [2021-12-06 17:17:03,581 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:17:03,582 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:17:03,582 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:17:03,582 INFO L85 PathProgramCache]: Analyzing trace with hash 1743478034, now seen corresponding path program 1 times [2021-12-06 17:17:03,583 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:17:03,583 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1776123070] [2021-12-06 17:17:03,583 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:17:03,583 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:17:03,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:17:03,611 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:17:03,611 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:17:03,611 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1776123070] [2021-12-06 17:17:03,611 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1776123070] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:17:03,611 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:17:03,611 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:17:03,611 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1222444110] [2021-12-06 17:17:03,612 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:17:03,612 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:17:03,612 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:17:03,612 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 17:17:03,613 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 17:17:03,613 INFO L87 Difference]: Start difference. First operand 108814 states and 154019 transitions. cyclomatic complexity: 45209 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:17:04,098 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:17:04,099 INFO L93 Difference]: Finished difference Result 142649 states and 200716 transitions. [2021-12-06 17:17:04,099 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 17:17:04,099 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 142649 states and 200716 transitions. [2021-12-06 17:17:04,600 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 142240 [2021-12-06 17:17:04,931 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 142649 states to 142649 states and 200716 transitions. [2021-12-06 17:17:04,931 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 142649 [2021-12-06 17:17:05,146 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 142649 [2021-12-06 17:17:05,147 INFO L73 IsDeterministic]: Start isDeterministic. Operand 142649 states and 200716 transitions. [2021-12-06 17:17:05,184 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:17:05,184 INFO L681 BuchiCegarLoop]: Abstraction has 142649 states and 200716 transitions. [2021-12-06 17:17:05,228 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142649 states and 200716 transitions. [2021-12-06 17:17:05,874 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142649 to 97465. [2021-12-06 17:17:05,935 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97465 states, 97465 states have (on average 1.4102703534602166) internal successors, (137452), 97464 states have internal predecessors, (137452), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:17:06,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97465 states to 97465 states and 137452 transitions. [2021-12-06 17:17:06,092 INFO L704 BuchiCegarLoop]: Abstraction has 97465 states and 137452 transitions. [2021-12-06 17:17:06,092 INFO L587 BuchiCegarLoop]: Abstraction has 97465 states and 137452 transitions. [2021-12-06 17:17:06,092 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-06 17:17:06,092 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97465 states and 137452 transitions. [2021-12-06 17:17:06,323 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 97152 [2021-12-06 17:17:06,323 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:17:06,323 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:17:06,327 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:17:06,327 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:17:06,327 INFO L791 eck$LassoCheckResult]: Stem: 1134075#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1134076#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1134014#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1134015#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1134297#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 1133886#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1133887#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1134265#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1133678#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1133679#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1134167#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1134168#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1133159#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1133160#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1133360#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1133777#L939 assume !(0 == ~M_E~0); 1134050#L939-2 assume !(0 == ~T1_E~0); 1134051#L944-1 assume !(0 == ~T2_E~0); 1133810#L949-1 assume !(0 == ~T3_E~0); 1133806#L954-1 assume !(0 == ~T4_E~0); 1133807#L959-1 assume !(0 == ~T5_E~0); 1134326#L964-1 assume !(0 == ~T6_E~0); 1133517#L969-1 assume !(0 == ~T7_E~0); 1133518#L974-1 assume !(0 == ~T8_E~0); 1134248#L979-1 assume !(0 == ~T9_E~0); 1134249#L984-1 assume !(0 == ~E_M~0); 1133690#L989-1 assume !(0 == ~E_1~0); 1133691#L994-1 assume !(0 == ~E_2~0); 1133568#L999-1 assume !(0 == ~E_3~0); 1133569#L1004-1 assume !(0 == ~E_4~0); 1133226#L1009-1 assume !(0 == ~E_5~0); 1133227#L1014-1 assume !(0 == ~E_6~0); 1133564#L1019-1 assume !(0 == ~E_7~0); 1134173#L1024-1 assume !(0 == ~E_8~0); 1133488#L1029-1 assume !(0 == ~E_9~0); 1133489#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1133584#L460 assume !(1 == ~m_pc~0); 1134463#L460-2 is_master_triggered_~__retres1~0#1 := 0; 1134135#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1134136#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1134503#L1167 assume !(0 != activate_threads_~tmp~1#1); 1133795#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1133796#L479 assume !(1 == ~t1_pc~0); 1133961#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1133962#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1134422#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1133502#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 1133503#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1133342#L498 assume !(1 == ~t2_pc~0); 1133343#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1133775#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1133776#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1134213#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 1134124#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1134125#L517 assume !(1 == ~t3_pc~0); 1134524#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1134525#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1133854#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1133533#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 1133534#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1134186#L536 assume !(1 == ~t4_pc~0); 1133844#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1133843#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1134312#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1133836#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 1133837#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1134093#L555 assume !(1 == ~t5_pc~0); 1134094#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1134174#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1133259#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1133260#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 1133367#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1133266#L574 assume !(1 == ~t6_pc~0); 1133267#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1133937#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1133370#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1133371#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 1134208#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1134475#L593 assume !(1 == ~t7_pc~0); 1133506#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1133507#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1134332#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1134531#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 1134430#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1133683#L612 assume !(1 == ~t8_pc~0); 1133684#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1134153#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1133981#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1133982#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 1133941#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1133942#L631 assume !(1 == ~t9_pc~0); 1134013#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1133256#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1133224#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1133225#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 1133778#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1134187#L1047 assume !(1 == ~M_E~0); 1133197#L1047-2 assume !(1 == ~T1_E~0); 1133198#L1052-1 assume !(1 == ~T2_E~0); 1133178#L1057-1 assume !(1 == ~T3_E~0); 1133179#L1062-1 assume !(1 == ~T4_E~0); 1133472#L1067-1 assume !(1 == ~T5_E~0); 1133799#L1072-1 assume !(1 == ~T6_E~0); 1133800#L1077-1 assume !(1 == ~T7_E~0); 1133356#L1082-1 assume !(1 == ~T8_E~0); 1133357#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1133155#L1092-1 assume !(1 == ~E_M~0); 1133156#L1097-1 assume !(1 == ~E_1~0); 1133180#L1102-1 assume !(1 == ~E_2~0); 1134008#L1107-1 assume !(1 == ~E_3~0); 1133935#L1112-1 assume !(1 == ~E_4~0); 1133936#L1117-1 assume !(1 == ~E_5~0); 1133983#L1122-1 assume !(1 == ~E_6~0); 1133855#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1133587#L1132-1 assume !(1 == ~E_8~0); 1133588#L1137-1 assume !(1 == ~E_9~0); 1133470#L1142-1 assume { :end_inline_reset_delta_events } true; 1133471#L1428-2 [2021-12-06 17:17:06,327 INFO L793 eck$LassoCheckResult]: Loop: 1133471#L1428-2 assume !false; 1225875#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1225870#L914 assume !false; 1225868#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1134158#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1133164#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1133165#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1134209#L783 assume !(0 != eval_~tmp~0#1); 1134210#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1230220#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1230219#L939-3 assume !(0 == ~M_E~0); 1230218#L939-5 assume !(0 == ~T1_E~0); 1230217#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1230215#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1230212#L954-3 assume !(0 == ~T4_E~0); 1230210#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1230208#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1230206#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1230204#L974-3 assume !(0 == ~T8_E~0); 1230202#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1230201#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1230198#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1230196#L994-3 assume !(0 == ~E_2~0); 1230194#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1230192#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1230190#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1230187#L1014-3 assume !(0 == ~E_6~0); 1230186#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1230185#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1230184#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1230182#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1230180#L460-33 assume !(1 == ~m_pc~0); 1230178#L460-35 is_master_triggered_~__retres1~0#1 := 0; 1230177#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1230174#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1230172#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1134016#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1133524#L479-33 assume !(1 == ~t1_pc~0); 1133525#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1133490#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1133491#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1134147#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 1134402#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1230167#L498-33 assume !(1 == ~t2_pc~0); 1230164#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1230162#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1230160#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1230158#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 1230156#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1134490#L517-33 assume !(1 == ~t3_pc~0); 1134491#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1134540#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1134536#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1134043#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1134044#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1133624#L536-33 assume 1 == ~t4_pc~0; 1133625#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1133702#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1133703#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1133912#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1229163#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1133201#L555-33 assume !(1 == ~t5_pc~0); 1133202#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1133974#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1133481#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1133482#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1134004#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1133172#L574-33 assume 1 == ~t6_pc~0; 1133173#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1134271#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1133496#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1133497#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1133772#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1133247#L593-33 assume !(1 == ~t7_pc~0); 1133248#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1226489#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1226488#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1226487#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1226486#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1226485#L612-33 assume 1 == ~t8_pc~0; 1226483#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1226480#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1226478#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1226476#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1226474#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1226473#L631-33 assume !(1 == ~t9_pc~0); 1203712#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 1226469#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1226467#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1226465#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1133411#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1133412#L1047-3 assume !(1 == ~M_E~0); 1133590#L1047-5 assume !(1 == ~T1_E~0); 1134325#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1134218#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1134219#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1133307#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1133308#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1133710#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1133542#L1082-3 assume !(1 == ~T8_E~0); 1133543#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1133623#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1133930#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1133852#L1102-3 assume !(1 == ~E_2~0); 1133853#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1134276#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1133535#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1133536#L1122-3 assume !(1 == ~E_6~0); 1133591#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1133592#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1223363#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1223362#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1133416#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1133290#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1133998#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1133999#L1447 assume !(0 == start_simulation_~tmp~3#1); 1191271#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1226012#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1226002#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1226001#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 1225905#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1225904#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1225893#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1225887#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 1133471#L1428-2 [2021-12-06 17:17:06,328 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:17:06,328 INFO L85 PathProgramCache]: Analyzing trace with hash 1638164041, now seen corresponding path program 1 times [2021-12-06 17:17:06,328 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:17:06,328 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [324153987] [2021-12-06 17:17:06,328 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:17:06,328 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:17:06,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:17:06,355 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:17:06,355 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:17:06,356 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [324153987] [2021-12-06 17:17:06,356 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [324153987] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:17:06,356 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:17:06,356 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:17:06,356 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1525848992] [2021-12-06 17:17:06,356 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:17:06,356 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:17:06,356 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:17:06,357 INFO L85 PathProgramCache]: Analyzing trace with hash 323893009, now seen corresponding path program 1 times [2021-12-06 17:17:06,357 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:17:06,357 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1636175614] [2021-12-06 17:17:06,357 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:17:06,357 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:17:06,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:17:06,374 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:17:06,375 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:17:06,375 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1636175614] [2021-12-06 17:17:06,375 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1636175614] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:17:06,375 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:17:06,375 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:17:06,375 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1107839672] [2021-12-06 17:17:06,375 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:17:06,376 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:17:06,376 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:17:06,376 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 17:17:06,376 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 17:17:06,376 INFO L87 Difference]: Start difference. First operand 97465 states and 137452 transitions. cyclomatic complexity: 39991 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:17:06,904 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:17:06,904 INFO L93 Difference]: Finished difference Result 154009 states and 216853 transitions. [2021-12-06 17:17:06,905 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 17:17:06,905 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 154009 states and 216853 transitions. [2021-12-06 17:17:07,492 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 153504 [2021-12-06 17:17:07,956 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 154009 states to 154009 states and 216853 transitions. [2021-12-06 17:17:07,956 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 154009 [2021-12-06 17:17:08,000 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 154009 [2021-12-06 17:17:08,000 INFO L73 IsDeterministic]: Start isDeterministic. Operand 154009 states and 216853 transitions. [2021-12-06 17:17:08,042 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:17:08,042 INFO L681 BuchiCegarLoop]: Abstraction has 154009 states and 216853 transitions. [2021-12-06 17:17:08,092 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 154009 states and 216853 transitions. [2021-12-06 17:17:08,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 154009 to 108814. [2021-12-06 17:17:08,897 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108814 states, 108814 states have (on average 1.4118863381550169) internal successors, (153633), 108813 states have internal predecessors, (153633), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:17:09,079 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108814 states to 108814 states and 153633 transitions. [2021-12-06 17:17:09,079 INFO L704 BuchiCegarLoop]: Abstraction has 108814 states and 153633 transitions. [2021-12-06 17:17:09,079 INFO L587 BuchiCegarLoop]: Abstraction has 108814 states and 153633 transitions. [2021-12-06 17:17:09,079 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-06 17:17:09,080 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108814 states and 153633 transitions. [2021-12-06 17:17:09,349 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 108416 [2021-12-06 17:17:09,350 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:17:09,350 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:17:09,354 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:17:09,354 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:17:09,355 INFO L791 eck$LassoCheckResult]: Stem: 1385556#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1385557#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1385499#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1385500#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1385777#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 1385374#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1385375#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1385748#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1385164#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1385165#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1385647#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1385648#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1384643#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1384644#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1384846#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1385260#L939 assume !(0 == ~M_E~0); 1385531#L939-2 assume !(0 == ~T1_E~0); 1385532#L944-1 assume !(0 == ~T2_E~0); 1385295#L949-1 assume !(0 == ~T3_E~0); 1385291#L954-1 assume !(0 == ~T4_E~0); 1385292#L959-1 assume !(0 == ~T5_E~0); 1385806#L964-1 assume !(0 == ~T6_E~0); 1385004#L969-1 assume !(0 == ~T7_E~0); 1385005#L974-1 assume !(0 == ~T8_E~0); 1385733#L979-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1385734#L984-1 assume !(0 == ~E_M~0); 1385177#L989-1 assume !(0 == ~E_1~0); 1385178#L994-1 assume !(0 == ~E_2~0); 1385056#L999-1 assume !(0 == ~E_3~0); 1385057#L1004-1 assume !(0 == ~E_4~0); 1384710#L1009-1 assume !(0 == ~E_5~0); 1384711#L1014-1 assume !(0 == ~E_6~0); 1385653#L1019-1 assume !(0 == ~E_7~0); 1385654#L1024-1 assume !(0 == ~E_8~0); 1385945#L1029-1 assume !(0 == ~E_9~0); 1386085#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1386084#L460 assume !(1 == ~m_pc~0); 1385998#L460-2 is_master_triggered_~__retres1~0#1 := 0; 1385999#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1386008#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1385987#L1167 assume !(0 != activate_threads_~tmp~1#1); 1385988#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1386082#L479 assume !(1 == ~t1_pc~0); 1386081#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1386000#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1385907#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1385908#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 1385349#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1385350#L498 assume !(1 == ~t2_pc~0); 1385664#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1385665#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1386078#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1385699#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 1385700#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1386043#L517 assume !(1 == ~t3_pc~0); 1386044#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1386019#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1386020#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1385020#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 1385021#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1385849#L536 assume !(1 == ~t4_pc~0); 1385850#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1385791#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1385792#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1385321#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 1385322#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1385575#L555 assume !(1 == ~t5_pc~0); 1385576#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1385728#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1384743#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1384744#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 1386076#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1386075#L574 assume !(1 == ~t6_pc~0); 1385424#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1385425#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1386074#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1385691#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 1385692#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1386073#L593 assume !(1 == ~t7_pc~0); 1384993#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1384994#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1386026#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1386027#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 1386072#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1385170#L612 assume !(1 == ~t8_pc~0); 1385171#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1385633#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1385467#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1385468#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 1386067#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1386066#L631 assume !(1 == ~t9_pc~0); 1386065#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1384739#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1384740#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1385261#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 1385262#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1385670#L1047 assume !(1 == ~M_E~0); 1385671#L1047-2 assume !(1 == ~T1_E~0); 1386064#L1052-1 assume !(1 == ~T2_E~0); 1386063#L1057-1 assume !(1 == ~T3_E~0); 1384954#L1062-1 assume !(1 == ~T4_E~0); 1384955#L1067-1 assume !(1 == ~T5_E~0); 1385284#L1072-1 assume !(1 == ~T6_E~0); 1385285#L1077-1 assume !(1 == ~T7_E~0); 1386062#L1082-1 assume !(1 == ~T8_E~0); 1386061#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1384639#L1092-1 assume !(1 == ~E_M~0); 1384640#L1097-1 assume !(1 == ~E_1~0); 1384664#L1102-1 assume !(1 == ~E_2~0); 1385493#L1107-1 assume !(1 == ~E_3~0); 1385421#L1112-1 assume !(1 == ~E_4~0); 1385422#L1117-1 assume !(1 == ~E_5~0); 1385469#L1122-1 assume !(1 == ~E_6~0); 1385341#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1385075#L1132-1 assume !(1 == ~E_8~0); 1385076#L1137-1 assume !(1 == ~E_9~0); 1384952#L1142-1 assume { :end_inline_reset_delta_events } true; 1384953#L1428-2 [2021-12-06 17:17:09,355 INFO L793 eck$LassoCheckResult]: Loop: 1384953#L1428-2 assume !false; 1478968#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1478961#L914 assume !false; 1478959#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1478911#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1478896#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1478890#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1478883#L783 assume !(0 != eval_~tmp~0#1); 1478877#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1478871#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1478865#L939-3 assume !(0 == ~M_E~0); 1478859#L939-5 assume !(0 == ~T1_E~0); 1478854#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1478847#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1478839#L954-3 assume !(0 == ~T4_E~0); 1478832#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1478823#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1478814#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1478806#L974-3 assume !(0 == ~T8_E~0); 1478795#L979-3 assume !(0 == ~T9_E~0); 1478796#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1490454#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1490452#L994-3 assume !(0 == ~E_2~0); 1490450#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1490448#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1490446#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1490444#L1014-3 assume !(0 == ~E_6~0); 1490442#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1490441#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1490439#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1490437#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1490435#L460-33 assume !(1 == ~m_pc~0); 1490433#L460-35 is_master_triggered_~__retres1~0#1 := 0; 1490431#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1490428#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1490426#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1490424#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1490422#L479-33 assume !(1 == ~t1_pc~0); 1490277#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1490419#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1490417#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1490415#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 1490413#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1490411#L498-33 assume !(1 == ~t2_pc~0); 1490408#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1490406#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1490403#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1490401#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 1490399#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1490397#L517-33 assume !(1 == ~t3_pc~0); 1477456#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1490394#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1490393#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1490392#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1490391#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1490390#L536-33 assume !(1 == ~t4_pc~0); 1490388#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 1490385#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1490383#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1490381#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1490379#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1490377#L555-33 assume !(1 == ~t5_pc~0); 1490375#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1490374#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1490372#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1490370#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1490368#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1490366#L574-33 assume 1 == ~t6_pc~0; 1490354#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1490352#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1490350#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1490348#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1490346#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1478340#L593-33 assume !(1 == ~t7_pc~0); 1478338#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1478336#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1478335#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1478333#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1478331#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1478329#L612-33 assume 1 == ~t8_pc~0; 1478240#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1478233#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1478227#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1478221#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1478215#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1478184#L631-33 assume !(1 == ~t9_pc~0); 1439737#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 1457496#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1457494#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1457492#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1457491#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1457490#L1047-3 assume !(1 == ~M_E~0); 1430763#L1047-5 assume !(1 == ~T1_E~0); 1457487#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1457485#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1457483#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1457482#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1457479#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1457477#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1457475#L1082-3 assume !(1 == ~T8_E~0); 1457473#L1087-3 assume !(1 == ~T9_E~0); 1457470#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1457467#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1457465#L1102-3 assume !(1 == ~E_2~0); 1457463#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1457461#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1457459#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1457457#L1122-3 assume !(1 == ~E_6~0); 1457454#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1457453#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1457450#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1457448#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1457442#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1457431#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1457429#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1437744#L1447 assume !(0 == start_simulation_~tmp~3#1); 1437745#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1479099#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1479027#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1479015#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 1479005#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1479004#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1478993#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1478984#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 1384953#L1428-2 [2021-12-06 17:17:09,355 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:17:09,355 INFO L85 PathProgramCache]: Analyzing trace with hash -1773294265, now seen corresponding path program 1 times [2021-12-06 17:17:09,355 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:17:09,355 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [274128445] [2021-12-06 17:17:09,356 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:17:09,356 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:17:09,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:17:09,377 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:17:09,377 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:17:09,377 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [274128445] [2021-12-06 17:17:09,378 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [274128445] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:17:09,378 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:17:09,378 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:17:09,378 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [736591318] [2021-12-06 17:17:09,378 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:17:09,378 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:17:09,379 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:17:09,379 INFO L85 PathProgramCache]: Analyzing trace with hash 1445949842, now seen corresponding path program 1 times [2021-12-06 17:17:09,379 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:17:09,379 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [129152868] [2021-12-06 17:17:09,379 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:17:09,379 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:17:09,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:17:09,402 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:17:09,402 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:17:09,402 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [129152868] [2021-12-06 17:17:09,402 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [129152868] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:17:09,403 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:17:09,403 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:17:09,403 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [941918924] [2021-12-06 17:17:09,403 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:17:09,403 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:17:09,403 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:17:09,404 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 17:17:09,404 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 17:17:09,404 INFO L87 Difference]: Start difference. First operand 108814 states and 153633 transitions. cyclomatic complexity: 44823 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:17:09,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:17:09,932 INFO L93 Difference]: Finished difference Result 142649 states and 200202 transitions. [2021-12-06 17:17:09,932 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 17:17:09,933 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 142649 states and 200202 transitions. [2021-12-06 17:17:10,370 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 142240 [2021-12-06 17:17:10,625 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 142649 states to 142649 states and 200202 transitions. [2021-12-06 17:17:10,626 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 142649 [2021-12-06 17:17:10,675 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 142649 [2021-12-06 17:17:10,675 INFO L73 IsDeterministic]: Start isDeterministic. Operand 142649 states and 200202 transitions. [2021-12-06 17:17:10,887 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:17:10,887 INFO L681 BuchiCegarLoop]: Abstraction has 142649 states and 200202 transitions. [2021-12-06 17:17:10,931 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142649 states and 200202 transitions. [2021-12-06 17:17:11,648 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142649 to 97465. [2021-12-06 17:17:11,710 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97465 states, 97465 states have (on average 1.4063099574206126) internal successors, (137066), 97464 states have internal predecessors, (137066), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:17:12,027 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97465 states to 97465 states and 137066 transitions. [2021-12-06 17:17:12,027 INFO L704 BuchiCegarLoop]: Abstraction has 97465 states and 137066 transitions. [2021-12-06 17:17:12,027 INFO L587 BuchiCegarLoop]: Abstraction has 97465 states and 137066 transitions. [2021-12-06 17:17:12,027 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-12-06 17:17:12,027 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97465 states and 137066 transitions. [2021-12-06 17:17:12,215 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 97152 [2021-12-06 17:17:12,215 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:17:12,215 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:17:12,218 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:17:12,218 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:17:12,219 INFO L791 eck$LassoCheckResult]: Stem: 1637020#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1637021#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1636964#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1636965#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1637241#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 1636834#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1636835#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1637212#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1636630#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1636631#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1637120#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1637121#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1636116#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1636117#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1636316#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1636724#L939 assume !(0 == ~M_E~0); 1636999#L939-2 assume !(0 == ~T1_E~0); 1637000#L944-1 assume !(0 == ~T2_E~0); 1636759#L949-1 assume !(0 == ~T3_E~0); 1636755#L954-1 assume !(0 == ~T4_E~0); 1636756#L959-1 assume !(0 == ~T5_E~0); 1637264#L964-1 assume !(0 == ~T6_E~0); 1636475#L969-1 assume !(0 == ~T7_E~0); 1636476#L974-1 assume !(0 == ~T8_E~0); 1637201#L979-1 assume !(0 == ~T9_E~0); 1637202#L984-1 assume !(0 == ~E_M~0); 1636642#L989-1 assume !(0 == ~E_1~0); 1636643#L994-1 assume !(0 == ~E_2~0); 1636523#L999-1 assume !(0 == ~E_3~0); 1636524#L1004-1 assume !(0 == ~E_4~0); 1636184#L1009-1 assume !(0 == ~E_5~0); 1636185#L1014-1 assume !(0 == ~E_6~0); 1636519#L1019-1 assume !(0 == ~E_7~0); 1637126#L1024-1 assume !(0 == ~E_8~0); 1636445#L1029-1 assume !(0 == ~E_9~0); 1636446#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1636540#L460 assume !(1 == ~m_pc~0); 1637410#L460-2 is_master_triggered_~__retres1~0#1 := 0; 1637085#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1637086#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1637446#L1167 assume !(0 != activate_threads_~tmp~1#1); 1636744#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1636745#L479 assume !(1 == ~t1_pc~0); 1636910#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1636911#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1637364#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1636459#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 1636460#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1636298#L498 assume !(1 == ~t2_pc~0); 1636299#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1636722#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1636723#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1637168#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 1637072#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1637073#L517 assume !(1 == ~t3_pc~0); 1637469#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1637470#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1636802#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1636491#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 1636492#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1637140#L536 assume !(1 == ~t4_pc~0); 1636792#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1636791#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1637250#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1636784#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 1636785#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1637039#L555 assume !(1 == ~t5_pc~0); 1637040#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1637127#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1636216#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1636217#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 1636323#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1636223#L574 assume !(1 == ~t6_pc~0); 1636224#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1636884#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1636326#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1636327#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 1637162#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1637417#L593 assume !(1 == ~t7_pc~0); 1636463#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1636464#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1637269#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1637479#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 1637374#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1636635#L612 assume !(1 == ~t8_pc~0); 1636636#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1637105#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1636931#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1636932#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 1636888#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1636889#L631 assume !(1 == ~t9_pc~0); 1636963#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1636213#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1636182#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1636183#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 1636725#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1637141#L1047 assume !(1 == ~M_E~0); 1636154#L1047-2 assume !(1 == ~T1_E~0); 1636155#L1052-1 assume !(1 == ~T2_E~0); 1636135#L1057-1 assume !(1 == ~T3_E~0); 1636136#L1062-1 assume !(1 == ~T4_E~0); 1636427#L1067-1 assume !(1 == ~T5_E~0); 1636748#L1072-1 assume !(1 == ~T6_E~0); 1636749#L1077-1 assume !(1 == ~T7_E~0); 1636312#L1082-1 assume !(1 == ~T8_E~0); 1636313#L1087-1 assume !(1 == ~T9_E~0); 1636112#L1092-1 assume !(1 == ~E_M~0); 1636113#L1097-1 assume !(1 == ~E_1~0); 1636137#L1102-1 assume !(1 == ~E_2~0); 1636957#L1107-1 assume !(1 == ~E_3~0); 1636882#L1112-1 assume !(1 == ~E_4~0); 1636883#L1117-1 assume !(1 == ~E_5~0); 1636933#L1122-1 assume !(1 == ~E_6~0); 1636803#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1636543#L1132-1 assume !(1 == ~E_8~0); 1636544#L1137-1 assume !(1 == ~E_9~0); 1636425#L1142-1 assume { :end_inline_reset_delta_events } true; 1636426#L1428-2 [2021-12-06 17:17:12,219 INFO L793 eck$LassoCheckResult]: Loop: 1636426#L1428-2 assume !false; 1712157#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1710731#L914 assume !false; 1712156#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1711945#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1711935#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1711933#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1711930#L783 assume !(0 != eval_~tmp~0#1); 1711931#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1733366#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1733364#L939-3 assume !(0 == ~M_E~0); 1733362#L939-5 assume !(0 == ~T1_E~0); 1733360#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1733358#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1733356#L954-3 assume !(0 == ~T4_E~0); 1733354#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1733353#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1733352#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1733350#L974-3 assume !(0 == ~T8_E~0); 1733348#L979-3 assume !(0 == ~T9_E~0); 1733346#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1733344#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1733342#L994-3 assume !(0 == ~E_2~0); 1733340#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1733338#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1733336#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1733334#L1014-3 assume !(0 == ~E_6~0); 1733332#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1733330#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1733328#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1733326#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1733324#L460-33 assume !(1 == ~m_pc~0); 1733322#L460-35 is_master_triggered_~__retres1~0#1 := 0; 1733320#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1733318#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1733316#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1733314#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1717539#L479-33 assume !(1 == ~t1_pc~0); 1717537#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1717535#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1717533#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1717531#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 1717529#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1717527#L498-33 assume !(1 == ~t2_pc~0); 1717524#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1717521#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1717519#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1717517#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 1717515#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1717513#L517-33 assume !(1 == ~t3_pc~0); 1717249#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1717511#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1717509#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1717507#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1717505#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1717503#L536-33 assume 1 == ~t4_pc~0; 1717499#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1717497#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1717495#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1717493#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1717491#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1717488#L555-33 assume !(1 == ~t5_pc~0); 1717486#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1717484#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1717482#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1717480#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1717478#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1717477#L574-33 assume 1 == ~t6_pc~0; 1717474#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1717472#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1717470#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1717468#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1717466#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1717454#L593-33 assume !(1 == ~t7_pc~0); 1716330#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1717434#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1717423#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1717233#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1717213#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1717203#L612-33 assume !(1 == ~t8_pc~0); 1717194#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 1717185#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1717179#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1717173#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1717172#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1717170#L631-33 assume !(1 == ~t9_pc~0); 1707872#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 1717165#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1717162#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1717159#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1717156#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1717155#L1047-3 assume !(1 == ~M_E~0); 1661317#L1047-5 assume !(1 == ~T1_E~0); 1717154#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1717152#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1717149#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1717147#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1717145#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1717143#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1717141#L1082-3 assume !(1 == ~T8_E~0); 1717139#L1087-3 assume !(1 == ~T9_E~0); 1717138#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1717137#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1717136#L1102-3 assume !(1 == ~E_2~0); 1717134#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1717131#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1717129#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1717127#L1122-3 assume !(1 == ~E_6~0); 1717125#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1717124#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1717123#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1717122#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1717115#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1717098#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1716990#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1661182#L1447 assume !(0 == start_simulation_~tmp~3#1); 1661183#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1713950#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1713940#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1713938#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 1713935#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1713933#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1713931#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1713929#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 1636426#L1428-2 [2021-12-06 17:17:12,219 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:17:12,219 INFO L85 PathProgramCache]: Analyzing trace with hash 1896329479, now seen corresponding path program 1 times [2021-12-06 17:17:12,219 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:17:12,219 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1960879506] [2021-12-06 17:17:12,219 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:17:12,220 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:17:12,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:17:12,243 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:17:12,243 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:17:12,243 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1960879506] [2021-12-06 17:17:12,244 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1960879506] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:17:12,244 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:17:12,244 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:17:12,244 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1323569310] [2021-12-06 17:17:12,244 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:17:12,244 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:17:12,244 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:17:12,244 INFO L85 PathProgramCache]: Analyzing trace with hash -565156718, now seen corresponding path program 1 times [2021-12-06 17:17:12,244 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:17:12,244 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1363816172] [2021-12-06 17:17:12,245 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:17:12,245 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:17:12,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:17:12,260 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:17:12,260 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:17:12,260 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1363816172] [2021-12-06 17:17:12,261 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1363816172] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:17:12,261 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:17:12,261 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:17:12,261 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1987053771] [2021-12-06 17:17:12,261 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:17:12,261 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:17:12,261 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:17:12,261 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 17:17:12,261 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 17:17:12,261 INFO L87 Difference]: Start difference. First operand 97465 states and 137066 transitions. cyclomatic complexity: 39605 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:17:12,628 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:17:12,628 INFO L93 Difference]: Finished difference Result 150769 states and 211187 transitions. [2021-12-06 17:17:12,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 17:17:12,629 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 150769 states and 211187 transitions. [2021-12-06 17:17:13,236 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 150208 [2021-12-06 17:17:13,481 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 150769 states to 150769 states and 211187 transitions. [2021-12-06 17:17:13,481 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 150769 [2021-12-06 17:17:13,531 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 150769 [2021-12-06 17:17:13,531 INFO L73 IsDeterministic]: Start isDeterministic. Operand 150769 states and 211187 transitions. [2021-12-06 17:17:13,577 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:17:13,577 INFO L681 BuchiCegarLoop]: Abstraction has 150769 states and 211187 transitions. [2021-12-06 17:17:13,628 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150769 states and 211187 transitions. [2021-12-06 17:17:14,359 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150769 to 108750. [2021-12-06 17:17:14,427 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108750 states, 108750 states have (on average 1.4026850574712644) internal successors, (152542), 108749 states have internal predecessors, (152542), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:17:14,620 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108750 states to 108750 states and 152542 transitions. [2021-12-06 17:17:14,620 INFO L704 BuchiCegarLoop]: Abstraction has 108750 states and 152542 transitions. [2021-12-06 17:17:14,620 INFO L587 BuchiCegarLoop]: Abstraction has 108750 states and 152542 transitions. [2021-12-06 17:17:14,620 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-12-06 17:17:14,620 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108750 states and 152542 transitions. [2021-12-06 17:17:15,026 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 108352 [2021-12-06 17:17:15,026 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:17:15,026 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:17:15,030 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:17:15,030 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:17:15,031 INFO L791 eck$LassoCheckResult]: Stem: 1885278#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1885279#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1885217#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1885218#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1885523#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 1885081#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1885082#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1885490#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1884876#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1884877#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1885376#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1885377#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1884360#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1884361#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1884561#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1884968#L939 assume !(0 == ~M_E~0); 1885254#L939-2 assume !(0 == ~T1_E~0); 1885255#L944-1 assume !(0 == ~T2_E~0); 1885003#L949-1 assume !(0 == ~T3_E~0); 1884999#L954-1 assume !(0 == ~T4_E~0); 1885000#L959-1 assume !(0 == ~T5_E~0); 1885545#L964-1 assume !(0 == ~T6_E~0); 1884720#L969-1 assume !(0 == ~T7_E~0); 1884721#L974-1 assume !(0 == ~T8_E~0); 1885474#L979-1 assume !(0 == ~T9_E~0); 1885475#L984-1 assume !(0 == ~E_M~0); 1884889#L989-1 assume !(0 == ~E_1~0); 1884890#L994-1 assume !(0 == ~E_2~0); 1884769#L999-1 assume !(0 == ~E_3~0); 1884770#L1004-1 assume !(0 == ~E_4~0); 1884428#L1009-1 assume !(0 == ~E_5~0); 1884429#L1014-1 assume !(0 == ~E_6~0); 1884765#L1019-1 assume 0 == ~E_7~0;~E_7~0 := 1; 1885384#L1024-1 assume !(0 == ~E_8~0); 1884687#L1029-1 assume !(0 == ~E_9~0); 1884688#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1885871#L460 assume !(1 == ~m_pc~0); 1885763#L460-2 is_master_triggered_~__retres1~0#1 := 0; 1885764#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1885773#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1885749#L1167 assume !(0 != activate_threads_~tmp~1#1); 1885750#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1885869#L479 assume !(1 == ~t1_pc~0); 1885868#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1885765#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1885766#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1884703#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 1884704#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1884543#L498 assume !(1 == ~t2_pc~0); 1884544#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1884966#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1884967#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1885434#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 1885435#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1885816#L517 assume !(1 == ~t3_pc~0); 1885817#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1885782#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1885783#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1884736#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 1884737#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1885582#L536 assume !(1 == ~t4_pc~0); 1885583#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1885533#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1885534#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1885028#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 1885029#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1885296#L555 assume !(1 == ~t5_pc~0); 1885297#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1885468#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1885469#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1884691#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 1884692#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1885866#L574 assume !(1 == ~t6_pc~0); 1885136#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1885137#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1884571#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1884572#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 1885806#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1885717#L593 assume !(1 == ~t7_pc~0); 1885718#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1885553#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1885554#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1885793#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 1885668#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1885669#L612 assume !(1 == ~t8_pc~0); 1885862#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1885861#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1885860#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1885574#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 1885575#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1885859#L631 assume !(1 == ~t9_pc~0); 1885858#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1884456#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1884457#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1884969#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 1884970#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1885405#L1047 assume !(1 == ~M_E~0); 1885406#L1047-2 assume !(1 == ~T1_E~0); 1885130#L1052-1 assume !(1 == ~T2_E~0); 1884379#L1057-1 assume !(1 == ~T3_E~0); 1884380#L1062-1 assume !(1 == ~T4_E~0); 1885547#L1067-1 assume !(1 == ~T5_E~0); 1885548#L1072-1 assume !(1 == ~T6_E~0); 1885363#L1077-1 assume !(1 == ~T7_E~0); 1885364#L1082-1 assume !(1 == ~T8_E~0); 1885109#L1087-1 assume !(1 == ~T9_E~0); 1885110#L1092-1 assume !(1 == ~E_M~0); 1884381#L1097-1 assume !(1 == ~E_1~0); 1884382#L1102-1 assume !(1 == ~E_2~0); 1885209#L1107-1 assume !(1 == ~E_3~0); 1885210#L1112-1 assume !(1 == ~E_4~0); 1885854#L1117-1 assume !(1 == ~E_5~0); 1885837#L1122-1 assume !(1 == ~E_6~0); 1885838#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1884790#L1132-1 assume !(1 == ~E_8~0); 1884791#L1137-1 assume !(1 == ~E_9~0); 1884667#L1142-1 assume { :end_inline_reset_delta_events } true; 1884668#L1428-2 [2021-12-06 17:17:15,031 INFO L793 eck$LassoCheckResult]: Loop: 1884668#L1428-2 assume !false; 1979997#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1979991#L914 assume !false; 1979988#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1979983#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1979972#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1979970#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1979966#L783 assume !(0 != eval_~tmp~0#1); 1979962#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1979959#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1979956#L939-3 assume !(0 == ~M_E~0); 1979953#L939-5 assume !(0 == ~T1_E~0); 1979951#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1979946#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1979943#L954-3 assume !(0 == ~T4_E~0); 1979940#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1979901#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1979899#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1979897#L974-3 assume !(0 == ~T8_E~0); 1979895#L979-3 assume !(0 == ~T9_E~0); 1979892#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1979889#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1979886#L994-3 assume !(0 == ~E_2~0); 1979883#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1979880#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1979876#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1979873#L1014-3 assume !(0 == ~E_6~0); 1979870#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1979869#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1979868#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1979867#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1979866#L460-33 assume !(1 == ~m_pc~0); 1979865#L460-35 is_master_triggered_~__retres1~0#1 := 0; 1979864#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1979863#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1979862#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1979861#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1979860#L479-33 assume !(1 == ~t1_pc~0); 1965539#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1979859#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1979858#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1979857#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 1979856#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1979855#L498-33 assume !(1 == ~t2_pc~0); 1979853#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1979852#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1979851#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1979850#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 1979849#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1979848#L517-33 assume !(1 == ~t3_pc~0); 1944386#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1979847#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1979846#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1979845#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1979844#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1979843#L536-33 assume !(1 == ~t4_pc~0); 1979842#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 1979840#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1979839#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1979838#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1979837#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1979836#L555-33 assume !(1 == ~t5_pc~0); 1979835#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1979834#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1979833#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1979832#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1979831#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1979830#L574-33 assume 1 == ~t6_pc~0; 1979828#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1979827#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1979826#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1979825#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1979824#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1979823#L593-33 assume !(1 == ~t7_pc~0); 1938270#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1979822#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1979821#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1979820#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1979819#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1979818#L612-33 assume 1 == ~t8_pc~0; 1979816#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1979815#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1979814#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1979813#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1979812#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1979811#L631-33 assume !(1 == ~t9_pc~0); 1921184#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 1979810#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1979809#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1979808#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1979807#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1979806#L1047-3 assume !(1 == ~M_E~0); 1938433#L1047-5 assume !(1 == ~T1_E~0); 1979805#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1979804#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1979803#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1979802#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1979801#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1979800#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1979799#L1082-3 assume !(1 == ~T8_E~0); 1979798#L1087-3 assume !(1 == ~T9_E~0); 1979797#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1979796#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1979795#L1102-3 assume !(1 == ~E_2~0); 1979794#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1979793#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1979792#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1979791#L1122-3 assume !(1 == ~E_6~0); 1979789#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1979787#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1979785#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1979783#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1979744#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1979734#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1979704#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1939561#L1447 assume !(0 == start_simulation_~tmp~3#1); 1939562#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1980138#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1980126#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1980118#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 1980036#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1980027#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1980018#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1980010#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 1884668#L1428-2 [2021-12-06 17:17:15,032 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:17:15,032 INFO L85 PathProgramCache]: Analyzing trace with hash 19846661, now seen corresponding path program 1 times [2021-12-06 17:17:15,032 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:17:15,032 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [83581621] [2021-12-06 17:17:15,032 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:17:15,032 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:17:15,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:17:15,051 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:17:15,051 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:17:15,051 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [83581621] [2021-12-06 17:17:15,051 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [83581621] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:17:15,051 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:17:15,052 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:17:15,052 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [994414898] [2021-12-06 17:17:15,052 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:17:15,052 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:17:15,052 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:17:15,052 INFO L85 PathProgramCache]: Analyzing trace with hash 1445949842, now seen corresponding path program 2 times [2021-12-06 17:17:15,052 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:17:15,052 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1068695155] [2021-12-06 17:17:15,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:17:15,053 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:17:15,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:17:15,071 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:17:15,071 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:17:15,071 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1068695155] [2021-12-06 17:17:15,071 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1068695155] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:17:15,072 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:17:15,072 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:17:15,072 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [509343040] [2021-12-06 17:17:15,072 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:17:15,072 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:17:15,072 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:17:15,073 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 17:17:15,073 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 17:17:15,073 INFO L87 Difference]: Start difference. First operand 108750 states and 152542 transitions. cyclomatic complexity: 43796 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:17:15,518 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:17:15,518 INFO L93 Difference]: Finished difference Result 138297 states and 193176 transitions. [2021-12-06 17:17:15,518 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 17:17:15,519 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 138297 states and 193176 transitions. [2021-12-06 17:17:16,083 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 137824 [2021-12-06 17:17:16,545 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 138297 states to 138297 states and 193176 transitions. [2021-12-06 17:17:16,545 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 138297 [2021-12-06 17:17:16,590 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 138297 [2021-12-06 17:17:16,591 INFO L73 IsDeterministic]: Start isDeterministic. Operand 138297 states and 193176 transitions. [2021-12-06 17:17:16,629 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:17:16,630 INFO L681 BuchiCegarLoop]: Abstraction has 138297 states and 193176 transitions. [2021-12-06 17:17:16,676 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138297 states and 193176 transitions. [2021-12-06 17:17:17,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138297 to 97465. [2021-12-06 17:17:17,447 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97465 states, 97465 states have (on average 1.3970963935771816) internal successors, (136168), 97464 states have internal predecessors, (136168), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:17:17,593 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97465 states to 97465 states and 136168 transitions. [2021-12-06 17:17:17,593 INFO L704 BuchiCegarLoop]: Abstraction has 97465 states and 136168 transitions. [2021-12-06 17:17:17,593 INFO L587 BuchiCegarLoop]: Abstraction has 97465 states and 136168 transitions. [2021-12-06 17:17:17,593 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-12-06 17:17:17,593 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97465 states and 136168 transitions. [2021-12-06 17:17:17,799 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 97152 [2021-12-06 17:17:17,799 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:17:17,799 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:17:17,803 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:17:17,803 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:17:17,803 INFO L791 eck$LassoCheckResult]: Stem: 2132317#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 2132318#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 2132260#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2132261#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2132540#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 2132136#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2132137#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2132512#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2131933#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2131934#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2132409#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2132410#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2131417#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2131418#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2131620#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2132029#L939 assume !(0 == ~M_E~0); 2132294#L939-2 assume !(0 == ~T1_E~0); 2132295#L944-1 assume !(0 == ~T2_E~0); 2132063#L949-1 assume !(0 == ~T3_E~0); 2132059#L954-1 assume !(0 == ~T4_E~0); 2132060#L959-1 assume !(0 == ~T5_E~0); 2132562#L964-1 assume !(0 == ~T6_E~0); 2131777#L969-1 assume !(0 == ~T7_E~0); 2131778#L974-1 assume !(0 == ~T8_E~0); 2132497#L979-1 assume !(0 == ~T9_E~0); 2132498#L984-1 assume !(0 == ~E_M~0); 2131945#L989-1 assume !(0 == ~E_1~0); 2131946#L994-1 assume !(0 == ~E_2~0); 2131827#L999-1 assume !(0 == ~E_3~0); 2131828#L1004-1 assume !(0 == ~E_4~0); 2131485#L1009-1 assume !(0 == ~E_5~0); 2131486#L1014-1 assume !(0 == ~E_6~0); 2131823#L1019-1 assume !(0 == ~E_7~0); 2132417#L1024-1 assume !(0 == ~E_8~0); 2131746#L1029-1 assume !(0 == ~E_9~0); 2131747#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2131843#L460 assume !(1 == ~m_pc~0); 2132696#L460-2 is_master_triggered_~__retres1~0#1 := 0; 2132376#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2132377#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2132737#L1167 assume !(0 != activate_threads_~tmp~1#1); 2132047#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2132048#L479 assume !(1 == ~t1_pc~0); 2132209#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2132210#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2132659#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2131760#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 2131761#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2131602#L498 assume !(1 == ~t2_pc~0); 2131603#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2132027#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2132028#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2132462#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 2132361#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2132362#L517 assume !(1 == ~t3_pc~0); 2132759#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2132760#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2132107#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2131793#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 2131794#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2132429#L536 assume !(1 == ~t4_pc~0); 2132097#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2132096#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2132551#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2132089#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 2132090#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2132334#L555 assume !(1 == ~t5_pc~0); 2132335#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2132418#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2131516#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2131517#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 2131627#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2131523#L574 assume !(1 == ~t6_pc~0); 2131524#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2132186#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2131630#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2131631#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 2132456#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2132703#L593 assume !(1 == ~t7_pc~0); 2131766#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2131767#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2132568#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2132768#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 2132668#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2131938#L612 assume !(1 == ~t8_pc~0); 2131939#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2132395#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2132228#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2132229#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 2132190#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2132191#L631 assume !(1 == ~t9_pc~0); 2132259#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2131513#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2131483#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2131484#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 2132030#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2132430#L1047 assume !(1 == ~M_E~0); 2131455#L1047-2 assume !(1 == ~T1_E~0); 2131456#L1052-1 assume !(1 == ~T2_E~0); 2131436#L1057-1 assume !(1 == ~T3_E~0); 2131437#L1062-1 assume !(1 == ~T4_E~0); 2131729#L1067-1 assume !(1 == ~T5_E~0); 2132051#L1072-1 assume !(1 == ~T6_E~0); 2132052#L1077-1 assume !(1 == ~T7_E~0); 2131616#L1082-1 assume !(1 == ~T8_E~0); 2131617#L1087-1 assume !(1 == ~T9_E~0); 2131413#L1092-1 assume !(1 == ~E_M~0); 2131414#L1097-1 assume !(1 == ~E_1~0); 2131438#L1102-1 assume !(1 == ~E_2~0); 2132255#L1107-1 assume !(1 == ~E_3~0); 2132184#L1112-1 assume !(1 == ~E_4~0); 2132185#L1117-1 assume !(1 == ~E_5~0); 2132230#L1122-1 assume !(1 == ~E_6~0); 2132108#L1127-1 assume !(1 == ~E_7~0); 2131846#L1132-1 assume !(1 == ~E_8~0); 2131847#L1137-1 assume !(1 == ~E_9~0); 2131727#L1142-1 assume { :end_inline_reset_delta_events } true; 2131728#L1428-2 [2021-12-06 17:17:17,804 INFO L793 eck$LassoCheckResult]: Loop: 2131728#L1428-2 assume !false; 2211543#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2211539#L914 assume !false; 2211537#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2211485#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2211475#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2211473#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2211470#L783 assume !(0 != eval_~tmp~0#1); 2211471#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2227850#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2227849#L939-3 assume !(0 == ~M_E~0); 2227848#L939-5 assume !(0 == ~T1_E~0); 2227847#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2227846#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2227845#L954-3 assume !(0 == ~T4_E~0); 2227844#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2227843#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2227841#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2227840#L974-3 assume !(0 == ~T8_E~0); 2227838#L979-3 assume !(0 == ~T9_E~0); 2227837#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2227835#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2227833#L994-3 assume !(0 == ~E_2~0); 2227831#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2227828#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2227823#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2227819#L1014-3 assume !(0 == ~E_6~0); 2227815#L1019-3 assume !(0 == ~E_7~0); 2227812#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2227808#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2227806#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2227804#L460-33 assume !(1 == ~m_pc~0); 2227802#L460-35 is_master_triggered_~__retres1~0#1 := 0; 2227798#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2227795#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2227791#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2227506#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2226606#L479-33 assume !(1 == ~t1_pc~0); 2226604#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 2226602#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2226600#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2226598#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 2226596#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2226595#L498-33 assume !(1 == ~t2_pc~0); 2226592#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 2226590#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2226588#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2226586#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 2226558#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2226552#L517-33 assume !(1 == ~t3_pc~0); 2224740#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 2226544#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2226538#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2226532#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2226526#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2226521#L536-33 assume !(1 == ~t4_pc~0); 2226515#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 2226507#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2226499#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2226492#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2226486#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2226479#L555-33 assume !(1 == ~t5_pc~0); 2226473#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 2226466#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2226461#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2226455#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2226450#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2226444#L574-33 assume !(1 == ~t6_pc~0); 2226439#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 2226431#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2226426#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2226420#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2226413#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2226407#L593-33 assume !(1 == ~t7_pc~0); 2225865#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 2226395#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2226390#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2226384#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2226378#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2226373#L612-33 assume 1 == ~t8_pc~0; 2226293#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2226284#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2226277#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2226270#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2226264#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2132791#L631-33 assume !(1 == ~t9_pc~0); 2132256#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 2131553#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2131554#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2131816#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2131668#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2131669#L1047-3 assume !(1 == ~M_E~0); 2131849#L1047-5 assume !(1 == ~T1_E~0); 2132561#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2132466#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2132467#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2131564#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2131565#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2131964#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2131802#L1082-3 assume !(1 == ~T8_E~0); 2131803#L1087-3 assume !(1 == ~T9_E~0); 2131880#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2132180#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2132105#L1102-3 assume !(1 == ~E_2~0); 2132106#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2132695#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2225510#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2225509#L1122-3 assume !(1 == ~E_6~0); 2225508#L1127-3 assume !(1 == ~E_7~0); 2225507#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2225506#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2225505#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2225503#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2225494#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2189339#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2131983#L1447 assume !(0 == start_simulation_~tmp~3#1); 2131984#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2211566#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2211556#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2211555#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 2211552#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 2211550#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2211548#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 2211546#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 2131728#L1428-2 [2021-12-06 17:17:17,804 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:17:17,804 INFO L85 PathProgramCache]: Analyzing trace with hash 1896389061, now seen corresponding path program 1 times [2021-12-06 17:17:17,804 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:17:17,804 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [561348278] [2021-12-06 17:17:17,804 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:17:17,804 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:17:17,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:17:17,812 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:17:17,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:17:17,885 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:17:17,885 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:17:17,885 INFO L85 PathProgramCache]: Analyzing trace with hash -2028747373, now seen corresponding path program 1 times [2021-12-06 17:17:17,885 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:17:17,885 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2050040619] [2021-12-06 17:17:17,885 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:17:17,886 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:17:17,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:17:17,913 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:17:17,914 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:17:17,914 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2050040619] [2021-12-06 17:17:17,914 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2050040619] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:17:17,914 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:17:17,914 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 17:17:17,914 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1255463787] [2021-12-06 17:17:17,914 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:17:17,914 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:17:17,915 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:17:17,915 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-06 17:17:17,915 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-06 17:17:17,915 INFO L87 Difference]: Start difference. First operand 97465 states and 136168 transitions. cyclomatic complexity: 38707 Second operand has 5 states, 5 states have (on average 24.8) internal successors, (124), 5 states have internal predecessors, (124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:17:18,403 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:17:18,403 INFO L93 Difference]: Finished difference Result 178809 states and 246888 transitions. [2021-12-06 17:17:18,403 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-06 17:17:18,404 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 178809 states and 246888 transitions. [2021-12-06 17:17:19,118 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 178304 [2021-12-06 17:17:19,423 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 178809 states to 178809 states and 246888 transitions. [2021-12-06 17:17:19,423 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 178809 [2021-12-06 17:17:19,481 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 178809 [2021-12-06 17:17:19,481 INFO L73 IsDeterministic]: Start isDeterministic. Operand 178809 states and 246888 transitions. [2021-12-06 17:17:19,536 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:17:19,536 INFO L681 BuchiCegarLoop]: Abstraction has 178809 states and 246888 transitions. [2021-12-06 17:17:19,606 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 178809 states and 246888 transitions. [2021-12-06 17:17:20,578 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 178809 to 97849. [2021-12-06 17:17:20,639 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97849 states, 97849 states have (on average 1.3955380228719763) internal successors, (136552), 97848 states have internal predecessors, (136552), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:17:20,821 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97849 states to 97849 states and 136552 transitions. [2021-12-06 17:17:20,821 INFO L704 BuchiCegarLoop]: Abstraction has 97849 states and 136552 transitions. [2021-12-06 17:17:20,822 INFO L587 BuchiCegarLoop]: Abstraction has 97849 states and 136552 transitions. [2021-12-06 17:17:20,822 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-12-06 17:17:20,822 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97849 states and 136552 transitions. [2021-12-06 17:17:21,171 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 97536 [2021-12-06 17:17:21,171 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:17:21,171 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:17:21,174 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:17:21,174 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:17:21,174 INFO L791 eck$LassoCheckResult]: Stem: 2408633#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 2408634#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 2408573#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2408574#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2408863#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 2408434#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2408435#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2408831#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2408227#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2408228#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2408734#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2408735#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2407707#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2407708#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2407909#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2408323#L939 assume !(0 == ~M_E~0); 2408610#L939-2 assume !(0 == ~T1_E~0); 2408611#L944-1 assume !(0 == ~T2_E~0); 2408357#L949-1 assume !(0 == ~T3_E~0); 2408353#L954-1 assume !(0 == ~T4_E~0); 2408354#L959-1 assume !(0 == ~T5_E~0); 2408891#L964-1 assume !(0 == ~T6_E~0); 2408063#L969-1 assume !(0 == ~T7_E~0); 2408064#L974-1 assume !(0 == ~T8_E~0); 2408815#L979-1 assume !(0 == ~T9_E~0); 2408816#L984-1 assume !(0 == ~E_M~0); 2408240#L989-1 assume !(0 == ~E_1~0); 2408241#L994-1 assume !(0 == ~E_2~0); 2408113#L999-1 assume !(0 == ~E_3~0); 2408114#L1004-1 assume !(0 == ~E_4~0); 2407775#L1009-1 assume !(0 == ~E_5~0); 2407776#L1014-1 assume !(0 == ~E_6~0); 2408109#L1019-1 assume !(0 == ~E_7~0); 2408741#L1024-1 assume !(0 == ~E_8~0); 2408033#L1029-1 assume !(0 == ~E_9~0); 2408034#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2408129#L460 assume !(1 == ~m_pc~0); 2409017#L460-2 is_master_triggered_~__retres1~0#1 := 0; 2408695#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2408696#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2409052#L1167 assume !(0 != activate_threads_~tmp~1#1); 2408341#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2408342#L479 assume !(1 == ~t1_pc~0); 2408514#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2408515#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2408979#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2408048#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 2408049#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2407891#L498 assume !(1 == ~t2_pc~0); 2407892#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2408321#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2408322#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2408781#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 2408685#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2408686#L517 assume !(1 == ~t3_pc~0); 2409075#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2409076#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2408401#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2408080#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 2408081#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2408754#L536 assume !(1 == ~t4_pc~0); 2408391#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2408390#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2408877#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2408383#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 2408384#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2408649#L555 assume !(1 == ~t5_pc~0); 2408650#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2408742#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2407807#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2407808#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 2407914#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2407814#L574 assume !(1 == ~t6_pc~0); 2407815#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2408490#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2407917#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2407918#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 2408777#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2409027#L593 assume !(1 == ~t7_pc~0); 2408052#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2408053#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2408897#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2409082#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 2408984#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2408233#L612 assume !(1 == ~t8_pc~0); 2408234#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2408719#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2408535#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2408536#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 2408494#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2408495#L631 assume !(1 == ~t9_pc~0); 2408572#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2407804#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2407773#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2407774#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 2408324#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2408755#L1047 assume !(1 == ~M_E~0); 2407745#L1047-2 assume !(1 == ~T1_E~0); 2407746#L1052-1 assume !(1 == ~T2_E~0); 2407726#L1057-1 assume !(1 == ~T3_E~0); 2407727#L1062-1 assume !(1 == ~T4_E~0); 2408017#L1067-1 assume !(1 == ~T5_E~0); 2408345#L1072-1 assume !(1 == ~T6_E~0); 2408346#L1077-1 assume !(1 == ~T7_E~0); 2407905#L1082-1 assume !(1 == ~T8_E~0); 2407906#L1087-1 assume !(1 == ~T9_E~0); 2407703#L1092-1 assume !(1 == ~E_M~0); 2407704#L1097-1 assume !(1 == ~E_1~0); 2407728#L1102-1 assume !(1 == ~E_2~0); 2408566#L1107-1 assume !(1 == ~E_3~0); 2408488#L1112-1 assume !(1 == ~E_4~0); 2408489#L1117-1 assume !(1 == ~E_5~0); 2408537#L1122-1 assume !(1 == ~E_6~0); 2408402#L1127-1 assume !(1 == ~E_7~0); 2408132#L1132-1 assume !(1 == ~E_8~0); 2408133#L1137-1 assume !(1 == ~E_9~0); 2408015#L1142-1 assume { :end_inline_reset_delta_events } true; 2408016#L1428-2 [2021-12-06 17:17:21,175 INFO L793 eck$LassoCheckResult]: Loop: 2408016#L1428-2 assume !false; 2480076#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2480072#L914 assume !false; 2480023#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2479733#L716 assume !(0 == ~m_st~0); 2479734#L720 assume !(0 == ~t1_st~0); 2479729#L724 assume !(0 == ~t2_st~0); 2479730#L728 assume !(0 == ~t3_st~0); 2479732#L732 assume !(0 == ~t4_st~0); 2479727#L736 assume !(0 == ~t5_st~0); 2479728#L740 assume !(0 == ~t6_st~0); 2479731#L744 assume !(0 == ~t7_st~0); 2479724#L748 assume !(0 == ~t8_st~0); 2479726#L752 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 2479722#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2479719#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2479720#L783 assume !(0 != eval_~tmp~0#1); 2480827#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2480809#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2480810#L939-3 assume !(0 == ~M_E~0); 2480791#L939-5 assume !(0 == ~T1_E~0); 2480792#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2480774#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2480775#L954-3 assume !(0 == ~T4_E~0); 2480756#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2480757#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2480737#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2480738#L974-3 assume !(0 == ~T8_E~0); 2480718#L979-3 assume !(0 == ~T9_E~0); 2480719#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2480697#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2480698#L994-3 assume !(0 == ~E_2~0); 2480679#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2480680#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2480661#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2480662#L1014-3 assume !(0 == ~E_6~0); 2480644#L1019-3 assume !(0 == ~E_7~0); 2480645#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2480628#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2480629#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2480611#L460-33 assume !(1 == ~m_pc~0); 2480612#L460-35 is_master_triggered_~__retres1~0#1 := 0; 2480591#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2480592#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2480572#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2480573#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2480557#L479-33 assume !(1 == ~t1_pc~0); 2478615#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 2480542#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2480543#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2480523#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 2480524#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2480505#L498-33 assume !(1 == ~t2_pc~0); 2480504#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 2480483#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2480484#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2480463#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 2480464#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2480444#L517-33 assume !(1 == ~t3_pc~0); 2480442#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 2480440#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2480438#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2480436#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2480434#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2480432#L536-33 assume !(1 == ~t4_pc~0); 2480429#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 2480426#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2480424#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2480422#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2480420#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2480418#L555-33 assume !(1 == ~t5_pc~0); 2480416#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 2480414#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2480412#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2480410#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2480408#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2480406#L574-33 assume !(1 == ~t6_pc~0); 2480403#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 2480400#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2480398#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2480396#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2480394#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2480392#L593-33 assume !(1 == ~t7_pc~0); 2474222#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 2480390#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2480388#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2480386#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2480384#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2480382#L612-33 assume !(1 == ~t8_pc~0); 2480379#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 2480376#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2480374#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2480372#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2480370#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2480368#L631-33 assume !(1 == ~t9_pc~0); 2472216#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 2480366#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2480364#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2480362#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2480360#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2480357#L1047-3 assume !(1 == ~M_E~0); 2480356#L1047-5 assume !(1 == ~T1_E~0); 2480355#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2480354#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2480353#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2480352#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2480351#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2480350#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2480349#L1082-3 assume !(1 == ~T8_E~0); 2480348#L1087-3 assume !(1 == ~T9_E~0); 2480347#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2480346#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2480345#L1102-3 assume !(1 == ~E_2~0); 2480344#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2480343#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2480342#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2480341#L1122-3 assume !(1 == ~E_6~0); 2480340#L1127-3 assume !(1 == ~E_7~0); 2480339#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2480338#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2480337#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2480335#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2480299#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2480201#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2480199#L1447 assume !(0 == start_simulation_~tmp~3#1); 2480103#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2480101#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2480090#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2480088#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 2480086#L1402 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 2480084#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2480082#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 2480080#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 2408016#L1428-2 [2021-12-06 17:17:21,175 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:17:21,175 INFO L85 PathProgramCache]: Analyzing trace with hash 1896389061, now seen corresponding path program 2 times [2021-12-06 17:17:21,175 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:17:21,175 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [230733216] [2021-12-06 17:17:21,175 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:17:21,176 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:17:21,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:17:21,183 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:17:21,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:17:21,210 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:17:21,210 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:17:21,210 INFO L85 PathProgramCache]: Analyzing trace with hash 525033193, now seen corresponding path program 1 times [2021-12-06 17:17:21,210 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:17:21,210 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [745451247] [2021-12-06 17:17:21,210 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:17:21,210 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:17:21,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:17:21,234 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:17:21,234 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:17:21,234 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [745451247] [2021-12-06 17:17:21,234 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [745451247] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:17:21,234 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:17:21,234 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 17:17:21,234 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1422437366] [2021-12-06 17:17:21,234 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:17:21,234 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:17:21,235 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:17:21,235 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-06 17:17:21,235 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-06 17:17:21,235 INFO L87 Difference]: Start difference. First operand 97849 states and 136552 transitions. cyclomatic complexity: 38707 Second operand has 5 states, 5 states have (on average 26.6) internal successors, (133), 5 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:17:22,267 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:17:22,267 INFO L93 Difference]: Finished difference Result 350073 states and 481960 transitions. [2021-12-06 17:17:22,267 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-06 17:17:22,268 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 350073 states and 481960 transitions. [2021-12-06 17:17:23,366 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 349184 [2021-12-06 17:17:24,168 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 350073 states to 350073 states and 481960 transitions. [2021-12-06 17:17:24,168 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 350073 [2021-12-06 17:17:24,314 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 350073 [2021-12-06 17:17:24,314 INFO L73 IsDeterministic]: Start isDeterministic. Operand 350073 states and 481960 transitions. [2021-12-06 17:17:24,433 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:17:24,433 INFO L681 BuchiCegarLoop]: Abstraction has 350073 states and 481960 transitions. [2021-12-06 17:17:24,589 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 350073 states and 481960 transitions. [2021-12-06 17:17:25,935 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 350073 to 98233. [2021-12-06 17:17:25,998 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 98233 states, 98233 states have (on average 1.3939918357374812) internal successors, (136936), 98232 states have internal predecessors, (136936), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:17:26,181 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98233 states to 98233 states and 136936 transitions. [2021-12-06 17:17:26,182 INFO L704 BuchiCegarLoop]: Abstraction has 98233 states and 136936 transitions. [2021-12-06 17:17:26,182 INFO L587 BuchiCegarLoop]: Abstraction has 98233 states and 136936 transitions. [2021-12-06 17:17:26,182 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-12-06 17:17:26,182 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 98233 states and 136936 transitions. [2021-12-06 17:17:26,460 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 97920 [2021-12-06 17:17:26,460 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:17:26,460 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:17:26,465 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:17:26,465 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:17:26,465 INFO L791 eck$LassoCheckResult]: Stem: 2856546#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 2856547#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 2856489#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2856490#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2856763#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 2856357#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2856358#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2856728#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2856157#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2856158#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2856637#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2856638#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2855646#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2855647#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2855845#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2856252#L939 assume !(0 == ~M_E~0); 2856523#L939-2 assume !(0 == ~T1_E~0); 2856524#L944-1 assume !(0 == ~T2_E~0); 2856283#L949-1 assume !(0 == ~T3_E~0); 2856279#L954-1 assume !(0 == ~T4_E~0); 2856280#L959-1 assume !(0 == ~T5_E~0); 2856787#L964-1 assume !(0 == ~T6_E~0); 2855999#L969-1 assume !(0 == ~T7_E~0); 2856000#L974-1 assume !(0 == ~T8_E~0); 2856712#L979-1 assume !(0 == ~T9_E~0); 2856713#L984-1 assume !(0 == ~E_M~0); 2856170#L989-1 assume !(0 == ~E_1~0); 2856171#L994-1 assume !(0 == ~E_2~0); 2856051#L999-1 assume !(0 == ~E_3~0); 2856052#L1004-1 assume !(0 == ~E_4~0); 2855714#L1009-1 assume !(0 == ~E_5~0); 2855715#L1014-1 assume !(0 == ~E_6~0); 2856047#L1019-1 assume !(0 == ~E_7~0); 2856643#L1024-1 assume !(0 == ~E_8~0); 2855968#L1029-1 assume !(0 == ~E_9~0); 2855969#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2856067#L460 assume !(1 == ~m_pc~0); 2856922#L460-2 is_master_triggered_~__retres1~0#1 := 0; 2856604#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2856605#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2856963#L1167 assume !(0 != activate_threads_~tmp~1#1); 2856267#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2856268#L479 assume !(1 == ~t1_pc~0); 2856435#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2856436#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2856883#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2855983#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 2855984#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2855827#L498 assume !(1 == ~t2_pc~0); 2855828#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2856250#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2856251#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2856681#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 2856595#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2856596#L517 assume !(1 == ~t3_pc~0); 2856986#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2856987#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2856326#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2856016#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 2856017#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2856655#L536 assume !(1 == ~t4_pc~0); 2856316#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2856315#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2856775#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2856308#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 2856309#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2856564#L555 assume !(1 == ~t5_pc~0); 2856565#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2856644#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2855745#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2855746#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 2855850#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2855752#L574 assume !(1 == ~t6_pc~0); 2855753#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2856411#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2855853#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2855854#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 2856677#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2856931#L593 assume !(1 == ~t7_pc~0); 2855988#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2855989#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2856793#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2856993#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 2856893#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2856163#L612 assume !(1 == ~t8_pc~0); 2856164#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2856624#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2856455#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2856456#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 2856415#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2856416#L631 assume !(1 == ~t9_pc~0); 2856488#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2855742#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2855712#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2855713#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 2856253#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2856656#L1047 assume !(1 == ~M_E~0); 2855684#L1047-2 assume !(1 == ~T1_E~0); 2855685#L1052-1 assume !(1 == ~T2_E~0); 2855665#L1057-1 assume !(1 == ~T3_E~0); 2855666#L1062-1 assume !(1 == ~T4_E~0); 2855951#L1067-1 assume !(1 == ~T5_E~0); 2856271#L1072-1 assume !(1 == ~T6_E~0); 2856272#L1077-1 assume !(1 == ~T7_E~0); 2855841#L1082-1 assume !(1 == ~T8_E~0); 2855842#L1087-1 assume !(1 == ~T9_E~0); 2855642#L1092-1 assume !(1 == ~E_M~0); 2855643#L1097-1 assume !(1 == ~E_1~0); 2855667#L1102-1 assume !(1 == ~E_2~0); 2856482#L1107-1 assume !(1 == ~E_3~0); 2856409#L1112-1 assume !(1 == ~E_4~0); 2856410#L1117-1 assume !(1 == ~E_5~0); 2856457#L1122-1 assume !(1 == ~E_6~0); 2856327#L1127-1 assume !(1 == ~E_7~0); 2856070#L1132-1 assume !(1 == ~E_8~0); 2856071#L1137-1 assume !(1 == ~E_9~0); 2855949#L1142-1 assume { :end_inline_reset_delta_events } true; 2855950#L1428-2 [2021-12-06 17:17:26,465 INFO L793 eck$LassoCheckResult]: Loop: 2855950#L1428-2 assume !false; 2930351#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2930010#L914 assume !false; 2930332#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2930330#L716 assume !(0 == ~m_st~0); 2930331#L720 assume !(0 == ~t1_st~0); 2930325#L724 assume !(0 == ~t2_st~0); 2930326#L728 assume !(0 == ~t3_st~0); 2930329#L732 assume !(0 == ~t4_st~0); 2930323#L736 assume !(0 == ~t5_st~0); 2930324#L740 assume !(0 == ~t6_st~0); 2930328#L744 assume !(0 == ~t7_st~0); 2930321#L748 assume !(0 == ~t8_st~0); 2930322#L752 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 2930327#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2930315#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2930316#L783 assume !(0 != eval_~tmp~0#1); 2930593#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2930585#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2930586#L939-3 assume !(0 == ~M_E~0); 2930579#L939-5 assume !(0 == ~T1_E~0); 2930580#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2930572#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2930573#L954-3 assume !(0 == ~T4_E~0); 2930566#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2930567#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2930560#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2930561#L974-3 assume !(0 == ~T8_E~0); 2930555#L979-3 assume !(0 == ~T9_E~0); 2930556#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2930549#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2930550#L994-3 assume !(0 == ~E_2~0); 2930543#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2930544#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2930536#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2930537#L1014-3 assume !(0 == ~E_6~0); 2930530#L1019-3 assume !(0 == ~E_7~0); 2930531#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2930524#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2930525#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2930519#L460-33 assume !(1 == ~m_pc~0); 2930520#L460-35 is_master_triggered_~__retres1~0#1 := 0; 2930513#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2930514#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2930507#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2930508#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2930504#L479-33 assume !(1 == ~t1_pc~0); 2930503#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 2930502#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2930501#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2930500#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 2930499#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2930498#L498-33 assume !(1 == ~t2_pc~0); 2930496#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 2930495#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2930494#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2930493#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 2930492#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2930491#L517-33 assume !(1 == ~t3_pc~0); 2923471#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 2930490#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2930489#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2930488#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2930487#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2930486#L536-33 assume 1 == ~t4_pc~0; 2930484#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2930483#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2930482#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2930481#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2930480#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2930479#L555-33 assume !(1 == ~t5_pc~0); 2930478#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 2930477#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2930476#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2930475#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2930474#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2930473#L574-33 assume !(1 == ~t6_pc~0); 2930472#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 2930470#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2930469#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2930468#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2930467#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2930466#L593-33 assume !(1 == ~t7_pc~0); 2928128#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 2930465#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2930464#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2930463#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2930462#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2930461#L612-33 assume !(1 == ~t8_pc~0); 2930460#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 2930458#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2930457#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2930456#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2930455#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2930454#L631-33 assume !(1 == ~t9_pc~0); 2926565#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 2930453#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2930452#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2930451#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2930450#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2930449#L1047-3 assume !(1 == ~M_E~0); 2927024#L1047-5 assume !(1 == ~T1_E~0); 2930448#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2930447#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2930446#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2930445#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2930444#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2930443#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2930442#L1082-3 assume !(1 == ~T8_E~0); 2930441#L1087-3 assume !(1 == ~T9_E~0); 2930440#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2930439#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2930438#L1102-3 assume !(1 == ~E_2~0); 2930437#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2930436#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2930435#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2930434#L1122-3 assume !(1 == ~E_6~0); 2930433#L1127-3 assume !(1 == ~E_7~0); 2930432#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2930431#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2930430#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2930428#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2930417#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2930415#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2930377#L1447 assume !(0 == start_simulation_~tmp~3#1); 2930371#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2930369#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2930360#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2930358#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 2930356#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2930354#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2930353#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 2930352#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 2855950#L1428-2 [2021-12-06 17:17:26,466 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:17:26,466 INFO L85 PathProgramCache]: Analyzing trace with hash 1896389061, now seen corresponding path program 3 times [2021-12-06 17:17:26,466 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:17:26,466 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [748485338] [2021-12-06 17:17:26,466 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:17:26,466 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:17:26,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:17:26,475 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:17:26,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:17:26,658 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:17:26,659 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:17:26,659 INFO L85 PathProgramCache]: Analyzing trace with hash -612655254, now seen corresponding path program 1 times [2021-12-06 17:17:26,659 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:17:26,659 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1936417698] [2021-12-06 17:17:26,659 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:17:26,659 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:17:26,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:17:26,715 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:17:26,715 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:17:26,715 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1936417698] [2021-12-06 17:17:26,715 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1936417698] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:17:26,715 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:17:26,716 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 17:17:26,716 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1553456669] [2021-12-06 17:17:26,716 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:17:26,716 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:17:26,716 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:17:26,717 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-06 17:17:26,717 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-06 17:17:26,717 INFO L87 Difference]: Start difference. First operand 98233 states and 136936 transitions. cyclomatic complexity: 38707 Second operand has 5 states, 5 states have (on average 26.6) internal successors, (133), 5 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:17:27,279 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:17:27,279 INFO L93 Difference]: Finished difference Result 196441 states and 272423 transitions. [2021-12-06 17:17:27,280 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-06 17:17:27,280 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 196441 states and 272423 transitions. [2021-12-06 17:17:28,091 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 196000 [2021-12-06 17:17:28,395 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 196441 states to 196441 states and 272423 transitions. [2021-12-06 17:17:28,396 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 196441 [2021-12-06 17:17:28,461 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 196441 [2021-12-06 17:17:28,461 INFO L73 IsDeterministic]: Start isDeterministic. Operand 196441 states and 272423 transitions. [2021-12-06 17:17:28,520 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:17:28,521 INFO L681 BuchiCegarLoop]: Abstraction has 196441 states and 272423 transitions. [2021-12-06 17:17:28,591 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 196441 states and 272423 transitions. [2021-12-06 17:17:29,422 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 196441 to 99961. [2021-12-06 17:17:29,484 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99961 states, 99961 states have (on average 1.3820489991096527) internal successors, (138151), 99960 states have internal predecessors, (138151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:17:29,671 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99961 states to 99961 states and 138151 transitions. [2021-12-06 17:17:29,671 INFO L704 BuchiCegarLoop]: Abstraction has 99961 states and 138151 transitions. [2021-12-06 17:17:29,671 INFO L587 BuchiCegarLoop]: Abstraction has 99961 states and 138151 transitions. [2021-12-06 17:17:29,671 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-12-06 17:17:29,672 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99961 states and 138151 transitions. [2021-12-06 17:17:29,938 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 99648 [2021-12-06 17:17:29,938 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:17:29,938 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:17:29,942 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:17:29,942 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:17:29,943 INFO L791 eck$LassoCheckResult]: Stem: 3151247#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 3151248#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 3151190#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3151191#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3151478#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 3151055#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3151056#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3151446#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3150846#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3150847#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3151342#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3151343#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3150333#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3150334#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3150532#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3150948#L939 assume !(0 == ~M_E~0); 3151226#L939-2 assume !(0 == ~T1_E~0); 3151227#L944-1 assume !(0 == ~T2_E~0); 3150982#L949-1 assume !(0 == ~T3_E~0); 3150978#L954-1 assume !(0 == ~T4_E~0); 3150979#L959-1 assume !(0 == ~T5_E~0); 3151506#L964-1 assume !(0 == ~T6_E~0); 3150690#L969-1 assume !(0 == ~T7_E~0); 3150691#L974-1 assume !(0 == ~T8_E~0); 3151427#L979-1 assume !(0 == ~T9_E~0); 3151428#L984-1 assume !(0 == ~E_M~0); 3150859#L989-1 assume !(0 == ~E_1~0); 3150860#L994-1 assume !(0 == ~E_2~0); 3150741#L999-1 assume !(0 == ~E_3~0); 3150742#L1004-1 assume !(0 == ~E_4~0); 3150401#L1009-1 assume !(0 == ~E_5~0); 3150402#L1014-1 assume !(0 == ~E_6~0); 3150735#L1019-1 assume !(0 == ~E_7~0); 3151352#L1024-1 assume !(0 == ~E_8~0); 3150658#L1029-1 assume !(0 == ~E_9~0); 3150659#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3150756#L460 assume !(1 == ~m_pc~0); 3151642#L460-2 is_master_triggered_~__retres1~0#1 := 0; 3151308#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3151309#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3151683#L1167 assume !(0 != activate_threads_~tmp~1#1); 3150966#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3150967#L479 assume !(1 == ~t1_pc~0); 3151134#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3151135#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3151598#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3150670#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 3150671#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3150514#L498 assume !(1 == ~t2_pc~0); 3150515#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3150946#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3150947#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3151392#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 3151296#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3151297#L517 assume !(1 == ~t3_pc~0); 3151701#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3151702#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3151024#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3150706#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 3150707#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3151363#L536 assume !(1 == ~t4_pc~0); 3151014#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3151013#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3151493#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3151006#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 3151007#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3151261#L555 assume !(1 == ~t5_pc~0); 3151262#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3151353#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3150430#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3150431#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 3150537#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3150438#L574 assume !(1 == ~t6_pc~0); 3150439#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3151113#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3150542#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3150543#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 3151385#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3151651#L593 assume !(1 == ~t7_pc~0); 3150678#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3150679#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3151511#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3151706#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 3151605#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3150854#L612 assume !(1 == ~t8_pc~0); 3150855#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3151330#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3151153#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3151154#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 3151115#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3151116#L631 assume !(1 == ~t9_pc~0); 3151189#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3150429#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3150399#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3150400#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 3150949#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3151366#L1047 assume !(1 == ~M_E~0); 3150369#L1047-2 assume !(1 == ~T1_E~0); 3150370#L1052-1 assume !(1 == ~T2_E~0); 3150352#L1057-1 assume !(1 == ~T3_E~0); 3150353#L1062-1 assume !(1 == ~T4_E~0); 3150641#L1067-1 assume !(1 == ~T5_E~0); 3150970#L1072-1 assume !(1 == ~T6_E~0); 3150971#L1077-1 assume !(1 == ~T7_E~0); 3150528#L1082-1 assume !(1 == ~T8_E~0); 3150529#L1087-1 assume !(1 == ~T9_E~0); 3150325#L1092-1 assume !(1 == ~E_M~0); 3150326#L1097-1 assume !(1 == ~E_1~0); 3150354#L1102-1 assume !(1 == ~E_2~0); 3151184#L1107-1 assume !(1 == ~E_3~0); 3151111#L1112-1 assume !(1 == ~E_4~0); 3151112#L1117-1 assume !(1 == ~E_5~0); 3151155#L1122-1 assume !(1 == ~E_6~0); 3151025#L1127-1 assume !(1 == ~E_7~0); 3150759#L1132-1 assume !(1 == ~E_8~0); 3150760#L1137-1 assume !(1 == ~E_9~0); 3150639#L1142-1 assume { :end_inline_reset_delta_events } true; 3150640#L1428-2 [2021-12-06 17:17:29,943 INFO L793 eck$LassoCheckResult]: Loop: 3150640#L1428-2 assume !false; 3187785#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3174901#L914 assume !false; 3187784#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3181991#L716 assume !(0 == ~m_st~0); 3181992#L720 assume !(0 == ~t1_st~0); 3181986#L724 assume !(0 == ~t2_st~0); 3181987#L728 assume !(0 == ~t3_st~0); 3181990#L732 assume !(0 == ~t4_st~0); 3181984#L736 assume !(0 == ~t5_st~0); 3181985#L740 assume !(0 == ~t6_st~0); 3181989#L744 assume !(0 == ~t7_st~0); 3181982#L748 assume !(0 == ~t8_st~0); 3181983#L752 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 3181988#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3181975#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3181976#L783 assume !(0 != eval_~tmp~0#1); 3197815#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3197813#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3197811#L939-3 assume !(0 == ~M_E~0); 3197809#L939-5 assume !(0 == ~T1_E~0); 3197807#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3197805#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3197803#L954-3 assume !(0 == ~T4_E~0); 3197801#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3197799#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3197797#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3197795#L974-3 assume !(0 == ~T8_E~0); 3197793#L979-3 assume !(0 == ~T9_E~0); 3197791#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3197789#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3197787#L994-3 assume !(0 == ~E_2~0); 3197785#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3197783#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3197781#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3197779#L1014-3 assume !(0 == ~E_6~0); 3197777#L1019-3 assume !(0 == ~E_7~0); 3197775#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3197773#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3197771#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3197769#L460-33 assume !(1 == ~m_pc~0); 3197767#L460-35 is_master_triggered_~__retres1~0#1 := 0; 3197765#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3197763#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3197761#L1167-33 assume !(0 != activate_threads_~tmp~1#1); 3197759#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3197757#L479-33 assume !(1 == ~t1_pc~0); 3186080#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 3197755#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3197753#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3197751#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 3197749#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3197747#L498-33 assume !(1 == ~t2_pc~0); 3197743#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 3197741#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3197739#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3197737#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 3197735#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3188006#L517-33 assume !(1 == ~t3_pc~0); 3188005#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 3188004#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3188003#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3188002#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3188001#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3188000#L536-33 assume 1 == ~t4_pc~0; 3187998#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3187997#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3187996#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3187995#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3187994#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3187993#L555-33 assume !(1 == ~t5_pc~0); 3187992#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 3187991#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3187990#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3187989#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3187988#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3187987#L574-33 assume 1 == ~t6_pc~0; 3187985#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3187984#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3187983#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3187982#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3187981#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3187980#L593-33 assume !(1 == ~t7_pc~0); 3185812#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 3187979#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3187977#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3187976#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3187975#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3187974#L612-33 assume 1 == ~t8_pc~0; 3187972#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3187971#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3187970#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3187969#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3187968#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3187967#L631-33 assume !(1 == ~t9_pc~0); 3171464#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 3187966#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3187965#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3187964#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3187963#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3187879#L1047-3 assume !(1 == ~M_E~0); 3187877#L1047-5 assume !(1 == ~T1_E~0); 3187876#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3187874#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3187872#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3187870#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3187868#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3187865#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3187863#L1082-3 assume !(1 == ~T8_E~0); 3187861#L1087-3 assume !(1 == ~T9_E~0); 3187859#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3187857#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3187855#L1102-3 assume !(1 == ~E_2~0); 3187853#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3187851#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3187849#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3187847#L1122-3 assume !(1 == ~E_6~0); 3187845#L1127-3 assume !(1 == ~E_7~0); 3187843#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3187841#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3187839#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3187833#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 3187823#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3187821#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 3187819#L1447 assume !(0 == start_simulation_~tmp~3#1); 3187817#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3187809#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 3187799#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3187797#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 3187795#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3187792#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3187790#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 3187788#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 3150640#L1428-2 [2021-12-06 17:17:29,943 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:17:29,943 INFO L85 PathProgramCache]: Analyzing trace with hash 1896389061, now seen corresponding path program 4 times [2021-12-06 17:17:29,943 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:17:29,943 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2100341963] [2021-12-06 17:17:29,944 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:17:29,944 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:17:29,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:17:29,954 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:17:29,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:17:29,982 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:17:29,983 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:17:29,983 INFO L85 PathProgramCache]: Analyzing trace with hash -750178454, now seen corresponding path program 1 times [2021-12-06 17:17:29,983 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:17:29,983 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2081758759] [2021-12-06 17:17:29,983 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:17:29,983 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:17:29,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:17:30,001 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:17:30,002 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:17:30,002 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2081758759] [2021-12-06 17:17:30,002 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2081758759] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:17:30,002 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:17:30,002 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:17:30,002 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1878959285] [2021-12-06 17:17:30,002 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:17:30,002 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:17:30,002 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:17:30,003 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:17:30,003 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:17:30,003 INFO L87 Difference]: Start difference. First operand 99961 states and 138151 transitions. cyclomatic complexity: 38194 Second operand has 3 states, 3 states have (on average 44.333333333333336) internal successors, (133), 3 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:17:30,625 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:17:30,625 INFO L93 Difference]: Finished difference Result 186990 states and 256344 transitions. [2021-12-06 17:17:30,625 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:17:30,626 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 186990 states and 256344 transitions. [2021-12-06 17:17:31,309 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 186400 [2021-12-06 17:17:31,668 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 186990 states to 186990 states and 256344 transitions. [2021-12-06 17:17:31,668 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 186990 [2021-12-06 17:17:31,738 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 186990 [2021-12-06 17:17:31,738 INFO L73 IsDeterministic]: Start isDeterministic. Operand 186990 states and 256344 transitions. [2021-12-06 17:17:31,803 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:17:31,803 INFO L681 BuchiCegarLoop]: Abstraction has 186990 states and 256344 transitions. [2021-12-06 17:17:31,880 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186990 states and 256344 transitions. [2021-12-06 17:17:33,082 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186990 to 186926. [2021-12-06 17:17:33,172 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 186926 states, 186926 states have (on average 1.3710238276109263) internal successors, (256280), 186925 states have internal predecessors, (256280), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:17:33,484 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186926 states to 186926 states and 256280 transitions. [2021-12-06 17:17:33,484 INFO L704 BuchiCegarLoop]: Abstraction has 186926 states and 256280 transitions. [2021-12-06 17:17:33,484 INFO L587 BuchiCegarLoop]: Abstraction has 186926 states and 256280 transitions. [2021-12-06 17:17:33,484 INFO L425 BuchiCegarLoop]: ======== Iteration 29============ [2021-12-06 17:17:33,484 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 186926 states and 256280 transitions. [2021-12-06 17:17:33,957 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 186336 [2021-12-06 17:17:33,958 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:17:33,958 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:17:33,964 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:17:33,964 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:17:33,964 INFO L791 eck$LassoCheckResult]: Stem: 3438204#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 3438205#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 3438139#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3438140#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3438433#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 3438007#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3438008#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3438400#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3437800#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3437801#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3438297#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3438298#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3437290#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3437291#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3437489#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3437898#L939 assume !(0 == ~M_E~0); 3438177#L939-2 assume !(0 == ~T1_E~0); 3438178#L944-1 assume !(0 == ~T2_E~0); 3437931#L949-1 assume !(0 == ~T3_E~0); 3437927#L954-1 assume !(0 == ~T4_E~0); 3437928#L959-1 assume !(0 == ~T5_E~0); 3438458#L964-1 assume !(0 == ~T6_E~0); 3437641#L969-1 assume !(0 == ~T7_E~0); 3437642#L974-1 assume !(0 == ~T8_E~0); 3438385#L979-1 assume !(0 == ~T9_E~0); 3438386#L984-1 assume !(0 == ~E_M~0); 3437815#L989-1 assume !(0 == ~E_1~0); 3437816#L994-1 assume !(0 == ~E_2~0); 3437692#L999-1 assume !(0 == ~E_3~0); 3437693#L1004-1 assume !(0 == ~E_4~0); 3437357#L1009-1 assume !(0 == ~E_5~0); 3437358#L1014-1 assume 0 == ~E_6~0;~E_6~0 := 1; 3437687#L1019-1 assume !(0 == ~E_7~0); 3438307#L1024-1 assume !(0 == ~E_8~0); 3438597#L1029-1 assume !(0 == ~E_9~0); 3437709#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3437710#L460 assume !(1 == ~m_pc~0); 3438606#L460-2 is_master_triggered_~__retres1~0#1 := 0; 3438264#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3438265#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3438779#L1167 assume !(0 != activate_threads_~tmp~1#1); 3437915#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3437916#L479 assume !(1 == ~t1_pc~0); 3438079#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3438080#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3438776#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3438775#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 3438774#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3438773#L498 assume !(1 == ~t2_pc~0); 3438320#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3438321#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3438771#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3438352#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 3438353#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3438699#L517 assume !(1 == ~t3_pc~0); 3438700#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3438673#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3437977#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3437657#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 3437658#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3438768#L536 assume !(1 == ~t4_pc~0); 3438767#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3438765#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3438688#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3437956#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 3437957#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3438220#L555 assume !(1 == ~t5_pc~0); 3438221#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3438763#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3438762#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3438761#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 3438760#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3438759#L574 assume !(1 == ~t6_pc~0); 3438758#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3438058#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3437497#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3437498#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 3438348#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3438755#L593 assume !(1 == ~t7_pc~0); 3438754#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3438753#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3438684#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3438685#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 3438752#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3437808#L612 assume !(1 == ~t8_pc~0); 3437809#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3438285#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3438107#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3438108#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 3438062#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3438063#L631 assume !(1 == ~t9_pc~0); 3438138#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3437385#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3437355#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3437356#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 3437899#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3438740#L1047 assume !(1 == ~M_E~0); 3438739#L1047-2 assume !(1 == ~T1_E~0); 3438738#L1052-1 assume !(1 == ~T2_E~0); 3438737#L1057-1 assume !(1 == ~T3_E~0); 3438736#L1062-1 assume !(1 == ~T4_E~0); 3438735#L1067-1 assume !(1 == ~T5_E~0); 3438734#L1072-1 assume !(1 == ~T6_E~0); 3438733#L1077-1 assume !(1 == ~T7_E~0); 3438732#L1082-1 assume !(1 == ~T8_E~0); 3438731#L1087-1 assume !(1 == ~T9_E~0); 3438730#L1092-1 assume !(1 == ~E_M~0); 3438729#L1097-1 assume !(1 == ~E_1~0); 3438728#L1102-1 assume !(1 == ~E_2~0); 3438727#L1107-1 assume !(1 == ~E_3~0); 3438726#L1112-1 assume !(1 == ~E_4~0); 3438725#L1117-1 assume !(1 == ~E_5~0); 3438718#L1122-1 assume 1 == ~E_6~0;~E_6~0 := 2; 3437978#L1127-1 assume !(1 == ~E_7~0); 3437713#L1132-1 assume !(1 == ~E_8~0); 3437714#L1137-1 assume !(1 == ~E_9~0); 3437593#L1142-1 assume { :end_inline_reset_delta_events } true; 3437594#L1428-2 [2021-12-06 17:17:33,964 INFO L793 eck$LassoCheckResult]: Loop: 3437594#L1428-2 assume !false; 3508776#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3508772#L914 assume !false; 3508771#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3508769#L716 assume !(0 == ~m_st~0); 3508770#L720 assume !(0 == ~t1_st~0); 3508765#L724 assume !(0 == ~t2_st~0); 3508766#L728 assume !(0 == ~t3_st~0); 3508768#L732 assume !(0 == ~t4_st~0); 3508763#L736 assume !(0 == ~t5_st~0); 3508764#L740 assume !(0 == ~t6_st~0); 3508767#L744 assume !(0 == ~t7_st~0); 3508760#L748 assume !(0 == ~t8_st~0); 3508762#L752 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 3508759#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3508757#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3508758#L783 assume !(0 != eval_~tmp~0#1); 3536648#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3536645#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3536643#L939-3 assume !(0 == ~M_E~0); 3536641#L939-5 assume !(0 == ~T1_E~0); 3536639#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3536637#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3536636#L954-3 assume !(0 == ~T4_E~0); 3536632#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3536630#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3536628#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3536626#L974-3 assume !(0 == ~T8_E~0); 3536623#L979-3 assume !(0 == ~T9_E~0); 3536621#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3536618#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3536617#L994-3 assume !(0 == ~E_2~0); 3536614#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3536612#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3536610#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3536607#L1014-3 assume !(0 == ~E_6~0); 3536608#L1019-3 assume !(0 == ~E_7~0); 3624135#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3623500#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3623499#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3623498#L460-33 assume !(1 == ~m_pc~0); 3623497#L460-35 is_master_triggered_~__retres1~0#1 := 0; 3623496#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3623495#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3623494#L1167-33 assume !(0 != activate_threads_~tmp~1#1); 3438141#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3437644#L479-33 assume !(1 == ~t1_pc~0); 3437645#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 3437613#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3437614#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3438278#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 3438531#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3437652#L498-33 assume !(1 == ~t2_pc~0); 3437399#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 3437400#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3437535#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3437536#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 3437509#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3437510#L517-33 assume !(1 == ~t3_pc~0); 3438634#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 3621384#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3621383#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3621382#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3621381#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3621380#L536-33 assume !(1 == ~t4_pc~0); 3621379#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 3621376#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3621375#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3621374#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3621373#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3621372#L555-33 assume !(1 == ~t5_pc~0); 3621370#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 3536578#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3536566#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3536564#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3536562#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3536558#L574-33 assume !(1 == ~t6_pc~0); 3536560#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 3618478#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3618477#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3618475#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3618473#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3508909#L593-33 assume !(1 == ~t7_pc~0); 3508907#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 3508903#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3508902#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3508900#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3508898#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3508896#L612-33 assume 1 == ~t8_pc~0; 3508893#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3508891#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3508889#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3508888#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3508887#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3508885#L631-33 assume !(1 == ~t9_pc~0); 3508883#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 3508881#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3508879#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3508877#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3508875#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3508873#L1047-3 assume !(1 == ~M_E~0); 3504279#L1047-5 assume !(1 == ~T1_E~0); 3508871#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3508869#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3508867#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3508865#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3508863#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3508861#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3508859#L1082-3 assume !(1 == ~T8_E~0); 3508857#L1087-3 assume !(1 == ~T9_E~0); 3508855#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3508853#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3508851#L1102-3 assume !(1 == ~E_2~0); 3508849#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3508847#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3508845#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3508842#L1122-3 assume !(1 == ~E_6~0); 3508840#L1127-3 assume !(1 == ~E_7~0); 3508838#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3508836#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3508834#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3508826#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 3508816#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3508814#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 3508812#L1447 assume !(0 == start_simulation_~tmp~3#1); 3508809#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3508803#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 3508792#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3508791#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 3508787#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3508784#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3508782#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 3508781#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 3437594#L1428-2 [2021-12-06 17:17:33,965 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:17:33,965 INFO L85 PathProgramCache]: Analyzing trace with hash -441850491, now seen corresponding path program 1 times [2021-12-06 17:17:33,965 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:17:33,965 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1751602551] [2021-12-06 17:17:33,965 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:17:33,965 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:17:33,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:17:33,986 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:17:33,986 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:17:33,987 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1751602551] [2021-12-06 17:17:33,987 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1751602551] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:17:33,987 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:17:33,987 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:17:33,987 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1530276417] [2021-12-06 17:17:33,987 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:17:33,987 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:17:33,987 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:17:33,987 INFO L85 PathProgramCache]: Analyzing trace with hash 627717740, now seen corresponding path program 1 times [2021-12-06 17:17:33,987 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:17:33,988 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1410939622] [2021-12-06 17:17:33,988 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:17:33,988 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:17:33,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:17:34,008 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:17:34,008 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:17:34,008 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1410939622] [2021-12-06 17:17:34,008 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1410939622] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:17:34,009 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:17:34,009 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:17:34,009 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [455008702] [2021-12-06 17:17:34,009 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:17:34,009 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:17:34,009 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:17:34,009 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 17:17:34,009 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 17:17:34,009 INFO L87 Difference]: Start difference. First operand 186926 states and 256280 transitions. cyclomatic complexity: 69358 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:17:34,843 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:17:34,843 INFO L93 Difference]: Finished difference Result 272645 states and 372934 transitions. [2021-12-06 17:17:34,844 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 17:17:34,844 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 272645 states and 372934 transitions. [2021-12-06 17:17:36,060 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 264928 [2021-12-06 17:17:36,666 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 272645 states to 272645 states and 372934 transitions. [2021-12-06 17:17:36,666 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 272645 [2021-12-06 17:17:36,789 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 272645 [2021-12-06 17:17:36,790 INFO L73 IsDeterministic]: Start isDeterministic. Operand 272645 states and 372934 transitions. [2021-12-06 17:17:36,887 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:17:36,887 INFO L681 BuchiCegarLoop]: Abstraction has 272645 states and 372934 transitions. [2021-12-06 17:17:37,008 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 272645 states and 372934 transitions. [2021-12-06 17:17:38,427 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 272645 to 186881. [2021-12-06 17:17:38,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 186881 states, 186881 states have (on average 1.3703693794446734) internal successors, (256096), 186880 states have internal predecessors, (256096), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:17:38,790 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186881 states to 186881 states and 256096 transitions. [2021-12-06 17:17:38,790 INFO L704 BuchiCegarLoop]: Abstraction has 186881 states and 256096 transitions. [2021-12-06 17:17:38,790 INFO L587 BuchiCegarLoop]: Abstraction has 186881 states and 256096 transitions. [2021-12-06 17:17:38,790 INFO L425 BuchiCegarLoop]: ======== Iteration 30============ [2021-12-06 17:17:38,790 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 186881 states and 256096 transitions. [2021-12-06 17:17:39,219 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 186336 [2021-12-06 17:17:39,219 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:17:39,220 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:17:39,224 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:17:39,225 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:17:39,225 INFO L791 eck$LassoCheckResult]: Stem: 3897772#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 3897773#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 3897711#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3897712#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3898007#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 3897586#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3897587#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3897976#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3897386#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3897387#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3897873#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3897874#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3896871#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3896872#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3897073#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3897479#L939 assume !(0 == ~M_E~0); 3897747#L939-2 assume !(0 == ~T1_E~0); 3897748#L944-1 assume !(0 == ~T2_E~0); 3897512#L949-1 assume !(0 == ~T3_E~0); 3897508#L954-1 assume !(0 == ~T4_E~0); 3897509#L959-1 assume !(0 == ~T5_E~0); 3898027#L964-1 assume !(0 == ~T6_E~0); 3897229#L969-1 assume !(0 == ~T7_E~0); 3897230#L974-1 assume !(0 == ~T8_E~0); 3897961#L979-1 assume !(0 == ~T9_E~0); 3897962#L984-1 assume !(0 == ~E_M~0); 3897399#L989-1 assume !(0 == ~E_1~0); 3897400#L994-1 assume !(0 == ~E_2~0); 3897278#L999-1 assume !(0 == ~E_3~0); 3897279#L1004-1 assume !(0 == ~E_4~0); 3896939#L1009-1 assume !(0 == ~E_5~0); 3896940#L1014-1 assume !(0 == ~E_6~0); 3897274#L1019-1 assume !(0 == ~E_7~0); 3897879#L1024-1 assume !(0 == ~E_8~0); 3897200#L1029-1 assume !(0 == ~E_9~0); 3897201#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3897294#L460 assume !(1 == ~m_pc~0); 3898177#L460-2 is_master_triggered_~__retres1~0#1 := 0; 3897841#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3897842#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3898227#L1167 assume !(0 != activate_threads_~tmp~1#1); 3897496#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3897497#L479 assume !(1 == ~t1_pc~0); 3897659#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3897660#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3898130#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3897214#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 3897215#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3897054#L498 assume !(1 == ~t2_pc~0); 3897055#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3897477#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3897478#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3897924#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 3897830#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3897831#L517 assume !(1 == ~t3_pc~0); 3898253#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3898254#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3897557#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3897245#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 3897246#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3897892#L536 assume !(1 == ~t4_pc~0); 3897545#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3897544#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3898016#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3897537#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 3897538#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3897793#L555 assume !(1 == ~t5_pc~0); 3897794#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3897880#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3896971#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3896972#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 3897080#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3896977#L574 assume !(1 == ~t6_pc~0); 3896978#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3897883#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3897083#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3897084#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 3898274#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3898188#L593 assume !(1 == ~t7_pc~0); 3898189#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3898036#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3898037#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3898265#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 3898141#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3898142#L612 assume !(1 == ~t8_pc~0); 3898331#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3898330#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3898329#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3898328#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 3898327#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3898326#L631 assume !(1 == ~t9_pc~0); 3898325#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3898324#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3896937#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3896938#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 3898246#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3898247#L1047 assume !(1 == ~M_E~0); 3898323#L1047-2 assume !(1 == ~T1_E~0); 3898322#L1052-1 assume !(1 == ~T2_E~0); 3898321#L1057-1 assume !(1 == ~T3_E~0); 3897183#L1062-1 assume !(1 == ~T4_E~0); 3897184#L1067-1 assume !(1 == ~T5_E~0); 3897500#L1072-1 assume !(1 == ~T6_E~0); 3897501#L1077-1 assume !(1 == ~T7_E~0); 3898320#L1082-1 assume !(1 == ~T8_E~0); 3898319#L1087-1 assume !(1 == ~T9_E~0); 3898318#L1092-1 assume !(1 == ~E_M~0); 3896891#L1097-1 assume !(1 == ~E_1~0); 3896892#L1102-1 assume !(1 == ~E_2~0); 3897705#L1107-1 assume !(1 == ~E_3~0); 3897634#L1112-1 assume !(1 == ~E_4~0); 3897635#L1117-1 assume !(1 == ~E_5~0); 3897680#L1122-1 assume !(1 == ~E_6~0); 3897558#L1127-1 assume !(1 == ~E_7~0); 3897297#L1132-1 assume !(1 == ~E_8~0); 3897298#L1137-1 assume !(1 == ~E_9~0); 3897181#L1142-1 assume { :end_inline_reset_delta_events } true; 3897182#L1428-2 [2021-12-06 17:17:39,225 INFO L793 eck$LassoCheckResult]: Loop: 3897182#L1428-2 assume !false; 3982613#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3982610#L914 assume !false; 3982609#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3982607#L716 assume !(0 == ~m_st~0); 3982608#L720 assume !(0 == ~t1_st~0); 3982602#L724 assume !(0 == ~t2_st~0); 3982603#L728 assume !(0 == ~t3_st~0); 3982606#L732 assume !(0 == ~t4_st~0); 3982600#L736 assume !(0 == ~t5_st~0); 3982601#L740 assume !(0 == ~t6_st~0); 3982605#L744 assume !(0 == ~t7_st~0); 3982598#L748 assume !(0 == ~t8_st~0); 3982599#L752 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 3982604#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3982589#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3982590#L783 assume !(0 != eval_~tmp~0#1); 3984496#L929 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3984276#L651-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3984277#L939-3 assume !(0 == ~M_E~0); 3984268#L939-5 assume !(0 == ~T1_E~0); 3984269#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3984260#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3984261#L954-3 assume !(0 == ~T4_E~0); 3984252#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3984253#L964-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3984244#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3984245#L974-3 assume !(0 == ~T8_E~0); 3984236#L979-3 assume !(0 == ~T9_E~0); 3984237#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3984228#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3984229#L994-3 assume !(0 == ~E_2~0); 3984220#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3984221#L1004-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3984212#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3984213#L1014-3 assume !(0 == ~E_6~0); 3984204#L1019-3 assume !(0 == ~E_7~0); 3984205#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3984196#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3984197#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3984188#L460-33 assume !(1 == ~m_pc~0); 3984189#L460-35 is_master_triggered_~__retres1~0#1 := 0; 3984180#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3984181#L472-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3984172#L1167-33 assume !(0 != activate_threads_~tmp~1#1); 3984173#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3984095#L479-33 assume !(1 == ~t1_pc~0); 3984089#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 3984083#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3984078#L491-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3984073#L1175-33 assume !(0 != activate_threads_~tmp___0~0#1); 3984068#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3984063#L498-33 assume !(1 == ~t2_pc~0); 3984057#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 3984052#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3984047#L510-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3984043#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 3984039#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3984035#L517-33 assume !(1 == ~t3_pc~0); 3977098#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 3984023#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3984019#L529-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3984014#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3984009#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3984003#L536-33 assume 1 == ~t4_pc~0; 3983997#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3983991#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3983986#L548-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3983981#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3983977#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3983973#L555-33 assume !(1 == ~t5_pc~0); 3983966#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 3983959#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3983953#L567-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3983947#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3983941#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3983926#L574-33 assume 1 == ~t6_pc~0; 3983925#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3983543#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3983542#L586-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3983541#L1215-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3983539#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3964892#L593-33 assume !(1 == ~t7_pc~0); 3964890#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 3964888#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3964886#L605-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3964884#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3964882#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3964880#L612-33 assume !(1 == ~t8_pc~0); 3964876#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 3964873#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3964871#L624-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3964869#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3964867#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3964865#L631-33 assume !(1 == ~t9_pc~0); 3945667#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 3964863#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3964861#L643-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3964859#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3964857#L1239-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3964855#L1047-3 assume !(1 == ~M_E~0); 3944524#L1047-5 assume !(1 == ~T1_E~0); 3964851#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3964849#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3964847#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3964845#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3964843#L1072-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3964840#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3964839#L1082-3 assume !(1 == ~T8_E~0); 3964836#L1087-3 assume !(1 == ~T9_E~0); 3964834#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3964832#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3964830#L1102-3 assume !(1 == ~E_2~0); 3964828#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3964827#L1112-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3964826#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3964287#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3964284#L1127-3 assume !(1 == ~E_7~0); 3964270#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3964259#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3964250#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3962696#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 3962682#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3962665#L769-1 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 3962104#L1447 assume !(0 == start_simulation_~tmp~3#1); 3962105#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3982638#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 3982628#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3982625#L769-2 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 3982622#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3982619#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3982617#L1410 start_simulation_#t~ret28#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 3982616#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 3897182#L1428-2 [2021-12-06 17:17:39,225 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:17:39,225 INFO L85 PathProgramCache]: Analyzing trace with hash 1896389061, now seen corresponding path program 5 times [2021-12-06 17:17:39,226 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:17:39,226 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [175355103] [2021-12-06 17:17:39,226 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:17:39,226 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:17:39,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:17:39,233 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:17:39,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:17:39,258 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:17:39,258 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:17:39,258 INFO L85 PathProgramCache]: Analyzing trace with hash -35308247, now seen corresponding path program 1 times [2021-12-06 17:17:39,258 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:17:39,258 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1438608579] [2021-12-06 17:17:39,258 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:17:39,258 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:17:39,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:17:39,276 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:17:39,277 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:17:39,277 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1438608579] [2021-12-06 17:17:39,277 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1438608579] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:17:39,277 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:17:39,277 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:17:39,277 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2071652786] [2021-12-06 17:17:39,277 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:17:39,278 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:17:39,278 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:17:39,278 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:17:39,278 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:17:39,278 INFO L87 Difference]: Start difference. First operand 186881 states and 256096 transitions. cyclomatic complexity: 69219 Second operand has 3 states, 3 states have (on average 44.333333333333336) internal successors, (133), 3 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:17:40,164 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:17:40,164 INFO L93 Difference]: Finished difference Result 309283 states and 419930 transitions. [2021-12-06 17:17:40,164 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:17:40,165 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 309283 states and 419930 transitions. [2021-12-06 17:17:41,381 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 308608 [2021-12-06 17:17:41,987 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 309283 states to 309283 states and 419930 transitions. [2021-12-06 17:17:41,987 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 309283 [2021-12-06 17:17:42,113 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 309283 [2021-12-06 17:17:42,113 INFO L73 IsDeterministic]: Start isDeterministic. Operand 309283 states and 419930 transitions. [2021-12-06 17:17:42,224 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:17:42,224 INFO L681 BuchiCegarLoop]: Abstraction has 309283 states and 419930 transitions. [2021-12-06 17:17:42,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 309283 states and 419930 transitions. [2021-12-06 17:17:44,088 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 309283 to 301283. [2021-12-06 17:17:44,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 301283 states, 301283 states have (on average 1.3591805710909677) internal successors, (409498), 301282 states have internal predecessors, (409498), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:17:45,048 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 301283 states to 301283 states and 409498 transitions. [2021-12-06 17:17:45,048 INFO L704 BuchiCegarLoop]: Abstraction has 301283 states and 409498 transitions. [2021-12-06 17:17:45,048 INFO L587 BuchiCegarLoop]: Abstraction has 301283 states and 409498 transitions. [2021-12-06 17:17:45,048 INFO L425 BuchiCegarLoop]: ======== Iteration 31============ [2021-12-06 17:17:45,048 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 301283 states and 409498 transitions. [2021-12-06 17:17:45,699 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 300608 [2021-12-06 17:17:45,699 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:17:45,699 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:17:45,700 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:17:45,700 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:17:45,700 INFO L791 eck$LassoCheckResult]: Stem: 4393966#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 4393967#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 4393908#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4393909#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4394198#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 4393774#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4393775#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4394167#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4393565#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4393566#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4394064#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4394065#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4393041#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4393042#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4393244#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4393663#L939 assume !(0 == ~M_E~0); 4393941#L939-2 assume !(0 == ~T1_E~0); 4393942#L944-1 assume !(0 == ~T2_E~0); 4393697#L949-1 assume !(0 == ~T3_E~0); 4393695#L954-1 assume !(0 == ~T4_E~0); 4393696#L959-1 assume !(0 == ~T5_E~0); 4394223#L964-1 assume !(0 == ~T6_E~0); 4393399#L969-1 assume !(0 == ~T7_E~0); 4393400#L974-1 assume !(0 == ~T8_E~0); 4394152#L979-1 assume !(0 == ~T9_E~0); 4394153#L984-1 assume !(0 == ~E_M~0); 4393579#L989-1 assume !(0 == ~E_1~0); 4393580#L994-1 assume !(0 == ~E_2~0); 4393452#L999-1 assume !(0 == ~E_3~0); 4393453#L1004-1 assume !(0 == ~E_4~0); 4393107#L1009-1 assume !(0 == ~E_5~0); 4393108#L1014-1 assume !(0 == ~E_6~0); 4393448#L1019-1 assume !(0 == ~E_7~0); 4394072#L1024-1 assume !(0 == ~E_8~0); 4393368#L1029-1 assume !(0 == ~E_9~0); 4393369#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4393469#L460 assume !(1 == ~m_pc~0); 4394374#L460-2 is_master_triggered_~__retres1~0#1 := 0; 4394029#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4394030#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4394422#L1167 assume !(0 != activate_threads_~tmp~1#1); 4393684#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4393685#L479 assume !(1 == ~t1_pc~0); 4393853#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4393854#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4394328#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4393383#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 4393384#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4393226#L498 assume !(1 == ~t2_pc~0); 4393227#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4393661#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4393662#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4394115#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 4394018#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4394019#L517 assume !(1 == ~t3_pc~0); 4394447#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4394448#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4393743#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4393415#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 4393416#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4394084#L536 assume !(1 == ~t4_pc~0); 4393733#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4393732#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4394210#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4393725#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 4393726#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4393987#L555 assume !(1 == ~t5_pc~0); 4393988#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4394071#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4393140#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4393141#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 4393249#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4393146#L574 assume !(1 == ~t6_pc~0); 4393147#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4394075#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4394469#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4394110#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 4394111#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4394533#L593 assume !(1 == ~t7_pc~0); 4393388#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4393389#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4394229#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4394453#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 4394336#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4394337#L612 assume !(1 == ~t8_pc~0); 4394529#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4394528#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4394527#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4394526#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 4394525#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4394524#L631 assume !(1 == ~t9_pc~0); 4394523#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4394522#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4393105#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4393106#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 4394439#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4394440#L1047 assume !(1 == ~M_E~0); 4394521#L1047-2 assume !(1 == ~T1_E~0); 4394520#L1052-1 assume !(1 == ~T2_E~0); 4394519#L1057-1 assume !(1 == ~T3_E~0); 4393351#L1062-1 assume !(1 == ~T4_E~0); 4393352#L1067-1 assume !(1 == ~T5_E~0); 4393688#L1072-1 assume !(1 == ~T6_E~0); 4393689#L1077-1 assume !(1 == ~T7_E~0); 4394516#L1082-1 assume !(1 == ~T8_E~0); 4394515#L1087-1 assume !(1 == ~T9_E~0); 4394514#L1092-1 assume !(1 == ~E_M~0); 4394513#L1097-1 assume !(1 == ~E_1~0); 4394512#L1102-1 assume !(1 == ~E_2~0); 4394511#L1107-1 assume !(1 == ~E_3~0); 4394510#L1112-1 assume !(1 == ~E_4~0); 4394509#L1117-1 assume !(1 == ~E_5~0); 4394508#L1122-1 assume !(1 == ~E_6~0); 4393744#L1127-1 assume !(1 == ~E_7~0); 4393472#L1132-1 assume !(1 == ~E_8~0); 4393473#L1137-1 assume !(1 == ~E_9~0); 4393349#L1142-1 assume { :end_inline_reset_delta_events } true; 4393350#L1428-2 assume !false; 4457346#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4457341#L914 [2021-12-06 17:17:45,700 INFO L793 eck$LassoCheckResult]: Loop: 4457341#L914 assume !false; 4457339#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 4457336#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4457335#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4457333#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4457331#L783 assume 0 != eval_~tmp~0#1; 4457329#L783-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 4457326#L791 assume !(0 != eval_~tmp_ndt_1~0#1); 4457325#L788 assume !(0 == ~t1_st~0); 4457324#L802 assume !(0 == ~t2_st~0); 4457660#L816 assume !(0 == ~t3_st~0); 4457656#L830 assume !(0 == ~t4_st~0); 4457651#L844 assume !(0 == ~t5_st~0); 4457458#L858 assume !(0 == ~t6_st~0); 4457453#L872 assume !(0 == ~t7_st~0); 4457351#L886 assume !(0 == ~t8_st~0); 4457345#L900 assume !(0 == ~t9_st~0); 4457341#L914 [2021-12-06 17:17:45,700 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:17:45,700 INFO L85 PathProgramCache]: Analyzing trace with hash 1363771783, now seen corresponding path program 1 times [2021-12-06 17:17:45,700 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:17:45,700 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [587933234] [2021-12-06 17:17:45,701 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:17:45,701 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:17:45,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:17:45,707 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:17:45,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:17:45,728 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:17:45,728 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:17:45,728 INFO L85 PathProgramCache]: Analyzing trace with hash 1724838997, now seen corresponding path program 1 times [2021-12-06 17:17:45,729 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:17:45,729 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1594546103] [2021-12-06 17:17:45,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:17:45,729 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:17:45,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:17:45,731 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:17:45,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:17:45,733 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:17:45,733 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:17:45,734 INFO L85 PathProgramCache]: Analyzing trace with hash 401862543, now seen corresponding path program 1 times [2021-12-06 17:17:45,734 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:17:45,734 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [132573869] [2021-12-06 17:17:45,734 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:17:45,734 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:17:45,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:17:45,753 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:17:45,753 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:17:45,753 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [132573869] [2021-12-06 17:17:45,754 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [132573869] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:17:45,754 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:17:45,754 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:17:45,754 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1685591500] [2021-12-06 17:17:45,754 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:17:45,824 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:17:45,825 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:17:45,825 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:17:45,825 INFO L87 Difference]: Start difference. First operand 301283 states and 409498 transitions. cyclomatic complexity: 108222 Second operand has 3 states, 3 states have (on average 45.333333333333336) internal successors, (136), 3 states have internal predecessors, (136), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:17:47,212 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:17:47,212 INFO L93 Difference]: Finished difference Result 582144 states and 786349 transitions. [2021-12-06 17:17:47,212 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:17:47,213 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 582144 states and 786349 transitions. [2021-12-06 17:17:49,680 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 580800 [2021-12-06 17:17:50,651 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 582144 states to 582144 states and 786349 transitions. [2021-12-06 17:17:50,651 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 582144 [2021-12-06 17:17:50,865 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 582144 [2021-12-06 17:17:50,865 INFO L73 IsDeterministic]: Start isDeterministic. Operand 582144 states and 786349 transitions. [2021-12-06 17:17:51,201 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:17:51,201 INFO L681 BuchiCegarLoop]: Abstraction has 582144 states and 786349 transitions. [2021-12-06 17:17:51,380 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 582144 states and 786349 transitions. [2021-12-06 17:17:54,854 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 582144 to 568480. [2021-12-06 17:17:55,139 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 568480 states, 568480 states have (on average 1.3517256543765832) internal successors, (768429), 568479 states have internal predecessors, (768429), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:17:56,523 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 568480 states to 568480 states and 768429 transitions. [2021-12-06 17:17:56,523 INFO L704 BuchiCegarLoop]: Abstraction has 568480 states and 768429 transitions. [2021-12-06 17:17:56,523 INFO L587 BuchiCegarLoop]: Abstraction has 568480 states and 768429 transitions. [2021-12-06 17:17:56,523 INFO L425 BuchiCegarLoop]: ======== Iteration 32============ [2021-12-06 17:17:56,523 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 568480 states and 768429 transitions. [2021-12-06 17:17:58,020 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 567136 [2021-12-06 17:17:58,020 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:17:58,020 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:17:58,021 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:17:58,021 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:17:58,022 INFO L791 eck$LassoCheckResult]: Stem: 5277406#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 5277407#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 5277342#L1391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5277343#L651 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5277631#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 5277206#L658-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 5277207#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5335761#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5335760#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5335759#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5335758#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 5335757#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 5335756#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 5335755#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5335754#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5335753#L939 assume !(0 == ~M_E~0); 5335752#L939-2 assume !(0 == ~T1_E~0); 5335751#L944-1 assume !(0 == ~T2_E~0); 5335750#L949-1 assume !(0 == ~T3_E~0); 5335749#L954-1 assume !(0 == ~T4_E~0); 5335748#L959-1 assume !(0 == ~T5_E~0); 5335747#L964-1 assume !(0 == ~T6_E~0); 5335746#L969-1 assume !(0 == ~T7_E~0); 5335745#L974-1 assume !(0 == ~T8_E~0); 5335744#L979-1 assume !(0 == ~T9_E~0); 5335743#L984-1 assume !(0 == ~E_M~0); 5335742#L989-1 assume !(0 == ~E_1~0); 5335741#L994-1 assume !(0 == ~E_2~0); 5335740#L999-1 assume !(0 == ~E_3~0); 5335739#L1004-1 assume !(0 == ~E_4~0); 5335738#L1009-1 assume !(0 == ~E_5~0); 5335737#L1014-1 assume !(0 == ~E_6~0); 5335736#L1019-1 assume !(0 == ~E_7~0); 5335735#L1024-1 assume !(0 == ~E_8~0); 5335734#L1029-1 assume !(0 == ~E_9~0); 5335733#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5335732#L460 assume !(1 == ~m_pc~0); 5335731#L460-2 is_master_triggered_~__retres1~0#1 := 0; 5335730#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5335729#L472 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5335728#L1167 assume !(0 != activate_threads_~tmp~1#1); 5335727#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5335726#L479 assume !(1 == ~t1_pc~0); 5335725#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5335724#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5335723#L491 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5335722#L1175 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5276819#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5276662#L498 assume !(1 == ~t2_pc~0); 5276663#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5277088#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5277089#L510 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5277559#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 5277463#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5277464#L517 assume !(1 == ~t3_pc~0); 5277902#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5277903#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5277175#L529 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5276852#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 5276853#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5277527#L536 assume !(1 == ~t4_pc~0); 5277162#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5277161#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5277640#L548 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5277154#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 5277155#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5277424#L555 assume !(1 == ~t5_pc~0); 5277425#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5277517#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5276576#L567 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5276577#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 5276685#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5276582#L574 assume !(1 == ~t6_pc~0); 5276583#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5277518#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5276688#L586 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5276689#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 5277927#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5277827#L593 assume !(1 == ~t7_pc~0); 5277828#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5277995#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5277920#L605 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5277921#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 5277994#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5277003#L612 assume !(1 == ~t8_pc~0); 5277004#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5277494#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5277307#L624 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5277308#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 5277262#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5277263#L631 assume !(1 == ~t9_pc~0); 5277341#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 5276572#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5276573#L643 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5277984#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 5277893#L1239-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5277894#L1047 assume !(1 == ~M_E~0); 5277983#L1047-2 assume !(1 == ~T1_E~0); 5277982#L1052-1 assume !(1 == ~T2_E~0); 5277981#L1057-1 assume !(1 == ~T3_E~0); 5276786#L1062-1 assume !(1 == ~T4_E~0); 5276787#L1067-1 assume !(1 == ~T5_E~0); 5277115#L1072-1 assume !(1 == ~T6_E~0); 5277116#L1077-1 assume !(1 == ~T7_E~0); 5277978#L1082-1 assume !(1 == ~T8_E~0); 5277977#L1087-1 assume !(1 == ~T9_E~0); 5277976#L1092-1 assume !(1 == ~E_M~0); 5277975#L1097-1 assume !(1 == ~E_1~0); 5277974#L1102-1 assume !(1 == ~E_2~0); 5277973#L1107-1 assume !(1 == ~E_3~0); 5277972#L1112-1 assume !(1 == ~E_4~0); 5277971#L1117-1 assume !(1 == ~E_5~0); 5277970#L1122-1 assume !(1 == ~E_6~0); 5277176#L1127-1 assume !(1 == ~E_7~0); 5276904#L1132-1 assume !(1 == ~E_8~0); 5276905#L1137-1 assume !(1 == ~E_9~0); 5276784#L1142-1 assume { :end_inline_reset_delta_events } true; 5276785#L1428-2 assume !false; 5344690#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5344684#L914 [2021-12-06 17:17:58,022 INFO L793 eck$LassoCheckResult]: Loop: 5344684#L914 assume !false; 5344682#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5344679#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 5344677#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 5344676#L769 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5344675#L783 assume 0 != eval_~tmp~0#1; 5344672#L783-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 5344669#L791 assume !(0 != eval_~tmp_ndt_1~0#1); 5344667#L788 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 5334787#L805 assume !(0 != eval_~tmp_ndt_2~0#1); 5334789#L802 assume !(0 == ~t2_st~0); 5344721#L816 assume !(0 == ~t3_st~0); 5344715#L830 assume !(0 == ~t4_st~0); 5344710#L844 assume !(0 == ~t5_st~0); 5344703#L858 assume !(0 == ~t6_st~0); 5344696#L872 assume !(0 == ~t7_st~0); 5344691#L886 assume !(0 == ~t8_st~0); 5344689#L900 assume !(0 == ~t9_st~0); 5344684#L914 [2021-12-06 17:17:58,022 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:17:58,022 INFO L85 PathProgramCache]: Analyzing trace with hash 981733315, now seen corresponding path program 1 times [2021-12-06 17:17:58,022 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:17:58,022 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [42980069] [2021-12-06 17:17:58,022 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:17:58,022 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:17:58,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:17:58,037 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:17:58,038 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:17:58,038 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [42980069] [2021-12-06 17:17:58,038 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [42980069] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:17:58,038 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:17:58,038 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:17:58,038 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [790415905] [2021-12-06 17:17:58,038 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:17:58,038 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:17:58,038 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:17:58,038 INFO L85 PathProgramCache]: Analyzing trace with hash -703348392, now seen corresponding path program 1 times [2021-12-06 17:17:58,039 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:17:58,039 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1906325421] [2021-12-06 17:17:58,039 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:17:58,039 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:17:58,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:17:58,041 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:17:58,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:17:58,044 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:17:58,116 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:17:58,116 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:17:58,116 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:17:58,116 INFO L87 Difference]: Start difference. First operand 568480 states and 768429 transitions. cyclomatic complexity: 199956 Second operand has 3 states, 3 states have (on average 39.666666666666664) internal successors, (119), 3 states have internal predecessors, (119), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:17:59,616 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:17:59,616 INFO L93 Difference]: Finished difference Result 568323 states and 768209 transitions. [2021-12-06 17:17:59,616 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:17:59,616 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 568323 states and 768209 transitions.