./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.13.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 839c364b Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb3ed0ee-f082-4d43-bc7f-66c30df9ade5/bin/uautomizer-DrprNOufMa/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb3ed0ee-f082-4d43-bc7f-66c30df9ade5/bin/uautomizer-DrprNOufMa/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb3ed0ee-f082-4d43-bc7f-66c30df9ade5/bin/uautomizer-DrprNOufMa/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb3ed0ee-f082-4d43-bc7f-66c30df9ade5/bin/uautomizer-DrprNOufMa/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.13.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb3ed0ee-f082-4d43-bc7f-66c30df9ade5/bin/uautomizer-DrprNOufMa/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb3ed0ee-f082-4d43-bc7f-66c30df9ade5/bin/uautomizer-DrprNOufMa --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 1b2c6a3c4af8091017033117c21d8fbc40cee2009788b890a114045d77587077 --- Real Ultimate output --- This is Ultimate 0.2.2-hotfix-svcomp22-839c364 [2021-12-07 00:34:08,554 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-07 00:34:08,556 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-07 00:34:08,587 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-07 00:34:08,588 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-07 00:34:08,589 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-07 00:34:08,591 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-07 00:34:08,593 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-07 00:34:08,595 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-07 00:34:08,596 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-07 00:34:08,597 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-07 00:34:08,599 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-07 00:34:08,599 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-07 00:34:08,600 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-07 00:34:08,602 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-07 00:34:08,604 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-07 00:34:08,605 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-07 00:34:08,606 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-07 00:34:08,608 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-07 00:34:08,610 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-07 00:34:08,612 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-07 00:34:08,613 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-07 00:34:08,614 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-07 00:34:08,615 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-07 00:34:08,618 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-07 00:34:08,618 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-07 00:34:08,618 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-07 00:34:08,619 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-07 00:34:08,620 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-07 00:34:08,621 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-07 00:34:08,621 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-07 00:34:08,621 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-07 00:34:08,622 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-07 00:34:08,623 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-07 00:34:08,624 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-07 00:34:08,624 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-07 00:34:08,624 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-07 00:34:08,625 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-07 00:34:08,625 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-07 00:34:08,626 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-07 00:34:08,626 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-07 00:34:08,627 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb3ed0ee-f082-4d43-bc7f-66c30df9ade5/bin/uautomizer-DrprNOufMa/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-07 00:34:08,646 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-07 00:34:08,646 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-07 00:34:08,646 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-07 00:34:08,647 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-07 00:34:08,647 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-07 00:34:08,648 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-07 00:34:08,648 INFO L138 SettingsManager]: * Use SBE=true [2021-12-07 00:34:08,648 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-07 00:34:08,648 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-07 00:34:08,648 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-07 00:34:08,648 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-07 00:34:08,648 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-07 00:34:08,649 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-07 00:34:08,649 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-07 00:34:08,649 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-07 00:34:08,649 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-07 00:34:08,649 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-07 00:34:08,649 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-07 00:34:08,649 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-07 00:34:08,650 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-07 00:34:08,650 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-07 00:34:08,650 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-07 00:34:08,650 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-07 00:34:08,650 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-07 00:34:08,650 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-07 00:34:08,650 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-07 00:34:08,650 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-07 00:34:08,651 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-07 00:34:08,651 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-07 00:34:08,651 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-07 00:34:08,651 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-07 00:34:08,651 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-07 00:34:08,652 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-07 00:34:08,652 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb3ed0ee-f082-4d43-bc7f-66c30df9ade5/bin/uautomizer-DrprNOufMa/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb3ed0ee-f082-4d43-bc7f-66c30df9ade5/bin/uautomizer-DrprNOufMa Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1b2c6a3c4af8091017033117c21d8fbc40cee2009788b890a114045d77587077 [2021-12-07 00:34:08,846 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-07 00:34:08,863 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-07 00:34:08,865 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-07 00:34:08,866 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-07 00:34:08,866 INFO L275 PluginConnector]: CDTParser initialized [2021-12-07 00:34:08,867 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb3ed0ee-f082-4d43-bc7f-66c30df9ade5/bin/uautomizer-DrprNOufMa/../../sv-benchmarks/c/systemc/token_ring.13.cil-1.c [2021-12-07 00:34:08,906 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb3ed0ee-f082-4d43-bc7f-66c30df9ade5/bin/uautomizer-DrprNOufMa/data/8b52700c0/ee4ed64d5cd443779fb08c7a8f5853b6/FLAG891d0a4cd [2021-12-07 00:34:09,320 INFO L306 CDTParser]: Found 1 translation units. [2021-12-07 00:34:09,321 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb3ed0ee-f082-4d43-bc7f-66c30df9ade5/sv-benchmarks/c/systemc/token_ring.13.cil-1.c [2021-12-07 00:34:09,335 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb3ed0ee-f082-4d43-bc7f-66c30df9ade5/bin/uautomizer-DrprNOufMa/data/8b52700c0/ee4ed64d5cd443779fb08c7a8f5853b6/FLAG891d0a4cd [2021-12-07 00:34:09,344 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb3ed0ee-f082-4d43-bc7f-66c30df9ade5/bin/uautomizer-DrprNOufMa/data/8b52700c0/ee4ed64d5cd443779fb08c7a8f5853b6 [2021-12-07 00:34:09,346 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-07 00:34:09,347 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-07 00:34:09,348 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-07 00:34:09,348 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-07 00:34:09,351 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-07 00:34:09,351 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 12:34:09" (1/1) ... [2021-12-07 00:34:09,352 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7815dc29 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:34:09, skipping insertion in model container [2021-12-07 00:34:09,352 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 12:34:09" (1/1) ... [2021-12-07 00:34:09,357 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-07 00:34:09,396 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-07 00:34:09,506 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb3ed0ee-f082-4d43-bc7f-66c30df9ade5/sv-benchmarks/c/systemc/token_ring.13.cil-1.c[671,684] [2021-12-07 00:34:09,627 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-07 00:34:09,638 INFO L203 MainTranslator]: Completed pre-run [2021-12-07 00:34:09,650 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb3ed0ee-f082-4d43-bc7f-66c30df9ade5/sv-benchmarks/c/systemc/token_ring.13.cil-1.c[671,684] [2021-12-07 00:34:09,708 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-07 00:34:09,729 INFO L208 MainTranslator]: Completed translation [2021-12-07 00:34:09,730 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:34:09 WrapperNode [2021-12-07 00:34:09,730 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-07 00:34:09,731 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-07 00:34:09,731 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-07 00:34:09,731 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-07 00:34:09,738 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:34:09" (1/1) ... [2021-12-07 00:34:09,754 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:34:09" (1/1) ... [2021-12-07 00:34:09,851 INFO L137 Inliner]: procedures = 54, calls = 71, calls flagged for inlining = 66, calls inlined = 303, statements flattened = 4665 [2021-12-07 00:34:09,851 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-07 00:34:09,852 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-07 00:34:09,852 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-07 00:34:09,852 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-07 00:34:09,861 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:34:09" (1/1) ... [2021-12-07 00:34:09,861 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:34:09" (1/1) ... [2021-12-07 00:34:09,872 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:34:09" (1/1) ... [2021-12-07 00:34:09,872 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:34:09" (1/1) ... [2021-12-07 00:34:09,916 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:34:09" (1/1) ... [2021-12-07 00:34:09,947 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:34:09" (1/1) ... [2021-12-07 00:34:09,953 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:34:09" (1/1) ... [2021-12-07 00:34:09,962 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-07 00:34:09,963 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-07 00:34:09,963 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-07 00:34:09,963 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-07 00:34:09,964 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:34:09" (1/1) ... [2021-12-07 00:34:09,970 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-07 00:34:09,980 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb3ed0ee-f082-4d43-bc7f-66c30df9ade5/bin/uautomizer-DrprNOufMa/z3 [2021-12-07 00:34:09,991 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb3ed0ee-f082-4d43-bc7f-66c30df9ade5/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-07 00:34:09,993 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb3ed0ee-f082-4d43-bc7f-66c30df9ade5/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-07 00:34:10,021 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-07 00:34:10,021 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-07 00:34:10,021 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-07 00:34:10,021 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-07 00:34:10,109 INFO L236 CfgBuilder]: Building ICFG [2021-12-07 00:34:10,110 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-07 00:34:11,429 INFO L277 CfgBuilder]: Performing block encoding [2021-12-07 00:34:11,450 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-07 00:34:11,450 INFO L301 CfgBuilder]: Removed 16 assume(true) statements. [2021-12-07 00:34:11,453 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 12:34:11 BoogieIcfgContainer [2021-12-07 00:34:11,453 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-07 00:34:11,454 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-07 00:34:11,454 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-07 00:34:11,457 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-07 00:34:11,457 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-07 00:34:11,457 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 07.12 12:34:09" (1/3) ... [2021-12-07 00:34:11,458 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@10dbf8e7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.12 12:34:11, skipping insertion in model container [2021-12-07 00:34:11,458 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-07 00:34:11,458 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:34:09" (2/3) ... [2021-12-07 00:34:11,458 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@10dbf8e7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.12 12:34:11, skipping insertion in model container [2021-12-07 00:34:11,458 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-07 00:34:11,458 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 12:34:11" (3/3) ... [2021-12-07 00:34:11,459 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.13.cil-1.c [2021-12-07 00:34:11,492 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-07 00:34:11,493 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-07 00:34:11,493 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-07 00:34:11,493 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-07 00:34:11,493 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-07 00:34:11,493 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-07 00:34:11,493 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-07 00:34:11,493 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-07 00:34:11,539 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2031 states, 2030 states have (on average 1.4965517241379311) internal successors, (3038), 2030 states have internal predecessors, (3038), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:11,614 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1852 [2021-12-07 00:34:11,614 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:34:11,614 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:34:11,631 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:11,632 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:11,632 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-07 00:34:11,636 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2031 states, 2030 states have (on average 1.4965517241379311) internal successors, (3038), 2030 states have internal predecessors, (3038), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:11,654 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1852 [2021-12-07 00:34:11,654 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:34:11,654 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:34:11,659 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:11,659 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:11,680 INFO L791 eck$LassoCheckResult]: Stem: 484#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1951#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1565#L1903true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1977#L907true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1850#L914true assume !(1 == ~m_i~0);~m_st~0 := 2; 836#L914-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 443#L919-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1245#L924-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1128#L929-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1855#L934-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1285#L939-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1654#L944-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 313#L949-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 1328#L954-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 1963#L959-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 648#L964-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 1195#L969-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 1764#L974-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 583#L979-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1887#L1291true assume 0 == ~M_E~0;~M_E~0 := 1; 1852#L1291-2true assume !(0 == ~T1_E~0); 1844#L1296-1true assume !(0 == ~T2_E~0); 694#L1301-1true assume !(0 == ~T3_E~0); 1240#L1306-1true assume !(0 == ~T4_E~0); 1212#L1311-1true assume !(0 == ~T5_E~0); 232#L1316-1true assume !(0 == ~T6_E~0); 1658#L1321-1true assume !(0 == ~T7_E~0); 703#L1326-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 142#L1331-1true assume !(0 == ~T9_E~0); 4#L1336-1true assume !(0 == ~T10_E~0); 1090#L1341-1true assume !(0 == ~T11_E~0); 37#L1346-1true assume !(0 == ~T12_E~0); 1453#L1351-1true assume !(0 == ~T13_E~0); 205#L1356-1true assume !(0 == ~E_M~0); 1971#L1361-1true assume !(0 == ~E_1~0); 1631#L1366-1true assume 0 == ~E_2~0;~E_2~0 := 1; 226#L1371-1true assume !(0 == ~E_3~0); 1433#L1376-1true assume !(0 == ~E_4~0); 755#L1381-1true assume !(0 == ~E_5~0); 1725#L1386-1true assume !(0 == ~E_6~0); 1884#L1391-1true assume !(0 == ~E_7~0); 1795#L1396-1true assume !(0 == ~E_8~0); 667#L1401-1true assume !(0 == ~E_9~0); 1302#L1406-1true assume 0 == ~E_10~0;~E_10~0 := 1; 908#L1411-1true assume !(0 == ~E_11~0); 1686#L1416-1true assume !(0 == ~E_12~0); 614#L1421-1true assume !(0 == ~E_13~0); 324#L1426-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 760#L640true assume !(1 == ~m_pc~0); 1799#L640-2true is_master_triggered_~__retres1~0#1 := 0; 719#L651true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1261#L652true activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 638#L1603true assume !(0 != activate_threads_~tmp~1#1); 1286#L1603-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 402#L659true assume 1 == ~t1_pc~0; 461#L660true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1416#L670true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1368#L671true activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 473#L1611true assume !(0 != activate_threads_~tmp___0~0#1); 481#L1611-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1599#L678true assume 1 == ~t2_pc~0; 1454#L679true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1703#L689true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1973#L690true activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 548#L1619true assume !(0 != activate_threads_~tmp___1~0#1); 691#L1619-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 636#L697true assume !(1 == ~t3_pc~0); 737#L697-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1501#L708true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 588#L709true activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 574#L1627true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1914#L1627-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1534#L716true assume 1 == ~t4_pc~0; 1510#L717true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 389#L727true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1556#L728true activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 121#L1635true assume !(0 != activate_threads_~tmp___3~0#1); 984#L1635-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1478#L735true assume !(1 == ~t5_pc~0); 104#L735-2true is_transmit5_triggered_~__retres1~5#1 := 0; 338#L746true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1646#L747true activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1015#L1643true assume !(0 != activate_threads_~tmp___4~0#1); 687#L1643-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 873#L754true assume 1 == ~t6_pc~0; 521#L755true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 452#L765true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1771#L766true activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 436#L1651true assume !(0 != activate_threads_~tmp___5~0#1); 1119#L1651-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1960#L773true assume !(1 == ~t7_pc~0); 897#L773-2true is_transmit7_triggered_~__retres1~7#1 := 0; 721#L784true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1258#L785true activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 695#L1659true assume !(0 != activate_threads_~tmp___6~0#1); 747#L1659-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 882#L792true assume 1 == ~t8_pc~0; 1953#L793true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1288#L803true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 742#L804true activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 689#L1667true assume !(0 != activate_threads_~tmp___7~0#1); 637#L1667-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 802#L811true assume 1 == ~t9_pc~0; 1340#L812true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1697#L822true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1146#L823true activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 799#L1675true assume !(0 != activate_threads_~tmp___8~0#1); 644#L1675-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1728#L830true assume !(1 == ~t10_pc~0); 2019#L830-2true is_transmit10_triggered_~__retres1~10#1 := 0; 196#L841true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45#L842true activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 185#L1683true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1791#L1683-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1140#L849true assume 1 == ~t11_pc~0; 1627#L850true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 91#L860true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 407#L861true activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1160#L1691true assume !(0 != activate_threads_~tmp___10~0#1); 1023#L1691-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1797#L868true assume !(1 == ~t12_pc~0); 1394#L868-2true is_transmit12_triggered_~__retres1~12#1 := 0; 568#L879true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 411#L880true activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1716#L1699true assume !(0 != activate_threads_~tmp___11~0#1); 213#L1699-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1629#L887true assume 1 == ~t13_pc~0; 1037#L888true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 569#L898true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 913#L899true activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1106#L1707true assume !(0 != activate_threads_~tmp___12~0#1); 63#L1707-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1680#L1439true assume !(1 == ~M_E~0); 684#L1439-2true assume !(1 == ~T1_E~0); 149#L1444-1true assume !(1 == ~T2_E~0); 914#L1449-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 404#L1454-1true assume !(1 == ~T4_E~0); 1452#L1459-1true assume !(1 == ~T5_E~0); 796#L1464-1true assume !(1 == ~T6_E~0); 858#L1469-1true assume !(1 == ~T7_E~0); 1706#L1474-1true assume !(1 == ~T8_E~0); 615#L1479-1true assume !(1 == ~T9_E~0); 800#L1484-1true assume !(1 == ~T10_E~0); 1262#L1489-1true assume 1 == ~T11_E~0;~T11_E~0 := 2; 535#L1494-1true assume !(1 == ~T12_E~0); 1835#L1499-1true assume !(1 == ~T13_E~0); 660#L1504-1true assume !(1 == ~E_M~0); 1509#L1509-1true assume !(1 == ~E_1~0); 1259#L1514-1true assume !(1 == ~E_2~0); 883#L1519-1true assume !(1 == ~E_3~0); 1952#L1524-1true assume !(1 == ~E_4~0); 1670#L1529-1true assume 1 == ~E_5~0;~E_5~0 := 2; 1765#L1534-1true assume !(1 == ~E_6~0); 60#L1539-1true assume !(1 == ~E_7~0); 270#L1544-1true assume !(1 == ~E_8~0); 1591#L1549-1true assume !(1 == ~E_9~0); 1614#L1554-1true assume !(1 == ~E_10~0); 1587#L1559-1true assume !(1 == ~E_11~0); 1320#L1564-1true assume !(1 == ~E_12~0); 1655#L1569-1true assume 1 == ~E_13~0;~E_13~0 := 2; 1743#L1574-1true assume { :end_inline_reset_delta_events } true; 148#L1940-2true [2021-12-07 00:34:11,684 INFO L793 eck$LassoCheckResult]: Loop: 148#L1940-2true assume !false; 1557#L1941true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1044#L1266true assume false; 486#L1281true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1604#L907-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 965#L1291-3true assume 0 == ~M_E~0;~M_E~0 := 1; 859#L1291-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1860#L1296-3true assume !(0 == ~T2_E~0); 1768#L1301-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1612#L1306-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 590#L1311-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 169#L1316-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 221#L1321-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 679#L1326-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1575#L1331-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 889#L1336-3true assume !(0 == ~T10_E~0); 1494#L1341-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 400#L1346-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 386#L1351-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 355#L1356-3true assume 0 == ~E_M~0;~E_M~0 := 1; 738#L1361-3true assume 0 == ~E_1~0;~E_1~0 := 1; 769#L1366-3true assume 0 == ~E_2~0;~E_2~0 := 1; 27#L1371-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1296#L1376-3true assume !(0 == ~E_4~0); 1545#L1381-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1092#L1386-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1678#L1391-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1332#L1396-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1975#L1401-3true assume 0 == ~E_9~0;~E_9~0 := 1; 203#L1406-3true assume 0 == ~E_10~0;~E_10~0 := 1; 125#L1411-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1767#L1416-3true assume !(0 == ~E_12~0); 491#L1421-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1127#L1426-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 566#L640-45true assume !(1 == ~m_pc~0); 1945#L640-47true is_master_triggered_~__retres1~0#1 := 0; 250#L651-15true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 523#L652-15true activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24#L1603-45true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1854#L1603-47true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66#L659-45true assume 1 == ~t1_pc~0; 1919#L660-15true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1780#L670-15true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 980#L671-15true activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1552#L1611-45true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 997#L1611-47true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1521#L678-45true assume 1 == ~t2_pc~0; 946#L679-15true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 571#L689-15true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 671#L690-15true activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1360#L1619-45true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1666#L1619-47true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1607#L697-45true assume !(1 == ~t3_pc~0); 1253#L697-47true is_transmit3_triggered_~__retres1~3#1 := 0; 1849#L708-15true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1502#L709-15true activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 898#L1627-45true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 931#L1627-47true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2013#L716-45true assume 1 == ~t4_pc~0; 625#L717-15true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2007#L727-15true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1133#L728-15true activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 629#L1635-45true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1505#L1635-47true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 410#L735-45true assume !(1 == ~t5_pc~0); 1197#L735-47true is_transmit5_triggered_~__retres1~5#1 := 0; 1660#L746-15true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1515#L747-15true activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1829#L1643-45true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1664#L1643-47true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1651#L754-45true assume !(1 == ~t6_pc~0); 1490#L754-47true is_transmit6_triggered_~__retres1~6#1 := 0; 1990#L765-15true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 363#L766-15true activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1966#L1651-45true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 761#L1651-47true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 552#L773-45true assume !(1 == ~t7_pc~0); 286#L773-47true is_transmit7_triggered_~__retres1~7#1 := 0; 937#L784-15true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1294#L785-15true activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1397#L1659-45true assume !(0 != activate_threads_~tmp___6~0#1); 559#L1659-47true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 353#L792-45true assume 1 == ~t8_pc~0; 1504#L793-15true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1205#L803-15true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 144#L804-15true activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 73#L1667-45true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 720#L1667-47true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 329#L811-45true assume !(1 == ~t9_pc~0); 283#L811-47true is_transmit9_triggered_~__retres1~9#1 := 0; 1107#L822-15true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1699#L823-15true activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 924#L1675-45true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 609#L1675-47true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 465#L830-45true assume 1 == ~t10_pc~0; 1341#L831-15true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 683#L841-15true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1597#L842-15true activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 155#L1683-45true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1374#L1683-47true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33#L849-45true assume !(1 == ~t11_pc~0); 1523#L849-47true is_transmit11_triggered_~__retres1~11#1 := 0; 260#L860-15true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 71#L861-15true activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28#L1691-45true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 187#L1691-47true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 152#L868-45true assume 1 == ~t12_pc~0; 398#L869-15true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 118#L879-15true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1026#L880-15true activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1916#L1699-45true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1388#L1699-47true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1936#L887-45true assume !(1 == ~t13_pc~0); 156#L887-47true is_transmit13_triggered_~__retres1~13#1 := 0; 1041#L898-15true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1645#L899-15true activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1944#L1707-45true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 136#L1707-47true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1057#L1439-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1028#L1439-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 147#L1444-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 228#L1449-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1611#L1454-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 847#L1459-3true assume !(1 == ~T5_E~0); 2011#L1464-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1396#L1469-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1301#L1474-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1622#L1479-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1398#L1484-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 594#L1489-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1186#L1494-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1792#L1499-3true assume !(1 == ~T13_E~0); 809#L1504-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1316#L1509-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1361#L1514-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1891#L1519-3true assume 1 == ~E_3~0;~E_3~0 := 2; 539#L1524-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1438#L1529-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1669#L1534-3true assume 1 == ~E_6~0;~E_6~0 := 2; 743#L1539-3true assume !(1 == ~E_7~0); 379#L1544-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1406#L1549-3true assume 1 == ~E_9~0;~E_9~0 := 2; 706#L1554-3true assume 1 == ~E_10~0;~E_10~0 := 2; 174#L1559-3true assume 1 == ~E_11~0;~E_11~0 := 2; 1216#L1564-3true assume 1 == ~E_12~0;~E_12~0 := 2; 932#L1569-3true assume 1 == ~E_13~0;~E_13~0 := 2; 1179#L1574-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 111#L992-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 168#L1064-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 134#L1065-1true start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 114#L1959true assume !(0 == start_simulation_~tmp~3#1); 130#L1959-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 892#L992-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 974#L1064-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1114#L1065-2true stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 1426#L1914true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1598#L1921true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1469#L1922true start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1613#L1972true assume !(0 != start_simulation_~tmp___0~1#1); 148#L1940-2true [2021-12-07 00:34:11,693 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:11,693 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 1 times [2021-12-07 00:34:11,702 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:11,702 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1436010931] [2021-12-07 00:34:11,703 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:11,704 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:11,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:11,897 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:11,897 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:11,897 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1436010931] [2021-12-07 00:34:11,898 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1436010931] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:11,898 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:11,898 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:11,899 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [526954385] [2021-12-07 00:34:11,900 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:11,903 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:34:11,904 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:11,904 INFO L85 PathProgramCache]: Analyzing trace with hash 1120841461, now seen corresponding path program 1 times [2021-12-07 00:34:11,904 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:11,904 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1129026164] [2021-12-07 00:34:11,904 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:11,905 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:11,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:11,944 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:11,944 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:11,944 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1129026164] [2021-12-07 00:34:11,945 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1129026164] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:11,945 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:11,945 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-07 00:34:11,945 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2136589987] [2021-12-07 00:34:11,945 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:11,946 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:34:11,947 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:34:11,970 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-12-07 00:34:11,970 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-12-07 00:34:11,975 INFO L87 Difference]: Start difference. First operand has 2031 states, 2030 states have (on average 1.4965517241379311) internal successors, (3038), 2030 states have internal predecessors, (3038), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 79.5) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:12,074 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:34:12,074 INFO L93 Difference]: Finished difference Result 2029 states and 3002 transitions. [2021-12-07 00:34:12,075 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-12-07 00:34:12,080 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2029 states and 3002 transitions. [2021-12-07 00:34:12,102 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-07 00:34:12,123 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2029 states to 2023 states and 2996 transitions. [2021-12-07 00:34:12,123 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2021-12-07 00:34:12,126 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2021-12-07 00:34:12,126 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2996 transitions. [2021-12-07 00:34:12,134 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:34:12,134 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2996 transitions. [2021-12-07 00:34:12,149 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2996 transitions. [2021-12-07 00:34:12,197 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2021-12-07 00:34:12,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.480968858131488) internal successors, (2996), 2022 states have internal predecessors, (2996), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:12,206 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2996 transitions. [2021-12-07 00:34:12,207 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2996 transitions. [2021-12-07 00:34:12,207 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2996 transitions. [2021-12-07 00:34:12,207 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-07 00:34:12,207 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2996 transitions. [2021-12-07 00:34:12,216 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-07 00:34:12,216 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:34:12,216 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:34:12,218 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:12,219 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:12,219 INFO L791 eck$LassoCheckResult]: Stem: 4996#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 4997#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 5995#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5996#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6081#L914 assume !(1 == ~m_i~0);~m_st~0 := 2; 5460#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4929#L919-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4930#L924-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5746#L929-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5747#L934-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5847#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5848#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4701#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4702#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5877#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5237#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 5238#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5798#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 5139#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5140#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 6082#L1291-2 assume !(0 == ~T1_E~0); 6080#L1296-1 assume !(0 == ~T2_E~0); 5296#L1301-1 assume !(0 == ~T3_E~0); 5297#L1306-1 assume !(0 == ~T4_E~0); 5806#L1311-1 assume !(0 == ~T5_E~0); 4544#L1316-1 assume !(0 == ~T6_E~0); 4545#L1321-1 assume !(0 == ~T7_E~0); 5309#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4372#L1331-1 assume !(0 == ~T9_E~0); 4071#L1336-1 assume !(0 == ~T10_E~0); 4072#L1341-1 assume !(0 == ~T11_E~0); 4152#L1346-1 assume !(0 == ~T12_E~0); 4153#L1351-1 assume !(0 == ~T13_E~0); 4493#L1356-1 assume !(0 == ~E_M~0); 4494#L1361-1 assume !(0 == ~E_1~0); 6021#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 4534#L1371-1 assume !(0 == ~E_3~0); 4535#L1376-1 assume !(0 == ~E_4~0); 5356#L1381-1 assume !(0 == ~E_5~0); 5357#L1386-1 assume !(0 == ~E_6~0); 6051#L1391-1 assume !(0 == ~E_7~0); 6069#L1396-1 assume !(0 == ~E_8~0); 5269#L1401-1 assume !(0 == ~E_9~0); 5270#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 5548#L1411-1 assume !(0 == ~E_11~0); 5549#L1416-1 assume !(0 == ~E_12~0); 5181#L1421-1 assume !(0 == ~E_13~0); 4724#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4725#L640 assume !(1 == ~m_pc~0); 5234#L640-2 is_master_triggered_~__retres1~0#1 := 0; 5233#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5325#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5219#L1603 assume !(0 != activate_threads_~tmp~1#1); 5220#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4854#L659 assume 1 == ~t1_pc~0; 4855#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4960#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5906#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4980#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 4981#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4994#L678 assume 1 == ~t2_pc~0; 5948#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5949#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6048#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5092#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 5093#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5214#L697 assume !(1 == ~t3_pc~0); 5215#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5337#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5145#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5124#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5125#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5985#L716 assume 1 == ~t4_pc~0; 5971#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4835#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4836#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4335#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 4336#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5627#L735 assume !(1 == ~t5_pc~0); 4296#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4297#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4747#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5654#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 5290#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5291#L754 assume 1 == ~t6_pc~0; 5044#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4942#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4943#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4916#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 4917#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5737#L773 assume !(1 == ~t7_pc~0); 4497#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4496#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5326#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5298#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 5299#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5346#L792 assume 1 == ~t8_pc~0; 5519#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5851#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5340#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5293#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 5217#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5218#L811 assume 1 == ~t9_pc~0; 5422#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5888#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5764#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5418#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 5230#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5231#L830 assume !(1 == ~t10_pc~0); 4952#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4476#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4169#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4170#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4457#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5755#L849 assume 1 == ~t11_pc~0; 5756#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4272#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4273#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4862#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 5661#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5662#L868 assume !(1 == ~t12_pc~0); 5077#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 5076#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4871#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 4872#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 4508#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4509#L887 assume 1 == ~t13_pc~0; 5676#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 5118#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 5119#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 5555#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 4212#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4213#L1439 assume !(1 == ~M_E~0); 5286#L1439-2 assume !(1 == ~T1_E~0); 4384#L1444-1 assume !(1 == ~T2_E~0); 4385#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4858#L1454-1 assume !(1 == ~T4_E~0); 4859#L1459-1 assume !(1 == ~T5_E~0); 5415#L1464-1 assume !(1 == ~T6_E~0); 5416#L1469-1 assume !(1 == ~T7_E~0); 5488#L1474-1 assume !(1 == ~T8_E~0); 5182#L1479-1 assume !(1 == ~T9_E~0); 5183#L1484-1 assume !(1 == ~T10_E~0); 5419#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5065#L1494-1 assume !(1 == ~T12_E~0); 5066#L1499-1 assume !(1 == ~T13_E~0); 5258#L1504-1 assume !(1 == ~E_M~0); 5259#L1509-1 assume !(1 == ~E_1~0); 5834#L1514-1 assume !(1 == ~E_2~0); 5521#L1519-1 assume !(1 == ~E_3~0); 5522#L1524-1 assume !(1 == ~E_4~0); 6034#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 6035#L1534-1 assume !(1 == ~E_6~0); 4205#L1539-1 assume !(1 == ~E_7~0); 4206#L1544-1 assume !(1 == ~E_8~0); 4620#L1549-1 assume !(1 == ~E_9~0); 6009#L1554-1 assume !(1 == ~E_10~0); 6005#L1559-1 assume !(1 == ~E_11~0); 5872#L1564-1 assume !(1 == ~E_12~0); 5873#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 6030#L1574-1 assume { :end_inline_reset_delta_events } true; 4382#L1940-2 [2021-12-07 00:34:12,220 INFO L793 eck$LassoCheckResult]: Loop: 4382#L1940-2 assume !false; 4383#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4665#L1266 assume !false; 5684#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4913#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4646#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5037#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5038#L1079 assume !(0 != eval_~tmp~0#1); 4999#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5000#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5604#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5489#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5490#L1296-3 assume !(0 == ~T2_E~0); 6062#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6016#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5147#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4423#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4424#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4524#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5281#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5530#L1336-3 assume !(0 == ~T10_E~0); 5531#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4851#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4831#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 4776#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4777#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5338#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4127#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4128#L1376-3 assume !(0 == ~E_4~0); 5857#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5717#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5718#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5880#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5881#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4490#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4344#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4345#L1416-3 assume !(0 == ~E_12~0); 5006#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5007#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5114#L640-45 assume !(1 == ~m_pc~0); 5115#L640-47 is_master_triggered_~__retres1~0#1 := 0; 4581#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4582#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4121#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4122#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4220#L659-45 assume 1 == ~t1_pc~0; 4221#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4660#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5619#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5620#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5641#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5642#L678-45 assume 1 == ~t2_pc~0; 5585#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5120#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5121#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5273#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5898#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6015#L697-45 assume 1 == ~t3_pc~0; 5378#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5379#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5967#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5537#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5538#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5568#L716-45 assume !(1 == ~t4_pc~0); 5201#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 5200#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5750#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5205#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5206#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4868#L735-45 assume 1 == ~t5_pc~0; 4869#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5412#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5974#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5975#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6033#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6028#L754-45 assume 1 == ~t6_pc~0; 5360#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5361#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4790#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4791#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5364#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5096#L773-45 assume 1 == ~t7_pc~0; 5097#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4654#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5574#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5856#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 5102#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4772#L792-45 assume 1 == ~t8_pc~0; 4773#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5802#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4375#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4234#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4235#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4730#L811-45 assume 1 == ~t9_pc~0; 4519#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4521#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5729#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5564#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5173#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4965#L830-45 assume !(1 == ~t10_pc~0); 4162#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 4163#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5285#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4395#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4396#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4141#L849-45 assume !(1 == ~t11_pc~0); 4142#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 4601#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4232#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4129#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4130#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4388#L868-45 assume 1 == ~t12_pc~0; 4389#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4328#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4329#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 5667#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 5918#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5919#L887-45 assume 1 == ~t13_pc~0; 5749#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4398#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 5680#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 6025#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4360#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4361#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5668#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4380#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4381#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4538#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5469#L1459-3 assume !(1 == ~T5_E~0); 5470#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5921#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5860#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5861#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5922#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5154#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5155#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5791#L1499-3 assume !(1 == ~T13_E~0); 5430#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5431#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5869#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5899#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5073#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5074#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5941#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5341#L1539-3 assume !(1 == ~E_7~0); 4817#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4818#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5313#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4434#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4435#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 5569#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 5570#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4311#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4082#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4357#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 4318#L1959 assume !(0 == start_simulation_~tmp~3#1); 4320#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4352#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4302#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5611#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 5732#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5939#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5953#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 5954#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 4382#L1940-2 [2021-12-07 00:34:12,220 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:12,220 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 2 times [2021-12-07 00:34:12,221 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:12,221 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [603424715] [2021-12-07 00:34:12,221 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:12,221 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:12,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:12,309 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:12,310 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:12,310 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [603424715] [2021-12-07 00:34:12,310 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [603424715] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:12,310 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:12,311 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:12,311 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [839367300] [2021-12-07 00:34:12,311 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:12,312 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:34:12,312 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:12,313 INFO L85 PathProgramCache]: Analyzing trace with hash -1800844194, now seen corresponding path program 1 times [2021-12-07 00:34:12,313 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:12,313 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [713320504] [2021-12-07 00:34:12,313 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:12,313 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:12,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:12,401 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:12,401 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:12,401 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [713320504] [2021-12-07 00:34:12,401 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [713320504] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:12,401 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:12,402 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:12,402 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [366654046] [2021-12-07 00:34:12,402 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:12,402 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:34:12,402 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:34:12,403 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:34:12,403 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:34:12,403 INFO L87 Difference]: Start difference. First operand 2023 states and 2996 transitions. cyclomatic complexity: 974 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:12,473 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:34:12,473 INFO L93 Difference]: Finished difference Result 2023 states and 2995 transitions. [2021-12-07 00:34:12,473 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:34:12,474 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2995 transitions. [2021-12-07 00:34:12,490 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-07 00:34:12,507 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2995 transitions. [2021-12-07 00:34:12,507 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2021-12-07 00:34:12,510 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2021-12-07 00:34:12,510 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2995 transitions. [2021-12-07 00:34:12,514 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:34:12,514 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2995 transitions. [2021-12-07 00:34:12,518 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2995 transitions. [2021-12-07 00:34:12,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2021-12-07 00:34:12,551 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4804745427582797) internal successors, (2995), 2022 states have internal predecessors, (2995), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:12,559 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2995 transitions. [2021-12-07 00:34:12,559 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2995 transitions. [2021-12-07 00:34:12,559 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2995 transitions. [2021-12-07 00:34:12,559 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-07 00:34:12,559 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2995 transitions. [2021-12-07 00:34:12,571 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-07 00:34:12,571 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:34:12,571 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:34:12,575 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:12,575 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:12,576 INFO L791 eck$LassoCheckResult]: Stem: 9049#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 9050#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 10048#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10049#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10134#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 9513#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8982#L919-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 8983#L924-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 9799#L929-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 9800#L934-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9900#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9901#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8754#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8755#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9930#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9290#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9291#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 9851#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 9192#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9193#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 10135#L1291-2 assume !(0 == ~T1_E~0); 10133#L1296-1 assume !(0 == ~T2_E~0); 9349#L1301-1 assume !(0 == ~T3_E~0); 9350#L1306-1 assume !(0 == ~T4_E~0); 9859#L1311-1 assume !(0 == ~T5_E~0); 8597#L1316-1 assume !(0 == ~T6_E~0); 8598#L1321-1 assume !(0 == ~T7_E~0); 9362#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8425#L1331-1 assume !(0 == ~T9_E~0); 8124#L1336-1 assume !(0 == ~T10_E~0); 8125#L1341-1 assume !(0 == ~T11_E~0); 8205#L1346-1 assume !(0 == ~T12_E~0); 8206#L1351-1 assume !(0 == ~T13_E~0); 8546#L1356-1 assume !(0 == ~E_M~0); 8547#L1361-1 assume !(0 == ~E_1~0); 10074#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 8587#L1371-1 assume !(0 == ~E_3~0); 8588#L1376-1 assume !(0 == ~E_4~0); 9409#L1381-1 assume !(0 == ~E_5~0); 9410#L1386-1 assume !(0 == ~E_6~0); 10104#L1391-1 assume !(0 == ~E_7~0); 10122#L1396-1 assume !(0 == ~E_8~0); 9322#L1401-1 assume !(0 == ~E_9~0); 9323#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 9601#L1411-1 assume !(0 == ~E_11~0); 9602#L1416-1 assume !(0 == ~E_12~0); 9234#L1421-1 assume !(0 == ~E_13~0); 8777#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8778#L640 assume !(1 == ~m_pc~0); 9287#L640-2 is_master_triggered_~__retres1~0#1 := 0; 9286#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9378#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9272#L1603 assume !(0 != activate_threads_~tmp~1#1); 9273#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8907#L659 assume 1 == ~t1_pc~0; 8908#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9013#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9959#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9033#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 9034#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9047#L678 assume 1 == ~t2_pc~0; 10001#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10002#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10101#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9145#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 9146#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9267#L697 assume !(1 == ~t3_pc~0); 9268#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9390#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9198#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9177#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9178#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10038#L716 assume 1 == ~t4_pc~0; 10024#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8888#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8889#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8388#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 8389#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9680#L735 assume !(1 == ~t5_pc~0); 8349#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8350#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8800#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9707#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 9343#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9344#L754 assume 1 == ~t6_pc~0; 9097#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8995#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8996#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8969#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 8970#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9790#L773 assume !(1 == ~t7_pc~0); 8550#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8549#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9379#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9351#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 9352#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9399#L792 assume 1 == ~t8_pc~0; 9572#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9904#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9393#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9346#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 9270#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9271#L811 assume 1 == ~t9_pc~0; 9475#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9941#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9817#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9471#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 9283#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9284#L830 assume !(1 == ~t10_pc~0); 9005#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8529#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8222#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8223#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8510#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9808#L849 assume 1 == ~t11_pc~0; 9809#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 8325#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8326#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8915#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 9714#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9715#L868 assume !(1 == ~t12_pc~0); 9130#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 9129#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8924#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 8925#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 8561#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 8562#L887 assume 1 == ~t13_pc~0; 9729#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 9171#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 9172#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 9608#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 8265#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8266#L1439 assume !(1 == ~M_E~0); 9339#L1439-2 assume !(1 == ~T1_E~0); 8437#L1444-1 assume !(1 == ~T2_E~0); 8438#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8911#L1454-1 assume !(1 == ~T4_E~0); 8912#L1459-1 assume !(1 == ~T5_E~0); 9468#L1464-1 assume !(1 == ~T6_E~0); 9469#L1469-1 assume !(1 == ~T7_E~0); 9541#L1474-1 assume !(1 == ~T8_E~0); 9235#L1479-1 assume !(1 == ~T9_E~0); 9236#L1484-1 assume !(1 == ~T10_E~0); 9472#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9118#L1494-1 assume !(1 == ~T12_E~0); 9119#L1499-1 assume !(1 == ~T13_E~0); 9311#L1504-1 assume !(1 == ~E_M~0); 9312#L1509-1 assume !(1 == ~E_1~0); 9887#L1514-1 assume !(1 == ~E_2~0); 9574#L1519-1 assume !(1 == ~E_3~0); 9575#L1524-1 assume !(1 == ~E_4~0); 10087#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 10088#L1534-1 assume !(1 == ~E_6~0); 8258#L1539-1 assume !(1 == ~E_7~0); 8259#L1544-1 assume !(1 == ~E_8~0); 8673#L1549-1 assume !(1 == ~E_9~0); 10062#L1554-1 assume !(1 == ~E_10~0); 10058#L1559-1 assume !(1 == ~E_11~0); 9925#L1564-1 assume !(1 == ~E_12~0); 9926#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 10083#L1574-1 assume { :end_inline_reset_delta_events } true; 8435#L1940-2 [2021-12-07 00:34:12,577 INFO L793 eck$LassoCheckResult]: Loop: 8435#L1940-2 assume !false; 8436#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8718#L1266 assume !false; 9737#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8966#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8699#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 9090#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 9091#L1079 assume !(0 != eval_~tmp~0#1); 9052#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9053#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9657#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9542#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9543#L1296-3 assume !(0 == ~T2_E~0); 10115#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10069#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9200#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8476#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8477#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8577#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9334#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9583#L1336-3 assume !(0 == ~T10_E~0); 9584#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 8904#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 8884#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 8829#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8830#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9391#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8180#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8181#L1376-3 assume !(0 == ~E_4~0); 9910#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9770#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9771#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9933#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9934#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8543#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8397#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 8398#L1416-3 assume !(0 == ~E_12~0); 9059#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 9060#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9167#L640-45 assume !(1 == ~m_pc~0); 9168#L640-47 is_master_triggered_~__retres1~0#1 := 0; 8634#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8635#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8174#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8175#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8273#L659-45 assume 1 == ~t1_pc~0; 8274#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8713#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9672#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9673#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9694#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9695#L678-45 assume 1 == ~t2_pc~0; 9638#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9173#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9174#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9326#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9951#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10068#L697-45 assume 1 == ~t3_pc~0; 9431#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9432#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10020#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9590#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9591#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9621#L716-45 assume 1 == ~t4_pc~0; 9252#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9253#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9803#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9258#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9259#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8921#L735-45 assume 1 == ~t5_pc~0; 8922#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9465#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10027#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10028#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10086#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10081#L754-45 assume 1 == ~t6_pc~0; 9413#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9414#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8843#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8844#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9417#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9149#L773-45 assume !(1 == ~t7_pc~0); 8706#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 8707#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9627#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9909#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 9155#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8825#L792-45 assume 1 == ~t8_pc~0; 8826#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9855#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8428#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8287#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8288#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8783#L811-45 assume 1 == ~t9_pc~0; 8572#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8574#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9782#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9617#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9226#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9018#L830-45 assume !(1 == ~t10_pc~0); 8215#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 8216#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9338#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8448#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8449#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8194#L849-45 assume !(1 == ~t11_pc~0); 8195#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 8654#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8285#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8182#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8183#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8441#L868-45 assume 1 == ~t12_pc~0; 8442#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 8381#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8382#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 9720#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 9971#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 9972#L887-45 assume !(1 == ~t13_pc~0); 8450#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 8451#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 9733#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 10078#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 8413#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8414#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9721#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8433#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8434#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8591#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9522#L1459-3 assume !(1 == ~T5_E~0); 9523#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9974#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9913#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 9914#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9975#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9207#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9208#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 9844#L1499-3 assume !(1 == ~T13_E~0); 9483#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9484#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9922#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9952#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9126#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9127#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9994#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9394#L1539-3 assume !(1 == ~E_7~0); 8870#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8871#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9366#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 8487#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 8488#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 9622#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 9623#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8364#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8135#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8410#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 8371#L1959 assume !(0 == start_simulation_~tmp~3#1); 8373#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8405#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8355#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 9664#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 9785#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9992#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10006#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 10007#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 8435#L1940-2 [2021-12-07 00:34:12,578 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:12,578 INFO L85 PathProgramCache]: Analyzing trace with hash 1533490443, now seen corresponding path program 1 times [2021-12-07 00:34:12,578 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:12,578 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [202368195] [2021-12-07 00:34:12,578 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:12,579 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:12,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:12,648 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:12,648 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:12,648 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [202368195] [2021-12-07 00:34:12,649 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [202368195] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:12,649 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:12,649 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:12,649 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1945148332] [2021-12-07 00:34:12,649 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:12,650 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:34:12,650 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:12,651 INFO L85 PathProgramCache]: Analyzing trace with hash 230524959, now seen corresponding path program 1 times [2021-12-07 00:34:12,651 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:12,651 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [307783775] [2021-12-07 00:34:12,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:12,651 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:12,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:12,730 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:12,730 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:12,730 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [307783775] [2021-12-07 00:34:12,730 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [307783775] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:12,731 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:12,731 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:12,731 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1360246073] [2021-12-07 00:34:12,731 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:12,732 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:34:12,732 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:34:12,732 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:34:12,732 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:34:12,732 INFO L87 Difference]: Start difference. First operand 2023 states and 2995 transitions. cyclomatic complexity: 973 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:12,777 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:34:12,777 INFO L93 Difference]: Finished difference Result 2023 states and 2994 transitions. [2021-12-07 00:34:12,778 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:34:12,779 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2994 transitions. [2021-12-07 00:34:12,793 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-07 00:34:12,808 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2994 transitions. [2021-12-07 00:34:12,808 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2021-12-07 00:34:12,811 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2021-12-07 00:34:12,811 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2994 transitions. [2021-12-07 00:34:12,815 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:34:12,815 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2994 transitions. [2021-12-07 00:34:12,819 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2994 transitions. [2021-12-07 00:34:12,847 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2021-12-07 00:34:12,851 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4799802273850717) internal successors, (2994), 2022 states have internal predecessors, (2994), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:12,857 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2994 transitions. [2021-12-07 00:34:12,858 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2994 transitions. [2021-12-07 00:34:12,858 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2994 transitions. [2021-12-07 00:34:12,858 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-07 00:34:12,858 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2994 transitions. [2021-12-07 00:34:12,869 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-07 00:34:12,869 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:34:12,869 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:34:12,872 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:12,872 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:12,872 INFO L791 eck$LassoCheckResult]: Stem: 13102#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 13103#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 14101#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14102#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14187#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 13566#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13035#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13036#L924-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 13852#L929-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 13853#L934-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13953#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13954#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12807#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12808#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 13983#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13343#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 13344#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 13904#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 13245#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13246#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 14188#L1291-2 assume !(0 == ~T1_E~0); 14186#L1296-1 assume !(0 == ~T2_E~0); 13402#L1301-1 assume !(0 == ~T3_E~0); 13403#L1306-1 assume !(0 == ~T4_E~0); 13912#L1311-1 assume !(0 == ~T5_E~0); 12650#L1316-1 assume !(0 == ~T6_E~0); 12651#L1321-1 assume !(0 == ~T7_E~0); 13415#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12478#L1331-1 assume !(0 == ~T9_E~0); 12177#L1336-1 assume !(0 == ~T10_E~0); 12178#L1341-1 assume !(0 == ~T11_E~0); 12258#L1346-1 assume !(0 == ~T12_E~0); 12259#L1351-1 assume !(0 == ~T13_E~0); 12599#L1356-1 assume !(0 == ~E_M~0); 12600#L1361-1 assume !(0 == ~E_1~0); 14127#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 12640#L1371-1 assume !(0 == ~E_3~0); 12641#L1376-1 assume !(0 == ~E_4~0); 13462#L1381-1 assume !(0 == ~E_5~0); 13463#L1386-1 assume !(0 == ~E_6~0); 14157#L1391-1 assume !(0 == ~E_7~0); 14175#L1396-1 assume !(0 == ~E_8~0); 13375#L1401-1 assume !(0 == ~E_9~0); 13376#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 13654#L1411-1 assume !(0 == ~E_11~0); 13655#L1416-1 assume !(0 == ~E_12~0); 13287#L1421-1 assume !(0 == ~E_13~0); 12830#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12831#L640 assume !(1 == ~m_pc~0); 13340#L640-2 is_master_triggered_~__retres1~0#1 := 0; 13339#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13431#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13325#L1603 assume !(0 != activate_threads_~tmp~1#1); 13326#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12960#L659 assume 1 == ~t1_pc~0; 12961#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13066#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14012#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13086#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 13087#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13100#L678 assume 1 == ~t2_pc~0; 14054#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14055#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14154#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13198#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 13199#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13320#L697 assume !(1 == ~t3_pc~0); 13321#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13443#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13251#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13230#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13231#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14091#L716 assume 1 == ~t4_pc~0; 14077#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12941#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12942#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12441#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 12442#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13733#L735 assume !(1 == ~t5_pc~0); 12402#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 12403#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12853#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13760#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 13396#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13397#L754 assume 1 == ~t6_pc~0; 13150#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13048#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13049#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13022#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 13023#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13843#L773 assume !(1 == ~t7_pc~0); 12603#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 12602#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13432#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13404#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 13405#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13452#L792 assume 1 == ~t8_pc~0; 13625#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13957#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13446#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13399#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 13323#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13324#L811 assume 1 == ~t9_pc~0; 13528#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13994#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13870#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13524#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 13336#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13337#L830 assume !(1 == ~t10_pc~0); 13058#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12582#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12275#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12276#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12563#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13861#L849 assume 1 == ~t11_pc~0; 13862#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 12378#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12379#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12968#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 13767#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 13768#L868 assume !(1 == ~t12_pc~0); 13183#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 13182#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12977#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 12978#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 12614#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12615#L887 assume 1 == ~t13_pc~0; 13782#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 13224#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13225#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 13661#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 12318#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12319#L1439 assume !(1 == ~M_E~0); 13392#L1439-2 assume !(1 == ~T1_E~0); 12490#L1444-1 assume !(1 == ~T2_E~0); 12491#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12964#L1454-1 assume !(1 == ~T4_E~0); 12965#L1459-1 assume !(1 == ~T5_E~0); 13521#L1464-1 assume !(1 == ~T6_E~0); 13522#L1469-1 assume !(1 == ~T7_E~0); 13594#L1474-1 assume !(1 == ~T8_E~0); 13288#L1479-1 assume !(1 == ~T9_E~0); 13289#L1484-1 assume !(1 == ~T10_E~0); 13525#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 13171#L1494-1 assume !(1 == ~T12_E~0); 13172#L1499-1 assume !(1 == ~T13_E~0); 13364#L1504-1 assume !(1 == ~E_M~0); 13365#L1509-1 assume !(1 == ~E_1~0); 13940#L1514-1 assume !(1 == ~E_2~0); 13627#L1519-1 assume !(1 == ~E_3~0); 13628#L1524-1 assume !(1 == ~E_4~0); 14140#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 14141#L1534-1 assume !(1 == ~E_6~0); 12311#L1539-1 assume !(1 == ~E_7~0); 12312#L1544-1 assume !(1 == ~E_8~0); 12726#L1549-1 assume !(1 == ~E_9~0); 14115#L1554-1 assume !(1 == ~E_10~0); 14111#L1559-1 assume !(1 == ~E_11~0); 13978#L1564-1 assume !(1 == ~E_12~0); 13979#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 14136#L1574-1 assume { :end_inline_reset_delta_events } true; 12488#L1940-2 [2021-12-07 00:34:12,873 INFO L793 eck$LassoCheckResult]: Loop: 12488#L1940-2 assume !false; 12489#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12771#L1266 assume !false; 13790#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13019#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12752#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 13143#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 13144#L1079 assume !(0 != eval_~tmp~0#1); 13105#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13106#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13710#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13595#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13596#L1296-3 assume !(0 == ~T2_E~0); 14168#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14122#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13253#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12529#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12530#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12630#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13387#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13636#L1336-3 assume !(0 == ~T10_E~0); 13637#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 12957#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 12937#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 12882#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12883#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13444#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12233#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12234#L1376-3 assume !(0 == ~E_4~0); 13963#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13823#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13824#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13986#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13987#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12596#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12450#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 12451#L1416-3 assume !(0 == ~E_12~0); 13112#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 13113#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13220#L640-45 assume !(1 == ~m_pc~0); 13221#L640-47 is_master_triggered_~__retres1~0#1 := 0; 12687#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12688#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12227#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12228#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12326#L659-45 assume 1 == ~t1_pc~0; 12327#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12766#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13725#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13726#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13747#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13748#L678-45 assume 1 == ~t2_pc~0; 13691#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13226#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13227#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13379#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14004#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14121#L697-45 assume 1 == ~t3_pc~0; 13484#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13485#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14073#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13643#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13644#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13674#L716-45 assume 1 == ~t4_pc~0; 13305#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13306#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13856#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13311#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13312#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12974#L735-45 assume !(1 == ~t5_pc~0); 12976#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 13518#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14080#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14081#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14139#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14134#L754-45 assume 1 == ~t6_pc~0; 13466#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13467#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12896#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12897#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13470#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13202#L773-45 assume 1 == ~t7_pc~0; 13203#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12760#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13680#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13962#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 13208#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12878#L792-45 assume !(1 == ~t8_pc~0); 12880#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 13908#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12481#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12340#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12341#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12836#L811-45 assume 1 == ~t9_pc~0; 12625#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12627#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13835#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13670#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13279#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13071#L830-45 assume 1 == ~t10_pc~0; 13072#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12269#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13391#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12501#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12502#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12247#L849-45 assume !(1 == ~t11_pc~0); 12248#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 12707#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12338#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12235#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 12236#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12494#L868-45 assume !(1 == ~t12_pc~0); 12496#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 12434#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12435#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 13773#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 14024#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 14025#L887-45 assume !(1 == ~t13_pc~0); 12503#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 12504#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13786#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 14131#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 12466#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12467#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13774#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12486#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12487#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12644#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13575#L1459-3 assume !(1 == ~T5_E~0); 13576#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14027#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13966#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13967#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14028#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 13260#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 13261#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 13897#L1499-3 assume !(1 == ~T13_E~0); 13536#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13537#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13975#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14005#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13179#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13180#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14047#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13447#L1539-3 assume !(1 == ~E_7~0); 12923#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12924#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13419#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12540#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12541#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 13675#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 13676#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12417#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12188#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12463#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 12424#L1959 assume !(0 == start_simulation_~tmp~3#1); 12426#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12458#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12408#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 13717#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 13838#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14045#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14059#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 14060#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 12488#L1940-2 [2021-12-07 00:34:12,873 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:12,873 INFO L85 PathProgramCache]: Analyzing trace with hash -992005239, now seen corresponding path program 1 times [2021-12-07 00:34:12,873 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:12,874 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1644914235] [2021-12-07 00:34:12,874 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:12,874 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:12,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:12,913 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:12,913 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:12,913 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1644914235] [2021-12-07 00:34:12,913 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1644914235] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:12,914 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:12,914 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:12,914 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1854033444] [2021-12-07 00:34:12,914 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:12,915 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:34:12,915 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:12,915 INFO L85 PathProgramCache]: Analyzing trace with hash -990138912, now seen corresponding path program 1 times [2021-12-07 00:34:12,915 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:12,915 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1477524294] [2021-12-07 00:34:12,916 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:12,916 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:12,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:12,988 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:12,988 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:12,988 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1477524294] [2021-12-07 00:34:12,989 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1477524294] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:12,989 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:12,989 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:12,989 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1497488453] [2021-12-07 00:34:12,989 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:12,990 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:34:12,990 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:34:12,991 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:34:12,991 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:34:12,991 INFO L87 Difference]: Start difference. First operand 2023 states and 2994 transitions. cyclomatic complexity: 972 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:13,033 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:34:13,033 INFO L93 Difference]: Finished difference Result 2023 states and 2993 transitions. [2021-12-07 00:34:13,034 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:34:13,035 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2993 transitions. [2021-12-07 00:34:13,050 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-07 00:34:13,066 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2993 transitions. [2021-12-07 00:34:13,066 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2021-12-07 00:34:13,068 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2021-12-07 00:34:13,068 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2993 transitions. [2021-12-07 00:34:13,072 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:34:13,072 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2993 transitions. [2021-12-07 00:34:13,076 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2993 transitions. [2021-12-07 00:34:13,102 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2021-12-07 00:34:13,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4794859120118635) internal successors, (2993), 2022 states have internal predecessors, (2993), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:13,110 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2993 transitions. [2021-12-07 00:34:13,111 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2993 transitions. [2021-12-07 00:34:13,111 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2993 transitions. [2021-12-07 00:34:13,111 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-07 00:34:13,111 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2993 transitions. [2021-12-07 00:34:13,117 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-07 00:34:13,117 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:34:13,118 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:34:13,120 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:13,120 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:13,120 INFO L791 eck$LassoCheckResult]: Stem: 17155#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 17156#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 18154#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18155#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18240#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 17619#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17088#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17089#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17905#L929-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 17906#L934-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 18006#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 18007#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 16860#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16861#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18036#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17396#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 17397#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 17957#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 17298#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17299#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 18241#L1291-2 assume !(0 == ~T1_E~0); 18239#L1296-1 assume !(0 == ~T2_E~0); 17455#L1301-1 assume !(0 == ~T3_E~0); 17456#L1306-1 assume !(0 == ~T4_E~0); 17965#L1311-1 assume !(0 == ~T5_E~0); 16703#L1316-1 assume !(0 == ~T6_E~0); 16704#L1321-1 assume !(0 == ~T7_E~0); 17468#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16531#L1331-1 assume !(0 == ~T9_E~0); 16230#L1336-1 assume !(0 == ~T10_E~0); 16231#L1341-1 assume !(0 == ~T11_E~0); 16311#L1346-1 assume !(0 == ~T12_E~0); 16312#L1351-1 assume !(0 == ~T13_E~0); 16652#L1356-1 assume !(0 == ~E_M~0); 16653#L1361-1 assume !(0 == ~E_1~0); 18180#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 16693#L1371-1 assume !(0 == ~E_3~0); 16694#L1376-1 assume !(0 == ~E_4~0); 17515#L1381-1 assume !(0 == ~E_5~0); 17516#L1386-1 assume !(0 == ~E_6~0); 18210#L1391-1 assume !(0 == ~E_7~0); 18228#L1396-1 assume !(0 == ~E_8~0); 17428#L1401-1 assume !(0 == ~E_9~0); 17429#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 17707#L1411-1 assume !(0 == ~E_11~0); 17708#L1416-1 assume !(0 == ~E_12~0); 17340#L1421-1 assume !(0 == ~E_13~0); 16883#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16884#L640 assume !(1 == ~m_pc~0); 17393#L640-2 is_master_triggered_~__retres1~0#1 := 0; 17392#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17484#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17378#L1603 assume !(0 != activate_threads_~tmp~1#1); 17379#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17013#L659 assume 1 == ~t1_pc~0; 17014#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17119#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18065#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17139#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 17140#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17153#L678 assume 1 == ~t2_pc~0; 18107#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18108#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18207#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17251#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 17252#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17373#L697 assume !(1 == ~t3_pc~0); 17374#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 17496#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17304#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17283#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17284#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18144#L716 assume 1 == ~t4_pc~0; 18130#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16994#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16995#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16494#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 16495#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17786#L735 assume !(1 == ~t5_pc~0); 16455#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 16456#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16906#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17813#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 17449#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17450#L754 assume 1 == ~t6_pc~0; 17203#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17101#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17102#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17075#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 17076#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17896#L773 assume !(1 == ~t7_pc~0); 16656#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 16655#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17485#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17457#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 17458#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17505#L792 assume 1 == ~t8_pc~0; 17678#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18010#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17499#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17452#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 17376#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17377#L811 assume 1 == ~t9_pc~0; 17581#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18047#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17923#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17577#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 17389#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17390#L830 assume !(1 == ~t10_pc~0); 17111#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 16635#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16328#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 16329#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16616#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17914#L849 assume 1 == ~t11_pc~0; 17915#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 16431#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16432#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 17021#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 17820#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17821#L868 assume !(1 == ~t12_pc~0); 17236#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 17235#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 17030#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 17031#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 16667#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16668#L887 assume 1 == ~t13_pc~0; 17835#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 17277#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 17278#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 17714#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 16371#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16372#L1439 assume !(1 == ~M_E~0); 17445#L1439-2 assume !(1 == ~T1_E~0); 16543#L1444-1 assume !(1 == ~T2_E~0); 16544#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17017#L1454-1 assume !(1 == ~T4_E~0); 17018#L1459-1 assume !(1 == ~T5_E~0); 17574#L1464-1 assume !(1 == ~T6_E~0); 17575#L1469-1 assume !(1 == ~T7_E~0); 17647#L1474-1 assume !(1 == ~T8_E~0); 17341#L1479-1 assume !(1 == ~T9_E~0); 17342#L1484-1 assume !(1 == ~T10_E~0); 17578#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17224#L1494-1 assume !(1 == ~T12_E~0); 17225#L1499-1 assume !(1 == ~T13_E~0); 17417#L1504-1 assume !(1 == ~E_M~0); 17418#L1509-1 assume !(1 == ~E_1~0); 17993#L1514-1 assume !(1 == ~E_2~0); 17680#L1519-1 assume !(1 == ~E_3~0); 17681#L1524-1 assume !(1 == ~E_4~0); 18193#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 18194#L1534-1 assume !(1 == ~E_6~0); 16364#L1539-1 assume !(1 == ~E_7~0); 16365#L1544-1 assume !(1 == ~E_8~0); 16779#L1549-1 assume !(1 == ~E_9~0); 18168#L1554-1 assume !(1 == ~E_10~0); 18164#L1559-1 assume !(1 == ~E_11~0); 18031#L1564-1 assume !(1 == ~E_12~0); 18032#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 18189#L1574-1 assume { :end_inline_reset_delta_events } true; 16541#L1940-2 [2021-12-07 00:34:13,121 INFO L793 eck$LassoCheckResult]: Loop: 16541#L1940-2 assume !false; 16542#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16824#L1266 assume !false; 17843#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 17072#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16805#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 17196#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 17197#L1079 assume !(0 != eval_~tmp~0#1); 17158#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17159#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17763#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17648#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17649#L1296-3 assume !(0 == ~T2_E~0); 18221#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18175#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17306#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16582#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16583#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16683#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17440#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17689#L1336-3 assume !(0 == ~T10_E~0); 17690#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 17010#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 16990#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 16935#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16936#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17497#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16286#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16287#L1376-3 assume !(0 == ~E_4~0); 18016#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17876#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17877#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18039#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 18040#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 16649#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16503#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16504#L1416-3 assume !(0 == ~E_12~0); 17165#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 17166#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17273#L640-45 assume !(1 == ~m_pc~0); 17274#L640-47 is_master_triggered_~__retres1~0#1 := 0; 16740#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16741#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16280#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16281#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16379#L659-45 assume 1 == ~t1_pc~0; 16380#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16819#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17778#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17779#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17800#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17801#L678-45 assume 1 == ~t2_pc~0; 17744#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17279#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17280#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17432#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18057#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18174#L697-45 assume 1 == ~t3_pc~0; 17537#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17538#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18126#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17696#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17697#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17727#L716-45 assume !(1 == ~t4_pc~0); 17360#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 17359#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17909#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17364#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17365#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17027#L735-45 assume 1 == ~t5_pc~0; 17028#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17571#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18133#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18134#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18192#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18187#L754-45 assume !(1 == ~t6_pc~0); 17521#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 17520#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16949#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16950#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17523#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17255#L773-45 assume 1 == ~t7_pc~0; 17256#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16813#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17733#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18015#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 17261#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16931#L792-45 assume 1 == ~t8_pc~0; 16932#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 17961#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16534#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16393#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16394#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16889#L811-45 assume 1 == ~t9_pc~0; 16678#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16680#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17888#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17723#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17332#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17124#L830-45 assume !(1 == ~t10_pc~0); 16321#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 16322#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17444#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 16554#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16555#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16300#L849-45 assume !(1 == ~t11_pc~0); 16301#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 16760#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16391#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 16288#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 16289#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16547#L868-45 assume 1 == ~t12_pc~0; 16548#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 16487#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 16488#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 17826#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 18077#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 18078#L887-45 assume 1 == ~t13_pc~0; 17908#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 16557#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 17839#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 18184#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 16519#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16520#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17827#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16539#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16540#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16697#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17628#L1459-3 assume !(1 == ~T5_E~0); 17629#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18080#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18019#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18020#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18081#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 17313#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17314#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 17950#L1499-3 assume !(1 == ~T13_E~0); 17589#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17590#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18028#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18058#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17232#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17233#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18100#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 17500#L1539-3 assume !(1 == ~E_7~0); 16976#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16977#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17472#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 16593#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 16594#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 17728#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 17729#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16470#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16241#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16516#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 16477#L1959 assume !(0 == start_simulation_~tmp~3#1); 16479#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16511#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16461#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 17770#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 17891#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18098#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18112#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 18113#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 16541#L1940-2 [2021-12-07 00:34:13,121 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:13,121 INFO L85 PathProgramCache]: Analyzing trace with hash -380736181, now seen corresponding path program 1 times [2021-12-07 00:34:13,121 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:13,121 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [117914158] [2021-12-07 00:34:13,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:13,122 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:13,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:13,150 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:13,150 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:13,150 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [117914158] [2021-12-07 00:34:13,150 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [117914158] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:13,151 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:13,151 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:13,151 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1836326115] [2021-12-07 00:34:13,151 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:13,151 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:34:13,152 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:13,152 INFO L85 PathProgramCache]: Analyzing trace with hash 1107441823, now seen corresponding path program 1 times [2021-12-07 00:34:13,152 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:13,152 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [140532952] [2021-12-07 00:34:13,152 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:13,153 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:13,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:13,198 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:13,198 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:13,198 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [140532952] [2021-12-07 00:34:13,199 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [140532952] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:13,199 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:13,199 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:13,199 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [20292542] [2021-12-07 00:34:13,199 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:13,200 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:34:13,200 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:34:13,200 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:34:13,200 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:34:13,201 INFO L87 Difference]: Start difference. First operand 2023 states and 2993 transitions. cyclomatic complexity: 971 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:13,235 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:34:13,235 INFO L93 Difference]: Finished difference Result 2023 states and 2992 transitions. [2021-12-07 00:34:13,235 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:34:13,236 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2992 transitions. [2021-12-07 00:34:13,246 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-07 00:34:13,261 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2992 transitions. [2021-12-07 00:34:13,261 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2021-12-07 00:34:13,263 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2021-12-07 00:34:13,263 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2992 transitions. [2021-12-07 00:34:13,277 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:34:13,278 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2992 transitions. [2021-12-07 00:34:13,281 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2992 transitions. [2021-12-07 00:34:13,304 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2021-12-07 00:34:13,308 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4789915966386555) internal successors, (2992), 2022 states have internal predecessors, (2992), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:13,315 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2992 transitions. [2021-12-07 00:34:13,315 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2992 transitions. [2021-12-07 00:34:13,316 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2992 transitions. [2021-12-07 00:34:13,316 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-07 00:34:13,316 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2992 transitions. [2021-12-07 00:34:13,322 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-07 00:34:13,322 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:34:13,322 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:34:13,325 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:13,325 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:13,325 INFO L791 eck$LassoCheckResult]: Stem: 21208#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 21209#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 22207#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22208#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22293#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 21672#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21141#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21142#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21958#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21959#L934-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 22059#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 22060#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 20913#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 20914#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22089#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21449#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21450#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 22010#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 21351#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21352#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 22294#L1291-2 assume !(0 == ~T1_E~0); 22292#L1296-1 assume !(0 == ~T2_E~0); 21508#L1301-1 assume !(0 == ~T3_E~0); 21509#L1306-1 assume !(0 == ~T4_E~0); 22018#L1311-1 assume !(0 == ~T5_E~0); 20756#L1316-1 assume !(0 == ~T6_E~0); 20757#L1321-1 assume !(0 == ~T7_E~0); 21521#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20584#L1331-1 assume !(0 == ~T9_E~0); 20283#L1336-1 assume !(0 == ~T10_E~0); 20284#L1341-1 assume !(0 == ~T11_E~0); 20364#L1346-1 assume !(0 == ~T12_E~0); 20365#L1351-1 assume !(0 == ~T13_E~0); 20705#L1356-1 assume !(0 == ~E_M~0); 20706#L1361-1 assume !(0 == ~E_1~0); 22233#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 20746#L1371-1 assume !(0 == ~E_3~0); 20747#L1376-1 assume !(0 == ~E_4~0); 21568#L1381-1 assume !(0 == ~E_5~0); 21569#L1386-1 assume !(0 == ~E_6~0); 22263#L1391-1 assume !(0 == ~E_7~0); 22281#L1396-1 assume !(0 == ~E_8~0); 21481#L1401-1 assume !(0 == ~E_9~0); 21482#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 21760#L1411-1 assume !(0 == ~E_11~0); 21761#L1416-1 assume !(0 == ~E_12~0); 21393#L1421-1 assume !(0 == ~E_13~0); 20936#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20937#L640 assume !(1 == ~m_pc~0); 21446#L640-2 is_master_triggered_~__retres1~0#1 := 0; 21445#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21537#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21431#L1603 assume !(0 != activate_threads_~tmp~1#1); 21432#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21066#L659 assume 1 == ~t1_pc~0; 21067#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21172#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22118#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21192#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 21193#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21206#L678 assume 1 == ~t2_pc~0; 22160#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22161#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22260#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21304#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 21305#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21426#L697 assume !(1 == ~t3_pc~0); 21427#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21549#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21357#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21336#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21337#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22197#L716 assume 1 == ~t4_pc~0; 22183#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21047#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21048#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20547#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 20548#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21839#L735 assume !(1 == ~t5_pc~0); 20508#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 20509#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20959#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21866#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 21502#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21503#L754 assume 1 == ~t6_pc~0; 21256#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21154#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21155#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21128#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 21129#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21949#L773 assume !(1 == ~t7_pc~0); 20709#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 20708#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21538#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21510#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 21511#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21558#L792 assume 1 == ~t8_pc~0; 21731#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22063#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21552#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21505#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 21429#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21430#L811 assume 1 == ~t9_pc~0; 21634#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22100#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21976#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21630#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 21442#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21443#L830 assume !(1 == ~t10_pc~0); 21164#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 20688#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20381#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 20382#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20669#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21967#L849 assume 1 == ~t11_pc~0; 21968#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 20484#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20485#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21074#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 21873#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21874#L868 assume !(1 == ~t12_pc~0); 21289#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 21288#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21083#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 21084#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 20720#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20721#L887 assume 1 == ~t13_pc~0; 21888#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 21330#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21331#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 21767#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 20424#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20425#L1439 assume !(1 == ~M_E~0); 21498#L1439-2 assume !(1 == ~T1_E~0); 20596#L1444-1 assume !(1 == ~T2_E~0); 20597#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21070#L1454-1 assume !(1 == ~T4_E~0); 21071#L1459-1 assume !(1 == ~T5_E~0); 21627#L1464-1 assume !(1 == ~T6_E~0); 21628#L1469-1 assume !(1 == ~T7_E~0); 21700#L1474-1 assume !(1 == ~T8_E~0); 21394#L1479-1 assume !(1 == ~T9_E~0); 21395#L1484-1 assume !(1 == ~T10_E~0); 21631#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21277#L1494-1 assume !(1 == ~T12_E~0); 21278#L1499-1 assume !(1 == ~T13_E~0); 21470#L1504-1 assume !(1 == ~E_M~0); 21471#L1509-1 assume !(1 == ~E_1~0); 22046#L1514-1 assume !(1 == ~E_2~0); 21733#L1519-1 assume !(1 == ~E_3~0); 21734#L1524-1 assume !(1 == ~E_4~0); 22246#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 22247#L1534-1 assume !(1 == ~E_6~0); 20417#L1539-1 assume !(1 == ~E_7~0); 20418#L1544-1 assume !(1 == ~E_8~0); 20832#L1549-1 assume !(1 == ~E_9~0); 22221#L1554-1 assume !(1 == ~E_10~0); 22217#L1559-1 assume !(1 == ~E_11~0); 22084#L1564-1 assume !(1 == ~E_12~0); 22085#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 22242#L1574-1 assume { :end_inline_reset_delta_events } true; 20594#L1940-2 [2021-12-07 00:34:13,326 INFO L793 eck$LassoCheckResult]: Loop: 20594#L1940-2 assume !false; 20595#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20877#L1266 assume !false; 21896#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 21125#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20858#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 21249#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 21250#L1079 assume !(0 != eval_~tmp~0#1); 21211#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21212#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21816#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21701#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21702#L1296-3 assume !(0 == ~T2_E~0); 22274#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22228#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21359#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20635#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20636#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20736#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21493#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21742#L1336-3 assume !(0 == ~T10_E~0); 21743#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 21063#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 21043#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 20988#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20989#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21550#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20339#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20340#L1376-3 assume !(0 == ~E_4~0); 22069#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 21929#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21930#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 22092#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22093#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 20702#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 20556#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 20557#L1416-3 assume !(0 == ~E_12~0); 21218#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 21219#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21326#L640-45 assume 1 == ~m_pc~0; 21328#L641-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 20793#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20794#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20333#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20334#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20432#L659-45 assume 1 == ~t1_pc~0; 20433#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20872#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21831#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21832#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21853#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21854#L678-45 assume 1 == ~t2_pc~0; 21797#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21332#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21333#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21485#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22110#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22227#L697-45 assume 1 == ~t3_pc~0; 21590#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21591#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22179#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21749#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21750#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21780#L716-45 assume 1 == ~t4_pc~0; 21411#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21412#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21962#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21417#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21418#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21080#L735-45 assume 1 == ~t5_pc~0; 21081#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 21624#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22186#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22187#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22245#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22240#L754-45 assume 1 == ~t6_pc~0; 21572#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21573#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21002#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21003#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21576#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21308#L773-45 assume !(1 == ~t7_pc~0); 20865#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 20866#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21786#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22068#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 21314#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20984#L792-45 assume 1 == ~t8_pc~0; 20985#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22014#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20587#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20446#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20447#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20942#L811-45 assume 1 == ~t9_pc~0; 20731#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20733#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21941#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21776#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21385#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21177#L830-45 assume !(1 == ~t10_pc~0); 20374#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 20375#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21497#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 20607#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20608#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20353#L849-45 assume !(1 == ~t11_pc~0); 20354#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 20813#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20444#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 20341#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 20342#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20600#L868-45 assume 1 == ~t12_pc~0; 20601#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20540#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20541#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 21879#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 22130#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 22131#L887-45 assume !(1 == ~t13_pc~0); 20609#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 20610#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21892#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 22237#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 20572#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20573#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21880#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20592#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20593#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20750#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21681#L1459-3 assume !(1 == ~T5_E~0); 21682#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 22133#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22072#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22073#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22134#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21366#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21367#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 22003#L1499-3 assume !(1 == ~T13_E~0); 21642#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21643#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22081#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22111#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21285#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21286#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22153#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21553#L1539-3 assume !(1 == ~E_7~0); 21029#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21030#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21525#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20646#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 20647#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 21781#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 21782#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20523#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20294#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20569#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 20530#L1959 assume !(0 == start_simulation_~tmp~3#1); 20532#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20564#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20514#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 21823#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 21944#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22151#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22165#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 22166#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 20594#L1940-2 [2021-12-07 00:34:13,326 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:13,326 INFO L85 PathProgramCache]: Analyzing trace with hash 1024455497, now seen corresponding path program 1 times [2021-12-07 00:34:13,326 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:13,326 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [753943790] [2021-12-07 00:34:13,327 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:13,327 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:13,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:13,363 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:13,364 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:13,364 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [753943790] [2021-12-07 00:34:13,364 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [753943790] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:13,364 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:13,364 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:13,365 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [407763513] [2021-12-07 00:34:13,365 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:13,365 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:34:13,365 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:13,366 INFO L85 PathProgramCache]: Analyzing trace with hash 2009983070, now seen corresponding path program 1 times [2021-12-07 00:34:13,366 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:13,366 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1167559824] [2021-12-07 00:34:13,366 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:13,366 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:13,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:13,417 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:13,417 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:13,417 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1167559824] [2021-12-07 00:34:13,417 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1167559824] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:13,417 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:13,418 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:13,418 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2136795296] [2021-12-07 00:34:13,418 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:13,418 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:34:13,418 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:34:13,419 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:34:13,419 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:34:13,419 INFO L87 Difference]: Start difference. First operand 2023 states and 2992 transitions. cyclomatic complexity: 970 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:13,450 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:34:13,451 INFO L93 Difference]: Finished difference Result 2023 states and 2991 transitions. [2021-12-07 00:34:13,451 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:34:13,452 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2991 transitions. [2021-12-07 00:34:13,461 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-07 00:34:13,475 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2991 transitions. [2021-12-07 00:34:13,475 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2021-12-07 00:34:13,476 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2021-12-07 00:34:13,477 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2991 transitions. [2021-12-07 00:34:13,479 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:34:13,479 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2991 transitions. [2021-12-07 00:34:13,482 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2991 transitions. [2021-12-07 00:34:13,499 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2021-12-07 00:34:13,502 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4784972812654473) internal successors, (2991), 2022 states have internal predecessors, (2991), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:13,507 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2991 transitions. [2021-12-07 00:34:13,507 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2991 transitions. [2021-12-07 00:34:13,507 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2991 transitions. [2021-12-07 00:34:13,507 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-07 00:34:13,507 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2991 transitions. [2021-12-07 00:34:13,512 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-07 00:34:13,512 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:34:13,512 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:34:13,513 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:13,513 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:13,514 INFO L791 eck$LassoCheckResult]: Stem: 25261#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 25262#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 26260#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26261#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26346#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 25725#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25194#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25195#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26011#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26012#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26112#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 26113#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 24966#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 24967#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 26142#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25502#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25503#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 26063#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 25404#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25405#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 26347#L1291-2 assume !(0 == ~T1_E~0); 26345#L1296-1 assume !(0 == ~T2_E~0); 25561#L1301-1 assume !(0 == ~T3_E~0); 25562#L1306-1 assume !(0 == ~T4_E~0); 26071#L1311-1 assume !(0 == ~T5_E~0); 24809#L1316-1 assume !(0 == ~T6_E~0); 24810#L1321-1 assume !(0 == ~T7_E~0); 25574#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24637#L1331-1 assume !(0 == ~T9_E~0); 24336#L1336-1 assume !(0 == ~T10_E~0); 24337#L1341-1 assume !(0 == ~T11_E~0); 24417#L1346-1 assume !(0 == ~T12_E~0); 24418#L1351-1 assume !(0 == ~T13_E~0); 24758#L1356-1 assume !(0 == ~E_M~0); 24759#L1361-1 assume !(0 == ~E_1~0); 26286#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 24799#L1371-1 assume !(0 == ~E_3~0); 24800#L1376-1 assume !(0 == ~E_4~0); 25621#L1381-1 assume !(0 == ~E_5~0); 25622#L1386-1 assume !(0 == ~E_6~0); 26316#L1391-1 assume !(0 == ~E_7~0); 26334#L1396-1 assume !(0 == ~E_8~0); 25534#L1401-1 assume !(0 == ~E_9~0); 25535#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 25813#L1411-1 assume !(0 == ~E_11~0); 25814#L1416-1 assume !(0 == ~E_12~0); 25446#L1421-1 assume !(0 == ~E_13~0); 24989#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24990#L640 assume !(1 == ~m_pc~0); 25499#L640-2 is_master_triggered_~__retres1~0#1 := 0; 25498#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25590#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25484#L1603 assume !(0 != activate_threads_~tmp~1#1); 25485#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25119#L659 assume 1 == ~t1_pc~0; 25120#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25225#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26171#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25245#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 25246#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25259#L678 assume 1 == ~t2_pc~0; 26213#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26214#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26313#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25357#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 25358#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25479#L697 assume !(1 == ~t3_pc~0); 25480#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25602#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25410#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25389#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25390#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26250#L716 assume 1 == ~t4_pc~0; 26236#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25100#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25101#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24600#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 24601#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25892#L735 assume !(1 == ~t5_pc~0); 24561#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 24562#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25012#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25919#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 25555#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25556#L754 assume 1 == ~t6_pc~0; 25309#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25207#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25208#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25181#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 25182#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26002#L773 assume !(1 == ~t7_pc~0); 24762#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 24761#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25591#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25563#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 25564#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25611#L792 assume 1 == ~t8_pc~0; 25784#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26116#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25605#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25558#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 25482#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25483#L811 assume 1 == ~t9_pc~0; 25687#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26153#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26029#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25683#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 25495#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25496#L830 assume !(1 == ~t10_pc~0); 25217#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 24741#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24434#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 24435#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24722#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26020#L849 assume 1 == ~t11_pc~0; 26021#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 24537#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24538#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25127#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 25926#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25927#L868 assume !(1 == ~t12_pc~0); 25342#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 25341#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25136#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 25137#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 24773#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 24774#L887 assume 1 == ~t13_pc~0; 25941#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 25383#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 25384#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 25820#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 24477#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24478#L1439 assume !(1 == ~M_E~0); 25551#L1439-2 assume !(1 == ~T1_E~0); 24649#L1444-1 assume !(1 == ~T2_E~0); 24650#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25123#L1454-1 assume !(1 == ~T4_E~0); 25124#L1459-1 assume !(1 == ~T5_E~0); 25680#L1464-1 assume !(1 == ~T6_E~0); 25681#L1469-1 assume !(1 == ~T7_E~0); 25753#L1474-1 assume !(1 == ~T8_E~0); 25447#L1479-1 assume !(1 == ~T9_E~0); 25448#L1484-1 assume !(1 == ~T10_E~0); 25684#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25330#L1494-1 assume !(1 == ~T12_E~0); 25331#L1499-1 assume !(1 == ~T13_E~0); 25523#L1504-1 assume !(1 == ~E_M~0); 25524#L1509-1 assume !(1 == ~E_1~0); 26099#L1514-1 assume !(1 == ~E_2~0); 25786#L1519-1 assume !(1 == ~E_3~0); 25787#L1524-1 assume !(1 == ~E_4~0); 26299#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 26300#L1534-1 assume !(1 == ~E_6~0); 24470#L1539-1 assume !(1 == ~E_7~0); 24471#L1544-1 assume !(1 == ~E_8~0); 24885#L1549-1 assume !(1 == ~E_9~0); 26274#L1554-1 assume !(1 == ~E_10~0); 26270#L1559-1 assume !(1 == ~E_11~0); 26137#L1564-1 assume !(1 == ~E_12~0); 26138#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 26295#L1574-1 assume { :end_inline_reset_delta_events } true; 24647#L1940-2 [2021-12-07 00:34:13,514 INFO L793 eck$LassoCheckResult]: Loop: 24647#L1940-2 assume !false; 24648#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24930#L1266 assume !false; 25949#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 25178#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24911#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 25302#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 25303#L1079 assume !(0 != eval_~tmp~0#1); 25264#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25265#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25869#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25754#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25755#L1296-3 assume !(0 == ~T2_E~0); 26327#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26281#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25412#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24688#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24689#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24789#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25546#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25795#L1336-3 assume !(0 == ~T10_E~0); 25796#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 25116#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 25096#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 25041#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25042#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25603#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24392#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24393#L1376-3 assume !(0 == ~E_4~0); 26122#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25982#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25983#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 26145#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 26146#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 24755#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 24609#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 24610#L1416-3 assume !(0 == ~E_12~0); 25271#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 25272#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25379#L640-45 assume !(1 == ~m_pc~0); 25380#L640-47 is_master_triggered_~__retres1~0#1 := 0; 24846#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24847#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24386#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24387#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24485#L659-45 assume 1 == ~t1_pc~0; 24486#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24925#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25884#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25885#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25906#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25907#L678-45 assume 1 == ~t2_pc~0; 25850#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25385#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25386#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25538#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26163#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26280#L697-45 assume 1 == ~t3_pc~0; 25643#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25644#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26232#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25802#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25803#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25833#L716-45 assume 1 == ~t4_pc~0; 25464#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25465#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26015#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25470#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25471#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25133#L735-45 assume 1 == ~t5_pc~0; 25134#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25677#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26239#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26240#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26298#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26293#L754-45 assume 1 == ~t6_pc~0; 25625#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25626#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25055#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25056#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25629#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25361#L773-45 assume 1 == ~t7_pc~0; 25362#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24919#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25839#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26121#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 25367#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25037#L792-45 assume 1 == ~t8_pc~0; 25038#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26067#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24640#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24499#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24500#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24995#L811-45 assume 1 == ~t9_pc~0; 24784#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24786#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25994#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25829#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25438#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25230#L830-45 assume !(1 == ~t10_pc~0); 24427#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 24428#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25550#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 24660#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24661#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24406#L849-45 assume !(1 == ~t11_pc~0); 24407#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 24866#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24497#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 24394#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 24395#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24653#L868-45 assume 1 == ~t12_pc~0; 24654#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 24593#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24594#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 25932#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 26183#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 26184#L887-45 assume !(1 == ~t13_pc~0); 24662#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 24663#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 25945#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 26290#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 24625#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24626#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25933#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24645#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24646#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24803#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25734#L1459-3 assume !(1 == ~T5_E~0); 25735#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26186#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26125#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26126#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 26187#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25419#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25420#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 26056#L1499-3 assume !(1 == ~T13_E~0); 25695#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25696#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26134#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26164#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25338#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25339#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26206#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25606#L1539-3 assume !(1 == ~E_7~0); 25082#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25083#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25578#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 24699#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 24700#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 25834#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 25835#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24576#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24347#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24622#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 24583#L1959 assume !(0 == start_simulation_~tmp~3#1); 24585#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24617#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24567#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 25876#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 25997#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26204#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26218#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 26219#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 24647#L1940-2 [2021-12-07 00:34:13,514 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:13,514 INFO L85 PathProgramCache]: Analyzing trace with hash -869878389, now seen corresponding path program 1 times [2021-12-07 00:34:13,514 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:13,514 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2034607036] [2021-12-07 00:34:13,514 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:13,515 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:13,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:13,542 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:13,543 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:13,543 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2034607036] [2021-12-07 00:34:13,543 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2034607036] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:13,543 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:13,543 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:13,543 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [404959013] [2021-12-07 00:34:13,544 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:13,544 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:34:13,544 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:13,544 INFO L85 PathProgramCache]: Analyzing trace with hash 1630672670, now seen corresponding path program 1 times [2021-12-07 00:34:13,545 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:13,545 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [437112373] [2021-12-07 00:34:13,545 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:13,545 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:13,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:13,589 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:13,589 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:13,589 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [437112373] [2021-12-07 00:34:13,590 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [437112373] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:13,590 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:13,590 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:13,590 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [601770344] [2021-12-07 00:34:13,590 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:13,591 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:34:13,591 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:34:13,591 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:34:13,591 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:34:13,592 INFO L87 Difference]: Start difference. First operand 2023 states and 2991 transitions. cyclomatic complexity: 969 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:13,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:34:13,628 INFO L93 Difference]: Finished difference Result 2023 states and 2990 transitions. [2021-12-07 00:34:13,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:34:13,629 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2990 transitions. [2021-12-07 00:34:13,638 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-07 00:34:13,653 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2990 transitions. [2021-12-07 00:34:13,653 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2021-12-07 00:34:13,655 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2021-12-07 00:34:13,655 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2990 transitions. [2021-12-07 00:34:13,658 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:34:13,658 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2990 transitions. [2021-12-07 00:34:13,662 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2990 transitions. [2021-12-07 00:34:13,686 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2021-12-07 00:34:13,689 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4780029658922393) internal successors, (2990), 2022 states have internal predecessors, (2990), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:13,694 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2990 transitions. [2021-12-07 00:34:13,694 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2990 transitions. [2021-12-07 00:34:13,694 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2990 transitions. [2021-12-07 00:34:13,694 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-07 00:34:13,694 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2990 transitions. [2021-12-07 00:34:13,699 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-07 00:34:13,699 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:34:13,699 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:34:13,700 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:13,700 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:13,701 INFO L791 eck$LassoCheckResult]: Stem: 29314#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 29315#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 30313#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30314#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30399#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 29778#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29247#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29248#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30064#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30065#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30165#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30166#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 29019#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 29020#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 30195#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29555#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29556#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 30116#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 29457#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29458#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 30400#L1291-2 assume !(0 == ~T1_E~0); 30398#L1296-1 assume !(0 == ~T2_E~0); 29614#L1301-1 assume !(0 == ~T3_E~0); 29615#L1306-1 assume !(0 == ~T4_E~0); 30124#L1311-1 assume !(0 == ~T5_E~0); 28862#L1316-1 assume !(0 == ~T6_E~0); 28863#L1321-1 assume !(0 == ~T7_E~0); 29627#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28690#L1331-1 assume !(0 == ~T9_E~0); 28389#L1336-1 assume !(0 == ~T10_E~0); 28390#L1341-1 assume !(0 == ~T11_E~0); 28470#L1346-1 assume !(0 == ~T12_E~0); 28471#L1351-1 assume !(0 == ~T13_E~0); 28811#L1356-1 assume !(0 == ~E_M~0); 28812#L1361-1 assume !(0 == ~E_1~0); 30339#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 28852#L1371-1 assume !(0 == ~E_3~0); 28853#L1376-1 assume !(0 == ~E_4~0); 29674#L1381-1 assume !(0 == ~E_5~0); 29675#L1386-1 assume !(0 == ~E_6~0); 30369#L1391-1 assume !(0 == ~E_7~0); 30387#L1396-1 assume !(0 == ~E_8~0); 29587#L1401-1 assume !(0 == ~E_9~0); 29588#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 29866#L1411-1 assume !(0 == ~E_11~0); 29867#L1416-1 assume !(0 == ~E_12~0); 29499#L1421-1 assume !(0 == ~E_13~0); 29042#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29043#L640 assume !(1 == ~m_pc~0); 29552#L640-2 is_master_triggered_~__retres1~0#1 := 0; 29551#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29643#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29537#L1603 assume !(0 != activate_threads_~tmp~1#1); 29538#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29172#L659 assume 1 == ~t1_pc~0; 29173#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29278#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30224#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29298#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 29299#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29312#L678 assume 1 == ~t2_pc~0; 30266#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30267#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30366#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29410#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 29411#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29532#L697 assume !(1 == ~t3_pc~0); 29533#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29655#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29463#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29442#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29443#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30303#L716 assume 1 == ~t4_pc~0; 30289#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29153#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29154#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28653#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 28654#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29945#L735 assume !(1 == ~t5_pc~0); 28614#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 28615#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29065#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29972#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 29608#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29609#L754 assume 1 == ~t6_pc~0; 29362#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29260#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29261#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29234#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 29235#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30055#L773 assume !(1 == ~t7_pc~0); 28815#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 28814#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29644#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29616#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 29617#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29664#L792 assume 1 == ~t8_pc~0; 29837#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30169#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29658#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29611#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 29535#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29536#L811 assume 1 == ~t9_pc~0; 29740#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30206#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30082#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29736#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 29548#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29549#L830 assume !(1 == ~t10_pc~0); 29270#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 28794#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28487#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28488#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28775#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30073#L849 assume 1 == ~t11_pc~0; 30074#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28590#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28591#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 29180#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 29979#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29980#L868 assume !(1 == ~t12_pc~0); 29395#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 29394#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 29189#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 29190#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 28826#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 28827#L887 assume 1 == ~t13_pc~0; 29994#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 29436#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 29437#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 29873#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 28530#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28531#L1439 assume !(1 == ~M_E~0); 29604#L1439-2 assume !(1 == ~T1_E~0); 28702#L1444-1 assume !(1 == ~T2_E~0); 28703#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29176#L1454-1 assume !(1 == ~T4_E~0); 29177#L1459-1 assume !(1 == ~T5_E~0); 29733#L1464-1 assume !(1 == ~T6_E~0); 29734#L1469-1 assume !(1 == ~T7_E~0); 29806#L1474-1 assume !(1 == ~T8_E~0); 29500#L1479-1 assume !(1 == ~T9_E~0); 29501#L1484-1 assume !(1 == ~T10_E~0); 29737#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29383#L1494-1 assume !(1 == ~T12_E~0); 29384#L1499-1 assume !(1 == ~T13_E~0); 29576#L1504-1 assume !(1 == ~E_M~0); 29577#L1509-1 assume !(1 == ~E_1~0); 30152#L1514-1 assume !(1 == ~E_2~0); 29839#L1519-1 assume !(1 == ~E_3~0); 29840#L1524-1 assume !(1 == ~E_4~0); 30352#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 30353#L1534-1 assume !(1 == ~E_6~0); 28523#L1539-1 assume !(1 == ~E_7~0); 28524#L1544-1 assume !(1 == ~E_8~0); 28938#L1549-1 assume !(1 == ~E_9~0); 30327#L1554-1 assume !(1 == ~E_10~0); 30323#L1559-1 assume !(1 == ~E_11~0); 30190#L1564-1 assume !(1 == ~E_12~0); 30191#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 30348#L1574-1 assume { :end_inline_reset_delta_events } true; 28700#L1940-2 [2021-12-07 00:34:13,701 INFO L793 eck$LassoCheckResult]: Loop: 28700#L1940-2 assume !false; 28701#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28983#L1266 assume !false; 30002#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 29231#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28964#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 29355#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 29356#L1079 assume !(0 != eval_~tmp~0#1); 29317#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29318#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29922#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29807#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29808#L1296-3 assume !(0 == ~T2_E~0); 30380#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30334#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29465#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28741#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28742#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28842#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29599#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29848#L1336-3 assume !(0 == ~T10_E~0); 29849#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29169#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 29149#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 29094#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29095#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29656#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 28445#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 28446#L1376-3 assume !(0 == ~E_4~0); 30175#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30035#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30036#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30198#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30199#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 28808#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 28662#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28663#L1416-3 assume !(0 == ~E_12~0); 29324#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 29325#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29432#L640-45 assume !(1 == ~m_pc~0); 29433#L640-47 is_master_triggered_~__retres1~0#1 := 0; 28899#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28900#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28439#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28440#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28538#L659-45 assume 1 == ~t1_pc~0; 28539#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 28978#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29937#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29938#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29959#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29960#L678-45 assume !(1 == ~t2_pc~0); 29904#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 29438#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29439#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29591#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30216#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30333#L697-45 assume 1 == ~t3_pc~0; 29696#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29697#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30285#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29855#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29856#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29886#L716-45 assume 1 == ~t4_pc~0; 29517#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29518#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30068#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29523#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29524#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29186#L735-45 assume 1 == ~t5_pc~0; 29187#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29730#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30292#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30293#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30351#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30346#L754-45 assume !(1 == ~t6_pc~0); 29680#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 29679#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29108#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29109#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29682#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29414#L773-45 assume 1 == ~t7_pc~0; 29415#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28972#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29892#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30174#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 29420#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29090#L792-45 assume 1 == ~t8_pc~0; 29091#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30120#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28693#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28552#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28553#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29048#L811-45 assume 1 == ~t9_pc~0; 28837#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28839#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30047#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29882#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29491#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29283#L830-45 assume !(1 == ~t10_pc~0); 28480#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 28481#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29603#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28713#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28714#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28459#L849-45 assume !(1 == ~t11_pc~0); 28460#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 28919#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28550#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28447#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28448#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 28706#L868-45 assume 1 == ~t12_pc~0; 28707#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 28646#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28647#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 29985#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 30236#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 30237#L887-45 assume 1 == ~t13_pc~0; 30067#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 28716#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 29998#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 30343#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 28678#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28679#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29986#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28698#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28699#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28856#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29787#L1459-3 assume !(1 == ~T5_E~0); 29788#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30239#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30178#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30179#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30240#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29472#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29473#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 30109#L1499-3 assume !(1 == ~T13_E~0); 29748#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29749#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30187#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30217#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 29391#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29392#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30259#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29659#L1539-3 assume !(1 == ~E_7~0); 29135#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 29136#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 29631#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 28752#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 28753#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 29887#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 29888#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28629#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28400#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28675#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 28636#L1959 assume !(0 == start_simulation_~tmp~3#1); 28638#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28670#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28620#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 29929#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 30050#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30257#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30271#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 30272#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 28700#L1940-2 [2021-12-07 00:34:13,701 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:13,701 INFO L85 PathProgramCache]: Analyzing trace with hash 1978508041, now seen corresponding path program 1 times [2021-12-07 00:34:13,702 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:13,702 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1951133399] [2021-12-07 00:34:13,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:13,702 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:13,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:13,727 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:13,728 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:13,728 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1951133399] [2021-12-07 00:34:13,728 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1951133399] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:13,728 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:13,728 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:13,728 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1872088344] [2021-12-07 00:34:13,728 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:13,729 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:34:13,729 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:13,729 INFO L85 PathProgramCache]: Analyzing trace with hash -1140908257, now seen corresponding path program 1 times [2021-12-07 00:34:13,729 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:13,729 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1702427140] [2021-12-07 00:34:13,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:13,730 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:13,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:13,764 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:13,764 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:13,764 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1702427140] [2021-12-07 00:34:13,764 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1702427140] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:13,765 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:13,765 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:13,765 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1571605859] [2021-12-07 00:34:13,765 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:13,765 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:34:13,765 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:34:13,766 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:34:13,766 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:34:13,766 INFO L87 Difference]: Start difference. First operand 2023 states and 2990 transitions. cyclomatic complexity: 968 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:13,784 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:34:13,784 INFO L93 Difference]: Finished difference Result 2023 states and 2989 transitions. [2021-12-07 00:34:13,784 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:34:13,785 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2989 transitions. [2021-12-07 00:34:13,791 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-07 00:34:13,801 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2989 transitions. [2021-12-07 00:34:13,801 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2021-12-07 00:34:13,802 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2021-12-07 00:34:13,802 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2989 transitions. [2021-12-07 00:34:13,804 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:34:13,804 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2989 transitions. [2021-12-07 00:34:13,807 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2989 transitions. [2021-12-07 00:34:13,825 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2021-12-07 00:34:13,828 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4775086505190311) internal successors, (2989), 2022 states have internal predecessors, (2989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:13,831 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2989 transitions. [2021-12-07 00:34:13,831 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2989 transitions. [2021-12-07 00:34:13,832 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2989 transitions. [2021-12-07 00:34:13,832 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-07 00:34:13,832 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2989 transitions. [2021-12-07 00:34:13,836 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-07 00:34:13,836 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:34:13,836 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:34:13,838 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:13,838 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:13,838 INFO L791 eck$LassoCheckResult]: Stem: 33367#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 33368#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 34366#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34367#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34452#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 33831#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33300#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33301#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34117#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34118#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34218#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34219#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 33072#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 33073#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 34248#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 33608#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33609#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 34169#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 33510#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33511#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 34453#L1291-2 assume !(0 == ~T1_E~0); 34451#L1296-1 assume !(0 == ~T2_E~0); 33667#L1301-1 assume !(0 == ~T3_E~0); 33668#L1306-1 assume !(0 == ~T4_E~0); 34177#L1311-1 assume !(0 == ~T5_E~0); 32915#L1316-1 assume !(0 == ~T6_E~0); 32916#L1321-1 assume !(0 == ~T7_E~0); 33680#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32743#L1331-1 assume !(0 == ~T9_E~0); 32442#L1336-1 assume !(0 == ~T10_E~0); 32443#L1341-1 assume !(0 == ~T11_E~0); 32523#L1346-1 assume !(0 == ~T12_E~0); 32524#L1351-1 assume !(0 == ~T13_E~0); 32864#L1356-1 assume !(0 == ~E_M~0); 32865#L1361-1 assume !(0 == ~E_1~0); 34392#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 32905#L1371-1 assume !(0 == ~E_3~0); 32906#L1376-1 assume !(0 == ~E_4~0); 33727#L1381-1 assume !(0 == ~E_5~0); 33728#L1386-1 assume !(0 == ~E_6~0); 34422#L1391-1 assume !(0 == ~E_7~0); 34440#L1396-1 assume !(0 == ~E_8~0); 33640#L1401-1 assume !(0 == ~E_9~0); 33641#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 33919#L1411-1 assume !(0 == ~E_11~0); 33920#L1416-1 assume !(0 == ~E_12~0); 33552#L1421-1 assume !(0 == ~E_13~0); 33095#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33096#L640 assume !(1 == ~m_pc~0); 33605#L640-2 is_master_triggered_~__retres1~0#1 := 0; 33604#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33696#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33590#L1603 assume !(0 != activate_threads_~tmp~1#1); 33591#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33225#L659 assume 1 == ~t1_pc~0; 33226#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33331#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34277#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33351#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 33352#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33365#L678 assume 1 == ~t2_pc~0; 34319#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34320#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34419#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33463#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 33464#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33585#L697 assume !(1 == ~t3_pc~0); 33586#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33708#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33516#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33495#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33496#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34356#L716 assume 1 == ~t4_pc~0; 34342#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33206#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33207#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32706#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 32707#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33998#L735 assume !(1 == ~t5_pc~0); 32667#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 32668#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33118#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34025#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 33661#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33662#L754 assume 1 == ~t6_pc~0; 33415#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33313#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33314#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33287#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 33288#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34108#L773 assume !(1 == ~t7_pc~0); 32868#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 32867#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33697#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33669#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 33670#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33717#L792 assume 1 == ~t8_pc~0; 33890#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 34222#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33711#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33664#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 33588#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33589#L811 assume 1 == ~t9_pc~0; 33793#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34259#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34135#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33789#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 33601#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33602#L830 assume !(1 == ~t10_pc~0); 33323#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 32847#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32540#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32541#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32828#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34126#L849 assume 1 == ~t11_pc~0; 34127#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32643#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32644#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 33233#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 34032#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 34033#L868 assume !(1 == ~t12_pc~0); 33448#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 33447#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 33242#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 33243#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 32879#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 32880#L887 assume 1 == ~t13_pc~0; 34047#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 33489#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 33490#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 33926#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 32583#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32584#L1439 assume !(1 == ~M_E~0); 33657#L1439-2 assume !(1 == ~T1_E~0); 32755#L1444-1 assume !(1 == ~T2_E~0); 32756#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33229#L1454-1 assume !(1 == ~T4_E~0); 33230#L1459-1 assume !(1 == ~T5_E~0); 33786#L1464-1 assume !(1 == ~T6_E~0); 33787#L1469-1 assume !(1 == ~T7_E~0); 33859#L1474-1 assume !(1 == ~T8_E~0); 33553#L1479-1 assume !(1 == ~T9_E~0); 33554#L1484-1 assume !(1 == ~T10_E~0); 33790#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33436#L1494-1 assume !(1 == ~T12_E~0); 33437#L1499-1 assume !(1 == ~T13_E~0); 33629#L1504-1 assume !(1 == ~E_M~0); 33630#L1509-1 assume !(1 == ~E_1~0); 34205#L1514-1 assume !(1 == ~E_2~0); 33892#L1519-1 assume !(1 == ~E_3~0); 33893#L1524-1 assume !(1 == ~E_4~0); 34405#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 34406#L1534-1 assume !(1 == ~E_6~0); 32576#L1539-1 assume !(1 == ~E_7~0); 32577#L1544-1 assume !(1 == ~E_8~0); 32991#L1549-1 assume !(1 == ~E_9~0); 34380#L1554-1 assume !(1 == ~E_10~0); 34376#L1559-1 assume !(1 == ~E_11~0); 34243#L1564-1 assume !(1 == ~E_12~0); 34244#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 34401#L1574-1 assume { :end_inline_reset_delta_events } true; 32753#L1940-2 [2021-12-07 00:34:13,838 INFO L793 eck$LassoCheckResult]: Loop: 32753#L1940-2 assume !false; 32754#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33036#L1266 assume !false; 34055#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 33284#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 33017#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 33408#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 33409#L1079 assume !(0 != eval_~tmp~0#1); 33370#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33371#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33975#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33860#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33861#L1296-3 assume !(0 == ~T2_E~0); 34433#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34387#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33518#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32794#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32795#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 32895#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33652#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33901#L1336-3 assume !(0 == ~T10_E~0); 33902#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 33222#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 33202#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 33147#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 33148#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33709#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32498#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32499#L1376-3 assume !(0 == ~E_4~0); 34228#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 34088#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 34089#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34251#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 34252#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 32861#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 32715#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32716#L1416-3 assume !(0 == ~E_12~0); 33377#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 33378#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33485#L640-45 assume !(1 == ~m_pc~0); 33486#L640-47 is_master_triggered_~__retres1~0#1 := 0; 32952#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32953#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32492#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 32493#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32591#L659-45 assume 1 == ~t1_pc~0; 32592#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33031#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33990#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33991#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34012#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34013#L678-45 assume 1 == ~t2_pc~0; 33956#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 33491#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33492#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33644#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34269#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34386#L697-45 assume 1 == ~t3_pc~0; 33749#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33750#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34338#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33908#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33909#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33939#L716-45 assume 1 == ~t4_pc~0; 33570#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33571#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34121#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33576#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33577#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33239#L735-45 assume 1 == ~t5_pc~0; 33240#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33783#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34345#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34346#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 34404#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34399#L754-45 assume 1 == ~t6_pc~0; 33731#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33732#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33161#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33162#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33735#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33467#L773-45 assume !(1 == ~t7_pc~0); 33024#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 33025#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33945#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34227#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 33473#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33143#L792-45 assume 1 == ~t8_pc~0; 33144#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 34173#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32746#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32605#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32606#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33101#L811-45 assume 1 == ~t9_pc~0; 32890#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32892#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34100#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33935#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 33544#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33336#L830-45 assume !(1 == ~t10_pc~0); 32533#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 32534#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33656#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32766#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32767#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32512#L849-45 assume !(1 == ~t11_pc~0); 32513#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 32972#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32603#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32500#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32501#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32759#L868-45 assume 1 == ~t12_pc~0; 32760#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 32699#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32700#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 34038#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 34289#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 34290#L887-45 assume !(1 == ~t13_pc~0); 32768#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 32769#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 34051#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 34396#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 32731#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32732#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 34039#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32751#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32752#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32909#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33840#L1459-3 assume !(1 == ~T5_E~0); 33841#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34292#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34231#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 34232#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34293#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33525#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33526#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 34162#L1499-3 assume !(1 == ~T13_E~0); 33801#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33802#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34240#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 34270#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33444#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33445#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 34312#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33712#L1539-3 assume !(1 == ~E_7~0); 33188#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 33189#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 33684#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32805#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 32806#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 33940#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 33941#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32682#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32453#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 32728#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 32689#L1959 assume !(0 == start_simulation_~tmp~3#1); 32691#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32723#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32673#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 33982#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 34103#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34310#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34324#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 34325#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 32753#L1940-2 [2021-12-07 00:34:13,839 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:13,839 INFO L85 PathProgramCache]: Analyzing trace with hash -1393291829, now seen corresponding path program 1 times [2021-12-07 00:34:13,839 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:13,839 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2075262554] [2021-12-07 00:34:13,839 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:13,839 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:13,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:13,864 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:13,864 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:13,864 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2075262554] [2021-12-07 00:34:13,864 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2075262554] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:13,865 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:13,865 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:13,865 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1627157917] [2021-12-07 00:34:13,865 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:13,865 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:34:13,865 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:13,866 INFO L85 PathProgramCache]: Analyzing trace with hash 230524959, now seen corresponding path program 2 times [2021-12-07 00:34:13,866 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:13,866 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [752815861] [2021-12-07 00:34:13,866 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:13,866 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:13,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:13,910 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:13,910 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:13,910 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [752815861] [2021-12-07 00:34:13,910 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [752815861] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:13,910 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:13,910 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:13,910 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1932391423] [2021-12-07 00:34:13,910 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:13,911 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:34:13,911 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:34:13,911 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:34:13,911 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:34:13,911 INFO L87 Difference]: Start difference. First operand 2023 states and 2989 transitions. cyclomatic complexity: 967 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:13,927 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:34:13,927 INFO L93 Difference]: Finished difference Result 2023 states and 2988 transitions. [2021-12-07 00:34:13,928 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:34:13,928 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2988 transitions. [2021-12-07 00:34:13,934 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-07 00:34:13,944 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2988 transitions. [2021-12-07 00:34:13,944 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2021-12-07 00:34:13,945 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2021-12-07 00:34:13,945 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2988 transitions. [2021-12-07 00:34:13,947 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:34:13,947 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2988 transitions. [2021-12-07 00:34:13,950 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2988 transitions. [2021-12-07 00:34:13,967 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2021-12-07 00:34:13,970 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4770143351458231) internal successors, (2988), 2022 states have internal predecessors, (2988), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:13,973 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2988 transitions. [2021-12-07 00:34:13,973 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2988 transitions. [2021-12-07 00:34:13,974 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2988 transitions. [2021-12-07 00:34:13,974 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-07 00:34:13,974 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2988 transitions. [2021-12-07 00:34:13,978 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-07 00:34:13,978 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:34:13,978 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:34:13,980 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:13,980 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:13,980 INFO L791 eck$LassoCheckResult]: Stem: 37420#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 37421#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 38419#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38420#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38505#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 37884#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37353#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37354#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38170#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38171#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 38271#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 38272#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37125#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37126#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 38301#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 37661#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37662#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 38222#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 37563#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37564#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 38506#L1291-2 assume !(0 == ~T1_E~0); 38504#L1296-1 assume !(0 == ~T2_E~0); 37720#L1301-1 assume !(0 == ~T3_E~0); 37721#L1306-1 assume !(0 == ~T4_E~0); 38230#L1311-1 assume !(0 == ~T5_E~0); 36968#L1316-1 assume !(0 == ~T6_E~0); 36969#L1321-1 assume !(0 == ~T7_E~0); 37733#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36796#L1331-1 assume !(0 == ~T9_E~0); 36495#L1336-1 assume !(0 == ~T10_E~0); 36496#L1341-1 assume !(0 == ~T11_E~0); 36576#L1346-1 assume !(0 == ~T12_E~0); 36577#L1351-1 assume !(0 == ~T13_E~0); 36917#L1356-1 assume !(0 == ~E_M~0); 36918#L1361-1 assume !(0 == ~E_1~0); 38445#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 36958#L1371-1 assume !(0 == ~E_3~0); 36959#L1376-1 assume !(0 == ~E_4~0); 37780#L1381-1 assume !(0 == ~E_5~0); 37781#L1386-1 assume !(0 == ~E_6~0); 38475#L1391-1 assume !(0 == ~E_7~0); 38493#L1396-1 assume !(0 == ~E_8~0); 37693#L1401-1 assume !(0 == ~E_9~0); 37694#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 37972#L1411-1 assume !(0 == ~E_11~0); 37973#L1416-1 assume !(0 == ~E_12~0); 37605#L1421-1 assume !(0 == ~E_13~0); 37148#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37149#L640 assume !(1 == ~m_pc~0); 37658#L640-2 is_master_triggered_~__retres1~0#1 := 0; 37657#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37749#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37643#L1603 assume !(0 != activate_threads_~tmp~1#1); 37644#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37278#L659 assume 1 == ~t1_pc~0; 37279#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37384#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38330#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37404#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 37405#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37418#L678 assume 1 == ~t2_pc~0; 38372#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38373#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38472#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37516#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 37517#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37638#L697 assume !(1 == ~t3_pc~0); 37639#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37761#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37569#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37548#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37549#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38409#L716 assume 1 == ~t4_pc~0; 38395#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37259#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37260#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36759#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 36760#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38051#L735 assume !(1 == ~t5_pc~0); 36720#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 36721#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37171#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38078#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 37714#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37715#L754 assume 1 == ~t6_pc~0; 37468#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37366#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37367#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37340#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 37341#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38161#L773 assume !(1 == ~t7_pc~0); 36921#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 36920#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37750#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37722#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 37723#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37770#L792 assume 1 == ~t8_pc~0; 37943#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38275#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37764#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37717#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 37641#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37642#L811 assume 1 == ~t9_pc~0; 37846#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 38312#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38188#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37842#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 37654#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37655#L830 assume !(1 == ~t10_pc~0); 37376#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36900#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36593#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36594#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 36881#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38179#L849 assume 1 == ~t11_pc~0; 38180#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 36696#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36697#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 37286#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 38085#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 38086#L868 assume !(1 == ~t12_pc~0); 37501#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 37500#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37295#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 37296#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 36932#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 36933#L887 assume 1 == ~t13_pc~0; 38100#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 37542#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 37543#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 37979#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 36636#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36637#L1439 assume !(1 == ~M_E~0); 37710#L1439-2 assume !(1 == ~T1_E~0); 36808#L1444-1 assume !(1 == ~T2_E~0); 36809#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37282#L1454-1 assume !(1 == ~T4_E~0); 37283#L1459-1 assume !(1 == ~T5_E~0); 37839#L1464-1 assume !(1 == ~T6_E~0); 37840#L1469-1 assume !(1 == ~T7_E~0); 37912#L1474-1 assume !(1 == ~T8_E~0); 37606#L1479-1 assume !(1 == ~T9_E~0); 37607#L1484-1 assume !(1 == ~T10_E~0); 37843#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37489#L1494-1 assume !(1 == ~T12_E~0); 37490#L1499-1 assume !(1 == ~T13_E~0); 37682#L1504-1 assume !(1 == ~E_M~0); 37683#L1509-1 assume !(1 == ~E_1~0); 38258#L1514-1 assume !(1 == ~E_2~0); 37945#L1519-1 assume !(1 == ~E_3~0); 37946#L1524-1 assume !(1 == ~E_4~0); 38458#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 38459#L1534-1 assume !(1 == ~E_6~0); 36629#L1539-1 assume !(1 == ~E_7~0); 36630#L1544-1 assume !(1 == ~E_8~0); 37044#L1549-1 assume !(1 == ~E_9~0); 38433#L1554-1 assume !(1 == ~E_10~0); 38429#L1559-1 assume !(1 == ~E_11~0); 38296#L1564-1 assume !(1 == ~E_12~0); 38297#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 38454#L1574-1 assume { :end_inline_reset_delta_events } true; 36806#L1940-2 [2021-12-07 00:34:13,980 INFO L793 eck$LassoCheckResult]: Loop: 36806#L1940-2 assume !false; 36807#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37089#L1266 assume !false; 38108#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 37337#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 37070#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 37461#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 37462#L1079 assume !(0 != eval_~tmp~0#1); 37423#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37424#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 38028#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37913#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37914#L1296-3 assume !(0 == ~T2_E~0); 38486#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38440#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37571#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36847#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36848#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36948#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37705#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37954#L1336-3 assume !(0 == ~T10_E~0); 37955#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 37275#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 37255#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 37200#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 37201#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37762#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36551#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36552#L1376-3 assume !(0 == ~E_4~0); 38281#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38141#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38142#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 38304#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 38305#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 36914#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 36768#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36769#L1416-3 assume !(0 == ~E_12~0); 37430#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 37431#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37538#L640-45 assume !(1 == ~m_pc~0); 37539#L640-47 is_master_triggered_~__retres1~0#1 := 0; 37005#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37006#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36545#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36546#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36644#L659-45 assume 1 == ~t1_pc~0; 36645#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37084#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38043#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38044#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38065#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38066#L678-45 assume 1 == ~t2_pc~0; 38009#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 37544#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37545#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37697#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38322#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38439#L697-45 assume 1 == ~t3_pc~0; 37802#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37803#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38391#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37961#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37962#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37992#L716-45 assume 1 == ~t4_pc~0; 37623#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37624#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38174#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37629#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37630#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37292#L735-45 assume 1 == ~t5_pc~0; 37293#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37836#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38398#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38399#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38457#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38452#L754-45 assume 1 == ~t6_pc~0; 37784#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37785#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37214#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37215#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 37788#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37520#L773-45 assume 1 == ~t7_pc~0; 37521#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37078#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37998#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38280#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 37526#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37196#L792-45 assume 1 == ~t8_pc~0; 37197#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38226#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36799#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36658#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36659#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37154#L811-45 assume !(1 == ~t9_pc~0); 36944#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 36945#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38153#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37988#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 37597#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37389#L830-45 assume !(1 == ~t10_pc~0); 36586#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 36587#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37709#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36819#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 36820#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36565#L849-45 assume !(1 == ~t11_pc~0); 36566#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 37025#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36656#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 36553#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 36554#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 36812#L868-45 assume 1 == ~t12_pc~0; 36813#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 36752#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36753#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 38091#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 38342#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 38343#L887-45 assume !(1 == ~t13_pc~0); 36821#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 36822#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 38104#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 38449#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 36784#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36785#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 38092#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36804#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36805#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36962#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37893#L1459-3 assume !(1 == ~T5_E~0); 37894#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 38345#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38284#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38285#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38346#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 37578#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37579#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 38215#L1499-3 assume !(1 == ~T13_E~0); 37854#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37855#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 38293#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38323#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37497#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37498#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38365#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 37765#L1539-3 assume !(1 == ~E_7~0); 37241#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37242#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 37737#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 36858#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 36859#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 37993#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 37994#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36735#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36506#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 36781#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 36742#L1959 assume !(0 == start_simulation_~tmp~3#1); 36744#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36776#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36726#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 38035#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 38156#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38363#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38377#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 38378#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 36806#L1940-2 [2021-12-07 00:34:13,981 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:13,981 INFO L85 PathProgramCache]: Analyzing trace with hash -1779154231, now seen corresponding path program 1 times [2021-12-07 00:34:13,981 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:13,981 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1535166210] [2021-12-07 00:34:13,981 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:13,981 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:13,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:14,007 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:14,007 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:14,007 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1535166210] [2021-12-07 00:34:14,007 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1535166210] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:14,008 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:14,008 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:14,008 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [496209251] [2021-12-07 00:34:14,008 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:14,008 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:34:14,008 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:14,008 INFO L85 PathProgramCache]: Analyzing trace with hash -324648545, now seen corresponding path program 1 times [2021-12-07 00:34:14,009 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:14,009 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [587755596] [2021-12-07 00:34:14,009 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:14,009 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:14,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:14,044 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:14,044 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:14,044 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [587755596] [2021-12-07 00:34:14,044 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [587755596] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:14,044 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:14,045 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:14,045 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1610056733] [2021-12-07 00:34:14,045 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:14,045 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:34:14,045 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:34:14,046 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:34:14,046 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:34:14,046 INFO L87 Difference]: Start difference. First operand 2023 states and 2988 transitions. cyclomatic complexity: 966 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:14,069 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:34:14,069 INFO L93 Difference]: Finished difference Result 2023 states and 2987 transitions. [2021-12-07 00:34:14,069 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:34:14,070 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2987 transitions. [2021-12-07 00:34:14,077 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-07 00:34:14,086 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2987 transitions. [2021-12-07 00:34:14,087 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2021-12-07 00:34:14,088 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2021-12-07 00:34:14,088 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2987 transitions. [2021-12-07 00:34:14,090 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:34:14,090 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2987 transitions. [2021-12-07 00:34:14,093 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2987 transitions. [2021-12-07 00:34:14,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2021-12-07 00:34:14,113 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.476520019772615) internal successors, (2987), 2022 states have internal predecessors, (2987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:14,118 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2987 transitions. [2021-12-07 00:34:14,118 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2987 transitions. [2021-12-07 00:34:14,118 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2987 transitions. [2021-12-07 00:34:14,118 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-07 00:34:14,118 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2987 transitions. [2021-12-07 00:34:14,123 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-07 00:34:14,123 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:34:14,123 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:34:14,124 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:14,124 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:14,125 INFO L791 eck$LassoCheckResult]: Stem: 41473#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 41474#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 42472#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42473#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42558#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 41937#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41406#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41407#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42223#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42224#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 42324#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 42325#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41178#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41179#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 42354#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 41714#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 41715#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 42275#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 41616#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41617#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 42559#L1291-2 assume !(0 == ~T1_E~0); 42557#L1296-1 assume !(0 == ~T2_E~0); 41773#L1301-1 assume !(0 == ~T3_E~0); 41774#L1306-1 assume !(0 == ~T4_E~0); 42283#L1311-1 assume !(0 == ~T5_E~0); 41021#L1316-1 assume !(0 == ~T6_E~0); 41022#L1321-1 assume !(0 == ~T7_E~0); 41786#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40849#L1331-1 assume !(0 == ~T9_E~0); 40548#L1336-1 assume !(0 == ~T10_E~0); 40549#L1341-1 assume !(0 == ~T11_E~0); 40629#L1346-1 assume !(0 == ~T12_E~0); 40630#L1351-1 assume !(0 == ~T13_E~0); 40970#L1356-1 assume !(0 == ~E_M~0); 40971#L1361-1 assume !(0 == ~E_1~0); 42498#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 41011#L1371-1 assume !(0 == ~E_3~0); 41012#L1376-1 assume !(0 == ~E_4~0); 41833#L1381-1 assume !(0 == ~E_5~0); 41834#L1386-1 assume !(0 == ~E_6~0); 42528#L1391-1 assume !(0 == ~E_7~0); 42546#L1396-1 assume !(0 == ~E_8~0); 41746#L1401-1 assume !(0 == ~E_9~0); 41747#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 42025#L1411-1 assume !(0 == ~E_11~0); 42026#L1416-1 assume !(0 == ~E_12~0); 41658#L1421-1 assume !(0 == ~E_13~0); 41201#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41202#L640 assume !(1 == ~m_pc~0); 41711#L640-2 is_master_triggered_~__retres1~0#1 := 0; 41710#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41802#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41696#L1603 assume !(0 != activate_threads_~tmp~1#1); 41697#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41331#L659 assume 1 == ~t1_pc~0; 41332#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41437#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42383#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41457#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 41458#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41471#L678 assume 1 == ~t2_pc~0; 42425#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42426#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42525#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41569#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 41570#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41691#L697 assume !(1 == ~t3_pc~0); 41692#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41814#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41622#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41601#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41602#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42462#L716 assume 1 == ~t4_pc~0; 42448#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41312#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41313#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40812#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 40813#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 42104#L735 assume !(1 == ~t5_pc~0); 40773#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 40774#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41224#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42131#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 41767#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41768#L754 assume 1 == ~t6_pc~0; 41521#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41419#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41420#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41393#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 41394#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42214#L773 assume !(1 == ~t7_pc~0); 40974#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 40973#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41803#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41775#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 41776#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41823#L792 assume 1 == ~t8_pc~0; 41996#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 42328#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41817#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41770#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 41694#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41695#L811 assume 1 == ~t9_pc~0; 41899#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 42365#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42241#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41895#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 41707#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41708#L830 assume !(1 == ~t10_pc~0); 41429#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 40953#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40646#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 40647#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 40934#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 42232#L849 assume 1 == ~t11_pc~0; 42233#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 40749#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40750#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 41339#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 42138#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 42139#L868 assume !(1 == ~t12_pc~0); 41554#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 41553#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 41348#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 41349#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 40985#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 40986#L887 assume 1 == ~t13_pc~0; 42153#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 41595#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 41596#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 42032#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 40689#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40690#L1439 assume !(1 == ~M_E~0); 41763#L1439-2 assume !(1 == ~T1_E~0); 40861#L1444-1 assume !(1 == ~T2_E~0); 40862#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41335#L1454-1 assume !(1 == ~T4_E~0); 41336#L1459-1 assume !(1 == ~T5_E~0); 41892#L1464-1 assume !(1 == ~T6_E~0); 41893#L1469-1 assume !(1 == ~T7_E~0); 41965#L1474-1 assume !(1 == ~T8_E~0); 41659#L1479-1 assume !(1 == ~T9_E~0); 41660#L1484-1 assume !(1 == ~T10_E~0); 41896#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41542#L1494-1 assume !(1 == ~T12_E~0); 41543#L1499-1 assume !(1 == ~T13_E~0); 41735#L1504-1 assume !(1 == ~E_M~0); 41736#L1509-1 assume !(1 == ~E_1~0); 42311#L1514-1 assume !(1 == ~E_2~0); 41998#L1519-1 assume !(1 == ~E_3~0); 41999#L1524-1 assume !(1 == ~E_4~0); 42511#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 42512#L1534-1 assume !(1 == ~E_6~0); 40682#L1539-1 assume !(1 == ~E_7~0); 40683#L1544-1 assume !(1 == ~E_8~0); 41097#L1549-1 assume !(1 == ~E_9~0); 42486#L1554-1 assume !(1 == ~E_10~0); 42482#L1559-1 assume !(1 == ~E_11~0); 42349#L1564-1 assume !(1 == ~E_12~0); 42350#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 42507#L1574-1 assume { :end_inline_reset_delta_events } true; 40859#L1940-2 [2021-12-07 00:34:14,125 INFO L793 eck$LassoCheckResult]: Loop: 40859#L1940-2 assume !false; 40860#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41142#L1266 assume !false; 42161#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 41390#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 41123#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 41514#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 41515#L1079 assume !(0 != eval_~tmp~0#1); 41476#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41477#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 42081#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 41966#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41967#L1296-3 assume !(0 == ~T2_E~0); 42539#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 42493#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 41624#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40900#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 40901#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 41001#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41758#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 42007#L1336-3 assume !(0 == ~T10_E~0); 42008#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 41328#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 41308#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 41253#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 41254#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 41815#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40604#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40605#L1376-3 assume !(0 == ~E_4~0); 42334#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42194#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 42195#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 42357#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 42358#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 40967#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 40821#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 40822#L1416-3 assume !(0 == ~E_12~0); 41483#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 41484#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41591#L640-45 assume !(1 == ~m_pc~0); 41592#L640-47 is_master_triggered_~__retres1~0#1 := 0; 41058#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41059#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40598#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 40599#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40697#L659-45 assume 1 == ~t1_pc~0; 40698#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41137#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42096#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42097#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42118#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42119#L678-45 assume 1 == ~t2_pc~0; 42062#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41597#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41598#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41750#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42375#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42492#L697-45 assume !(1 == ~t3_pc~0); 41857#L697-47 is_transmit3_triggered_~__retres1~3#1 := 0; 41856#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42444#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 42014#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 42015#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42045#L716-45 assume 1 == ~t4_pc~0; 41676#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41677#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42227#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41682#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41683#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41345#L735-45 assume 1 == ~t5_pc~0; 41346#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41889#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42451#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42452#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 42510#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42505#L754-45 assume 1 == ~t6_pc~0; 41837#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41838#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41267#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41268#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 41841#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41573#L773-45 assume 1 == ~t7_pc~0; 41574#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41131#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42051#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42333#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 41579#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41249#L792-45 assume 1 == ~t8_pc~0; 41250#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 42279#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40852#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40711#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 40712#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41207#L811-45 assume 1 == ~t9_pc~0; 40996#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40998#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42206#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 42041#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 41650#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41442#L830-45 assume 1 == ~t10_pc~0; 41443#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 40640#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41762#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 40872#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 40873#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40618#L849-45 assume !(1 == ~t11_pc~0); 40619#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 41078#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40709#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 40606#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 40607#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 40865#L868-45 assume 1 == ~t12_pc~0; 40866#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 40805#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40806#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 42144#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 42395#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 42396#L887-45 assume 1 == ~t13_pc~0; 42226#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 40875#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42157#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 42502#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 40837#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40838#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 42145#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40857#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40858#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41015#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41946#L1459-3 assume !(1 == ~T5_E~0); 41947#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42398#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42337#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 42338#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42399#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 41631#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41632#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 42268#L1499-3 assume !(1 == ~T13_E~0); 41907#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41908#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 42346#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 42376#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 41550#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41551#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 42418#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 41818#L1539-3 assume !(1 == ~E_7~0); 41294#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41295#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 41790#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 40911#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 40912#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 42046#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 42047#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 40788#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 40559#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 40834#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 40795#L1959 assume !(0 == start_simulation_~tmp~3#1); 40797#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 40829#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 40779#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 42088#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 42209#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42416#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 42430#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 42431#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 40859#L1940-2 [2021-12-07 00:34:14,125 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:14,125 INFO L85 PathProgramCache]: Analyzing trace with hash 584687431, now seen corresponding path program 1 times [2021-12-07 00:34:14,125 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:14,125 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1137566304] [2021-12-07 00:34:14,126 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:14,126 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:14,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:14,163 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:14,163 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:14,163 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1137566304] [2021-12-07 00:34:14,163 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1137566304] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:14,163 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:14,164 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:14,164 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [789230638] [2021-12-07 00:34:14,164 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:14,164 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:34:14,165 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:14,165 INFO L85 PathProgramCache]: Analyzing trace with hash 222566493, now seen corresponding path program 1 times [2021-12-07 00:34:14,165 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:14,165 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1441815240] [2021-12-07 00:34:14,165 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:14,166 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:14,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:14,211 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:14,211 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:14,211 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1441815240] [2021-12-07 00:34:14,211 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1441815240] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:14,211 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:14,211 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:14,212 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2067365921] [2021-12-07 00:34:14,212 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:14,212 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:34:14,212 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:34:14,212 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:34:14,212 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:34:14,213 INFO L87 Difference]: Start difference. First operand 2023 states and 2987 transitions. cyclomatic complexity: 965 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:14,232 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:34:14,232 INFO L93 Difference]: Finished difference Result 2023 states and 2986 transitions. [2021-12-07 00:34:14,232 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:34:14,233 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2986 transitions. [2021-12-07 00:34:14,239 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-07 00:34:14,247 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2986 transitions. [2021-12-07 00:34:14,247 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2021-12-07 00:34:14,248 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2021-12-07 00:34:14,249 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2986 transitions. [2021-12-07 00:34:14,251 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:34:14,251 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2986 transitions. [2021-12-07 00:34:14,254 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2986 transitions. [2021-12-07 00:34:14,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2021-12-07 00:34:14,276 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4760257043994067) internal successors, (2986), 2022 states have internal predecessors, (2986), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:14,280 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2986 transitions. [2021-12-07 00:34:14,280 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2986 transitions. [2021-12-07 00:34:14,281 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2986 transitions. [2021-12-07 00:34:14,281 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-07 00:34:14,281 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2986 transitions. [2021-12-07 00:34:14,285 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-07 00:34:14,285 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:34:14,285 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:34:14,286 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:14,286 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:14,287 INFO L791 eck$LassoCheckResult]: Stem: 45526#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 45527#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 46525#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46526#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46611#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 45990#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45459#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45460#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46276#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46277#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46377#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46378#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 45231#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 45232#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 46407#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 45767#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 45768#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 46328#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 45669#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45670#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 46612#L1291-2 assume !(0 == ~T1_E~0); 46610#L1296-1 assume !(0 == ~T2_E~0); 45826#L1301-1 assume !(0 == ~T3_E~0); 45827#L1306-1 assume !(0 == ~T4_E~0); 46336#L1311-1 assume !(0 == ~T5_E~0); 45074#L1316-1 assume !(0 == ~T6_E~0); 45075#L1321-1 assume !(0 == ~T7_E~0); 45839#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44902#L1331-1 assume !(0 == ~T9_E~0); 44601#L1336-1 assume !(0 == ~T10_E~0); 44602#L1341-1 assume !(0 == ~T11_E~0); 44682#L1346-1 assume !(0 == ~T12_E~0); 44683#L1351-1 assume !(0 == ~T13_E~0); 45023#L1356-1 assume !(0 == ~E_M~0); 45024#L1361-1 assume !(0 == ~E_1~0); 46551#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 45064#L1371-1 assume !(0 == ~E_3~0); 45065#L1376-1 assume !(0 == ~E_4~0); 45886#L1381-1 assume !(0 == ~E_5~0); 45887#L1386-1 assume !(0 == ~E_6~0); 46581#L1391-1 assume !(0 == ~E_7~0); 46599#L1396-1 assume !(0 == ~E_8~0); 45799#L1401-1 assume !(0 == ~E_9~0); 45800#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 46078#L1411-1 assume !(0 == ~E_11~0); 46079#L1416-1 assume !(0 == ~E_12~0); 45711#L1421-1 assume !(0 == ~E_13~0); 45254#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45255#L640 assume !(1 == ~m_pc~0); 45764#L640-2 is_master_triggered_~__retres1~0#1 := 0; 45763#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45855#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45749#L1603 assume !(0 != activate_threads_~tmp~1#1); 45750#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45384#L659 assume 1 == ~t1_pc~0; 45385#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 45490#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46436#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45510#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 45511#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45524#L678 assume 1 == ~t2_pc~0; 46478#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46479#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46578#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45622#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 45623#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45744#L697 assume !(1 == ~t3_pc~0); 45745#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 45867#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45675#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45654#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45655#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46515#L716 assume 1 == ~t4_pc~0; 46501#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45365#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45366#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44865#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 44866#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46157#L735 assume !(1 == ~t5_pc~0); 44826#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 44827#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45277#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46184#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 45820#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45821#L754 assume 1 == ~t6_pc~0; 45574#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45472#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45473#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45446#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 45447#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46267#L773 assume !(1 == ~t7_pc~0); 45027#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 45026#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45856#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 45828#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 45829#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45876#L792 assume 1 == ~t8_pc~0; 46049#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 46381#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45870#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 45823#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 45747#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45748#L811 assume 1 == ~t9_pc~0; 45952#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46418#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46294#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45948#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 45760#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45761#L830 assume !(1 == ~t10_pc~0); 45482#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 45006#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44699#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 44700#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 44987#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 46285#L849 assume 1 == ~t11_pc~0; 46286#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 44802#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44803#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 45392#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 46191#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 46192#L868 assume !(1 == ~t12_pc~0); 45607#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 45606#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 45401#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 45402#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 45038#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 45039#L887 assume 1 == ~t13_pc~0; 46206#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 45648#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 45649#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 46085#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 44742#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44743#L1439 assume !(1 == ~M_E~0); 45816#L1439-2 assume !(1 == ~T1_E~0); 44914#L1444-1 assume !(1 == ~T2_E~0); 44915#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45388#L1454-1 assume !(1 == ~T4_E~0); 45389#L1459-1 assume !(1 == ~T5_E~0); 45945#L1464-1 assume !(1 == ~T6_E~0); 45946#L1469-1 assume !(1 == ~T7_E~0); 46018#L1474-1 assume !(1 == ~T8_E~0); 45712#L1479-1 assume !(1 == ~T9_E~0); 45713#L1484-1 assume !(1 == ~T10_E~0); 45949#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45595#L1494-1 assume !(1 == ~T12_E~0); 45596#L1499-1 assume !(1 == ~T13_E~0); 45788#L1504-1 assume !(1 == ~E_M~0); 45789#L1509-1 assume !(1 == ~E_1~0); 46364#L1514-1 assume !(1 == ~E_2~0); 46051#L1519-1 assume !(1 == ~E_3~0); 46052#L1524-1 assume !(1 == ~E_4~0); 46564#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 46565#L1534-1 assume !(1 == ~E_6~0); 44735#L1539-1 assume !(1 == ~E_7~0); 44736#L1544-1 assume !(1 == ~E_8~0); 45150#L1549-1 assume !(1 == ~E_9~0); 46539#L1554-1 assume !(1 == ~E_10~0); 46535#L1559-1 assume !(1 == ~E_11~0); 46402#L1564-1 assume !(1 == ~E_12~0); 46403#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 46560#L1574-1 assume { :end_inline_reset_delta_events } true; 44912#L1940-2 [2021-12-07 00:34:14,287 INFO L793 eck$LassoCheckResult]: Loop: 44912#L1940-2 assume !false; 44913#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 45195#L1266 assume !false; 46214#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 45443#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 45176#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 45567#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 45568#L1079 assume !(0 != eval_~tmp~0#1); 45529#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 45530#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46134#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 46019#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 46020#L1296-3 assume !(0 == ~T2_E~0); 46592#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46546#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45677#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44953#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 44954#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 45054#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45811#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 46060#L1336-3 assume !(0 == ~T10_E~0); 46061#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 45381#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 45361#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 45306#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 45307#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 45868#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 44657#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 44658#L1376-3 assume !(0 == ~E_4~0); 46387#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 46247#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 46248#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 46410#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 46411#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 45020#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 44874#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 44875#L1416-3 assume !(0 == ~E_12~0); 45536#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 45537#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45644#L640-45 assume !(1 == ~m_pc~0); 45645#L640-47 is_master_triggered_~__retres1~0#1 := 0; 45111#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45112#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44651#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 44652#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44750#L659-45 assume !(1 == ~t1_pc~0); 44752#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 45190#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46149#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46150#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46171#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46172#L678-45 assume 1 == ~t2_pc~0; 46115#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 45650#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45651#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45803#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46428#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46545#L697-45 assume 1 == ~t3_pc~0; 45908#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 45909#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46497#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46067#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46068#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46098#L716-45 assume 1 == ~t4_pc~0; 45729#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45730#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46280#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45735#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 45736#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45398#L735-45 assume 1 == ~t5_pc~0; 45399#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 45942#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46504#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46505#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46563#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46558#L754-45 assume 1 == ~t6_pc~0; 45890#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45891#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45320#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45321#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 45894#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45626#L773-45 assume 1 == ~t7_pc~0; 45627#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45184#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46104#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46386#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 45632#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45302#L792-45 assume 1 == ~t8_pc~0; 45303#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 46332#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44905#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 44764#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 44765#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45260#L811-45 assume 1 == ~t9_pc~0; 45049#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 45051#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46259#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46094#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 45703#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45495#L830-45 assume !(1 == ~t10_pc~0); 44692#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 44693#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45815#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 44925#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 44926#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44671#L849-45 assume !(1 == ~t11_pc~0); 44672#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 45131#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44762#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 44659#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 44660#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44918#L868-45 assume 1 == ~t12_pc~0; 44919#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 44858#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44859#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 46197#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 46448#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 46449#L887-45 assume 1 == ~t13_pc~0; 46279#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 44928#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46210#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 46555#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 44890#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44891#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 46198#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44910#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44911#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45068#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45999#L1459-3 assume !(1 == ~T5_E~0); 46000#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46451#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46390#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 46391#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46452#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 45684#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45685#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 46321#L1499-3 assume !(1 == ~T13_E~0); 45960#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 45961#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 46399#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46429#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 45603#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 45604#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 46471#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 45871#L1539-3 assume !(1 == ~E_7~0); 45347#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 45348#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 45843#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 44964#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 44965#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 46099#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 46100#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 44841#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 44612#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 44887#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 44848#L1959 assume !(0 == start_simulation_~tmp~3#1); 44850#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 44882#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 44832#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 46141#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 46262#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46469#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46483#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 46484#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 44912#L1940-2 [2021-12-07 00:34:14,287 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:14,287 INFO L85 PathProgramCache]: Analyzing trace with hash 1907866377, now seen corresponding path program 1 times [2021-12-07 00:34:14,287 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:14,287 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [291380840] [2021-12-07 00:34:14,288 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:14,288 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:14,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:14,313 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:14,313 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:14,313 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [291380840] [2021-12-07 00:34:14,314 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [291380840] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:14,314 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:14,314 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:14,314 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1311937390] [2021-12-07 00:34:14,314 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:14,314 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:34:14,314 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:14,315 INFO L85 PathProgramCache]: Analyzing trace with hash 2099019294, now seen corresponding path program 1 times [2021-12-07 00:34:14,315 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:14,315 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1842173396] [2021-12-07 00:34:14,315 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:14,315 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:14,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:14,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:14,348 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:14,348 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1842173396] [2021-12-07 00:34:14,349 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1842173396] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:14,349 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:14,349 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:14,349 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [219808039] [2021-12-07 00:34:14,349 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:14,349 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:34:14,349 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:34:14,349 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:34:14,350 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:34:14,350 INFO L87 Difference]: Start difference. First operand 2023 states and 2986 transitions. cyclomatic complexity: 964 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:14,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:34:14,364 INFO L93 Difference]: Finished difference Result 2023 states and 2985 transitions. [2021-12-07 00:34:14,365 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:34:14,365 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2985 transitions. [2021-12-07 00:34:14,370 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-07 00:34:14,377 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2985 transitions. [2021-12-07 00:34:14,378 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2021-12-07 00:34:14,378 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2021-12-07 00:34:14,378 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2985 transitions. [2021-12-07 00:34:14,380 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:34:14,380 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2985 transitions. [2021-12-07 00:34:14,383 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2985 transitions. [2021-12-07 00:34:14,399 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2021-12-07 00:34:14,401 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4755313890261987) internal successors, (2985), 2022 states have internal predecessors, (2985), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:14,404 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2985 transitions. [2021-12-07 00:34:14,405 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2985 transitions. [2021-12-07 00:34:14,405 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2985 transitions. [2021-12-07 00:34:14,405 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-07 00:34:14,405 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2985 transitions. [2021-12-07 00:34:14,409 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-07 00:34:14,409 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:34:14,409 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:34:14,410 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:14,410 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:14,411 INFO L791 eck$LassoCheckResult]: Stem: 49579#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 49580#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 50578#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50579#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50664#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 50043#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49512#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49513#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50329#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50330#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50430#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50431#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49284#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49285#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 50460#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 49820#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 49821#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 50381#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 49722#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49723#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 50665#L1291-2 assume !(0 == ~T1_E~0); 50663#L1296-1 assume !(0 == ~T2_E~0); 49879#L1301-1 assume !(0 == ~T3_E~0); 49880#L1306-1 assume !(0 == ~T4_E~0); 50389#L1311-1 assume !(0 == ~T5_E~0); 49127#L1316-1 assume !(0 == ~T6_E~0); 49128#L1321-1 assume !(0 == ~T7_E~0); 49892#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 48955#L1331-1 assume !(0 == ~T9_E~0); 48654#L1336-1 assume !(0 == ~T10_E~0); 48655#L1341-1 assume !(0 == ~T11_E~0); 48735#L1346-1 assume !(0 == ~T12_E~0); 48736#L1351-1 assume !(0 == ~T13_E~0); 49076#L1356-1 assume !(0 == ~E_M~0); 49077#L1361-1 assume !(0 == ~E_1~0); 50604#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 49117#L1371-1 assume !(0 == ~E_3~0); 49118#L1376-1 assume !(0 == ~E_4~0); 49939#L1381-1 assume !(0 == ~E_5~0); 49940#L1386-1 assume !(0 == ~E_6~0); 50634#L1391-1 assume !(0 == ~E_7~0); 50652#L1396-1 assume !(0 == ~E_8~0); 49852#L1401-1 assume !(0 == ~E_9~0); 49853#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 50131#L1411-1 assume !(0 == ~E_11~0); 50132#L1416-1 assume !(0 == ~E_12~0); 49764#L1421-1 assume !(0 == ~E_13~0); 49307#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49308#L640 assume !(1 == ~m_pc~0); 49817#L640-2 is_master_triggered_~__retres1~0#1 := 0; 49816#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49908#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49802#L1603 assume !(0 != activate_threads_~tmp~1#1); 49803#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49437#L659 assume 1 == ~t1_pc~0; 49438#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49543#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50489#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49563#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 49564#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49577#L678 assume 1 == ~t2_pc~0; 50531#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50532#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50631#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49675#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 49676#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49797#L697 assume !(1 == ~t3_pc~0); 49798#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 49920#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49728#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49707#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49708#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50568#L716 assume 1 == ~t4_pc~0; 50554#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 49418#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49419#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48918#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 48919#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50210#L735 assume !(1 == ~t5_pc~0); 48879#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 48880#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49330#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50237#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 49873#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49874#L754 assume 1 == ~t6_pc~0; 49627#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 49525#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49526#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49499#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 49500#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50320#L773 assume !(1 == ~t7_pc~0); 49080#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 49079#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49909#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49881#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 49882#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49929#L792 assume 1 == ~t8_pc~0; 50102#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50434#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49923#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49876#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 49800#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49801#L811 assume 1 == ~t9_pc~0; 50005#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50471#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50347#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50001#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 49813#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49814#L830 assume !(1 == ~t10_pc~0); 49535#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 49059#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48752#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 48753#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 49040#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 50338#L849 assume 1 == ~t11_pc~0; 50339#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 48855#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 48856#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 49445#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 50244#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50245#L868 assume !(1 == ~t12_pc~0); 49660#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 49659#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 49454#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 49455#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 49091#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 49092#L887 assume 1 == ~t13_pc~0; 50259#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 49701#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 49702#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 50138#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 48795#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48796#L1439 assume !(1 == ~M_E~0); 49869#L1439-2 assume !(1 == ~T1_E~0); 48967#L1444-1 assume !(1 == ~T2_E~0); 48968#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49441#L1454-1 assume !(1 == ~T4_E~0); 49442#L1459-1 assume !(1 == ~T5_E~0); 49998#L1464-1 assume !(1 == ~T6_E~0); 49999#L1469-1 assume !(1 == ~T7_E~0); 50071#L1474-1 assume !(1 == ~T8_E~0); 49765#L1479-1 assume !(1 == ~T9_E~0); 49766#L1484-1 assume !(1 == ~T10_E~0); 50002#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 49648#L1494-1 assume !(1 == ~T12_E~0); 49649#L1499-1 assume !(1 == ~T13_E~0); 49841#L1504-1 assume !(1 == ~E_M~0); 49842#L1509-1 assume !(1 == ~E_1~0); 50417#L1514-1 assume !(1 == ~E_2~0); 50104#L1519-1 assume !(1 == ~E_3~0); 50105#L1524-1 assume !(1 == ~E_4~0); 50617#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 50618#L1534-1 assume !(1 == ~E_6~0); 48788#L1539-1 assume !(1 == ~E_7~0); 48789#L1544-1 assume !(1 == ~E_8~0); 49203#L1549-1 assume !(1 == ~E_9~0); 50592#L1554-1 assume !(1 == ~E_10~0); 50588#L1559-1 assume !(1 == ~E_11~0); 50455#L1564-1 assume !(1 == ~E_12~0); 50456#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 50613#L1574-1 assume { :end_inline_reset_delta_events } true; 48965#L1940-2 [2021-12-07 00:34:14,411 INFO L793 eck$LassoCheckResult]: Loop: 48965#L1940-2 assume !false; 48966#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49248#L1266 assume !false; 50267#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 49496#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 49229#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 49620#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 49621#L1079 assume !(0 != eval_~tmp~0#1); 49582#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49583#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50187#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50072#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 50073#L1296-3 assume !(0 == ~T2_E~0); 50645#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 50599#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49730#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 49006#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 49007#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49107#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 49864#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 50113#L1336-3 assume !(0 == ~T10_E~0); 50114#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 49434#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 49414#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 49359#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 49360#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 49921#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 48710#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 48711#L1376-3 assume !(0 == ~E_4~0); 50440#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50300#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50301#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50463#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 50464#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 49073#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 48927#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 48928#L1416-3 assume !(0 == ~E_12~0); 49589#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 49590#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49697#L640-45 assume !(1 == ~m_pc~0); 49698#L640-47 is_master_triggered_~__retres1~0#1 := 0; 49164#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49165#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48704#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 48705#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48803#L659-45 assume 1 == ~t1_pc~0; 48804#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49243#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50202#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50203#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50224#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50225#L678-45 assume 1 == ~t2_pc~0; 50168#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 49703#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49704#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49856#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50481#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50598#L697-45 assume 1 == ~t3_pc~0; 49961#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49962#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50550#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50120#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50121#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50151#L716-45 assume 1 == ~t4_pc~0; 49782#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 49783#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50333#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49788#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49789#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49451#L735-45 assume 1 == ~t5_pc~0; 49452#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49995#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50557#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50558#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 50616#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50611#L754-45 assume 1 == ~t6_pc~0; 49943#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 49944#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49373#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49374#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 49947#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49679#L773-45 assume 1 == ~t7_pc~0; 49680#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49237#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50157#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50439#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 49685#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49355#L792-45 assume 1 == ~t8_pc~0; 49356#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50385#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48958#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 48817#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 48818#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49313#L811-45 assume 1 == ~t9_pc~0; 49102#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49104#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50312#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50147#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 49756#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49548#L830-45 assume !(1 == ~t10_pc~0); 48745#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 48746#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49868#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 48978#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 48979#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48724#L849-45 assume !(1 == ~t11_pc~0); 48725#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 49184#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 48815#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 48712#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 48713#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 48971#L868-45 assume 1 == ~t12_pc~0; 48972#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 48911#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 48912#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 50250#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 50501#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 50502#L887-45 assume !(1 == ~t13_pc~0); 48980#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 48981#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50263#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 50608#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 48943#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48944#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 50251#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 48963#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48964#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49121#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50052#L1459-3 assume !(1 == ~T5_E~0); 50053#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50504#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50443#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 50444#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50505#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 49737#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 49738#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 50374#L1499-3 assume !(1 == ~T13_E~0); 50013#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 50014#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50452#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50482#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 49656#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49657#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 50524#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 49924#L1539-3 assume !(1 == ~E_7~0); 49400#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49401#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 49896#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 49017#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 49018#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 50152#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 50153#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 48894#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 48665#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 48940#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 48901#L1959 assume !(0 == start_simulation_~tmp~3#1); 48903#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 48935#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 48885#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 50194#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 50315#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50522#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50536#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 50537#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 48965#L1940-2 [2021-12-07 00:34:14,411 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:14,411 INFO L85 PathProgramCache]: Analyzing trace with hash 10886919, now seen corresponding path program 1 times [2021-12-07 00:34:14,411 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:14,411 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1316998384] [2021-12-07 00:34:14,411 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:14,412 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:14,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:14,437 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:14,437 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:14,437 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1316998384] [2021-12-07 00:34:14,437 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1316998384] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:14,437 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:14,437 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:14,437 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [202797681] [2021-12-07 00:34:14,437 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:14,438 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:34:14,438 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:14,438 INFO L85 PathProgramCache]: Analyzing trace with hash 1630672670, now seen corresponding path program 2 times [2021-12-07 00:34:14,438 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:14,438 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [58564621] [2021-12-07 00:34:14,438 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:14,438 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:14,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:14,470 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:14,470 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:14,471 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [58564621] [2021-12-07 00:34:14,471 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [58564621] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:14,471 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:14,471 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:14,471 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1226083337] [2021-12-07 00:34:14,471 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:14,471 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:34:14,471 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:34:14,472 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:34:14,472 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:34:14,472 INFO L87 Difference]: Start difference. First operand 2023 states and 2985 transitions. cyclomatic complexity: 963 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:14,486 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:34:14,486 INFO L93 Difference]: Finished difference Result 2023 states and 2984 transitions. [2021-12-07 00:34:14,486 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:34:14,487 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2984 transitions. [2021-12-07 00:34:14,493 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-07 00:34:14,511 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2984 transitions. [2021-12-07 00:34:14,511 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2021-12-07 00:34:14,512 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2021-12-07 00:34:14,512 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2984 transitions. [2021-12-07 00:34:14,515 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:34:14,515 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2984 transitions. [2021-12-07 00:34:14,518 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2984 transitions. [2021-12-07 00:34:14,538 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2021-12-07 00:34:14,540 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4750370736529905) internal successors, (2984), 2022 states have internal predecessors, (2984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:14,543 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2984 transitions. [2021-12-07 00:34:14,543 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2984 transitions. [2021-12-07 00:34:14,543 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2984 transitions. [2021-12-07 00:34:14,543 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-07 00:34:14,543 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2984 transitions. [2021-12-07 00:34:14,547 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-07 00:34:14,547 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:34:14,547 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:34:14,549 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:14,549 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:14,549 INFO L791 eck$LassoCheckResult]: Stem: 53632#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 53633#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 54631#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 54632#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 54717#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 54096#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53565#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53566#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 54382#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 54383#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 54483#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 54484#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 53337#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 53338#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 54513#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 53873#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 53874#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 54434#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 53775#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53776#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 54718#L1291-2 assume !(0 == ~T1_E~0); 54716#L1296-1 assume !(0 == ~T2_E~0); 53932#L1301-1 assume !(0 == ~T3_E~0); 53933#L1306-1 assume !(0 == ~T4_E~0); 54442#L1311-1 assume !(0 == ~T5_E~0); 53180#L1316-1 assume !(0 == ~T6_E~0); 53181#L1321-1 assume !(0 == ~T7_E~0); 53945#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53008#L1331-1 assume !(0 == ~T9_E~0); 52707#L1336-1 assume !(0 == ~T10_E~0); 52708#L1341-1 assume !(0 == ~T11_E~0); 52788#L1346-1 assume !(0 == ~T12_E~0); 52789#L1351-1 assume !(0 == ~T13_E~0); 53129#L1356-1 assume !(0 == ~E_M~0); 53130#L1361-1 assume !(0 == ~E_1~0); 54657#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 53170#L1371-1 assume !(0 == ~E_3~0); 53171#L1376-1 assume !(0 == ~E_4~0); 53992#L1381-1 assume !(0 == ~E_5~0); 53993#L1386-1 assume !(0 == ~E_6~0); 54687#L1391-1 assume !(0 == ~E_7~0); 54705#L1396-1 assume !(0 == ~E_8~0); 53905#L1401-1 assume !(0 == ~E_9~0); 53906#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 54184#L1411-1 assume !(0 == ~E_11~0); 54185#L1416-1 assume !(0 == ~E_12~0); 53817#L1421-1 assume !(0 == ~E_13~0); 53360#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53361#L640 assume !(1 == ~m_pc~0); 53870#L640-2 is_master_triggered_~__retres1~0#1 := 0; 53869#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53961#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53855#L1603 assume !(0 != activate_threads_~tmp~1#1); 53856#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53490#L659 assume 1 == ~t1_pc~0; 53491#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53596#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54542#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53616#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 53617#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53630#L678 assume 1 == ~t2_pc~0; 54584#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54585#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54684#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53728#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 53729#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53850#L697 assume !(1 == ~t3_pc~0); 53851#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 53973#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53781#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53760#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53761#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54621#L716 assume 1 == ~t4_pc~0; 54607#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53471#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53472#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 52971#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 52972#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54263#L735 assume !(1 == ~t5_pc~0); 52932#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 52933#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53383#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54290#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 53926#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53927#L754 assume 1 == ~t6_pc~0; 53680#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53578#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53579#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53552#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 53553#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54373#L773 assume !(1 == ~t7_pc~0); 53133#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 53132#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53962#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 53934#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 53935#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53982#L792 assume 1 == ~t8_pc~0; 54155#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 54487#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53976#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 53929#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 53853#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53854#L811 assume 1 == ~t9_pc~0; 54058#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 54524#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54400#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 54054#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 53866#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53867#L830 assume !(1 == ~t10_pc~0); 53588#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 53112#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 52805#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 52806#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53093#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54391#L849 assume 1 == ~t11_pc~0; 54392#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 52908#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 52909#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 53498#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 54297#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54298#L868 assume !(1 == ~t12_pc~0); 53713#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 53712#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53507#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 53508#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 53144#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 53145#L887 assume 1 == ~t13_pc~0; 54312#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 53754#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 53755#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 54191#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 52848#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52849#L1439 assume !(1 == ~M_E~0); 53922#L1439-2 assume !(1 == ~T1_E~0); 53020#L1444-1 assume !(1 == ~T2_E~0); 53021#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53494#L1454-1 assume !(1 == ~T4_E~0); 53495#L1459-1 assume !(1 == ~T5_E~0); 54051#L1464-1 assume !(1 == ~T6_E~0); 54052#L1469-1 assume !(1 == ~T7_E~0); 54124#L1474-1 assume !(1 == ~T8_E~0); 53818#L1479-1 assume !(1 == ~T9_E~0); 53819#L1484-1 assume !(1 == ~T10_E~0); 54055#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 53701#L1494-1 assume !(1 == ~T12_E~0); 53702#L1499-1 assume !(1 == ~T13_E~0); 53894#L1504-1 assume !(1 == ~E_M~0); 53895#L1509-1 assume !(1 == ~E_1~0); 54470#L1514-1 assume !(1 == ~E_2~0); 54157#L1519-1 assume !(1 == ~E_3~0); 54158#L1524-1 assume !(1 == ~E_4~0); 54670#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 54671#L1534-1 assume !(1 == ~E_6~0); 52841#L1539-1 assume !(1 == ~E_7~0); 52842#L1544-1 assume !(1 == ~E_8~0); 53256#L1549-1 assume !(1 == ~E_9~0); 54645#L1554-1 assume !(1 == ~E_10~0); 54641#L1559-1 assume !(1 == ~E_11~0); 54508#L1564-1 assume !(1 == ~E_12~0); 54509#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 54666#L1574-1 assume { :end_inline_reset_delta_events } true; 53018#L1940-2 [2021-12-07 00:34:14,549 INFO L793 eck$LassoCheckResult]: Loop: 53018#L1940-2 assume !false; 53019#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53301#L1266 assume !false; 54320#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 53549#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 53282#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53673#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 53674#L1079 assume !(0 != eval_~tmp~0#1); 53635#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 53636#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 54240#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 54125#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 54126#L1296-3 assume !(0 == ~T2_E~0); 54698#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54652#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 53783#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 53059#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 53060#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53160#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53917#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 54166#L1336-3 assume !(0 == ~T10_E~0); 54167#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 53487#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 53467#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 53412#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 53413#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 53974#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 52763#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 52764#L1376-3 assume !(0 == ~E_4~0); 54493#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54353#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 54354#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 54516#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 54517#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 53126#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 52980#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 52981#L1416-3 assume !(0 == ~E_12~0); 53642#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 53643#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53750#L640-45 assume !(1 == ~m_pc~0); 53751#L640-47 is_master_triggered_~__retres1~0#1 := 0; 53217#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53218#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 52757#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 52758#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52856#L659-45 assume 1 == ~t1_pc~0; 52857#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53296#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54255#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54256#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 54277#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54278#L678-45 assume 1 == ~t2_pc~0; 54221#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 53756#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53757#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53909#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54534#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54651#L697-45 assume !(1 == ~t3_pc~0); 54016#L697-47 is_transmit3_triggered_~__retres1~3#1 := 0; 54015#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54603#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54173#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54174#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54204#L716-45 assume 1 == ~t4_pc~0; 53835#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53836#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54386#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53841#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 53842#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53504#L735-45 assume 1 == ~t5_pc~0; 53505#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 54048#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54610#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54611#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 54669#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54664#L754-45 assume 1 == ~t6_pc~0; 53996#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53997#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53426#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53427#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54000#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53732#L773-45 assume 1 == ~t7_pc~0; 53733#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 53290#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54210#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54492#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 53738#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53408#L792-45 assume 1 == ~t8_pc~0; 53409#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 54438#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53011#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 52870#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 52871#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53366#L811-45 assume 1 == ~t9_pc~0; 53155#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 53157#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54365#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 54200#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 53809#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53601#L830-45 assume 1 == ~t10_pc~0; 53602#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 52799#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53921#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 53031#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53032#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 52777#L849-45 assume !(1 == ~t11_pc~0); 52778#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 53237#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 52868#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 52765#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 52766#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53024#L868-45 assume 1 == ~t12_pc~0; 53025#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 52964#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 52965#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 54303#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 54554#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 54555#L887-45 assume 1 == ~t13_pc~0; 54385#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 53034#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 54316#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 54661#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 52996#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52997#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 54304#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 53016#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 53017#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53174#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 54105#L1459-3 assume !(1 == ~T5_E~0); 54106#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 54557#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 54496#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 54497#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 54558#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 53790#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 53791#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 54427#L1499-3 assume !(1 == ~T13_E~0); 54066#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 54067#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 54505#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 54535#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 53709#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53710#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 54577#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 53977#L1539-3 assume !(1 == ~E_7~0); 53453#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 53454#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 53949#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 53070#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 53071#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 54205#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 54206#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 52947#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 52718#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 52993#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 52954#L1959 assume !(0 == start_simulation_~tmp~3#1); 52956#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 52988#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 52938#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 54247#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 54368#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54575#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54589#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 54590#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 53018#L1940-2 [2021-12-07 00:34:14,549 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:14,550 INFO L85 PathProgramCache]: Analyzing trace with hash -327400631, now seen corresponding path program 1 times [2021-12-07 00:34:14,550 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:14,550 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [629734800] [2021-12-07 00:34:14,550 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:14,550 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:14,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:14,582 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:14,582 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:14,582 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [629734800] [2021-12-07 00:34:14,583 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [629734800] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:14,583 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:14,583 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-07 00:34:14,583 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1976474964] [2021-12-07 00:34:14,583 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:14,583 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:34:14,583 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:14,584 INFO L85 PathProgramCache]: Analyzing trace with hash 222566493, now seen corresponding path program 2 times [2021-12-07 00:34:14,584 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:14,584 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1562725968] [2021-12-07 00:34:14,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:14,584 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:14,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:14,619 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:14,619 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:14,619 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1562725968] [2021-12-07 00:34:14,619 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1562725968] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:14,619 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:14,619 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:14,620 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [587388146] [2021-12-07 00:34:14,620 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:14,620 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:34:14,620 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:34:14,620 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:34:14,620 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:34:14,620 INFO L87 Difference]: Start difference. First operand 2023 states and 2984 transitions. cyclomatic complexity: 962 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:14,680 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:34:14,680 INFO L93 Difference]: Finished difference Result 3771 states and 5546 transitions. [2021-12-07 00:34:14,681 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:34:14,681 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3771 states and 5546 transitions. [2021-12-07 00:34:14,698 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3596 [2021-12-07 00:34:14,711 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3771 states to 3771 states and 5546 transitions. [2021-12-07 00:34:14,711 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3771 [2021-12-07 00:34:14,714 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3771 [2021-12-07 00:34:14,714 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3771 states and 5546 transitions. [2021-12-07 00:34:14,718 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:34:14,718 INFO L681 BuchiCegarLoop]: Abstraction has 3771 states and 5546 transitions. [2021-12-07 00:34:14,723 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3771 states and 5546 transitions. [2021-12-07 00:34:14,764 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3771 to 3771. [2021-12-07 00:34:14,768 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3771 states, 3771 states have (on average 1.4706974277380005) internal successors, (5546), 3770 states have internal predecessors, (5546), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:14,774 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3771 states to 3771 states and 5546 transitions. [2021-12-07 00:34:14,774 INFO L704 BuchiCegarLoop]: Abstraction has 3771 states and 5546 transitions. [2021-12-07 00:34:14,774 INFO L587 BuchiCegarLoop]: Abstraction has 3771 states and 5546 transitions. [2021-12-07 00:34:14,774 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-07 00:34:14,774 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3771 states and 5546 transitions. [2021-12-07 00:34:14,783 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3596 [2021-12-07 00:34:14,783 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:34:14,783 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:34:14,785 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:14,785 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:14,785 INFO L791 eck$LassoCheckResult]: Stem: 59438#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 59439#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 60454#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 60455#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60552#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 59908#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 59369#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 59370#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 60200#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 60201#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 60302#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 60303#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 59139#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 59140#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 60332#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 59680#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 59681#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 60252#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 59581#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 59582#L1291 assume !(0 == ~M_E~0); 60553#L1291-2 assume !(0 == ~T1_E~0); 60551#L1296-1 assume !(0 == ~T2_E~0); 59741#L1301-1 assume !(0 == ~T3_E~0); 59742#L1306-1 assume !(0 == ~T4_E~0); 60260#L1311-1 assume !(0 == ~T5_E~0); 58982#L1316-1 assume !(0 == ~T6_E~0); 58983#L1321-1 assume !(0 == ~T7_E~0); 59754#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 58810#L1331-1 assume !(0 == ~T9_E~0); 58508#L1336-1 assume !(0 == ~T10_E~0); 58509#L1341-1 assume !(0 == ~T11_E~0); 58589#L1346-1 assume !(0 == ~T12_E~0); 58590#L1351-1 assume !(0 == ~T13_E~0); 58931#L1356-1 assume !(0 == ~E_M~0); 58932#L1361-1 assume !(0 == ~E_1~0); 60482#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 58972#L1371-1 assume !(0 == ~E_3~0); 58973#L1376-1 assume !(0 == ~E_4~0); 59804#L1381-1 assume !(0 == ~E_5~0); 59805#L1386-1 assume !(0 == ~E_6~0); 60517#L1391-1 assume !(0 == ~E_7~0); 60539#L1396-1 assume !(0 == ~E_8~0); 59713#L1401-1 assume !(0 == ~E_9~0); 59714#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 59997#L1411-1 assume !(0 == ~E_11~0); 59998#L1416-1 assume !(0 == ~E_12~0); 59624#L1421-1 assume !(0 == ~E_13~0); 59164#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59165#L640 assume !(1 == ~m_pc~0); 59677#L640-2 is_master_triggered_~__retres1~0#1 := 0; 59676#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59770#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 59662#L1603 assume !(0 != activate_threads_~tmp~1#1); 59663#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59294#L659 assume 1 == ~t1_pc~0; 59295#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 59401#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60363#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 59422#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 59423#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59436#L678 assume 1 == ~t2_pc~0; 60406#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 60407#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60512#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 59534#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 59535#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59657#L697 assume !(1 == ~t3_pc~0); 59658#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 59785#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59587#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59566#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 59567#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60444#L716 assume 1 == ~t4_pc~0; 60430#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 59276#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59277#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 58773#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 58774#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 60078#L735 assume !(1 == ~t5_pc~0); 58734#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 58735#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 59185#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 60104#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 59735#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 59736#L754 assume 1 == ~t6_pc~0; 59486#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 59383#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59384#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 59356#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 59357#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 60190#L773 assume !(1 == ~t7_pc~0); 58935#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 58934#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 59771#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 59743#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 59744#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 59794#L792 assume 1 == ~t8_pc~0; 59970#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 60306#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 59788#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 59738#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 59660#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 59661#L811 assume 1 == ~t9_pc~0; 59871#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 60343#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 60217#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 59866#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 59673#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 59674#L830 assume !(1 == ~t10_pc~0); 59393#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 58914#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 58606#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 58607#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 58895#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 60208#L849 assume 1 == ~t11_pc~0; 60209#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 58710#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 58711#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 59302#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 60113#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 60114#L868 assume !(1 == ~t12_pc~0); 59519#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 59518#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 59311#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 59312#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 58946#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 58947#L887 assume 1 == ~t13_pc~0; 60126#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 59560#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 59561#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 60004#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 58649#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 58650#L1439 assume !(1 == ~M_E~0); 59733#L1439-2 assume !(1 == ~T1_E~0); 58822#L1444-1 assume !(1 == ~T2_E~0); 58823#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 59300#L1454-1 assume !(1 == ~T4_E~0); 59301#L1459-1 assume !(1 == ~T5_E~0); 59863#L1464-1 assume !(1 == ~T6_E~0); 59864#L1469-1 assume !(1 == ~T7_E~0); 59937#L1474-1 assume !(1 == ~T8_E~0); 59625#L1479-1 assume !(1 == ~T9_E~0); 59626#L1484-1 assume !(1 == ~T10_E~0); 59867#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59507#L1494-1 assume !(1 == ~T12_E~0); 59508#L1499-1 assume !(1 == ~T13_E~0); 59702#L1504-1 assume !(1 == ~E_M~0); 59703#L1509-1 assume !(1 == ~E_1~0); 60289#L1514-1 assume !(1 == ~E_2~0); 59972#L1519-1 assume !(1 == ~E_3~0); 59973#L1524-1 assume !(1 == ~E_4~0); 60497#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 60498#L1534-1 assume !(1 == ~E_6~0); 58642#L1539-1 assume !(1 == ~E_7~0); 58643#L1544-1 assume !(1 == ~E_8~0); 59058#L1549-1 assume !(1 == ~E_9~0); 60473#L1554-1 assume !(1 == ~E_10~0); 60465#L1559-1 assume !(1 == ~E_11~0); 60327#L1564-1 assume !(1 == ~E_12~0); 60328#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 60492#L1574-1 assume { :end_inline_reset_delta_events } true; 58820#L1940-2 [2021-12-07 00:34:14,785 INFO L793 eck$LassoCheckResult]: Loop: 58820#L1940-2 assume !false; 58821#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 59103#L1266 assume !false; 60135#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 59353#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 59084#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 59480#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 59481#L1079 assume !(0 != eval_~tmp~0#1); 59441#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 59442#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 60053#L1291-3 assume !(0 == ~M_E~0); 60054#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 62088#L1296-3 assume !(0 == ~T2_E~0); 62087#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 62086#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 62085#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 62084#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 62083#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 62082#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 62081#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 62080#L1336-3 assume !(0 == ~T10_E~0); 62079#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 62078#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 62077#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 62076#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 62075#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 62074#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 62073#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 62072#L1376-3 assume !(0 == ~E_4~0); 62071#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 62070#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 62069#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 62068#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 62067#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 62066#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 62065#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 62064#L1416-3 assume !(0 == ~E_12~0); 62063#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 62062#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62061#L640-45 assume 1 == ~m_pc~0; 62059#L641-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 62058#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62057#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 62056#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 62055#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 62054#L659-45 assume 1 == ~t1_pc~0; 62052#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 62051#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62050#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 62049#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62048#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62047#L678-45 assume !(1 == ~t2_pc~0); 62045#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 62044#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62043#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 62042#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 62041#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62040#L697-45 assume 1 == ~t3_pc~0; 62038#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 62037#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62036#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 62035#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 62034#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62033#L716-45 assume 1 == ~t4_pc~0; 62032#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 62030#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62029#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 62028#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 62027#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62026#L735-45 assume 1 == ~t5_pc~0; 62024#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 62023#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 62022#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 62021#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 62020#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 62019#L754-45 assume !(1 == ~t6_pc~0); 62017#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 62016#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 62015#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 62014#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 62013#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62012#L773-45 assume 1 == ~t7_pc~0; 62010#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 62009#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 62008#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 62007#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 62006#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 62005#L792-45 assume 1 == ~t8_pc~0; 62003#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 62002#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 62001#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 62000#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 61999#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 61935#L811-45 assume !(1 == ~t9_pc~0); 61933#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 60180#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 60181#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 60509#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 61931#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 59406#L830-45 assume !(1 == ~t10_pc~0); 59408#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 61930#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 61929#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 61928#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 61927#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 61926#L849-45 assume 1 == ~t11_pc~0; 59778#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 59779#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 61925#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 58566#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 58567#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 58826#L868-45 assume 1 == ~t12_pc~0; 58827#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 59286#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 61920#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 61919#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 61918#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 61917#L887-45 assume !(1 == ~t13_pc~0); 61915#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 60129#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 60130#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 60487#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 58798#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 58799#L1439-3 assume !(1 == ~M_E~0); 60118#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 58818#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 58819#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 58976#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 59918#L1459-3 assume !(1 == ~T5_E~0); 59919#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 60378#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 60315#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 60316#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 60379#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 59594#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59595#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 60245#L1499-3 assume !(1 == ~T13_E~0); 59878#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 59879#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 60324#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 60356#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 59515#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 59516#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 60399#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 59789#L1539-3 assume !(1 == ~E_7~0); 59256#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 59257#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 59757#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 58872#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 58873#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 60018#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 60019#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 58749#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 58519#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 58795#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 58756#L1959 assume !(0 == start_simulation_~tmp~3#1); 58758#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 58790#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 58740#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 60061#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 60184#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 60397#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 60412#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 60413#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 58820#L1940-2 [2021-12-07 00:34:14,786 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:14,786 INFO L85 PathProgramCache]: Analyzing trace with hash -867830137, now seen corresponding path program 1 times [2021-12-07 00:34:14,786 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:14,786 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1935101018] [2021-12-07 00:34:14,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:14,786 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:14,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:14,818 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:14,818 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:14,818 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1935101018] [2021-12-07 00:34:14,818 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1935101018] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:14,819 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:14,819 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:14,819 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2083010152] [2021-12-07 00:34:14,819 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:14,819 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:34:14,820 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:14,820 INFO L85 PathProgramCache]: Analyzing trace with hash 1928462239, now seen corresponding path program 1 times [2021-12-07 00:34:14,820 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:14,820 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [921573764] [2021-12-07 00:34:14,820 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:14,820 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:14,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:14,862 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:14,862 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:14,862 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [921573764] [2021-12-07 00:34:14,862 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [921573764] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:14,863 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:14,863 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:14,863 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1799805447] [2021-12-07 00:34:14,863 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:14,863 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:34:14,863 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:34:14,864 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-07 00:34:14,864 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-07 00:34:14,864 INFO L87 Difference]: Start difference. First operand 3771 states and 5546 transitions. cyclomatic complexity: 1776 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:14,971 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:34:14,971 INFO L93 Difference]: Finished difference Result 5511 states and 8090 transitions. [2021-12-07 00:34:14,971 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-07 00:34:14,972 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5511 states and 8090 transitions. [2021-12-07 00:34:14,987 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5316 [2021-12-07 00:34:15,002 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5511 states to 5511 states and 8090 transitions. [2021-12-07 00:34:15,002 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5511 [2021-12-07 00:34:15,004 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5511 [2021-12-07 00:34:15,005 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5511 states and 8090 transitions. [2021-12-07 00:34:15,008 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:34:15,008 INFO L681 BuchiCegarLoop]: Abstraction has 5511 states and 8090 transitions. [2021-12-07 00:34:15,013 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5511 states and 8090 transitions. [2021-12-07 00:34:15,052 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5511 to 3771. [2021-12-07 00:34:15,056 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3771 states, 3771 states have (on average 1.469901882789711) internal successors, (5543), 3770 states have internal predecessors, (5543), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:15,062 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3771 states to 3771 states and 5543 transitions. [2021-12-07 00:34:15,062 INFO L704 BuchiCegarLoop]: Abstraction has 3771 states and 5543 transitions. [2021-12-07 00:34:15,062 INFO L587 BuchiCegarLoop]: Abstraction has 3771 states and 5543 transitions. [2021-12-07 00:34:15,062 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-07 00:34:15,062 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3771 states and 5543 transitions. [2021-12-07 00:34:15,070 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3596 [2021-12-07 00:34:15,070 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:34:15,070 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:34:15,072 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:15,072 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:15,072 INFO L791 eck$LassoCheckResult]: Stem: 68726#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 68727#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 69726#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 69727#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 69812#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 69190#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 68658#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 68659#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 69477#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 69478#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 69577#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 69578#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 68433#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 68434#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 69607#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 68967#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 68968#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 69528#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 68870#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 68871#L1291 assume !(0 == ~M_E~0); 69813#L1291-2 assume !(0 == ~T1_E~0); 69811#L1296-1 assume !(0 == ~T2_E~0); 69026#L1301-1 assume !(0 == ~T3_E~0); 69027#L1306-1 assume !(0 == ~T4_E~0); 69537#L1311-1 assume !(0 == ~T5_E~0); 68273#L1316-1 assume !(0 == ~T6_E~0); 68274#L1321-1 assume !(0 == ~T7_E~0); 69039#L1326-1 assume !(0 == ~T8_E~0); 68101#L1331-1 assume !(0 == ~T9_E~0); 67800#L1336-1 assume !(0 == ~T10_E~0); 67801#L1341-1 assume !(0 == ~T11_E~0); 67881#L1346-1 assume !(0 == ~T12_E~0); 67882#L1351-1 assume !(0 == ~T13_E~0); 68222#L1356-1 assume !(0 == ~E_M~0); 68223#L1361-1 assume !(0 == ~E_1~0); 69752#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 68263#L1371-1 assume !(0 == ~E_3~0); 68264#L1376-1 assume !(0 == ~E_4~0); 69086#L1381-1 assume !(0 == ~E_5~0); 69087#L1386-1 assume !(0 == ~E_6~0); 69782#L1391-1 assume !(0 == ~E_7~0); 69800#L1396-1 assume !(0 == ~E_8~0); 68999#L1401-1 assume !(0 == ~E_9~0); 69000#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 69278#L1411-1 assume !(0 == ~E_11~0); 69279#L1416-1 assume !(0 == ~E_12~0); 68911#L1421-1 assume !(0 == ~E_13~0); 68457#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68458#L640 assume !(1 == ~m_pc~0); 68964#L640-2 is_master_triggered_~__retres1~0#1 := 0; 68963#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69055#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 68949#L1603 assume !(0 != activate_threads_~tmp~1#1); 68950#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68583#L659 assume 1 == ~t1_pc~0; 68584#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 68690#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69636#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 68710#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 68711#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68724#L678 assume 1 == ~t2_pc~0; 69678#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 69679#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69779#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 68822#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 68823#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68944#L697 assume !(1 == ~t3_pc~0); 68945#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 69067#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68875#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 68854#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 68855#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69716#L716 assume 1 == ~t4_pc~0; 69702#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 68566#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68567#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 68064#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 68065#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 69358#L735 assume !(1 == ~t5_pc~0); 68025#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 68026#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 68476#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 69386#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 69020#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 69021#L754 assume 1 == ~t6_pc~0; 68776#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 68672#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 68673#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 68645#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 68646#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 69467#L773 assume !(1 == ~t7_pc~0); 68226#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 68225#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 69056#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 69028#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 69029#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 69076#L792 assume 1 == ~t8_pc~0; 69251#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 69581#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 69070#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 69024#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 68947#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 68948#L811 assume 1 == ~t9_pc~0; 69153#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 69618#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 69494#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 69148#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 68960#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 68961#L830 assume !(1 == ~t10_pc~0); 68684#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 68205#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 67898#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 67899#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 68186#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 69485#L849 assume 1 == ~t11_pc~0; 69486#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 68001#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 68002#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 68593#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 69393#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 69394#L868 assume !(1 == ~t12_pc~0); 68807#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 68806#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 68600#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 68601#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 68237#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 68238#L887 assume 1 == ~t13_pc~0; 69406#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 68848#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 68849#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 69285#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 67941#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 67942#L1439 assume !(1 == ~M_E~0); 69018#L1439-2 assume !(1 == ~T1_E~0); 68113#L1444-1 assume !(1 == ~T2_E~0); 68114#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 68589#L1454-1 assume !(1 == ~T4_E~0); 68590#L1459-1 assume !(1 == ~T5_E~0); 69145#L1464-1 assume !(1 == ~T6_E~0); 69146#L1469-1 assume !(1 == ~T7_E~0); 69221#L1474-1 assume !(1 == ~T8_E~0); 68912#L1479-1 assume !(1 == ~T9_E~0); 68913#L1484-1 assume !(1 == ~T10_E~0); 69149#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 68798#L1494-1 assume !(1 == ~T12_E~0); 68799#L1499-1 assume !(1 == ~T13_E~0); 68988#L1504-1 assume !(1 == ~E_M~0); 68989#L1509-1 assume !(1 == ~E_1~0); 69564#L1514-1 assume !(1 == ~E_2~0); 69253#L1519-1 assume !(1 == ~E_3~0); 69254#L1524-1 assume !(1 == ~E_4~0); 69765#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 69766#L1534-1 assume !(1 == ~E_6~0); 67934#L1539-1 assume !(1 == ~E_7~0); 67935#L1544-1 assume !(1 == ~E_8~0); 68349#L1549-1 assume !(1 == ~E_9~0); 69744#L1554-1 assume !(1 == ~E_10~0); 69737#L1559-1 assume !(1 == ~E_11~0); 69602#L1564-1 assume !(1 == ~E_12~0); 69603#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 69761#L1574-1 assume { :end_inline_reset_delta_events } true; 68111#L1940-2 [2021-12-07 00:34:15,073 INFO L793 eck$LassoCheckResult]: Loop: 68111#L1940-2 assume !false; 68112#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 68394#L1266 assume !false; 69414#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68642#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68375#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68767#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 68768#L1079 assume !(0 != eval_~tmp~0#1); 68729#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 68730#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 69334#L1291-3 assume !(0 == ~M_E~0); 69218#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 69219#L1296-3 assume !(0 == ~T2_E~0); 69793#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 69747#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 68877#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 68152#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 68153#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 68253#L1326-3 assume !(0 == ~T8_E~0); 69011#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 69260#L1336-3 assume !(0 == ~T10_E~0); 69261#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 68580#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 68560#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 68505#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 68506#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 69068#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 67856#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 67857#L1376-3 assume !(0 == ~E_4~0); 69587#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 69447#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 69448#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 69610#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 69611#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 68219#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 68073#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 68074#L1416-3 assume !(0 == ~E_12~0); 68736#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 68737#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68844#L640-45 assume !(1 == ~m_pc~0); 68845#L640-47 is_master_triggered_~__retres1~0#1 := 0; 68310#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68311#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 67850#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 67851#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 67949#L659-45 assume !(1 == ~t1_pc~0); 67951#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 68392#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69349#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 69350#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 69371#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69372#L678-45 assume 1 == ~t2_pc~0; 69315#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 68850#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68851#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 69003#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 69628#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 69746#L697-45 assume 1 == ~t3_pc~0; 69108#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 69109#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69697#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 69267#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 69268#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69298#L716-45 assume 1 == ~t4_pc~0; 68929#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 68930#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 69480#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 68935#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 68936#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 68597#L735-45 assume !(1 == ~t5_pc~0); 68599#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 69142#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 69705#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 69706#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 69764#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 69759#L754-45 assume 1 == ~t6_pc~0; 69090#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 69091#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 68519#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 68520#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 69094#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 68826#L773-45 assume 1 == ~t7_pc~0; 68827#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 68384#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 69304#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 69586#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 68832#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 68501#L792-45 assume !(1 == ~t8_pc~0); 68503#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 69532#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 68104#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 67963#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 67964#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 68459#L811-45 assume !(1 == ~t9_pc~0); 68251#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 68252#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 69459#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 69294#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 68903#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 68694#L830-45 assume !(1 == ~t10_pc~0); 67891#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 67892#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 69015#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 68124#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 68125#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 67867#L849-45 assume 1 == ~t11_pc~0; 67869#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 68330#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 67961#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 67858#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 67859#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 68117#L868-45 assume !(1 == ~t12_pc~0); 68119#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 68055#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 68056#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 69397#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 69648#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 69649#L887-45 assume 1 == ~t13_pc~0; 69479#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 68127#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 69408#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 69756#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 68089#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68090#L1439-3 assume !(1 == ~M_E~0); 69398#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 68109#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 68110#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 68267#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69199#L1459-3 assume !(1 == ~T5_E~0); 69200#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 69651#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 69590#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 69591#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 69652#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 68882#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 68883#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 69521#L1499-3 assume !(1 == ~T13_E~0); 69160#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 69161#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 69599#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 69629#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 68803#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 68804#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 69671#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 69071#L1539-3 assume !(1 == ~E_7~0); 68546#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 68547#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 69042#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 68163#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 68164#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 69299#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 69300#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68040#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 67811#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68086#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 68047#L1959 assume !(0 == start_simulation_~tmp~3#1); 68049#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68081#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68031#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 69341#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 69462#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 69668#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 69683#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 69684#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 68111#L1940-2 [2021-12-07 00:34:15,073 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:15,073 INFO L85 PathProgramCache]: Analyzing trace with hash 1809696709, now seen corresponding path program 1 times [2021-12-07 00:34:15,073 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:15,073 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1198935493] [2021-12-07 00:34:15,073 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:15,073 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:15,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:15,109 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:15,109 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:15,109 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1198935493] [2021-12-07 00:34:15,110 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1198935493] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:15,110 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:15,110 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-07 00:34:15,110 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [804795050] [2021-12-07 00:34:15,110 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:15,110 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:34:15,111 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:15,111 INFO L85 PathProgramCache]: Analyzing trace with hash 1716026143, now seen corresponding path program 1 times [2021-12-07 00:34:15,111 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:15,111 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2050364239] [2021-12-07 00:34:15,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:15,111 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:15,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:15,144 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:15,144 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:15,144 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2050364239] [2021-12-07 00:34:15,144 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2050364239] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:15,144 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:15,144 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:15,145 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1561229415] [2021-12-07 00:34:15,145 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:15,145 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:34:15,145 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:34:15,145 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:34:15,145 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:34:15,146 INFO L87 Difference]: Start difference. First operand 3771 states and 5543 transitions. cyclomatic complexity: 1773 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:15,194 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:34:15,194 INFO L93 Difference]: Finished difference Result 3771 states and 5505 transitions. [2021-12-07 00:34:15,194 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:34:15,195 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3771 states and 5505 transitions. [2021-12-07 00:34:15,205 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3596 [2021-12-07 00:34:15,214 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3771 states to 3771 states and 5505 transitions. [2021-12-07 00:34:15,214 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3771 [2021-12-07 00:34:15,216 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3771 [2021-12-07 00:34:15,216 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3771 states and 5505 transitions. [2021-12-07 00:34:15,218 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:34:15,218 INFO L681 BuchiCegarLoop]: Abstraction has 3771 states and 5505 transitions. [2021-12-07 00:34:15,220 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3771 states and 5505 transitions. [2021-12-07 00:34:15,256 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3771 to 3771. [2021-12-07 00:34:15,260 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3771 states, 3771 states have (on average 1.4598249801113763) internal successors, (5505), 3770 states have internal predecessors, (5505), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:15,266 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3771 states to 3771 states and 5505 transitions. [2021-12-07 00:34:15,266 INFO L704 BuchiCegarLoop]: Abstraction has 3771 states and 5505 transitions. [2021-12-07 00:34:15,266 INFO L587 BuchiCegarLoop]: Abstraction has 3771 states and 5505 transitions. [2021-12-07 00:34:15,266 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-07 00:34:15,266 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3771 states and 5505 transitions. [2021-12-07 00:34:15,274 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3596 [2021-12-07 00:34:15,274 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:34:15,274 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:34:15,275 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:15,275 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:15,276 INFO L791 eck$LassoCheckResult]: Stem: 76277#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 76278#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 77359#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 77360#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77482#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 76751#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76206#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76207#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 77056#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 77057#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 77178#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 77179#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 75980#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 75981#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 77212#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 76521#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 76522#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 77115#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 76425#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 76426#L1291 assume !(0 == ~M_E~0); 77483#L1291-2 assume !(0 == ~T1_E~0); 77480#L1296-1 assume !(0 == ~T2_E~0); 76582#L1301-1 assume !(0 == ~T3_E~0); 76583#L1306-1 assume !(0 == ~T4_E~0); 77128#L1311-1 assume !(0 == ~T5_E~0); 75820#L1316-1 assume !(0 == ~T6_E~0); 75821#L1321-1 assume !(0 == ~T7_E~0); 76597#L1326-1 assume !(0 == ~T8_E~0); 75649#L1331-1 assume !(0 == ~T9_E~0); 75349#L1336-1 assume !(0 == ~T10_E~0); 75350#L1341-1 assume !(0 == ~T11_E~0); 75429#L1346-1 assume !(0 == ~T12_E~0); 75430#L1351-1 assume !(0 == ~T13_E~0); 75769#L1356-1 assume !(0 == ~E_M~0); 75770#L1361-1 assume !(0 == ~E_1~0); 77393#L1366-1 assume !(0 == ~E_2~0); 75810#L1371-1 assume !(0 == ~E_3~0); 75811#L1376-1 assume !(0 == ~E_4~0); 76646#L1381-1 assume !(0 == ~E_5~0); 76647#L1386-1 assume !(0 == ~E_6~0); 77444#L1391-1 assume !(0 == ~E_7~0); 77466#L1396-1 assume !(0 == ~E_8~0); 76553#L1401-1 assume !(0 == ~E_9~0); 76554#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 76841#L1411-1 assume !(0 == ~E_11~0); 76842#L1416-1 assume !(0 == ~E_12~0); 76466#L1421-1 assume !(0 == ~E_13~0); 76002#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76003#L640 assume !(1 == ~m_pc~0); 76518#L640-2 is_master_triggered_~__retres1~0#1 := 0; 76517#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76613#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 76503#L1603 assume !(0 != activate_threads_~tmp~1#1); 76504#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76131#L659 assume 1 == ~t1_pc~0; 76132#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 76238#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77244#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 76260#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 76261#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76275#L678 assume !(1 == ~t2_pc~0); 77295#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 77437#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 77438#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 76375#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 76376#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76498#L697 assume !(1 == ~t3_pc~0); 76499#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 76627#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 76430#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 76409#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 76410#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77341#L716 assume 1 == ~t4_pc~0; 77324#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 76114#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76115#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 75612#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 75613#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76923#L735 assume !(1 == ~t5_pc~0); 75574#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 75575#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76023#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 76953#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 76575#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 76576#L754 assume 1 == ~t6_pc~0; 76327#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 76220#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76221#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 76193#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 76194#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 77045#L773 assume !(1 == ~t7_pc~0); 75773#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 75772#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 76614#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 76584#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 76585#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 76636#L792 assume 1 == ~t8_pc~0; 76813#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 77182#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 76630#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 76579#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 76501#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 76502#L811 assume 1 == ~t9_pc~0; 76713#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 77223#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 77074#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 76708#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 76514#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 76515#L830 assume !(1 == ~t10_pc~0); 76232#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 75752#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 75446#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 75447#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 75733#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77065#L849 assume 1 == ~t11_pc~0; 77066#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 75550#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 75551#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 76141#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 76962#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 76963#L868 assume !(1 == ~t12_pc~0); 76360#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 76359#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 76148#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 76149#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 75784#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 75785#L887 assume 1 == ~t13_pc~0; 76975#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 76403#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 76404#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 76848#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 75490#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 75491#L1439 assume !(1 == ~M_E~0); 76573#L1439-2 assume !(1 == ~T1_E~0); 75661#L1444-1 assume !(1 == ~T2_E~0); 75662#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 76137#L1454-1 assume !(1 == ~T4_E~0); 76138#L1459-1 assume !(1 == ~T5_E~0); 76705#L1464-1 assume !(1 == ~T6_E~0); 76706#L1469-1 assume !(1 == ~T7_E~0); 76781#L1474-1 assume !(1 == ~T8_E~0); 76467#L1479-1 assume !(1 == ~T9_E~0); 76468#L1484-1 assume !(1 == ~T10_E~0); 76709#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 76351#L1494-1 assume !(1 == ~T12_E~0); 76352#L1499-1 assume !(1 == ~T13_E~0); 76542#L1504-1 assume !(1 == ~E_M~0); 76543#L1509-1 assume !(1 == ~E_1~0); 77161#L1514-1 assume !(1 == ~E_2~0); 76815#L1519-1 assume !(1 == ~E_3~0); 76816#L1524-1 assume !(1 == ~E_4~0); 77419#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 77420#L1534-1 assume !(1 == ~E_6~0); 75483#L1539-1 assume !(1 == ~E_7~0); 75484#L1544-1 assume !(1 == ~E_8~0); 75896#L1549-1 assume !(1 == ~E_9~0); 77380#L1554-1 assume !(1 == ~E_10~0); 77373#L1559-1 assume !(1 == ~E_11~0); 77207#L1564-1 assume !(1 == ~E_12~0); 77208#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 77408#L1574-1 assume { :end_inline_reset_delta_events } true; 75659#L1940-2 [2021-12-07 00:34:15,276 INFO L793 eck$LassoCheckResult]: Loop: 75659#L1940-2 assume !false; 75660#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 76985#L1266 assume !false; 76986#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 76190#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 75922#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 76320#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 76321#L1079 assume !(0 != eval_~tmp~0#1); 77588#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 77385#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 76900#L1291-3 assume !(0 == ~M_E~0); 76782#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 76783#L1296-3 assume !(0 == ~T2_E~0); 77456#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 77457#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 77583#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 77582#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 77581#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 77580#L1326-3 assume !(0 == ~T8_E~0); 77366#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 76822#L1336-3 assume !(0 == ~T10_E~0); 76823#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 77578#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 77577#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 77576#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 77575#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 77574#L1366-3 assume !(0 == ~E_2~0); 77573#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 77189#L1376-3 assume !(0 == ~E_4~0); 77190#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 77022#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 77023#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 77215#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 77216#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 75766#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 75621#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 75622#L1416-3 assume !(0 == ~E_12~0); 76287#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 76288#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77567#L640-45 assume 1 == ~m_pc~0; 77081#L641-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 75857#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75858#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 77565#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 77564#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77563#L659-45 assume 1 == ~t1_pc~0; 77561#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 77560#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77559#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 77354#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 76938#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76939#L678-45 assume !(1 == ~t2_pc~0); 77556#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 77555#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 77554#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 77235#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 77236#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77386#L697-45 assume 1 == ~t3_pc~0; 76668#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 76669#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77481#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 77550#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 77549#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77548#L716-45 assume 1 == ~t4_pc~0; 76484#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 76485#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77503#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 76489#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 76490#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77546#L735-45 assume !(1 == ~t5_pc~0); 77545#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 77411#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77412#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 77543#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 77414#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 77415#L754-45 assume 1 == ~t6_pc~0; 76650#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 76651#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 77502#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 77541#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 77540#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 77539#L773-45 assume 1 == ~t7_pc~0; 77107#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 75930#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 76869#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 77262#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 77263#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 77537#L792-45 assume !(1 == ~t8_pc~0); 77536#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 77120#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 75652#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 75512#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 75513#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 76006#L811-45 assume 1 == ~t9_pc~0; 75795#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 75797#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 77434#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 76859#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 76458#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 76243#L830-45 assume !(1 == ~t10_pc~0); 76245#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 77525#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 77381#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 75672#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 75673#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77523#L849-45 assume 1 == ~t11_pc~0; 76621#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 75877#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 75510#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 75406#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 75407#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 75665#L868-45 assume !(1 == ~t12_pc~0); 75667#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 75605#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 75606#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 76966#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 77492#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 77512#L887-45 assume 1 == ~t13_pc~0; 77511#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 76979#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 76980#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 77509#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 77508#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76993#L1439-3 assume !(1 == ~M_E~0); 76967#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 75657#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 75658#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 75814#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 76760#L1459-3 assume !(1 == ~T5_E~0); 76761#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 77261#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 77193#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 77194#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 77264#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 76439#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 76440#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 77108#L1499-3 assume !(1 == ~T13_E~0); 76720#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 76721#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 77204#L1514-3 assume !(1 == ~E_2~0); 77237#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 76356#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 76357#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 77287#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 76631#L1539-3 assume !(1 == ~E_7~0); 76094#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 76095#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 76600#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 75710#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 75711#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 76864#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 76865#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 75589#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 75360#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 75634#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 75595#L1959 assume !(0 == start_simulation_~tmp~3#1); 75597#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 75629#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 75580#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 76906#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 77040#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 77283#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 77300#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 77301#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 75659#L1940-2 [2021-12-07 00:34:15,276 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:15,277 INFO L85 PathProgramCache]: Analyzing trace with hash 350046660, now seen corresponding path program 1 times [2021-12-07 00:34:15,277 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:15,277 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [798256598] [2021-12-07 00:34:15,277 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:15,277 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:15,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:15,308 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:15,308 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:15,308 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [798256598] [2021-12-07 00:34:15,308 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [798256598] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:15,308 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:15,308 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:15,308 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1355974206] [2021-12-07 00:34:15,308 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:15,309 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:34:15,309 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:15,309 INFO L85 PathProgramCache]: Analyzing trace with hash 1602224605, now seen corresponding path program 1 times [2021-12-07 00:34:15,309 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:15,309 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1994776354] [2021-12-07 00:34:15,310 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:15,310 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:15,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:15,353 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:15,353 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:15,353 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1994776354] [2021-12-07 00:34:15,353 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1994776354] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:15,353 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:15,353 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:15,353 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1371240857] [2021-12-07 00:34:15,354 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:15,354 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:34:15,354 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:34:15,354 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-07 00:34:15,354 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-07 00:34:15,355 INFO L87 Difference]: Start difference. First operand 3771 states and 5505 transitions. cyclomatic complexity: 1735 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:15,484 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:34:15,484 INFO L93 Difference]: Finished difference Result 5396 states and 7860 transitions. [2021-12-07 00:34:15,484 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-07 00:34:15,485 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5396 states and 7860 transitions. [2021-12-07 00:34:15,499 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5216 [2021-12-07 00:34:15,510 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5396 states to 5396 states and 7860 transitions. [2021-12-07 00:34:15,510 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5396 [2021-12-07 00:34:15,512 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5396 [2021-12-07 00:34:15,512 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5396 states and 7860 transitions. [2021-12-07 00:34:15,515 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:34:15,515 INFO L681 BuchiCegarLoop]: Abstraction has 5396 states and 7860 transitions. [2021-12-07 00:34:15,519 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5396 states and 7860 transitions. [2021-12-07 00:34:15,564 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5396 to 3771. [2021-12-07 00:34:15,568 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3771 states, 3771 states have (on average 1.4590294351630868) internal successors, (5502), 3770 states have internal predecessors, (5502), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:15,575 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3771 states to 3771 states and 5502 transitions. [2021-12-07 00:34:15,575 INFO L704 BuchiCegarLoop]: Abstraction has 3771 states and 5502 transitions. [2021-12-07 00:34:15,575 INFO L587 BuchiCegarLoop]: Abstraction has 3771 states and 5502 transitions. [2021-12-07 00:34:15,575 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-07 00:34:15,575 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3771 states and 5502 transitions. [2021-12-07 00:34:15,584 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3596 [2021-12-07 00:34:15,584 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:34:15,584 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:34:15,586 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:15,586 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:15,587 INFO L791 eck$LassoCheckResult]: Stem: 85451#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 85452#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 86463#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 86464#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 86554#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 85917#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 85382#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 85383#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 86208#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 86209#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 86311#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 86312#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 85156#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 85157#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 86341#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 85691#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 85692#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 86261#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 85595#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 85596#L1291 assume !(0 == ~M_E~0); 86555#L1291-2 assume !(0 == ~T1_E~0); 86553#L1296-1 assume !(0 == ~T2_E~0); 85751#L1301-1 assume !(0 == ~T3_E~0); 85752#L1306-1 assume !(0 == ~T4_E~0); 86270#L1311-1 assume !(0 == ~T5_E~0); 84996#L1316-1 assume !(0 == ~T6_E~0); 84997#L1321-1 assume !(0 == ~T7_E~0); 85764#L1326-1 assume !(0 == ~T8_E~0); 84825#L1331-1 assume !(0 == ~T9_E~0); 84526#L1336-1 assume !(0 == ~T10_E~0); 84527#L1341-1 assume !(0 == ~T11_E~0); 84606#L1346-1 assume !(0 == ~T12_E~0); 84607#L1351-1 assume !(0 == ~T13_E~0); 84945#L1356-1 assume !(0 == ~E_M~0); 84946#L1361-1 assume !(0 == ~E_1~0); 86491#L1366-1 assume !(0 == ~E_2~0); 84986#L1371-1 assume !(0 == ~E_3~0); 84987#L1376-1 assume !(0 == ~E_4~0); 85811#L1381-1 assume !(0 == ~E_5~0); 85812#L1386-1 assume !(0 == ~E_6~0); 86522#L1391-1 assume !(0 == ~E_7~0); 86541#L1396-1 assume !(0 == ~E_8~0); 85723#L1401-1 assume !(0 == ~E_9~0); 85724#L1406-1 assume !(0 == ~E_10~0); 86005#L1411-1 assume !(0 == ~E_11~0); 86006#L1416-1 assume !(0 == ~E_12~0); 85636#L1421-1 assume !(0 == ~E_13~0); 85180#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 85181#L640 assume !(1 == ~m_pc~0); 85688#L640-2 is_master_triggered_~__retres1~0#1 := 0; 85687#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 85780#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 85673#L1603 assume !(0 != activate_threads_~tmp~1#1); 85674#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 85307#L659 assume 1 == ~t1_pc~0; 85308#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 85414#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86371#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 85434#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 85435#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 85448#L678 assume !(1 == ~t2_pc~0); 86416#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 86518#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 86519#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 85547#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 85548#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 85668#L697 assume !(1 == ~t3_pc~0); 85669#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 85792#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 85600#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 85579#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 85580#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 86453#L716 assume 1 == ~t4_pc~0; 86439#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 85290#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 85291#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 84788#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 84789#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 86088#L735 assume !(1 == ~t5_pc~0); 84750#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 84751#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 85199#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 86116#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 85744#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 85745#L754 assume 1 == ~t6_pc~0; 85501#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 85396#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 85397#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 85369#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 85370#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 86198#L773 assume !(1 == ~t7_pc~0); 84949#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 84948#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 85781#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 85753#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 85754#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 85801#L792 assume 1 == ~t8_pc~0; 85978#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 86315#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 85795#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 85748#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 85671#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 85672#L811 assume 1 == ~t9_pc~0; 85878#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 86352#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 86226#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 85873#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 85684#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 85685#L830 assume !(1 == ~t10_pc~0); 85408#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 84928#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 84623#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 84624#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 84909#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 86217#L849 assume 1 == ~t11_pc~0; 86218#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 84726#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 84727#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 85317#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 86123#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 86124#L868 assume !(1 == ~t12_pc~0); 85532#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 85531#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 85324#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 85325#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 84960#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 84961#L887 assume 1 == ~t13_pc~0; 86136#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 85573#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 85574#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 86012#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 84666#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 84667#L1439 assume !(1 == ~M_E~0); 85742#L1439-2 assume !(1 == ~T1_E~0); 84837#L1444-1 assume !(1 == ~T2_E~0); 84838#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 85313#L1454-1 assume !(1 == ~T4_E~0); 85314#L1459-1 assume !(1 == ~T5_E~0); 85870#L1464-1 assume !(1 == ~T6_E~0); 85871#L1469-1 assume !(1 == ~T7_E~0); 85948#L1474-1 assume !(1 == ~T8_E~0); 85637#L1479-1 assume !(1 == ~T9_E~0); 85638#L1484-1 assume !(1 == ~T10_E~0); 85874#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 85523#L1494-1 assume !(1 == ~T12_E~0); 85524#L1499-1 assume !(1 == ~T13_E~0); 85712#L1504-1 assume !(1 == ~E_M~0); 85713#L1509-1 assume !(1 == ~E_1~0); 86298#L1514-1 assume !(1 == ~E_2~0); 85980#L1519-1 assume !(1 == ~E_3~0); 85981#L1524-1 assume !(1 == ~E_4~0); 86504#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 86505#L1534-1 assume !(1 == ~E_6~0); 84659#L1539-1 assume !(1 == ~E_7~0); 84660#L1544-1 assume !(1 == ~E_8~0); 85072#L1549-1 assume !(1 == ~E_9~0); 86483#L1554-1 assume !(1 == ~E_10~0); 86476#L1559-1 assume !(1 == ~E_11~0); 86336#L1564-1 assume !(1 == ~E_12~0); 86337#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 86500#L1574-1 assume { :end_inline_reset_delta_events } true; 84835#L1940-2 [2021-12-07 00:34:15,587 INFO L793 eck$LassoCheckResult]: Loop: 84835#L1940-2 assume !false; 84836#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 85117#L1266 assume !false; 86144#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 85366#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 85098#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 85492#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 85493#L1079 assume !(0 != eval_~tmp~0#1); 85454#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 85455#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 86063#L1291-3 assume !(0 == ~M_E~0); 85945#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 85946#L1296-3 assume !(0 == ~T2_E~0); 86534#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 86486#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 85602#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 84875#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 84876#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 84976#L1326-3 assume !(0 == ~T8_E~0); 85735#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 85987#L1336-3 assume !(0 == ~T10_E~0); 85988#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 85304#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 85284#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 85228#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 85229#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 85793#L1366-3 assume !(0 == ~E_2~0); 84581#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 84582#L1376-3 assume !(0 == ~E_4~0); 86321#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 86177#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 86178#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 86344#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 86345#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 84944#L1406-3 assume !(0 == ~E_10~0); 84797#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 84798#L1416-3 assume !(0 == ~E_12~0); 85461#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 85462#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 85569#L640-45 assume 1 == ~m_pc~0; 85571#L641-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 85033#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 85034#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 84575#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 84576#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 84674#L659-45 assume 1 == ~t1_pc~0; 84675#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 85115#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86079#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 86080#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 86101#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 86102#L678-45 assume !(1 == ~t2_pc~0); 86044#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 85575#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 85576#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 85727#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 86363#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 86485#L697-45 assume 1 == ~t3_pc~0; 85833#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 85834#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86434#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 85994#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 85995#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 86025#L716-45 assume 1 == ~t4_pc~0; 85654#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 85655#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 86212#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 85659#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 85660#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 85321#L735-45 assume !(1 == ~t5_pc~0); 85323#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 85867#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 86442#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 86443#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 86503#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 86498#L754-45 assume 1 == ~t6_pc~0; 85815#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 85816#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 85243#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 85244#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 85819#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 85551#L773-45 assume 1 == ~t7_pc~0; 85552#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 85107#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 86031#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 86320#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 85557#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 85223#L792-45 assume !(1 == ~t8_pc~0); 85225#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 86264#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 84828#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 84688#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 84689#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 85182#L811-45 assume 1 == ~t9_pc~0; 84971#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 84973#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 86190#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 86021#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 85628#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 85418#L830-45 assume !(1 == ~t10_pc~0); 84616#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 84617#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 85739#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 84848#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 84849#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 84595#L849-45 assume 1 == ~t11_pc~0; 84597#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 85053#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 84686#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 84583#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 84584#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 84841#L868-45 assume !(1 == ~t12_pc~0); 84843#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 84779#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 84780#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 86127#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 86383#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 86384#L887-45 assume 1 == ~t13_pc~0; 86211#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 84851#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 86138#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 86495#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 84813#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 84814#L1439-3 assume !(1 == ~M_E~0); 86128#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 84833#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 84834#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 84990#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 85926#L1459-3 assume !(1 == ~T5_E~0); 85927#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 86386#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 86324#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 86325#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 86387#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 85607#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 85608#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 86254#L1499-3 assume !(1 == ~T13_E~0); 85885#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 85886#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 86333#L1514-3 assume !(1 == ~E_2~0); 86364#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 85528#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 85529#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 86407#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 85796#L1539-3 assume !(1 == ~E_7~0); 85270#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 85271#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 85767#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 84886#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 84887#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 86026#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 86027#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 84765#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 84537#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 84810#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 84771#L1959 assume !(0 == start_simulation_~tmp~3#1); 84773#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 84805#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 84756#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 86069#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 86193#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 86404#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 86420#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 86421#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 84835#L1940-2 [2021-12-07 00:34:15,588 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:15,588 INFO L85 PathProgramCache]: Analyzing trace with hash -1492429054, now seen corresponding path program 1 times [2021-12-07 00:34:15,588 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:15,588 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [894598897] [2021-12-07 00:34:15,588 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:15,588 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:15,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:15,622 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:15,622 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:15,622 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [894598897] [2021-12-07 00:34:15,623 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [894598897] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:15,623 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:15,623 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:15,623 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [238218135] [2021-12-07 00:34:15,623 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:15,624 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:34:15,624 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:15,624 INFO L85 PathProgramCache]: Analyzing trace with hash -2017582565, now seen corresponding path program 1 times [2021-12-07 00:34:15,624 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:15,624 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [881488073] [2021-12-07 00:34:15,625 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:15,625 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:15,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:15,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:15,673 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:15,673 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [881488073] [2021-12-07 00:34:15,673 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [881488073] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:15,674 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:15,674 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:15,674 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [209049945] [2021-12-07 00:34:15,674 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:15,674 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:34:15,675 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:34:15,675 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-07 00:34:15,675 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-07 00:34:15,675 INFO L87 Difference]: Start difference. First operand 3771 states and 5502 transitions. cyclomatic complexity: 1732 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:15,950 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:34:15,950 INFO L93 Difference]: Finished difference Result 10636 states and 15357 transitions. [2021-12-07 00:34:15,950 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-07 00:34:15,951 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10636 states and 15357 transitions. [2021-12-07 00:34:15,991 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10253 [2021-12-07 00:34:16,026 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10636 states to 10636 states and 15357 transitions. [2021-12-07 00:34:16,027 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10636 [2021-12-07 00:34:16,034 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10636 [2021-12-07 00:34:16,034 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10636 states and 15357 transitions. [2021-12-07 00:34:16,064 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:34:16,064 INFO L681 BuchiCegarLoop]: Abstraction has 10636 states and 15357 transitions. [2021-12-07 00:34:16,070 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10636 states and 15357 transitions. [2021-12-07 00:34:16,166 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10636 to 10252. [2021-12-07 00:34:16,178 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10252 states, 10252 states have (on average 1.4458642216152946) internal successors, (14823), 10251 states have internal predecessors, (14823), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:16,200 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10252 states to 10252 states and 14823 transitions. [2021-12-07 00:34:16,200 INFO L704 BuchiCegarLoop]: Abstraction has 10252 states and 14823 transitions. [2021-12-07 00:34:16,200 INFO L587 BuchiCegarLoop]: Abstraction has 10252 states and 14823 transitions. [2021-12-07 00:34:16,200 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-07 00:34:16,200 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10252 states and 14823 transitions. [2021-12-07 00:34:16,223 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10069 [2021-12-07 00:34:16,223 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:34:16,223 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:34:16,225 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:16,225 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:16,225 INFO L791 eck$LassoCheckResult]: Stem: 99871#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 99872#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 101020#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 101021#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 101167#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 100369#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 99800#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 99801#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 100695#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 100696#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 100823#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 100824#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 99569#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 99570#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 100856#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 100121#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 100122#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 100759#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 100022#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 100023#L1291 assume !(0 == ~M_E~0); 101168#L1291-2 assume !(0 == ~T1_E~0); 101166#L1296-1 assume !(0 == ~T2_E~0); 100187#L1301-1 assume !(0 == ~T3_E~0); 100188#L1306-1 assume !(0 == ~T4_E~0); 100770#L1311-1 assume !(0 == ~T5_E~0); 99413#L1316-1 assume !(0 == ~T6_E~0); 99414#L1321-1 assume !(0 == ~T7_E~0); 100200#L1326-1 assume !(0 == ~T8_E~0); 99240#L1331-1 assume !(0 == ~T9_E~0); 98943#L1336-1 assume !(0 == ~T10_E~0); 98944#L1341-1 assume !(0 == ~T11_E~0); 99022#L1346-1 assume !(0 == ~T12_E~0); 99023#L1351-1 assume !(0 == ~T13_E~0); 99361#L1356-1 assume !(0 == ~E_M~0); 99362#L1361-1 assume !(0 == ~E_1~0); 101057#L1366-1 assume !(0 == ~E_2~0); 99403#L1371-1 assume !(0 == ~E_3~0); 99404#L1376-1 assume !(0 == ~E_4~0); 100254#L1381-1 assume !(0 == ~E_5~0); 100255#L1386-1 assume !(0 == ~E_6~0); 101109#L1391-1 assume !(0 == ~E_7~0); 101138#L1396-1 assume !(0 == ~E_8~0); 100155#L1401-1 assume !(0 == ~E_9~0); 100156#L1406-1 assume !(0 == ~E_10~0); 100462#L1411-1 assume !(0 == ~E_11~0); 100463#L1416-1 assume !(0 == ~E_12~0); 100068#L1421-1 assume !(0 == ~E_13~0); 99594#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 99595#L640 assume !(1 == ~m_pc~0); 100265#L640-2 is_master_triggered_~__retres1~0#1 := 0; 100218#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 100219#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 100105#L1603 assume !(0 != activate_threads_~tmp~1#1); 100106#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 99724#L659 assume !(1 == ~t1_pc~0); 99725#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 100916#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 100887#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 99854#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 99855#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 99869#L678 assume !(1 == ~t2_pc~0); 100949#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 101101#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 101102#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 99973#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 99974#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 100100#L697 assume !(1 == ~t3_pc~0); 100101#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 100235#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 100028#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 100007#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 100008#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 100999#L716 assume 1 == ~t4_pc~0; 100982#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 99705#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 99706#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 99203#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 99204#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 100545#L735 assume !(1 == ~t5_pc~0); 99165#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 99166#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 99616#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 100575#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 100179#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 100180#L754 assume 1 == ~t6_pc~0; 99923#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 99814#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 99815#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 99785#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 99786#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 100685#L773 assume !(1 == ~t7_pc~0); 99365#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 99364#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 100220#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 100189#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 100190#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 100244#L792 assume 1 == ~t8_pc~0; 100429#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 100827#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 100238#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 100182#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 100103#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 100104#L811 assume 1 == ~t9_pc~0; 100323#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 100867#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 100713#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 100319#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 100117#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 100118#L830 assume !(1 == ~t10_pc~0); 99824#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 99344#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 99039#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 99040#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 99326#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 100704#L849 assume 1 == ~t11_pc~0; 100705#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 99141#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 99142#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 99731#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 100586#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 100587#L868 assume !(1 == ~t12_pc~0); 99957#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 99956#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 99740#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 99741#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 99376#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 99377#L887 assume 1 == ~t13_pc~0; 100603#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 100001#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 100002#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 100472#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 99082#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 99083#L1439 assume !(1 == ~M_E~0); 100175#L1439-2 assume !(1 == ~T1_E~0); 99252#L1444-1 assume !(1 == ~T2_E~0); 99253#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 99727#L1454-1 assume !(1 == ~T4_E~0); 99728#L1459-1 assume !(1 == ~T5_E~0); 100316#L1464-1 assume !(1 == ~T6_E~0); 100317#L1469-1 assume !(1 == ~T7_E~0); 100398#L1474-1 assume !(1 == ~T8_E~0); 100069#L1479-1 assume !(1 == ~T9_E~0); 100070#L1484-1 assume !(1 == ~T10_E~0); 100320#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 99945#L1494-1 assume !(1 == ~T12_E~0); 99946#L1499-1 assume !(1 == ~T13_E~0); 100144#L1504-1 assume !(1 == ~E_M~0); 100145#L1509-1 assume !(1 == ~E_1~0); 100806#L1514-1 assume !(1 == ~E_2~0); 100431#L1519-1 assume !(1 == ~E_3~0); 100432#L1524-1 assume !(1 == ~E_4~0); 101082#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 101083#L1534-1 assume !(1 == ~E_6~0); 99075#L1539-1 assume !(1 == ~E_7~0); 99076#L1544-1 assume !(1 == ~E_8~0); 99489#L1549-1 assume !(1 == ~E_9~0); 101039#L1554-1 assume !(1 == ~E_10~0); 101036#L1559-1 assume !(1 == ~E_11~0); 100850#L1564-1 assume !(1 == ~E_12~0); 100851#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 101072#L1574-1 assume { :end_inline_reset_delta_events } true; 99250#L1940-2 [2021-12-07 00:34:16,226 INFO L793 eck$LassoCheckResult]: Loop: 99250#L1940-2 assume !false; 99251#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 100613#L1266 assume !false; 100614#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 101176#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 100804#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 100805#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 100811#L1079 assume !(0 != eval_~tmp~0#1); 99874#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 99875#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 100521#L1291-3 assume !(0 == ~M_E~0); 100399#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 100400#L1296-3 assume !(0 == ~T2_E~0); 101131#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 101050#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 100031#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 99290#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 99291#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 99392#L1326-3 assume !(0 == ~T8_E~0); 100170#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 100440#L1336-3 assume !(0 == ~T10_E~0); 100441#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 100974#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 108923#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 108922#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 108920#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 108918#L1366-3 assume !(0 == ~E_2~0); 108916#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 108914#L1376-3 assume !(0 == ~E_4~0); 108912#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 108910#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 108908#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 108906#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 108904#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 108902#L1406-3 assume !(0 == ~E_10~0); 108901#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 108900#L1416-3 assume !(0 == ~E_12~0); 108899#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 108898#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 99998#L640-45 assume !(1 == ~m_pc~0); 99999#L640-47 is_master_triggered_~__retres1~0#1 := 0; 99450#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 99451#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 98991#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 98992#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 99090#L659-45 assume !(1 == ~t1_pc~0); 99091#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 99529#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 100536#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 100537#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 100559#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 100560#L678-45 assume !(1 == ~t2_pc~0); 100504#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 100003#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 100004#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 100161#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 100877#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 101047#L697-45 assume !(1 == ~t3_pc~0); 101049#L697-47 is_transmit3_triggered_~__retres1~3#1 := 0; 108781#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 108779#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 108778#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 108768#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 108767#L716-45 assume !(1 == ~t4_pc~0); 108765#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 108764#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 108763#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 108762#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 100979#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 99737#L735-45 assume !(1 == ~t5_pc~0); 99739#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 100313#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 100985#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 100986#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 101078#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 101070#L754-45 assume 1 == ~t6_pc~0; 100260#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 100261#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 99660#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 99661#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 100264#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 99978#L773-45 assume !(1 == ~t7_pc~0); 99522#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 99523#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 100490#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 100832#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 99984#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 99640#L792-45 assume 1 == ~t8_pc~0; 99641#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 100765#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 99243#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 99103#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 99104#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 99598#L811-45 assume 1 == ~t9_pc~0; 99387#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 99389#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 100675#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 100481#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 100060#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 99837#L830-45 assume !(1 == ~t10_pc~0); 99032#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 99033#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 100174#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 99263#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 99264#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 99008#L849-45 assume !(1 == ~t11_pc~0); 99009#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 99470#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 99101#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 98999#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 99000#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 99256#L868-45 assume 1 == ~t12_pc~0; 99257#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 99194#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 99195#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 100590#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 100899#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 100900#L887-45 assume !(1 == ~t13_pc~0); 99265#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 99266#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 100606#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 101067#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 99228#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 99229#L1439-3 assume !(1 == ~M_E~0); 100618#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 99248#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 99249#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 99407#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 100379#L1459-3 assume !(1 == ~T5_E~0); 100380#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 100902#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 100836#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 100837#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 100903#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 100036#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 100037#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 100752#L1499-3 assume !(1 == ~T13_E~0); 100333#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 100334#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 100847#L1514-3 assume !(1 == ~E_2~0); 100878#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 99953#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 99954#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 100930#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 100239#L1539-3 assume !(1 == ~E_7~0); 99687#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 99688#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 100203#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 99301#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 99302#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 100486#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 100487#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 99180#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 98954#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 99225#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 99186#L1959 assume !(0 == start_simulation_~tmp~3#1); 99188#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 99220#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 107648#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 107647#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 107646#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 107644#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 107642#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 101051#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 99250#L1940-2 [2021-12-07 00:34:16,226 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:16,226 INFO L85 PathProgramCache]: Analyzing trace with hash -121367293, now seen corresponding path program 1 times [2021-12-07 00:34:16,226 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:16,226 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [918693425] [2021-12-07 00:34:16,226 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:16,226 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:16,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:16,263 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:16,263 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:16,263 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [918693425] [2021-12-07 00:34:16,263 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [918693425] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:16,263 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:16,264 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-07 00:34:16,264 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1639192179] [2021-12-07 00:34:16,264 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:16,264 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:34:16,264 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:16,264 INFO L85 PathProgramCache]: Analyzing trace with hash 1500039968, now seen corresponding path program 1 times [2021-12-07 00:34:16,264 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:16,265 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1970994675] [2021-12-07 00:34:16,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:16,265 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:16,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:16,295 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:16,295 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:16,295 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1970994675] [2021-12-07 00:34:16,295 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1970994675] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:16,296 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:16,296 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:16,296 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [56882293] [2021-12-07 00:34:16,296 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:16,296 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:34:16,296 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:34:16,296 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-07 00:34:16,297 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-07 00:34:16,297 INFO L87 Difference]: Start difference. First operand 10252 states and 14823 transitions. cyclomatic complexity: 4573 Second operand has 5 states, 5 states have (on average 32.2) internal successors, (161), 5 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:16,586 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:34:16,586 INFO L93 Difference]: Finished difference Result 28084 states and 40677 transitions. [2021-12-07 00:34:16,586 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-07 00:34:16,587 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28084 states and 40677 transitions. [2021-12-07 00:34:16,693 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 27680 [2021-12-07 00:34:16,745 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28084 states to 28084 states and 40677 transitions. [2021-12-07 00:34:16,746 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28084 [2021-12-07 00:34:16,756 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28084 [2021-12-07 00:34:16,756 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28084 states and 40677 transitions. [2021-12-07 00:34:16,766 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:34:16,766 INFO L681 BuchiCegarLoop]: Abstraction has 28084 states and 40677 transitions. [2021-12-07 00:34:16,776 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28084 states and 40677 transitions. [2021-12-07 00:34:17,010 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28084 to 10516. [2021-12-07 00:34:17,022 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10516 states, 10516 states have (on average 1.4346709775580069) internal successors, (15087), 10515 states have internal predecessors, (15087), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:17,046 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10516 states to 10516 states and 15087 transitions. [2021-12-07 00:34:17,047 INFO L704 BuchiCegarLoop]: Abstraction has 10516 states and 15087 transitions. [2021-12-07 00:34:17,047 INFO L587 BuchiCegarLoop]: Abstraction has 10516 states and 15087 transitions. [2021-12-07 00:34:17,047 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-07 00:34:17,047 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10516 states and 15087 transitions. [2021-12-07 00:34:17,077 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10330 [2021-12-07 00:34:17,077 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:34:17,077 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:34:17,079 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:17,079 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:17,079 INFO L791 eck$LassoCheckResult]: Stem: 138244#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 138245#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 139577#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 139578#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 139788#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 138783#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 138171#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 138172#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 139144#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 139145#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 139324#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 139325#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 137928#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 137929#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 139364#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 138509#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 138510#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 139217#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 138407#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 138408#L1291 assume !(0 == ~M_E~0); 139789#L1291-2 assume !(0 == ~T1_E~0); 139785#L1296-1 assume !(0 == ~T2_E~0); 138578#L1301-1 assume !(0 == ~T3_E~0); 138579#L1306-1 assume !(0 == ~T4_E~0); 139237#L1311-1 assume !(0 == ~T5_E~0); 137769#L1316-1 assume !(0 == ~T6_E~0); 137770#L1321-1 assume !(0 == ~T7_E~0); 138591#L1326-1 assume !(0 == ~T8_E~0); 137594#L1331-1 assume !(0 == ~T9_E~0); 137292#L1336-1 assume !(0 == ~T10_E~0); 137293#L1341-1 assume !(0 == ~T11_E~0); 137371#L1346-1 assume !(0 == ~T12_E~0); 137372#L1351-1 assume !(0 == ~T13_E~0); 137716#L1356-1 assume !(0 == ~E_M~0); 137717#L1361-1 assume !(0 == ~E_1~0); 139636#L1366-1 assume !(0 == ~E_2~0); 137759#L1371-1 assume !(0 == ~E_3~0); 137760#L1376-1 assume !(0 == ~E_4~0); 138656#L1381-1 assume !(0 == ~E_5~0); 138657#L1386-1 assume !(0 == ~E_6~0); 139705#L1391-1 assume !(0 == ~E_7~0); 139754#L1396-1 assume !(0 == ~E_8~0); 138544#L1401-1 assume !(0 == ~E_9~0); 138545#L1406-1 assume !(0 == ~E_10~0); 138884#L1411-1 assume !(0 == ~E_11~0); 138885#L1416-1 assume !(0 == ~E_12~0); 138452#L1421-1 assume !(0 == ~E_13~0); 137954#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 137955#L640 assume !(1 == ~m_pc~0); 138666#L640-2 is_master_triggered_~__retres1~0#1 := 0; 138612#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 138613#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 138494#L1603 assume !(0 != activate_threads_~tmp~1#1); 138495#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 138091#L659 assume !(1 == ~t1_pc~0); 138092#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 139446#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 139409#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 138226#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 138227#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 138242#L678 assume !(1 == ~t2_pc~0); 139482#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 139696#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 139697#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 138353#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 138354#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 138489#L697 assume !(1 == ~t3_pc~0); 138490#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 138630#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 139518#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 138389#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 138390#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 139547#L716 assume 1 == ~t4_pc~0; 139525#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 138070#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 138071#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 137553#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 137554#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 138976#L735 assume !(1 == ~t5_pc~0); 137513#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 137514#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 137977#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 139010#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 138570#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 138571#L754 assume 1 == ~t6_pc~0; 138303#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 138186#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 138187#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 138156#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 138157#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 139130#L773 assume !(1 == ~t7_pc~0); 137720#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 137719#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 138614#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 138580#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 138581#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 138643#L792 assume 1 == ~t8_pc~0; 138854#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 139328#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 138636#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 138573#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 138492#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 138493#L811 assume 1 == ~t9_pc~0; 138733#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 139380#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 139168#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 138728#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 138505#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 138506#L830 assume !(1 == ~t10_pc~0); 138198#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 137699#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 137388#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 137389#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 137681#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 139157#L849 assume 1 == ~t11_pc~0; 139158#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 137489#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 137490#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 138099#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 139022#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 139023#L868 assume !(1 == ~t12_pc~0); 138338#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 138337#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 138108#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 138109#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 137731#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 137732#L887 assume 1 == ~t13_pc~0; 139036#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 138383#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 138384#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 138894#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 137430#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 137431#L1439 assume !(1 == ~M_E~0); 138566#L1439-2 assume !(1 == ~T1_E~0); 137606#L1444-1 assume !(1 == ~T2_E~0); 137607#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 138097#L1454-1 assume !(1 == ~T4_E~0); 138098#L1459-1 assume !(1 == ~T5_E~0); 138725#L1464-1 assume !(1 == ~T6_E~0); 138726#L1469-1 assume !(1 == ~T7_E~0); 138815#L1474-1 assume !(1 == ~T8_E~0); 138453#L1479-1 assume !(1 == ~T9_E~0); 138454#L1484-1 assume !(1 == ~T10_E~0); 138729#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 138326#L1494-1 assume !(1 == ~T12_E~0); 138327#L1499-1 assume !(1 == ~T13_E~0); 138532#L1504-1 assume !(1 == ~E_M~0); 138533#L1509-1 assume !(1 == ~E_1~0); 139294#L1514-1 assume !(1 == ~E_2~0); 138856#L1519-1 assume !(1 == ~E_3~0); 138857#L1524-1 assume !(1 == ~E_4~0); 139669#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 139670#L1534-1 assume !(1 == ~E_6~0); 137423#L1539-1 assume !(1 == ~E_7~0); 137424#L1544-1 assume !(1 == ~E_8~0); 137847#L1549-1 assume !(1 == ~E_9~0); 139606#L1554-1 assume !(1 == ~E_10~0); 139599#L1559-1 assume !(1 == ~E_11~0); 139356#L1564-1 assume !(1 == ~E_12~0); 139357#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 139657#L1574-1 assume { :end_inline_reset_delta_events } true; 139716#L1940-2 [2021-12-07 00:34:17,080 INFO L793 eck$LassoCheckResult]: Loop: 139716#L1940-2 assume !false; 140327#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 140323#L1266 assume !false; 140315#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 140316#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 139292#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 139293#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 139308#L1079 assume !(0 != eval_~tmp~0#1); 139310#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 143509#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 143507#L1291-3 assume !(0 == ~M_E~0); 143503#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 143504#L1296-3 assume !(0 == ~T2_E~0); 143497#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 143498#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 143491#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 143492#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 143485#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 143486#L1326-3 assume !(0 == ~T8_E~0); 143479#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 143480#L1336-3 assume !(0 == ~T10_E~0); 143473#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 143474#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 143467#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 143468#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 143461#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 143462#L1366-3 assume !(0 == ~E_2~0); 143455#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 143456#L1376-3 assume !(0 == ~E_4~0); 143449#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 143450#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 143443#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 143444#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 143429#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 143430#L1406-3 assume !(0 == ~E_10~0); 143425#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 143426#L1416-3 assume !(0 == ~E_12~0); 138256#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 138257#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 138379#L640-45 assume !(1 == ~m_pc~0); 138380#L640-47 is_master_triggered_~__retres1~0#1 := 0; 144795#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 144794#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 144793#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 144792#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 144791#L659-45 assume !(1 == ~t1_pc~0); 144790#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 144789#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 144788#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 144787#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 144786#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 144785#L678-45 assume !(1 == ~t2_pc~0); 144783#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 144782#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 144781#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 144780#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 144779#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 144778#L697-45 assume 1 == ~t3_pc~0; 144776#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 144774#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 144772#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 144770#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 144769#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 144768#L716-45 assume !(1 == ~t4_pc~0); 144766#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 144765#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 144764#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 144763#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 144762#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 144761#L735-45 assume 1 == ~t5_pc~0; 144759#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 144758#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 144757#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 144756#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 144755#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 144754#L754-45 assume !(1 == ~t6_pc~0); 144752#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 144751#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 144750#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 144749#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 144748#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 144720#L773-45 assume !(1 == ~t7_pc~0); 144718#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 144715#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 144712#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 144710#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 144708#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 144706#L792-45 assume !(1 == ~t8_pc~0); 144704#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 144701#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 144698#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 144696#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 144694#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 144692#L811-45 assume 1 == ~t9_pc~0; 144690#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 144687#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 144684#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 144682#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 144680#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 144678#L830-45 assume 1 == ~t10_pc~0; 144675#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 144671#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 144670#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 144669#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 144312#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 144310#L849-45 assume !(1 == ~t11_pc~0); 144307#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 144304#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 144302#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 144300#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 144298#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 144296#L868-45 assume !(1 == ~t12_pc~0); 144294#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 144290#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 144288#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 144286#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 144284#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 144282#L887-45 assume !(1 == ~t13_pc~0); 144279#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 144278#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 144275#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 144273#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 144271#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 144269#L1439-3 assume !(1 == ~M_E~0); 144265#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 144263#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 144260#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 144258#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 144256#L1459-3 assume !(1 == ~T5_E~0); 144254#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 144252#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 144250#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 144249#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 144248#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 144247#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 144246#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 144245#L1499-3 assume !(1 == ~T13_E~0); 144244#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 144243#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 144242#L1514-3 assume !(1 == ~E_2~0); 144241#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 144240#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 144239#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 144238#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 144237#L1539-3 assume !(1 == ~E_7~0); 144236#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 144235#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 144234#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 144233#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 144232#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 144231#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 144230#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 144221#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 144208#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 144207#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 144206#L1959 assume !(0 == start_simulation_~tmp~3#1); 144204#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 143544#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 143531#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 143530#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 143529#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 143528#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 143527#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 143526#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 139716#L1940-2 [2021-12-07 00:34:17,080 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:17,080 INFO L85 PathProgramCache]: Analyzing trace with hash -2061949307, now seen corresponding path program 1 times [2021-12-07 00:34:17,080 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:17,080 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2095965232] [2021-12-07 00:34:17,081 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:17,081 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:17,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:17,109 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:17,110 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:17,110 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2095965232] [2021-12-07 00:34:17,110 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2095965232] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:17,110 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:17,110 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-07 00:34:17,110 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1017148510] [2021-12-07 00:34:17,110 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:17,110 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:34:17,111 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:17,111 INFO L85 PathProgramCache]: Analyzing trace with hash 670605600, now seen corresponding path program 1 times [2021-12-07 00:34:17,111 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:17,111 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1934467899] [2021-12-07 00:34:17,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:17,111 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:17,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:17,140 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:17,140 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:17,140 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1934467899] [2021-12-07 00:34:17,140 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1934467899] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:17,140 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:17,140 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:17,140 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1841960574] [2021-12-07 00:34:17,140 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:17,141 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:34:17,141 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:34:17,141 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:34:17,141 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:34:17,141 INFO L87 Difference]: Start difference. First operand 10516 states and 15087 transitions. cyclomatic complexity: 4573 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:17,289 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:34:17,289 INFO L93 Difference]: Finished difference Result 20156 states and 28805 transitions. [2021-12-07 00:34:17,289 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:34:17,290 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20156 states and 28805 transitions. [2021-12-07 00:34:17,346 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 19949 [2021-12-07 00:34:17,384 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20156 states to 20156 states and 28805 transitions. [2021-12-07 00:34:17,385 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20156 [2021-12-07 00:34:17,393 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20156 [2021-12-07 00:34:17,393 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20156 states and 28805 transitions. [2021-12-07 00:34:17,408 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:34:17,408 INFO L681 BuchiCegarLoop]: Abstraction has 20156 states and 28805 transitions. [2021-12-07 00:34:17,416 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20156 states and 28805 transitions. [2021-12-07 00:34:17,545 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20156 to 20144. [2021-12-07 00:34:17,561 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20144 states, 20144 states have (on average 1.4293586179507545) internal successors, (28793), 20143 states have internal predecessors, (28793), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:17,603 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20144 states to 20144 states and 28793 transitions. [2021-12-07 00:34:17,603 INFO L704 BuchiCegarLoop]: Abstraction has 20144 states and 28793 transitions. [2021-12-07 00:34:17,603 INFO L587 BuchiCegarLoop]: Abstraction has 20144 states and 28793 transitions. [2021-12-07 00:34:17,603 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-07 00:34:17,603 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20144 states and 28793 transitions. [2021-12-07 00:34:17,659 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 19937 [2021-12-07 00:34:17,659 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:34:17,660 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:34:17,662 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:17,662 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:17,662 INFO L791 eck$LassoCheckResult]: Stem: 168901#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 168902#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 170024#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 170025#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 170162#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 169393#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 168834#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 168835#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 169720#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 169721#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 169847#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 169848#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 168601#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 168602#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 169877#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 169146#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 169147#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 169787#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 169050#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 169051#L1291 assume !(0 == ~M_E~0); 170163#L1291-2 assume !(0 == ~T1_E~0); 170158#L1296-1 assume !(0 == ~T2_E~0); 169211#L1301-1 assume !(0 == ~T3_E~0); 169212#L1306-1 assume !(0 == ~T4_E~0); 169798#L1311-1 assume !(0 == ~T5_E~0); 168442#L1316-1 assume !(0 == ~T6_E~0); 168443#L1321-1 assume !(0 == ~T7_E~0); 169223#L1326-1 assume !(0 == ~T8_E~0); 168269#L1331-1 assume !(0 == ~T9_E~0); 167971#L1336-1 assume !(0 == ~T10_E~0); 167972#L1341-1 assume !(0 == ~T11_E~0); 168050#L1346-1 assume !(0 == ~T12_E~0); 168051#L1351-1 assume !(0 == ~T13_E~0); 168389#L1356-1 assume !(0 == ~E_M~0); 168390#L1361-1 assume !(0 == ~E_1~0); 170060#L1366-1 assume !(0 == ~E_2~0); 168432#L1371-1 assume !(0 == ~E_3~0); 168433#L1376-1 assume !(0 == ~E_4~0); 169277#L1381-1 assume !(0 == ~E_5~0); 169278#L1386-1 assume !(0 == ~E_6~0); 170106#L1391-1 assume !(0 == ~E_7~0); 170139#L1396-1 assume !(0 == ~E_8~0); 169179#L1401-1 assume !(0 == ~E_9~0); 169180#L1406-1 assume !(0 == ~E_10~0); 169486#L1411-1 assume !(0 == ~E_11~0); 169487#L1416-1 assume !(0 == ~E_12~0); 169095#L1421-1 assume !(0 == ~E_13~0); 168626#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 168627#L640 assume !(1 == ~m_pc~0); 169287#L640-2 is_master_triggered_~__retres1~0#1 := 0; 169240#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 169241#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 169131#L1603 assume !(0 != activate_threads_~tmp~1#1); 169132#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 168760#L659 assume !(1 == ~t1_pc~0); 168761#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 169938#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 169910#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 168885#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 168886#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 168899#L678 assume !(1 == ~t2_pc~0); 169961#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 170100#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 170101#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 169003#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 169004#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 169126#L697 assume !(1 == ~t3_pc~0); 169127#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 169257#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 169056#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 169035#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 169036#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 170004#L716 assume !(1 == ~t4_pc~0); 169561#L716-2 is_transmit4_triggered_~__retres1~4#1 := 0; 168737#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 168738#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 168231#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 168232#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 169575#L735 assume !(1 == ~t5_pc~0); 168193#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 168194#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 168647#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 169605#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 169204#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 169205#L754 assume 1 == ~t6_pc~0; 168954#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 168848#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 168849#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 168820#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 168821#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 169710#L773 assume !(1 == ~t7_pc~0); 168393#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 168392#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 169242#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 169213#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 169214#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 169266#L792 assume 1 == ~t8_pc~0; 169459#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 169851#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 169260#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 169207#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 169129#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 169130#L811 assume 1 == ~t9_pc~0; 169348#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 169889#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 169742#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 169344#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 169142#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 169143#L830 assume !(1 == ~t10_pc~0); 168858#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 168372#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 168067#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 168068#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 168353#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 169732#L849 assume 1 == ~t11_pc~0; 169733#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 168169#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 168170#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 168767#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 169615#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 169616#L868 assume !(1 == ~t12_pc~0); 168988#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 168987#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 168776#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 168777#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 168405#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 168406#L887 assume 1 == ~t13_pc~0; 169628#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 169029#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 169030#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 169496#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 168110#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 168111#L1439 assume !(1 == ~M_E~0); 169200#L1439-2 assume !(1 == ~T1_E~0); 168281#L1444-1 assume !(1 == ~T2_E~0); 168282#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 168765#L1454-1 assume !(1 == ~T4_E~0); 168766#L1459-1 assume !(1 == ~T5_E~0); 169341#L1464-1 assume !(1 == ~T6_E~0); 169342#L1469-1 assume !(1 == ~T7_E~0); 169424#L1474-1 assume !(1 == ~T8_E~0); 169096#L1479-1 assume !(1 == ~T9_E~0); 169097#L1484-1 assume !(1 == ~T10_E~0); 169345#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 168976#L1494-1 assume !(1 == ~T12_E~0); 168977#L1499-1 assume !(1 == ~T13_E~0); 169168#L1504-1 assume !(1 == ~E_M~0); 169169#L1509-1 assume !(1 == ~E_1~0); 169830#L1514-1 assume !(1 == ~E_2~0); 169461#L1519-1 assume !(1 == ~E_3~0); 169462#L1524-1 assume !(1 == ~E_4~0); 170083#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 170084#L1534-1 assume !(1 == ~E_6~0); 168103#L1539-1 assume !(1 == ~E_7~0); 168104#L1544-1 assume !(1 == ~E_8~0); 168521#L1549-1 assume !(1 == ~E_9~0); 170041#L1554-1 assume !(1 == ~E_10~0); 170037#L1559-1 assume !(1 == ~E_11~0); 169872#L1564-1 assume !(1 == ~E_12~0); 169873#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 170075#L1574-1 assume { :end_inline_reset_delta_events } true; 168279#L1940-2 [2021-12-07 00:34:17,663 INFO L793 eck$LassoCheckResult]: Loop: 168279#L1940-2 assume !false; 168280#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 168566#L1266 assume !false; 169639#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 168817#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 168547#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 168944#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 168945#L1079 assume !(0 != eval_~tmp~0#1); 169837#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 187633#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 187631#L1291-3 assume !(0 == ~M_E~0); 187629#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 187627#L1296-3 assume !(0 == ~T2_E~0); 187625#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 187623#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 187622#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 187621#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 187620#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 187619#L1326-3 assume !(0 == ~T8_E~0); 187618#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 187617#L1336-3 assume !(0 == ~T10_E~0); 187616#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 187615#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 187614#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 187613#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 187612#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 187611#L1366-3 assume !(0 == ~E_2~0); 187610#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 187609#L1376-3 assume !(0 == ~E_4~0); 187608#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 187607#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 187606#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 187605#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 170198#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 168388#L1406-3 assume !(0 == ~E_10~0); 168240#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 168241#L1416-3 assume !(0 == ~E_12~0); 168913#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 168914#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 169026#L640-45 assume !(1 == ~m_pc~0); 169027#L640-47 is_master_triggered_~__retres1~0#1 := 0; 170194#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 187357#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 187356#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 187355#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 187354#L659-45 assume !(1 == ~t1_pc~0); 187353#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 187352#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 187351#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 187350#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 187349#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 187348#L678-45 assume !(1 == ~t2_pc~0); 187346#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 187345#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 187344#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 187343#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 187342#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 187341#L697-45 assume !(1 == ~t3_pc~0); 187339#L697-47 is_transmit3_triggered_~__retres1~3#1 := 0; 187337#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 187335#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 187334#L1627-45 assume !(0 != activate_threads_~tmp___2~0#1); 187332#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 187331#L716-45 assume !(1 == ~t4_pc~0); 187330#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 187329#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 187328#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 187327#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 187326#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 187325#L735-45 assume 1 == ~t5_pc~0; 187323#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 187322#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 187321#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 187320#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 187319#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 187318#L754-45 assume !(1 == ~t6_pc~0); 187316#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 187315#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 168691#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 168692#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 169286#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 169007#L773-45 assume 1 == ~t7_pc~0; 169008#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 168555#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 169517#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 169856#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 169013#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 168672#L792-45 assume !(1 == ~t8_pc~0); 168674#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 169792#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 168272#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 168131#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 168132#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 168630#L811-45 assume 1 == ~t9_pc~0; 168416#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 168418#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 169699#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 169506#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 169087#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 168870#L830-45 assume 1 == ~t10_pc~0; 168871#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 168061#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 169199#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 168292#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 168293#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 168039#L849-45 assume !(1 == ~t11_pc~0); 168040#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 168502#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 168129#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 168027#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 168028#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 168285#L868-45 assume 1 == ~t12_pc~0; 168286#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 186506#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 186505#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 186503#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 186500#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 186498#L887-45 assume 1 == ~t13_pc~0; 186496#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 186493#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 186491#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 186489#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 186488#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 186486#L1439-3 assume !(1 == ~M_E~0); 186482#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 186480#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 186478#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 186475#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 186473#L1459-3 assume !(1 == ~T5_E~0); 186471#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 186469#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 186467#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 186465#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 186461#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 186459#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 186457#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 186455#L1499-3 assume !(1 == ~T13_E~0); 186452#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 186448#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 186445#L1514-3 assume !(1 == ~E_2~0); 186432#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 186417#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 183419#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 183420#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 183331#L1539-3 assume !(1 == ~E_7~0); 183332#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 177294#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 177284#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 177285#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 177269#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 177270#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 177261#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 177262#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 177225#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 177226#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 177037#L1959 assume !(0 == start_simulation_~tmp~3#1); 177038#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 187003#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 186989#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 186987#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 186986#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 186984#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 186982#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 170055#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 168279#L1940-2 [2021-12-07 00:34:17,663 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:17,663 INFO L85 PathProgramCache]: Analyzing trace with hash 846336710, now seen corresponding path program 1 times [2021-12-07 00:34:17,663 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:17,663 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [490671892] [2021-12-07 00:34:17,663 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:17,664 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:17,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:17,700 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:17,700 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:17,701 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [490671892] [2021-12-07 00:34:17,701 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [490671892] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:17,701 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:17,701 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:17,701 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [239043369] [2021-12-07 00:34:17,701 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:17,701 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:34:17,701 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:17,701 INFO L85 PathProgramCache]: Analyzing trace with hash -719325600, now seen corresponding path program 1 times [2021-12-07 00:34:17,702 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:17,702 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1398833782] [2021-12-07 00:34:17,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:17,702 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:17,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:17,725 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:17,726 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:17,726 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1398833782] [2021-12-07 00:34:17,726 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1398833782] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:17,726 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:17,726 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:17,726 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1443068533] [2021-12-07 00:34:17,726 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:17,726 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:34:17,726 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:34:17,727 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-07 00:34:17,727 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-07 00:34:17,727 INFO L87 Difference]: Start difference. First operand 20144 states and 28793 transitions. cyclomatic complexity: 8653 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:18,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:34:18,066 INFO L93 Difference]: Finished difference Result 57805 states and 82024 transitions. [2021-12-07 00:34:18,066 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-07 00:34:18,067 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57805 states and 82024 transitions. [2021-12-07 00:34:18,279 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 56663 [2021-12-07 00:34:18,416 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57805 states to 57805 states and 82024 transitions. [2021-12-07 00:34:18,416 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 57805 [2021-12-07 00:34:18,443 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 57805 [2021-12-07 00:34:18,444 INFO L73 IsDeterministic]: Start isDeterministic. Operand 57805 states and 82024 transitions. [2021-12-07 00:34:18,526 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:34:18,526 INFO L681 BuchiCegarLoop]: Abstraction has 57805 states and 82024 transitions. [2021-12-07 00:34:18,547 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57805 states and 82024 transitions. [2021-12-07 00:34:18,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57805 to 56249. [2021-12-07 00:34:18,902 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 56249 states, 56249 states have (on average 1.4205408096143932) internal successors, (79904), 56248 states have internal predecessors, (79904), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:18,994 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56249 states to 56249 states and 79904 transitions. [2021-12-07 00:34:18,994 INFO L704 BuchiCegarLoop]: Abstraction has 56249 states and 79904 transitions. [2021-12-07 00:34:18,994 INFO L587 BuchiCegarLoop]: Abstraction has 56249 states and 79904 transitions. [2021-12-07 00:34:18,994 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-07 00:34:18,994 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 56249 states and 79904 transitions. [2021-12-07 00:34:19,121 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 55979 [2021-12-07 00:34:19,121 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:34:19,121 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:34:19,123 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:19,123 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:19,123 INFO L791 eck$LassoCheckResult]: Stem: 246865#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 246866#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 248065#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 248066#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 248207#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 247377#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 246797#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 246798#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 247711#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 247712#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 247848#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 247849#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 246558#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 246559#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 247880#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 247117#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 247118#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 247780#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 247011#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 247012#L1291 assume !(0 == ~M_E~0); 248208#L1291-2 assume !(0 == ~T1_E~0); 248206#L1296-1 assume !(0 == ~T2_E~0); 247184#L1301-1 assume !(0 == ~T3_E~0); 247185#L1306-1 assume !(0 == ~T4_E~0); 247796#L1311-1 assume !(0 == ~T5_E~0); 246399#L1316-1 assume !(0 == ~T6_E~0); 246400#L1321-1 assume !(0 == ~T7_E~0); 247198#L1326-1 assume !(0 == ~T8_E~0); 246225#L1331-1 assume !(0 == ~T9_E~0); 245930#L1336-1 assume !(0 == ~T10_E~0); 245931#L1341-1 assume !(0 == ~T11_E~0); 246008#L1346-1 assume !(0 == ~T12_E~0); 246009#L1351-1 assume !(0 == ~T13_E~0); 246345#L1356-1 assume !(0 == ~E_M~0); 246346#L1361-1 assume !(0 == ~E_1~0); 248100#L1366-1 assume !(0 == ~E_2~0); 246389#L1371-1 assume !(0 == ~E_3~0); 246390#L1376-1 assume !(0 == ~E_4~0); 247255#L1381-1 assume !(0 == ~E_5~0); 247256#L1386-1 assume !(0 == ~E_6~0); 248149#L1391-1 assume !(0 == ~E_7~0); 248188#L1396-1 assume !(0 == ~E_8~0); 247149#L1401-1 assume !(0 == ~E_9~0); 247150#L1406-1 assume !(0 == ~E_10~0); 247469#L1411-1 assume !(0 == ~E_11~0); 247470#L1416-1 assume !(0 == ~E_12~0); 247060#L1421-1 assume !(0 == ~E_13~0); 246584#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 246585#L640 assume !(1 == ~m_pc~0); 247264#L640-2 is_master_triggered_~__retres1~0#1 := 0; 247216#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 247217#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 247101#L1603 assume !(0 != activate_threads_~tmp~1#1); 247102#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 246723#L659 assume !(1 == ~t1_pc~0); 246724#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 247949#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 247917#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 246849#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 246850#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 246863#L678 assume !(1 == ~t2_pc~0); 247977#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 248139#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 248140#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 246964#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 246965#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 247096#L697 assume !(1 == ~t3_pc~0); 247097#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 247233#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 248015#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 246995#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 246996#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 248041#L716 assume !(1 == ~t4_pc~0); 247545#L716-2 is_transmit4_triggered_~__retres1~4#1 := 0; 246702#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 246703#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 246188#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 246189#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 247559#L735 assume !(1 == ~t5_pc~0); 246150#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 246151#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 246609#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 247590#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 247176#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 247177#L754 assume !(1 == ~t6_pc~0); 247427#L754-2 is_transmit6_triggered_~__retres1~6#1 := 0; 246812#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 246813#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 246783#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 246784#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 247702#L773 assume !(1 == ~t7_pc~0); 246349#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 246348#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 247218#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 247186#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 247187#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 247243#L792 assume 1 == ~t8_pc~0; 247439#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 247852#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 247237#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 247179#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 247099#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 247100#L811 assume 1 == ~t9_pc~0; 247329#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 247893#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 247733#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 247325#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 247112#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 247113#L830 assume !(1 == ~t10_pc~0); 246822#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 246329#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 246025#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 246026#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 246310#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 247723#L849 assume 1 == ~t11_pc~0; 247724#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 246126#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 246127#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 246731#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 247598#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 247599#L868 assume !(1 == ~t12_pc~0); 246948#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 246947#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 246740#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 246741#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 246361#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 246362#L887 assume 1 == ~t13_pc~0; 247615#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 246989#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 246990#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 247480#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 246067#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 246068#L1439 assume !(1 == ~M_E~0); 247172#L1439-2 assume !(1 == ~T1_E~0); 246237#L1444-1 assume !(1 == ~T2_E~0); 246238#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 246727#L1454-1 assume !(1 == ~T4_E~0); 246728#L1459-1 assume !(1 == ~T5_E~0); 247322#L1464-1 assume !(1 == ~T6_E~0); 247323#L1469-1 assume !(1 == ~T7_E~0); 247407#L1474-1 assume !(1 == ~T8_E~0); 247061#L1479-1 assume !(1 == ~T9_E~0); 247062#L1484-1 assume !(1 == ~T10_E~0); 247326#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 246935#L1494-1 assume !(1 == ~T12_E~0); 246936#L1499-1 assume !(1 == ~T13_E~0); 247138#L1504-1 assume !(1 == ~E_M~0); 247139#L1509-1 assume !(1 == ~E_1~0); 247833#L1514-1 assume !(1 == ~E_2~0); 247441#L1519-1 assume !(1 == ~E_3~0); 247442#L1524-1 assume !(1 == ~E_4~0); 248118#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 248119#L1534-1 assume !(1 == ~E_6~0); 246060#L1539-1 assume !(1 == ~E_7~0); 246061#L1544-1 assume !(1 == ~E_8~0); 246478#L1549-1 assume !(1 == ~E_9~0); 248084#L1554-1 assume !(1 == ~E_10~0); 248081#L1559-1 assume !(1 == ~E_11~0); 247874#L1564-1 assume !(1 == ~E_12~0); 247875#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 248113#L1574-1 assume { :end_inline_reset_delta_events } true; 248156#L1940-2 [2021-12-07 00:34:19,124 INFO L793 eck$LassoCheckResult]: Loop: 248156#L1940-2 assume !false; 293420#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 293415#L1266 assume !false; 293414#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 293156#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 293147#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 293145#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 293142#L1079 assume !(0 != eval_~tmp~0#1); 293140#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 293138#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 293136#L1291-3 assume !(0 == ~M_E~0); 293134#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 293131#L1296-3 assume !(0 == ~T2_E~0); 293129#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 293127#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 293125#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 293123#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 293121#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 293118#L1326-3 assume !(0 == ~T8_E~0); 293116#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 293114#L1336-3 assume !(0 == ~T10_E~0); 293112#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 293110#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 293108#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 293105#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 293103#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 293101#L1366-3 assume !(0 == ~E_2~0); 293099#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 293097#L1376-3 assume !(0 == ~E_4~0); 293095#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 293092#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 293090#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 293088#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 293086#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 293084#L1406-3 assume !(0 == ~E_10~0); 293082#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 293079#L1416-3 assume !(0 == ~E_12~0); 293077#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 293075#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 293073#L640-45 assume !(1 == ~m_pc~0); 293071#L640-47 is_master_triggered_~__retres1~0#1 := 0; 293069#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 293066#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 293064#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 293062#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 293060#L659-45 assume !(1 == ~t1_pc~0); 293058#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 293056#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 293053#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 293051#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 293049#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 293047#L678-45 assume !(1 == ~t2_pc~0); 293044#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 293043#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 293042#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 293038#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 293036#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 293034#L697-45 assume !(1 == ~t3_pc~0); 293031#L697-47 is_transmit3_triggered_~__retres1~3#1 := 0; 293030#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 293025#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 293020#L1627-45 assume !(0 != activate_threads_~tmp___2~0#1); 293016#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 293015#L716-45 assume !(1 == ~t4_pc~0); 293014#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 293013#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 293012#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 293011#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 293010#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 293009#L735-45 assume !(1 == ~t5_pc~0); 293008#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 293006#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 293005#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 293004#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 293003#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 293002#L754-45 assume !(1 == ~t6_pc~0); 293001#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 293000#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 292999#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 292998#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 292997#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 292996#L773-45 assume 1 == ~t7_pc~0; 292994#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 292993#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 292992#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 292991#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 292990#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 292989#L792-45 assume !(1 == ~t8_pc~0); 292988#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 292986#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 292985#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 292984#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 292983#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 292982#L811-45 assume !(1 == ~t9_pc~0); 292980#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 292979#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 292978#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 292977#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 292976#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 292975#L830-45 assume 1 == ~t10_pc~0; 292973#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 292972#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 292971#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 292970#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 292969#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 292968#L849-45 assume !(1 == ~t11_pc~0); 292966#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 292965#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 292964#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 292963#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 292962#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 292961#L868-45 assume !(1 == ~t12_pc~0); 292960#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 292958#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 292957#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 292956#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 292955#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 292954#L887-45 assume !(1 == ~t13_pc~0); 292952#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 292951#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 292950#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 292949#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 292948#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 292947#L1439-3 assume !(1 == ~M_E~0); 275293#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 292946#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 292945#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 292944#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 292943#L1459-3 assume !(1 == ~T5_E~0); 292942#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 292941#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 292940#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 292939#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 292938#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 292937#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 292936#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 292935#L1499-3 assume !(1 == ~T13_E~0); 292934#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 292933#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 292932#L1514-3 assume !(1 == ~E_2~0); 292931#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 292930#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 292929#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 292928#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 292927#L1539-3 assume !(1 == ~E_7~0); 292926#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 292925#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 292924#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 292923#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 292922#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 292921#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 292920#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 292918#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 292905#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 292903#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 292901#L1959 assume !(0 == start_simulation_~tmp~3#1); 292902#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 293456#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 293440#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 293438#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 293436#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 293435#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 293430#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 293425#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 248156#L1940-2 [2021-12-07 00:34:19,124 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:19,124 INFO L85 PathProgramCache]: Analyzing trace with hash -995977081, now seen corresponding path program 1 times [2021-12-07 00:34:19,124 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:19,124 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1000823198] [2021-12-07 00:34:19,124 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:19,124 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:19,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:19,153 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:19,154 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:19,154 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1000823198] [2021-12-07 00:34:19,154 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1000823198] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:19,154 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:19,154 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-07 00:34:19,154 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [752684470] [2021-12-07 00:34:19,154 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:19,154 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:34:19,155 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:19,155 INFO L85 PathProgramCache]: Analyzing trace with hash -673976668, now seen corresponding path program 1 times [2021-12-07 00:34:19,155 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:19,155 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [667804194] [2021-12-07 00:34:19,155 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:19,155 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:19,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:19,178 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:19,178 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:19,178 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [667804194] [2021-12-07 00:34:19,178 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [667804194] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:19,178 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:19,178 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:19,179 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [18302870] [2021-12-07 00:34:19,179 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:19,179 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:34:19,179 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:34:19,179 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:34:19,179 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:34:19,179 INFO L87 Difference]: Start difference. First operand 56249 states and 79904 transitions. cyclomatic complexity: 23663 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:19,644 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:34:19,644 INFO L93 Difference]: Finished difference Result 108229 states and 153240 transitions. [2021-12-07 00:34:19,644 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:34:19,644 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 108229 states and 153240 transitions. [2021-12-07 00:34:20,055 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 107792 [2021-12-07 00:34:20,301 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 108229 states to 108229 states and 153240 transitions. [2021-12-07 00:34:20,301 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 108229 [2021-12-07 00:34:20,343 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 108229 [2021-12-07 00:34:20,343 INFO L73 IsDeterministic]: Start isDeterministic. Operand 108229 states and 153240 transitions. [2021-12-07 00:34:20,382 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:34:20,383 INFO L681 BuchiCegarLoop]: Abstraction has 108229 states and 153240 transitions. [2021-12-07 00:34:20,422 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108229 states and 153240 transitions. [2021-12-07 00:34:21,173 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108229 to 108157. [2021-12-07 00:34:21,239 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108157 states, 108157 states have (on average 1.4161635400390173) internal successors, (153168), 108156 states have internal predecessors, (153168), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:21,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108157 states to 108157 states and 153168 transitions. [2021-12-07 00:34:21,431 INFO L704 BuchiCegarLoop]: Abstraction has 108157 states and 153168 transitions. [2021-12-07 00:34:21,431 INFO L587 BuchiCegarLoop]: Abstraction has 108157 states and 153168 transitions. [2021-12-07 00:34:21,431 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-12-07 00:34:21,431 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108157 states and 153168 transitions. [2021-12-07 00:34:21,702 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 107720 [2021-12-07 00:34:21,702 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:34:21,702 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:34:21,705 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:21,705 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:21,705 INFO L791 eck$LassoCheckResult]: Stem: 411343#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 411344#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 412488#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 412489#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 412624#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 411835#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 411273#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 411274#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 412149#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 412150#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 412288#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 412289#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 411042#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 411043#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 412323#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 411589#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 411590#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 412222#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 411492#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 411493#L1291 assume !(0 == ~M_E~0); 412625#L1291-2 assume !(0 == ~T1_E~0); 412622#L1296-1 assume !(0 == ~T2_E~0); 411654#L1301-1 assume !(0 == ~T3_E~0); 411655#L1306-1 assume !(0 == ~T4_E~0); 412235#L1311-1 assume !(0 == ~T5_E~0); 410884#L1316-1 assume !(0 == ~T6_E~0); 410885#L1321-1 assume !(0 == ~T7_E~0); 411667#L1326-1 assume !(0 == ~T8_E~0); 410711#L1331-1 assume !(0 == ~T9_E~0); 410415#L1336-1 assume !(0 == ~T10_E~0); 410416#L1341-1 assume !(0 == ~T11_E~0); 410493#L1346-1 assume !(0 == ~T12_E~0); 410494#L1351-1 assume !(0 == ~T13_E~0); 410830#L1356-1 assume !(0 == ~E_M~0); 410831#L1361-1 assume !(0 == ~E_1~0); 412521#L1366-1 assume !(0 == ~E_2~0); 410874#L1371-1 assume !(0 == ~E_3~0); 410875#L1376-1 assume !(0 == ~E_4~0); 411720#L1381-1 assume !(0 == ~E_5~0); 411721#L1386-1 assume !(0 == ~E_6~0); 412571#L1391-1 assume !(0 == ~E_7~0); 412604#L1396-1 assume !(0 == ~E_8~0); 411621#L1401-1 assume !(0 == ~E_9~0); 411622#L1406-1 assume !(0 == ~E_10~0); 411924#L1411-1 assume !(0 == ~E_11~0); 411925#L1416-1 assume !(0 == ~E_12~0); 411536#L1421-1 assume !(0 == ~E_13~0); 411067#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 411068#L640 assume !(1 == ~m_pc~0); 411728#L640-2 is_master_triggered_~__retres1~0#1 := 0; 411684#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 411685#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 411573#L1603 assume !(0 != activate_threads_~tmp~1#1); 411574#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 411200#L659 assume !(1 == ~t1_pc~0); 411201#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 412391#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 412359#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 411325#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 411326#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 411341#L678 assume !(1 == ~t2_pc~0); 412417#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 412563#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 412564#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 411442#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 411443#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 411568#L697 assume !(1 == ~t3_pc~0); 411569#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 411701#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 412449#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 411475#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 411476#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 412472#L716 assume !(1 == ~t4_pc~0); 411997#L716-2 is_transmit4_triggered_~__retres1~4#1 := 0; 411179#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 411180#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 410673#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 410674#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 412011#L735 assume !(1 == ~t5_pc~0); 410635#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 410636#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 411090#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 412039#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 411647#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 411648#L754 assume !(1 == ~t6_pc~0); 411883#L754-2 is_transmit6_triggered_~__retres1~6#1 := 0; 411288#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 411289#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 411260#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 411261#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 412138#L773 assume !(1 == ~t7_pc~0); 410834#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 410833#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 411686#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 411656#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 411657#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 411710#L792 assume !(1 == ~t8_pc~0); 411895#L792-2 is_transmit8_triggered_~__retres1~8#1 := 0; 412292#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 411704#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 411650#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 411571#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 411572#L811 assume 1 == ~t9_pc~0; 411792#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 412336#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 412172#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 411788#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 411584#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 411585#L830 assume !(1 == ~t10_pc~0); 411298#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 410814#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 410510#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 410511#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 410796#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 412159#L849 assume 1 == ~t11_pc~0; 412160#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 410611#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 410612#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 411207#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 412048#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 412049#L868 assume !(1 == ~t12_pc~0); 411427#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 411426#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 411216#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 411217#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 410846#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 410847#L887 assume 1 == ~t13_pc~0; 412063#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 411469#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 411470#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 411935#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 410552#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 410553#L1439 assume !(1 == ~M_E~0); 411643#L1439-2 assume !(1 == ~T1_E~0); 410723#L1444-1 assume !(1 == ~T2_E~0); 410724#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 411203#L1454-1 assume !(1 == ~T4_E~0); 411204#L1459-1 assume !(1 == ~T5_E~0); 411785#L1464-1 assume !(1 == ~T6_E~0); 411786#L1469-1 assume !(1 == ~T7_E~0); 411863#L1474-1 assume !(1 == ~T8_E~0); 411537#L1479-1 assume !(1 == ~T9_E~0); 411538#L1484-1 assume !(1 == ~T10_E~0); 411789#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 411415#L1494-1 assume !(1 == ~T12_E~0); 411416#L1499-1 assume !(1 == ~T13_E~0); 411610#L1504-1 assume !(1 == ~E_M~0); 411611#L1509-1 assume !(1 == ~E_1~0); 412271#L1514-1 assume !(1 == ~E_2~0); 411896#L1519-1 assume !(1 == ~E_3~0); 411897#L1524-1 assume !(1 == ~E_4~0); 412543#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 412544#L1534-1 assume !(1 == ~E_6~0); 410545#L1539-1 assume !(1 == ~E_7~0); 410546#L1544-1 assume !(1 == ~E_8~0); 410961#L1549-1 assume !(1 == ~E_9~0); 412503#L1554-1 assume !(1 == ~E_10~0); 412498#L1559-1 assume !(1 == ~E_11~0); 412315#L1564-1 assume !(1 == ~E_12~0); 412316#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 412535#L1574-1 assume { :end_inline_reset_delta_events } true; 412583#L1940-2 [2021-12-07 00:34:21,706 INFO L793 eck$LassoCheckResult]: Loop: 412583#L1940-2 assume !false; 438688#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 438684#L1266 assume !false; 438677#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 438678#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 447582#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 447580#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 438637#L1079 assume !(0 != eval_~tmp~0#1); 438639#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 500741#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 500739#L1291-3 assume !(0 == ~M_E~0); 500737#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 500735#L1296-3 assume !(0 == ~T2_E~0); 500733#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 500731#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 500730#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 500728#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 500726#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 500724#L1326-3 assume !(0 == ~T8_E~0); 500722#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 500720#L1336-3 assume !(0 == ~T10_E~0); 500717#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 500715#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 500713#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 500711#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 500709#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 500707#L1366-3 assume !(0 == ~E_2~0); 500705#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 500703#L1376-3 assume !(0 == ~E_4~0); 500701#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 500699#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 500697#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 500695#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 500694#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 500691#L1406-3 assume !(0 == ~E_10~0); 500689#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 500687#L1416-3 assume !(0 == ~E_12~0); 500685#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 500683#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 500681#L640-45 assume !(1 == ~m_pc~0); 464032#L640-47 is_master_triggered_~__retres1~0#1 := 0; 464031#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 464030#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 464029#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 464027#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 464026#L659-45 assume !(1 == ~t1_pc~0); 464025#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 464024#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 464023#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 464022#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 464020#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 464017#L678-45 assume !(1 == ~t2_pc~0); 464014#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 464012#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 464010#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 464008#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 464006#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 464005#L697-45 assume 1 == ~t3_pc~0; 464003#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 464004#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 464028#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 463994#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 463991#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 463989#L716-45 assume !(1 == ~t4_pc~0); 463987#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 463985#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 463983#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 463981#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 463980#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 463979#L735-45 assume !(1 == ~t5_pc~0); 463978#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 463976#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 463975#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 463974#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 463973#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 463971#L754-45 assume !(1 == ~t6_pc~0); 463970#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 463969#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 463967#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 463965#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 463964#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 460143#L773-45 assume !(1 == ~t7_pc~0); 460140#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 460137#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 460135#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 460133#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 460131#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 460129#L792-45 assume !(1 == ~t8_pc~0); 460128#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 460126#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 460124#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 460122#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 460120#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 460118#L811-45 assume 1 == ~t9_pc~0; 460114#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 460111#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 460109#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 460107#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 460105#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 460103#L830-45 assume !(1 == ~t10_pc~0); 460101#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 460098#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 460096#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 460094#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 460092#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 460089#L849-45 assume 1 == ~t11_pc~0; 460087#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 460084#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 460082#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 460080#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 460078#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 460075#L868-45 assume !(1 == ~t12_pc~0); 460073#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 460070#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 460068#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 459624#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 457578#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 457575#L887-45 assume !(1 == ~t13_pc~0); 457572#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 457570#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 457568#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 457566#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 457565#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 454278#L1439-3 assume !(1 == ~M_E~0); 454273#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 454271#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 454269#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 454267#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 454265#L1459-3 assume !(1 == ~T5_E~0); 454263#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 454260#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 454258#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 454256#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 454254#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 454252#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 454250#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 454249#L1499-3 assume !(1 == ~T13_E~0); 454246#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 454244#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 454242#L1514-3 assume !(1 == ~E_2~0); 454240#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 454238#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 454236#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 454233#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 454231#L1539-3 assume !(1 == ~E_7~0); 454229#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 454227#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 454225#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 454223#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 453498#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 453487#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 452229#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 438751#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 438737#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 438734#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 438731#L1959 assume !(0 == start_simulation_~tmp~3#1); 438728#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 438720#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 438705#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 438706#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 448297#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 448295#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 438695#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 438693#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 412583#L1940-2 [2021-12-07 00:34:21,706 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:21,706 INFO L85 PathProgramCache]: Analyzing trace with hash -618334264, now seen corresponding path program 1 times [2021-12-07 00:34:21,706 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:21,706 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1842393990] [2021-12-07 00:34:21,706 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:21,707 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:21,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:21,883 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:21,883 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:21,883 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1842393990] [2021-12-07 00:34:21,883 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1842393990] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:21,884 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:21,884 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:21,884 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1503328502] [2021-12-07 00:34:21,884 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:21,884 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:34:21,885 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:21,885 INFO L85 PathProgramCache]: Analyzing trace with hash 1952502753, now seen corresponding path program 1 times [2021-12-07 00:34:21,885 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:21,885 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [639575148] [2021-12-07 00:34:21,885 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:21,885 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:21,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:21,912 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:21,912 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:21,912 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [639575148] [2021-12-07 00:34:21,912 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [639575148] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:21,912 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:21,912 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:21,913 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [187374899] [2021-12-07 00:34:21,913 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:21,913 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:34:21,913 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:34:21,913 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-07 00:34:21,913 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-07 00:34:21,913 INFO L87 Difference]: Start difference. First operand 108157 states and 153168 transitions. cyclomatic complexity: 45027 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:22,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:34:22,831 INFO L93 Difference]: Finished difference Result 309716 states and 435997 transitions. [2021-12-07 00:34:22,832 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-07 00:34:22,832 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 309716 states and 435997 transitions. [2021-12-07 00:34:24,024 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 305200 [2021-12-07 00:34:24,678 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 309716 states to 309716 states and 435997 transitions. [2021-12-07 00:34:24,678 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 309716 [2021-12-07 00:34:24,786 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 309716 [2021-12-07 00:34:24,786 INFO L73 IsDeterministic]: Start isDeterministic. Operand 309716 states and 435997 transitions. [2021-12-07 00:34:24,879 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:34:24,879 INFO L681 BuchiCegarLoop]: Abstraction has 309716 states and 435997 transitions. [2021-12-07 00:34:24,993 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 309716 states and 435997 transitions. [2021-12-07 00:34:26,937 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 309716 to 303492. [2021-12-07 00:34:27,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 303492 states, 303492 states have (on average 1.4091343429151344) internal successors, (427661), 303491 states have internal predecessors, (427661), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:27,894 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 303492 states to 303492 states and 427661 transitions. [2021-12-07 00:34:27,894 INFO L704 BuchiCegarLoop]: Abstraction has 303492 states and 427661 transitions. [2021-12-07 00:34:27,894 INFO L587 BuchiCegarLoop]: Abstraction has 303492 states and 427661 transitions. [2021-12-07 00:34:27,894 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-12-07 00:34:27,894 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 303492 states and 427661 transitions. [2021-12-07 00:34:28,651 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 302608 [2021-12-07 00:34:28,651 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:34:28,651 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:34:28,653 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:28,653 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:28,653 INFO L791 eck$LassoCheckResult]: Stem: 829228#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 829229#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 830480#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 830481#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 830657#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 829744#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 829156#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 829157#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 830112#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 830113#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 830256#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 830257#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 828921#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 828922#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 830286#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 829485#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 829486#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 830190#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 829382#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 829383#L1291 assume !(0 == ~M_E~0); 830658#L1291-2 assume !(0 == ~T1_E~0); 830654#L1296-1 assume !(0 == ~T2_E~0); 829547#L1301-1 assume !(0 == ~T3_E~0); 829548#L1306-1 assume !(0 == ~T4_E~0); 830202#L1311-1 assume !(0 == ~T5_E~0); 828761#L1316-1 assume !(0 == ~T6_E~0); 828762#L1321-1 assume !(0 == ~T7_E~0); 829565#L1326-1 assume !(0 == ~T8_E~0); 828593#L1331-1 assume !(0 == ~T9_E~0); 828298#L1336-1 assume !(0 == ~T10_E~0); 828299#L1341-1 assume !(0 == ~T11_E~0); 828376#L1346-1 assume !(0 == ~T12_E~0); 828377#L1351-1 assume !(0 == ~T13_E~0); 828709#L1356-1 assume !(0 == ~E_M~0); 828710#L1361-1 assume !(0 == ~E_1~0); 830527#L1366-1 assume !(0 == ~E_2~0); 828750#L1371-1 assume !(0 == ~E_3~0); 828751#L1376-1 assume !(0 == ~E_4~0); 829625#L1381-1 assume !(0 == ~E_5~0); 829626#L1386-1 assume !(0 == ~E_6~0); 830584#L1391-1 assume !(0 == ~E_7~0); 830622#L1396-1 assume !(0 == ~E_8~0); 829516#L1401-1 assume !(0 == ~E_9~0); 829517#L1406-1 assume !(0 == ~E_10~0); 829850#L1411-1 assume !(0 == ~E_11~0); 829851#L1416-1 assume !(0 == ~E_12~0); 829427#L1421-1 assume !(0 == ~E_13~0); 828946#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 828947#L640 assume !(1 == ~m_pc~0); 829635#L640-2 is_master_triggered_~__retres1~0#1 := 0; 829585#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 829586#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 829469#L1603 assume !(0 != activate_threads_~tmp~1#1); 829470#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 829081#L659 assume !(1 == ~t1_pc~0); 829082#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 830357#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 830322#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 829211#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 829212#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 829226#L678 assume !(1 == ~t2_pc~0); 830383#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 830573#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 830574#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 829333#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 829334#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 829464#L697 assume !(1 == ~t3_pc~0); 829465#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 829602#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 830429#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 829367#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 829368#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 830452#L716 assume !(1 == ~t4_pc~0); 829928#L716-2 is_transmit4_triggered_~__retres1~4#1 := 0; 829062#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 829063#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 828555#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 828556#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 829945#L735 assume !(1 == ~t5_pc~0); 828517#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 828518#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 828968#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 829981#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 829539#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 829540#L754 assume !(1 == ~t6_pc~0); 829801#L754-2 is_transmit6_triggered_~__retres1~6#1 := 0; 829171#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 829172#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 829141#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 829142#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 830102#L773 assume !(1 == ~t7_pc~0); 828713#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 828712#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 829587#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 829549#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 829550#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 829612#L792 assume !(1 == ~t8_pc~0); 829816#L792-2 is_transmit8_triggered_~__retres1~8#1 := 0; 830260#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 829606#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 829544#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 829467#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 829468#L811 assume !(1 == ~t9_pc~0); 829700#L811-2 is_transmit9_triggered_~__retres1~9#1 := 0; 830339#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 830134#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 829695#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 829480#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 829481#L830 assume !(1 == ~t10_pc~0); 829184#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 828693#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 828393#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 828394#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 828675#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 830123#L849 assume 1 == ~t11_pc~0; 830124#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 828493#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 828494#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 829090#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 829991#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 829992#L868 assume !(1 == ~t12_pc~0); 829318#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 829317#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 829097#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 829098#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 828726#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 828727#L887 assume 1 == ~t13_pc~0; 830005#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 829361#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 829362#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 829857#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 828434#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 828435#L1439 assume !(1 == ~M_E~0); 829537#L1439-2 assume !(1 == ~T1_E~0); 828605#L1444-1 assume !(1 == ~T2_E~0); 828606#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 829086#L1454-1 assume !(1 == ~T4_E~0); 829087#L1459-1 assume !(1 == ~T5_E~0); 829692#L1464-1 assume !(1 == ~T6_E~0); 829693#L1469-1 assume !(1 == ~T7_E~0); 829781#L1474-1 assume !(1 == ~T8_E~0); 829428#L1479-1 assume !(1 == ~T9_E~0); 829429#L1484-1 assume !(1 == ~T10_E~0); 829696#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 829309#L1494-1 assume !(1 == ~T12_E~0); 829310#L1499-1 assume !(1 == ~T13_E~0); 829505#L1504-1 assume !(1 == ~E_M~0); 829506#L1509-1 assume !(1 == ~E_1~0); 830236#L1514-1 assume !(1 == ~E_2~0); 829817#L1519-1 assume !(1 == ~E_3~0); 829818#L1524-1 assume !(1 == ~E_4~0); 830552#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 830553#L1534-1 assume !(1 == ~E_6~0); 828428#L1539-1 assume !(1 == ~E_7~0); 828429#L1544-1 assume !(1 == ~E_8~0); 828836#L1549-1 assume !(1 == ~E_9~0); 830508#L1554-1 assume !(1 == ~E_10~0); 830500#L1559-1 assume !(1 == ~E_11~0); 830281#L1564-1 assume !(1 == ~E_12~0); 830282#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 830543#L1574-1 assume { :end_inline_reset_delta_events } true; 830593#L1940-2 [2021-12-07 00:34:28,653 INFO L793 eck$LassoCheckResult]: Loop: 830593#L1940-2 assume !false; 965699#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 965694#L1266 assume !false; 965693#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 965684#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 965675#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 965673#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 965670#L1079 assume !(0 != eval_~tmp~0#1); 965668#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 965666#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 965664#L1291-3 assume !(0 == ~M_E~0); 965662#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 965660#L1296-3 assume !(0 == ~T2_E~0); 965658#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 965656#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 965653#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 965651#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 965649#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 965647#L1326-3 assume !(0 == ~T8_E~0); 965645#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 965643#L1336-3 assume !(0 == ~T10_E~0); 965642#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 965638#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 965636#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 965634#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 965632#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 965629#L1366-3 assume !(0 == ~E_2~0); 965627#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 965625#L1376-3 assume !(0 == ~E_4~0); 965623#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 965621#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 965619#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 965617#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 965615#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 965613#L1406-3 assume !(0 == ~E_10~0); 965610#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 965608#L1416-3 assume !(0 == ~E_12~0); 965606#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 965604#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 965602#L640-45 assume !(1 == ~m_pc~0); 965600#L640-47 is_master_triggered_~__retres1~0#1 := 0; 965598#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 965596#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 965594#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 965592#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 965590#L659-45 assume !(1 == ~t1_pc~0); 965588#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 965587#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 965584#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 965582#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 965580#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 965578#L678-45 assume !(1 == ~t2_pc~0); 965575#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 965573#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 965571#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 965569#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 965567#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 965565#L697-45 assume 1 == ~t3_pc~0; 965563#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 965564#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 966478#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 965554#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 965552#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 965550#L716-45 assume !(1 == ~t4_pc~0); 965548#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 965546#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 965543#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 965541#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 965539#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 965537#L735-45 assume !(1 == ~t5_pc~0); 965518#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 965515#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 965513#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 965511#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 965509#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 965507#L754-45 assume !(1 == ~t6_pc~0); 965504#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 965502#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 965500#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 965468#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 965462#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 965452#L773-45 assume !(1 == ~t7_pc~0); 965444#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 965254#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 965253#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 965252#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 965251#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 965250#L792-45 assume !(1 == ~t8_pc~0); 965249#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 965248#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 965246#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 965244#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 965243#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 965242#L811-45 assume !(1 == ~t9_pc~0); 965241#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 965240#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 965239#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 965238#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 965237#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 965236#L830-45 assume 1 == ~t10_pc~0; 965234#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 965233#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 965232#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 965231#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 965230#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 965229#L849-45 assume 1 == ~t11_pc~0; 965228#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 965226#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 965225#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 965224#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 965222#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 965221#L868-45 assume !(1 == ~t12_pc~0); 965220#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 965218#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 965217#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 965216#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 965215#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 965213#L887-45 assume !(1 == ~t13_pc~0); 965210#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 965208#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 965206#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 965204#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 965202#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 965200#L1439-3 assume !(1 == ~M_E~0); 964776#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 965197#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 965195#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 965193#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 965191#L1459-3 assume !(1 == ~T5_E~0); 965188#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 965186#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 965184#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 965182#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 965180#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 965178#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 965174#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 965172#L1499-3 assume !(1 == ~T13_E~0); 965170#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 965168#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 965165#L1514-3 assume !(1 == ~E_2~0); 965163#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 965161#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 965159#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 965157#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 965155#L1539-3 assume !(1 == ~E_7~0); 965153#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 965151#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 965149#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 965146#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 965144#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 965142#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 965140#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 965134#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 965120#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 965118#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 965115#L1959 assume !(0 == start_simulation_~tmp~3#1); 965116#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 965735#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 965719#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 965717#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 965715#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 965714#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 965709#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 965704#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 830593#L1940-2 [2021-12-07 00:34:28,653 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:28,654 INFO L85 PathProgramCache]: Analyzing trace with hash -1649665079, now seen corresponding path program 1 times [2021-12-07 00:34:28,654 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:28,654 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1631306355] [2021-12-07 00:34:28,654 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:28,654 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:28,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:28,681 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:28,681 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:28,681 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1631306355] [2021-12-07 00:34:28,682 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1631306355] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:28,682 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:28,682 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-07 00:34:28,682 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [255164116] [2021-12-07 00:34:28,682 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:28,682 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:34:28,682 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:28,682 INFO L85 PathProgramCache]: Analyzing trace with hash -380461279, now seen corresponding path program 1 times [2021-12-07 00:34:28,682 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:28,683 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1263493458] [2021-12-07 00:34:28,683 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:28,683 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:28,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:28,704 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:28,704 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:28,704 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1263493458] [2021-12-07 00:34:28,704 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1263493458] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:28,704 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:28,704 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:28,704 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1990392413] [2021-12-07 00:34:28,705 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:28,705 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:34:28,705 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:34:28,705 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-07 00:34:28,705 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-07 00:34:28,705 INFO L87 Difference]: Start difference. First operand 303492 states and 427661 transitions. cyclomatic complexity: 124201 Second operand has 5 states, 5 states have (on average 32.2) internal successors, (161), 5 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:30,691 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:34:30,691 INFO L93 Difference]: Finished difference Result 710321 states and 1011636 transitions. [2021-12-07 00:34:30,692 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-07 00:34:30,692 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 710321 states and 1011636 transitions. [2021-12-07 00:34:33,146 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 707964 [2021-12-07 00:34:34,777 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 710321 states to 710321 states and 1011636 transitions. [2021-12-07 00:34:34,777 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 710321 [2021-12-07 00:34:34,929 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 710321 [2021-12-07 00:34:34,930 INFO L73 IsDeterministic]: Start isDeterministic. Operand 710321 states and 1011636 transitions. [2021-12-07 00:34:35,112 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:34:35,112 INFO L681 BuchiCegarLoop]: Abstraction has 710321 states and 1011636 transitions. [2021-12-07 00:34:35,338 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 710321 states and 1011636 transitions. [2021-12-07 00:34:38,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 710321 to 311139. [2021-12-07 00:34:38,317 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 311139 states, 311139 states have (on average 1.3990788682871642) internal successors, (435308), 311138 states have internal predecessors, (435308), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:39,166 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 311139 states to 311139 states and 435308 transitions. [2021-12-07 00:34:39,167 INFO L704 BuchiCegarLoop]: Abstraction has 311139 states and 435308 transitions. [2021-12-07 00:34:39,167 INFO L587 BuchiCegarLoop]: Abstraction has 311139 states and 435308 transitions. [2021-12-07 00:34:39,167 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-12-07 00:34:39,167 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 311139 states and 435308 transitions. [2021-12-07 00:34:39,683 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 310252 [2021-12-07 00:34:39,684 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:34:39,684 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:34:39,685 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:39,685 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:39,686 INFO L791 eck$LassoCheckResult]: Stem: 1843065#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1843066#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1844276#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1844277#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1844439#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 1843568#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1842989#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1842990#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1843916#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1843917#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1844058#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1844059#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1842751#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1842752#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1844094#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1843319#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1843320#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1843992#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1843218#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1843219#L1291 assume !(0 == ~M_E~0); 1844440#L1291-2 assume !(0 == ~T1_E~0); 1844437#L1296-1 assume !(0 == ~T2_E~0); 1843382#L1301-1 assume !(0 == ~T3_E~0); 1843383#L1306-1 assume !(0 == ~T4_E~0); 1844006#L1311-1 assume !(0 == ~T5_E~0); 1842592#L1316-1 assume !(0 == ~T6_E~0); 1842593#L1321-1 assume !(0 == ~T7_E~0); 1843398#L1326-1 assume !(0 == ~T8_E~0); 1842421#L1331-1 assume !(0 == ~T9_E~0); 1842124#L1336-1 assume !(0 == ~T10_E~0); 1842125#L1341-1 assume !(0 == ~T11_E~0); 1842202#L1346-1 assume !(0 == ~T12_E~0); 1842203#L1351-1 assume !(0 == ~T13_E~0); 1842543#L1356-1 assume !(0 == ~E_M~0); 1842544#L1361-1 assume !(0 == ~E_1~0); 1844320#L1366-1 assume !(0 == ~E_2~0); 1842582#L1371-1 assume !(0 == ~E_3~0); 1842583#L1376-1 assume !(0 == ~E_4~0); 1843452#L1381-1 assume !(0 == ~E_5~0); 1843453#L1386-1 assume !(0 == ~E_6~0); 1844384#L1391-1 assume !(0 == ~E_7~0); 1844417#L1396-1 assume !(0 == ~E_8~0); 1843350#L1401-1 assume !(0 == ~E_9~0); 1843351#L1406-1 assume !(0 == ~E_10~0); 1843671#L1411-1 assume !(0 == ~E_11~0); 1843672#L1416-1 assume !(0 == ~E_12~0); 1843265#L1421-1 assume !(0 == ~E_13~0); 1842776#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1842777#L640 assume !(1 == ~m_pc~0); 1843461#L640-2 is_master_triggered_~__retres1~0#1 := 0; 1843416#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1843417#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1843302#L1603 assume !(0 != activate_threads_~tmp~1#1); 1843303#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1842915#L659 assume !(1 == ~t1_pc~0); 1842916#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1844166#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1844130#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1843046#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 1843047#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1843063#L678 assume !(1 == ~t2_pc~0); 1844197#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1844370#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1844371#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1843167#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 1843168#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1843297#L697 assume !(1 == ~t3_pc~0); 1843298#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1843433#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1844232#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1843203#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 1843204#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1844256#L716 assume !(1 == ~t4_pc~0); 1843747#L716-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1842894#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1842895#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1842381#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 1842382#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1843761#L735 assume !(1 == ~t5_pc~0); 1842343#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1842344#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1842802#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1843791#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 1843375#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1843376#L754 assume !(1 == ~t6_pc~0); 1843624#L754-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1843003#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1843004#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1842976#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 1842977#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1843907#L773 assume !(1 == ~t7_pc~0); 1842547#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1842546#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1843419#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1843384#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 1843385#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1843442#L792 assume !(1 == ~t8_pc~0); 1843637#L792-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1844062#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1843436#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1843378#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 1843300#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1843301#L811 assume !(1 == ~t9_pc~0); 1843525#L811-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1844146#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1843937#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1843521#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 1843314#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1843315#L830 assume !(1 == ~t10_pc~0); 1843015#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1842525#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1842526#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1842506#L1683 assume !(0 != activate_threads_~tmp___9~0#1); 1842507#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1843926#L849 assume 1 == ~t11_pc~0; 1843927#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1842319#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1842320#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1842922#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 1843803#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1843804#L868 assume !(1 == ~t12_pc~0); 1843152#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1843151#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1842931#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1842932#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 1842558#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1842559#L887 assume 1 == ~t13_pc~0; 1843821#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1843196#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1843197#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1843680#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 1842260#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1842261#L1439 assume !(1 == ~M_E~0); 1843371#L1439-2 assume !(1 == ~T1_E~0); 1842433#L1444-1 assume !(1 == ~T2_E~0); 1842434#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1842918#L1454-1 assume !(1 == ~T4_E~0); 1842919#L1459-1 assume !(1 == ~T5_E~0); 1843517#L1464-1 assume !(1 == ~T6_E~0); 1843518#L1469-1 assume !(1 == ~T7_E~0); 1843601#L1474-1 assume !(1 == ~T8_E~0); 1843266#L1479-1 assume !(1 == ~T9_E~0); 1843267#L1484-1 assume !(1 == ~T10_E~0); 1843522#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1843140#L1494-1 assume !(1 == ~T12_E~0); 1843141#L1499-1 assume !(1 == ~T13_E~0); 1843339#L1504-1 assume !(1 == ~E_M~0); 1843340#L1509-1 assume !(1 == ~E_1~0); 1844043#L1514-1 assume !(1 == ~E_2~0); 1843638#L1519-1 assume !(1 == ~E_3~0); 1843639#L1524-1 assume !(1 == ~E_4~0); 1844344#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1844345#L1534-1 assume !(1 == ~E_6~0); 1842254#L1539-1 assume !(1 == ~E_7~0); 1842255#L1544-1 assume !(1 == ~E_8~0); 1842668#L1549-1 assume !(1 == ~E_9~0); 1844298#L1554-1 assume !(1 == ~E_10~0); 1844293#L1559-1 assume !(1 == ~E_11~0); 1844088#L1564-1 assume !(1 == ~E_12~0); 1844089#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 1844337#L1574-1 assume { :end_inline_reset_delta_events } true; 1844391#L1940-2 [2021-12-07 00:34:39,686 INFO L793 eck$LassoCheckResult]: Loop: 1844391#L1940-2 assume !false; 1924228#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1924220#L1266 assume !false; 1924221#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1919350#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1919343#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1919336#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1919337#L1079 assume !(0 != eval_~tmp~0#1); 1933420#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1933418#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1933416#L1291-3 assume !(0 == ~M_E~0); 1933414#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1933412#L1296-3 assume !(0 == ~T2_E~0); 1933410#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1933332#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1933329#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1933250#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1933245#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1933241#L1326-3 assume !(0 == ~T8_E~0); 1933236#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1933232#L1336-3 assume !(0 == ~T10_E~0); 1933228#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1933224#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1933219#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1933215#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1933210#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1933206#L1366-3 assume !(0 == ~E_2~0); 1933202#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1933129#L1376-3 assume !(0 == ~E_4~0); 1933123#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1933040#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1933033#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1933028#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1933022#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1933015#L1406-3 assume !(0 == ~E_10~0); 1933010#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1933003#L1416-3 assume !(0 == ~E_12~0); 1932998#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 1932994#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1932993#L640-45 assume !(1 == ~m_pc~0); 1932992#L640-47 is_master_triggered_~__retres1~0#1 := 0; 1932991#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1932990#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1932989#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1932988#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1932987#L659-45 assume !(1 == ~t1_pc~0); 1932986#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 1932985#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1932984#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1932983#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1932982#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1932981#L678-45 assume !(1 == ~t2_pc~0); 1932979#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 1932978#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1932977#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1932976#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1932975#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1932974#L697-45 assume !(1 == ~t3_pc~0); 1932973#L697-47 is_transmit3_triggered_~__retres1~3#1 := 0; 1932971#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1932969#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1932967#L1627-45 assume !(0 != activate_threads_~tmp___2~0#1); 1932965#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1932964#L716-45 assume !(1 == ~t4_pc~0); 1932963#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 1932962#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1932961#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1932960#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1932959#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1932958#L735-45 assume !(1 == ~t5_pc~0); 1932957#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 1932955#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1932954#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1932953#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1932952#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1932951#L754-45 assume !(1 == ~t6_pc~0); 1932950#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 1932949#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1932948#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1932947#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1932946#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1932945#L773-45 assume 1 == ~t7_pc~0; 1932943#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1932941#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1932939#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1932937#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 1932935#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1932933#L792-45 assume !(1 == ~t8_pc~0); 1932931#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 1932928#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1932926#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1932924#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1932922#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1932920#L811-45 assume !(1 == ~t9_pc~0); 1932918#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 1932916#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1932913#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1932910#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1932907#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1932906#L830-45 assume !(1 == ~t10_pc~0); 1932905#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 1932903#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1932901#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1932899#L1683-45 assume !(0 != activate_threads_~tmp___9~0#1); 1932845#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1932841#L849-45 assume 1 == ~t11_pc~0; 1932837#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1932831#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1932826#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1932822#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1932817#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1932813#L868-45 assume !(1 == ~t12_pc~0); 1932809#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 1932802#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1932723#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1932719#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1932716#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1932710#L887-45 assume !(1 == ~t13_pc~0); 1932705#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 1932700#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1932696#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1932623#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1932618#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1932614#L1439-3 assume !(1 == ~M_E~0); 1931201#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1932605#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1932600#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1932595#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1932590#L1459-3 assume !(1 == ~T5_E~0); 1932585#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1932579#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1932574#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1932569#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1932564#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1932559#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1932554#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1932548#L1499-3 assume !(1 == ~T13_E~0); 1932543#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1932469#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1932463#L1514-3 assume !(1 == ~E_2~0); 1932457#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1932452#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1932448#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1932445#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1932430#L1539-3 assume !(1 == ~E_7~0); 1932413#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1932409#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1932405#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1932401#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1932398#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1932395#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 1932392#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1932280#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1932264#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1932261#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1932257#L1959 assume !(0 == start_simulation_~tmp~3#1); 1932258#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1924269#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1924253#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1924251#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 1924249#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1924247#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1924248#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1924234#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 1844391#L1940-2 [2021-12-07 00:34:39,686 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:39,686 INFO L85 PathProgramCache]: Analyzing trace with hash -1665183797, now seen corresponding path program 1 times [2021-12-07 00:34:39,687 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:39,687 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1929091164] [2021-12-07 00:34:39,687 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:39,687 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:39,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:39,714 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:39,714 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:39,714 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1929091164] [2021-12-07 00:34:39,714 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1929091164] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:39,714 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:39,714 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:39,714 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [768372871] [2021-12-07 00:34:39,714 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:39,715 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:34:39,715 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:39,715 INFO L85 PathProgramCache]: Analyzing trace with hash -1598395674, now seen corresponding path program 1 times [2021-12-07 00:34:39,715 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:39,715 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1482744322] [2021-12-07 00:34:39,715 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:39,715 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:39,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:39,737 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:39,737 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:39,737 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1482744322] [2021-12-07 00:34:39,737 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1482744322] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:39,738 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:39,738 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:39,738 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1198131620] [2021-12-07 00:34:39,738 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:39,738 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:34:39,738 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:34:39,738 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-07 00:34:39,738 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-07 00:34:39,739 INFO L87 Difference]: Start difference. First operand 311139 states and 435308 transitions. cyclomatic complexity: 124201 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:42,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:34:42,016 INFO L93 Difference]: Finished difference Result 886882 states and 1234609 transitions. [2021-12-07 00:34:42,017 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-07 00:34:42,017 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 886882 states and 1234609 transitions. [2021-12-07 00:34:45,808 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 877020 [2021-12-07 00:34:47,694 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 886882 states to 886882 states and 1234609 transitions. [2021-12-07 00:34:47,694 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 886882 [2021-12-07 00:34:48,024 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 886882 [2021-12-07 00:34:48,024 INFO L73 IsDeterministic]: Start isDeterministic. Operand 886882 states and 1234609 transitions. [2021-12-07 00:34:48,447 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:34:48,447 INFO L681 BuchiCegarLoop]: Abstraction has 886882 states and 1234609 transitions. [2021-12-07 00:34:48,787 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 886882 states and 1234609 transitions. [2021-12-07 00:34:54,511 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 886882 to 874338. [2021-12-07 00:34:54,832 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 874338 states, 874338 states have (on average 1.393256383686858) internal successors, (1218177), 874337 states have internal predecessors, (1218177), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:34:56,987 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 874338 states to 874338 states and 1218177 transitions. [2021-12-07 00:34:56,987 INFO L704 BuchiCegarLoop]: Abstraction has 874338 states and 1218177 transitions. [2021-12-07 00:34:56,987 INFO L587 BuchiCegarLoop]: Abstraction has 874338 states and 1218177 transitions. [2021-12-07 00:34:56,987 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-12-07 00:34:56,987 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 874338 states and 1218177 transitions. [2021-12-07 00:34:59,194 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 872268 [2021-12-07 00:34:59,194 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:34:59,194 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:34:59,196 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:59,196 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:34:59,197 INFO L791 eck$LassoCheckResult]: Stem: 3041098#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 3041099#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 3042351#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3042352#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3042527#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 3041633#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3041023#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3041024#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3041984#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3041985#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3042124#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3042125#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3040783#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3040784#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3042159#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 3041366#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 3041367#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 3042059#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 3041260#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3041261#L1291 assume !(0 == ~M_E~0); 3042528#L1291-2 assume !(0 == ~T1_E~0); 3042522#L1296-1 assume !(0 == ~T2_E~0); 3041429#L1301-1 assume !(0 == ~T3_E~0); 3041430#L1306-1 assume !(0 == ~T4_E~0); 3042071#L1311-1 assume !(0 == ~T5_E~0); 3040626#L1316-1 assume !(0 == ~T6_E~0); 3040627#L1321-1 assume !(0 == ~T7_E~0); 3041444#L1326-1 assume !(0 == ~T8_E~0); 3040453#L1331-1 assume !(0 == ~T9_E~0); 3040155#L1336-1 assume !(0 == ~T10_E~0); 3040156#L1341-1 assume !(0 == ~T11_E~0); 3040232#L1346-1 assume !(0 == ~T12_E~0); 3040233#L1351-1 assume !(0 == ~T13_E~0); 3040576#L1356-1 assume !(0 == ~E_M~0); 3040577#L1361-1 assume !(0 == ~E_1~0); 3042394#L1366-1 assume !(0 == ~E_2~0); 3040616#L1371-1 assume !(0 == ~E_3~0); 3040617#L1376-1 assume !(0 == ~E_4~0); 3041508#L1381-1 assume !(0 == ~E_5~0); 3041509#L1386-1 assume !(0 == ~E_6~0); 3042450#L1391-1 assume !(0 == ~E_7~0); 3042500#L1396-1 assume !(0 == ~E_8~0); 3041397#L1401-1 assume !(0 == ~E_9~0); 3041398#L1406-1 assume !(0 == ~E_10~0); 3041732#L1411-1 assume !(0 == ~E_11~0); 3041733#L1416-1 assume !(0 == ~E_12~0); 3041308#L1421-1 assume !(0 == ~E_13~0); 3040808#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3040809#L640 assume !(1 == ~m_pc~0); 3041517#L640-2 is_master_triggered_~__retres1~0#1 := 0; 3041465#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3041466#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3041350#L1603 assume !(0 != activate_threads_~tmp~1#1); 3041351#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3040948#L659 assume !(1 == ~t1_pc~0); 3040949#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3042233#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3042198#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3041079#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 3041080#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3041095#L678 assume !(1 == ~t2_pc~0); 3042257#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3042441#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3042442#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3041206#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 3041207#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3041345#L697 assume !(1 == ~t3_pc~0); 3041346#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3041485#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3042299#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3041245#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 3041246#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3042328#L716 assume !(1 == ~t4_pc~0); 3041806#L716-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3040927#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3040928#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3040415#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 3040416#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3041819#L735 assume !(1 == ~t5_pc~0); 3040377#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3040378#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3040832#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3041851#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 3041422#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3041423#L754 assume !(1 == ~t6_pc~0); 3041687#L754-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3041037#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3041038#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3041009#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 3041010#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3041973#L773 assume !(1 == ~t7_pc~0); 3040580#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3040579#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3041467#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3041431#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 3041432#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3041498#L792 assume !(1 == ~t8_pc~0); 3041702#L792-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3042128#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3041491#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3041425#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 3041348#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3041349#L811 assume !(1 == ~t9_pc~0); 3041582#L811-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3042213#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3042004#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3041578#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 3041362#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3041363#L830 assume !(1 == ~t10_pc~0); 3041048#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3042602#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3040249#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3040250#L1683 assume !(0 != activate_threads_~tmp___9~0#1); 3040539#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3041995#L849 assume !(1 == ~t11_pc~0); 3041996#L849-2 is_transmit11_triggered_~__retres1~11#1 := 0; 3040352#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3040353#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 3040955#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 3041860#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 3041861#L868 assume !(1 == ~t12_pc~0); 3041190#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 3041189#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3040964#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 3040965#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 3040591#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 3040592#L887 assume 1 == ~t13_pc~0; 3041876#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 3041237#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 3041238#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 3041741#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 3040291#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3040292#L1439 assume !(1 == ~M_E~0); 3041418#L1439-2 assume !(1 == ~T1_E~0); 3040465#L1444-1 assume !(1 == ~T2_E~0); 3040466#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3040951#L1454-1 assume !(1 == ~T4_E~0); 3040952#L1459-1 assume !(1 == ~T5_E~0); 3041574#L1464-1 assume !(1 == ~T6_E~0); 3041575#L1469-1 assume !(1 == ~T7_E~0); 3041665#L1474-1 assume !(1 == ~T8_E~0); 3041309#L1479-1 assume !(1 == ~T9_E~0); 3041310#L1484-1 assume !(1 == ~T10_E~0); 3041579#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 3041178#L1494-1 assume !(1 == ~T12_E~0); 3041179#L1499-1 assume !(1 == ~T13_E~0); 3041386#L1504-1 assume !(1 == ~E_M~0); 3041387#L1509-1 assume !(1 == ~E_1~0); 3042106#L1514-1 assume !(1 == ~E_2~0); 3041703#L1519-1 assume !(1 == ~E_3~0); 3041704#L1524-1 assume !(1 == ~E_4~0); 3042415#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 3042416#L1534-1 assume !(1 == ~E_6~0); 3040285#L1539-1 assume !(1 == ~E_7~0); 3040286#L1544-1 assume !(1 == ~E_8~0); 3040701#L1549-1 assume !(1 == ~E_9~0); 3042374#L1554-1 assume !(1 == ~E_10~0); 3042369#L1559-1 assume !(1 == ~E_11~0); 3042154#L1564-1 assume !(1 == ~E_12~0); 3042155#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 3042408#L1574-1 assume { :end_inline_reset_delta_events } true; 3042464#L1940-2 [2021-12-07 00:34:59,197 INFO L793 eck$LassoCheckResult]: Loop: 3042464#L1940-2 assume !false; 3427721#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3427715#L1266 assume !false; 3427714#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 3360592#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 3360583#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 3360580#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3360578#L1079 assume !(0 != eval_~tmp~0#1); 3360579#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3429907#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3429899#L1291-3 assume !(0 == ~M_E~0); 3429891#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3429883#L1296-3 assume !(0 == ~T2_E~0); 3429874#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3429864#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3429854#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3429845#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3429836#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3429827#L1326-3 assume !(0 == ~T8_E~0); 3429818#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3429809#L1336-3 assume !(0 == ~T10_E~0); 3429801#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 3429794#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 3429787#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 3429779#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3429771#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3429762#L1366-3 assume !(0 == ~E_2~0); 3429754#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3429746#L1376-3 assume !(0 == ~E_4~0); 3429737#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3429730#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3429722#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3429716#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3429709#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3429703#L1406-3 assume !(0 == ~E_10~0); 3429698#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3429691#L1416-3 assume !(0 == ~E_12~0); 3429684#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 3429676#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3429670#L640-45 assume !(1 == ~m_pc~0); 3429664#L640-47 is_master_triggered_~__retres1~0#1 := 0; 3429656#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3429647#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3429639#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3429632#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3429625#L659-45 assume !(1 == ~t1_pc~0); 3429618#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 3429611#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3429601#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3429594#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3429586#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3429579#L678-45 assume !(1 == ~t2_pc~0); 3429571#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 3429561#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3429552#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3429543#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3429533#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3429523#L697-45 assume 1 == ~t3_pc~0; 3429513#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3429503#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3429493#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3429482#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3429473#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3429464#L716-45 assume !(1 == ~t4_pc~0); 3429458#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 3429453#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3429446#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3429439#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3429431#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3429424#L735-45 assume 1 == ~t5_pc~0; 3429416#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3429408#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3429399#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3429393#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3429385#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3429378#L754-45 assume !(1 == ~t6_pc~0); 3429372#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 3429363#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3429358#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3429350#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3429342#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3429335#L773-45 assume 1 == ~t7_pc~0; 3429288#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3429277#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3429269#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3429262#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 3429256#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3429249#L792-45 assume !(1 == ~t8_pc~0); 3429244#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 3429239#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3429232#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3429226#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3429220#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3429213#L811-45 assume !(1 == ~t9_pc~0); 3429204#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 3429195#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3429185#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3429176#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3429168#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3429160#L830-45 assume 1 == ~t10_pc~0; 3429152#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 3429143#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3429135#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3429127#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3429121#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3429115#L849-45 assume !(1 == ~t11_pc~0); 3429107#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 3429093#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3429057#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 3429050#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3429044#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 3429035#L868-45 assume 1 == ~t12_pc~0; 3429033#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 3429021#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3428984#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 3428981#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 3428979#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 3428977#L887-45 assume !(1 == ~t13_pc~0); 3428974#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 3428972#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 3428970#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 3428968#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 3428966#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3428964#L1439-3 assume !(1 == ~M_E~0); 3428465#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3428936#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3428928#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3428921#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3428908#L1459-3 assume !(1 == ~T5_E~0); 3428907#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3428906#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3428904#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3428902#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3428900#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3428898#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 3428896#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 3428894#L1499-3 assume !(1 == ~T13_E~0); 3428892#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3428890#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3428888#L1514-3 assume !(1 == ~E_2~0); 3428886#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3428884#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3428882#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3428880#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3428878#L1539-3 assume !(1 == ~E_7~0); 3428876#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3428874#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3428873#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3428872#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 3428871#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 3428869#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 3428654#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 3428123#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 3428103#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 3428095#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 3428086#L1959 assume !(0 == start_simulation_~tmp~3#1); 3427826#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 3427751#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 3427737#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 3427735#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 3427734#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3427730#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3427727#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 3427722#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 3042464#L1940-2 [2021-12-07 00:34:59,197 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:59,197 INFO L85 PathProgramCache]: Analyzing trace with hash 736341324, now seen corresponding path program 1 times [2021-12-07 00:34:59,198 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:59,198 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2055875086] [2021-12-07 00:34:59,198 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:59,198 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:59,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:59,225 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:59,225 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:59,225 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2055875086] [2021-12-07 00:34:59,225 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2055875086] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:59,225 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:59,225 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-07 00:34:59,225 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1469787267] [2021-12-07 00:34:59,225 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:59,226 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:34:59,226 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:34:59,226 INFO L85 PathProgramCache]: Analyzing trace with hash 389210591, now seen corresponding path program 1 times [2021-12-07 00:34:59,226 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:34:59,226 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [215298773] [2021-12-07 00:34:59,226 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:34:59,227 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:34:59,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:34:59,252 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:34:59,252 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:34:59,253 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [215298773] [2021-12-07 00:34:59,253 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [215298773] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:34:59,253 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:34:59,253 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:34:59,253 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1538442411] [2021-12-07 00:34:59,253 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:34:59,253 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:34:59,254 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:34:59,254 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:34:59,254 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:34:59,254 INFO L87 Difference]: Start difference. First operand 874338 states and 1218177 transitions. cyclomatic complexity: 343903 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:35:04,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:35:04,126 INFO L93 Difference]: Finished difference Result 1675561 states and 2328734 transitions. [2021-12-07 00:35:04,127 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:35:04,127 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1675561 states and 2328734 transitions. [2021-12-07 00:35:10,856 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 1670300 [2021-12-07 00:35:14,754 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1675561 states to 1675561 states and 2328734 transitions. [2021-12-07 00:35:14,754 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1675561 [2021-12-07 00:35:15,389 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1675561 [2021-12-07 00:35:15,389 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1675561 states and 2328734 transitions. [2021-12-07 00:35:16,173 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:35:16,173 INFO L681 BuchiCegarLoop]: Abstraction has 1675561 states and 2328734 transitions. [2021-12-07 00:35:16,845 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1675561 states and 2328734 transitions.