./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.02.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 839c364b Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66751a00-5c53-4330-b56f-b5f6ba4bb390/bin/uautomizer-DrprNOufMa/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66751a00-5c53-4330-b56f-b5f6ba4bb390/bin/uautomizer-DrprNOufMa/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66751a00-5c53-4330-b56f-b5f6ba4bb390/bin/uautomizer-DrprNOufMa/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66751a00-5c53-4330-b56f-b5f6ba4bb390/bin/uautomizer-DrprNOufMa/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.02.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66751a00-5c53-4330-b56f-b5f6ba4bb390/bin/uautomizer-DrprNOufMa/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66751a00-5c53-4330-b56f-b5f6ba4bb390/bin/uautomizer-DrprNOufMa --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 2cbfaf31aa56f767af01fea9a12ccb47d60ab19076d72b85e8ca46d6ff778e4c --- Real Ultimate output --- This is Ultimate 0.2.2-hotfix-svcomp22-839c364 [2021-12-07 00:26:04,339 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-07 00:26:04,341 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-07 00:26:04,364 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-07 00:26:04,364 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-07 00:26:04,365 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-07 00:26:04,366 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-07 00:26:04,368 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-07 00:26:04,370 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-07 00:26:04,371 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-07 00:26:04,371 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-07 00:26:04,372 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-07 00:26:04,373 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-07 00:26:04,374 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-07 00:26:04,375 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-07 00:26:04,376 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-07 00:26:04,377 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-07 00:26:04,378 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-07 00:26:04,380 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-07 00:26:04,382 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-07 00:26:04,383 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-07 00:26:04,384 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-07 00:26:04,385 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-07 00:26:04,386 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-07 00:26:04,389 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-07 00:26:04,389 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-07 00:26:04,390 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-07 00:26:04,391 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-07 00:26:04,391 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-07 00:26:04,392 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-07 00:26:04,392 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-07 00:26:04,393 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-07 00:26:04,393 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-07 00:26:04,394 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-07 00:26:04,395 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-07 00:26:04,395 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-07 00:26:04,396 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-07 00:26:04,396 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-07 00:26:04,396 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-07 00:26:04,397 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-07 00:26:04,397 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-07 00:26:04,398 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66751a00-5c53-4330-b56f-b5f6ba4bb390/bin/uautomizer-DrprNOufMa/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-07 00:26:04,418 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-07 00:26:04,418 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-07 00:26:04,419 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-07 00:26:04,419 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-07 00:26:04,420 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-07 00:26:04,420 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-07 00:26:04,420 INFO L138 SettingsManager]: * Use SBE=true [2021-12-07 00:26:04,420 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-07 00:26:04,420 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-07 00:26:04,420 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-07 00:26:04,420 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-07 00:26:04,420 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-07 00:26:04,421 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-07 00:26:04,421 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-07 00:26:04,425 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-07 00:26:04,426 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-07 00:26:04,426 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-07 00:26:04,426 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-07 00:26:04,426 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-07 00:26:04,426 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-07 00:26:04,426 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-07 00:26:04,426 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-07 00:26:04,426 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-07 00:26:04,427 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-07 00:26:04,427 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-07 00:26:04,427 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-07 00:26:04,427 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-07 00:26:04,427 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-07 00:26:04,427 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-07 00:26:04,427 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-07 00:26:04,428 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-07 00:26:04,428 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-07 00:26:04,428 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-07 00:26:04,429 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66751a00-5c53-4330-b56f-b5f6ba4bb390/bin/uautomizer-DrprNOufMa/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66751a00-5c53-4330-b56f-b5f6ba4bb390/bin/uautomizer-DrprNOufMa Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2cbfaf31aa56f767af01fea9a12ccb47d60ab19076d72b85e8ca46d6ff778e4c [2021-12-07 00:26:04,598 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-07 00:26:04,613 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-07 00:26:04,614 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-07 00:26:04,615 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-07 00:26:04,616 INFO L275 PluginConnector]: CDTParser initialized [2021-12-07 00:26:04,616 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66751a00-5c53-4330-b56f-b5f6ba4bb390/bin/uautomizer-DrprNOufMa/../../sv-benchmarks/c/systemc/transmitter.02.cil.c [2021-12-07 00:26:04,657 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66751a00-5c53-4330-b56f-b5f6ba4bb390/bin/uautomizer-DrprNOufMa/data/8afd421de/6f37e6d79a6b4e81954b4da18af06dfa/FLAGbd1e60dc9 [2021-12-07 00:26:05,035 INFO L306 CDTParser]: Found 1 translation units. [2021-12-07 00:26:05,035 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66751a00-5c53-4330-b56f-b5f6ba4bb390/sv-benchmarks/c/systemc/transmitter.02.cil.c [2021-12-07 00:26:05,042 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66751a00-5c53-4330-b56f-b5f6ba4bb390/bin/uautomizer-DrprNOufMa/data/8afd421de/6f37e6d79a6b4e81954b4da18af06dfa/FLAGbd1e60dc9 [2021-12-07 00:26:05,052 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66751a00-5c53-4330-b56f-b5f6ba4bb390/bin/uautomizer-DrprNOufMa/data/8afd421de/6f37e6d79a6b4e81954b4da18af06dfa [2021-12-07 00:26:05,054 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-07 00:26:05,055 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-07 00:26:05,056 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-07 00:26:05,056 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-07 00:26:05,058 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-07 00:26:05,059 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 12:26:05" (1/1) ... [2021-12-07 00:26:05,060 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@79d7406e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:26:05, skipping insertion in model container [2021-12-07 00:26:05,060 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.12 12:26:05" (1/1) ... [2021-12-07 00:26:05,065 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-07 00:26:05,085 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-07 00:26:05,192 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66751a00-5c53-4330-b56f-b5f6ba4bb390/sv-benchmarks/c/systemc/transmitter.02.cil.c[706,719] [2021-12-07 00:26:05,224 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-07 00:26:05,231 INFO L203 MainTranslator]: Completed pre-run [2021-12-07 00:26:05,239 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66751a00-5c53-4330-b56f-b5f6ba4bb390/sv-benchmarks/c/systemc/transmitter.02.cil.c[706,719] [2021-12-07 00:26:05,257 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-07 00:26:05,268 INFO L208 MainTranslator]: Completed translation [2021-12-07 00:26:05,268 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:26:05 WrapperNode [2021-12-07 00:26:05,268 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-07 00:26:05,269 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-07 00:26:05,269 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-07 00:26:05,269 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-07 00:26:05,275 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:26:05" (1/1) ... [2021-12-07 00:26:05,281 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:26:05" (1/1) ... [2021-12-07 00:26:05,306 INFO L137 Inliner]: procedures = 32, calls = 36, calls flagged for inlining = 31, calls inlined = 44, statements flattened = 530 [2021-12-07 00:26:05,306 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-07 00:26:05,307 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-07 00:26:05,307 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-07 00:26:05,307 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-07 00:26:05,313 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:26:05" (1/1) ... [2021-12-07 00:26:05,313 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:26:05" (1/1) ... [2021-12-07 00:26:05,315 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:26:05" (1/1) ... [2021-12-07 00:26:05,316 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:26:05" (1/1) ... [2021-12-07 00:26:05,322 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:26:05" (1/1) ... [2021-12-07 00:26:05,329 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:26:05" (1/1) ... [2021-12-07 00:26:05,331 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:26:05" (1/1) ... [2021-12-07 00:26:05,335 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-07 00:26:05,336 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-07 00:26:05,336 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-07 00:26:05,336 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-07 00:26:05,337 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:26:05" (1/1) ... [2021-12-07 00:26:05,343 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-07 00:26:05,355 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66751a00-5c53-4330-b56f-b5f6ba4bb390/bin/uautomizer-DrprNOufMa/z3 [2021-12-07 00:26:05,366 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66751a00-5c53-4330-b56f-b5f6ba4bb390/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-07 00:26:05,368 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66751a00-5c53-4330-b56f-b5f6ba4bb390/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-07 00:26:05,403 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-07 00:26:05,404 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-07 00:26:05,404 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-07 00:26:05,404 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-07 00:26:05,465 INFO L236 CfgBuilder]: Building ICFG [2021-12-07 00:26:05,466 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-07 00:26:05,789 INFO L277 CfgBuilder]: Performing block encoding [2021-12-07 00:26:05,803 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-07 00:26:05,803 INFO L301 CfgBuilder]: Removed 6 assume(true) statements. [2021-12-07 00:26:05,806 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 12:26:05 BoogieIcfgContainer [2021-12-07 00:26:05,806 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-07 00:26:05,807 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-07 00:26:05,807 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-07 00:26:05,809 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-07 00:26:05,810 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-07 00:26:05,810 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 07.12 12:26:05" (1/3) ... [2021-12-07 00:26:05,811 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7d5333dc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.12 12:26:05, skipping insertion in model container [2021-12-07 00:26:05,811 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-07 00:26:05,811 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.12 12:26:05" (2/3) ... [2021-12-07 00:26:05,811 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7d5333dc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.12 12:26:05, skipping insertion in model container [2021-12-07 00:26:05,811 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-07 00:26:05,811 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 12:26:05" (3/3) ... [2021-12-07 00:26:05,812 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.02.cil.c [2021-12-07 00:26:05,846 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-07 00:26:05,846 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-07 00:26:05,846 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-07 00:26:05,846 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-07 00:26:05,846 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-07 00:26:05,846 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-07 00:26:05,846 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-07 00:26:05,846 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-07 00:26:05,864 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 205 states, 204 states have (on average 1.5392156862745099) internal successors, (314), 204 states have internal predecessors, (314), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:26:05,893 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 160 [2021-12-07 00:26:05,893 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:26:05,893 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:26:05,901 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:26:05,901 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:26:05,901 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-07 00:26:05,902 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 205 states, 204 states have (on average 1.5392156862745099) internal successors, (314), 204 states have internal predecessors, (314), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:26:05,914 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 160 [2021-12-07 00:26:05,914 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:26:05,914 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:26:05,916 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:26:05,916 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:26:05,921 INFO L791 eck$LassoCheckResult]: Stem: 197#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 144#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 4#L491true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 200#L214true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 176#L221true assume !(1 == ~m_i~0);~m_st~0 := 2; 55#L221-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 38#L226-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 149#L231-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31#L334true assume !(0 == ~M_E~0); 156#L334-2true assume !(0 == ~T1_E~0); 99#L339-1true assume !(0 == ~T2_E~0); 94#L344-1true assume 0 == ~E_1~0;~E_1~0 := 1; 131#L349-1true assume !(0 == ~E_2~0); 37#L354-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 105#L156true assume !(1 == ~m_pc~0); 142#L156-2true is_master_triggered_~__retres1~0#1 := 0; 125#L167true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 115#L168true activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 71#L405true assume !(0 != activate_threads_~tmp~1#1); 58#L405-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 113#L175true assume 1 == ~t1_pc~0; 148#L176true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 59#L186true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 101#L187true activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 102#L413true assume !(0 != activate_threads_~tmp___0~0#1); 179#L413-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 182#L194true assume !(1 == ~t2_pc~0); 201#L194-2true is_transmit2_triggered_~__retres1~2#1 := 0; 65#L205true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32#L206true activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 25#L421true assume !(0 != activate_threads_~tmp___1~0#1); 76#L421-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12#L367true assume !(1 == ~M_E~0); 181#L367-2true assume !(1 == ~T1_E~0); 119#L372-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 122#L377-1true assume !(1 == ~E_1~0); 22#L382-1true assume !(1 == ~E_2~0); 73#L387-1true assume { :end_inline_reset_delta_events } true; 93#L528-2true [2021-12-07 00:26:05,922 INFO L793 eck$LassoCheckResult]: Loop: 93#L528-2true assume !false; 77#L529true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 175#L309true assume false; 13#L324true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 72#L214-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 204#L334-3true assume 0 == ~M_E~0;~M_E~0 := 1; 145#L334-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 103#L339-3true assume !(0 == ~T2_E~0); 177#L344-3true assume 0 == ~E_1~0;~E_1~0 := 1; 69#L349-3true assume 0 == ~E_2~0;~E_2~0 := 1; 30#L354-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 88#L156-9true assume !(1 == ~m_pc~0); 6#L156-11true is_master_triggered_~__retres1~0#1 := 0; 53#L167-3true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 167#L168-3true activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 106#L405-9true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19#L405-11true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 189#L175-9true assume !(1 == ~t1_pc~0); 129#L175-11true is_transmit1_triggered_~__retres1~1#1 := 0; 14#L186-3true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 100#L187-3true activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 141#L413-9true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 135#L413-11true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 186#L194-9true assume !(1 == ~t2_pc~0); 26#L194-11true is_transmit2_triggered_~__retres1~2#1 := 0; 193#L205-3true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75#L206-3true activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 97#L421-9true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 132#L421-11true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51#L367-3true assume 1 == ~M_E~0;~M_E~0 := 2; 8#L367-5true assume !(1 == ~T1_E~0); 33#L372-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 17#L377-3true assume 1 == ~E_1~0;~E_1~0 := 2; 28#L382-3true assume 1 == ~E_2~0;~E_2~0 := 2; 98#L387-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 133#L244-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 169#L261-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 23#L262-1true start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 140#L547true assume !(0 == start_simulation_~tmp~3#1); 152#L547-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 137#L244-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 49#L261-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 166#L262-2true stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 36#L502true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46#L509true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 174#L510true start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 18#L560true assume !(0 != start_simulation_~tmp___0~1#1); 93#L528-2true [2021-12-07 00:26:05,926 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:26:05,926 INFO L85 PathProgramCache]: Analyzing trace with hash -886407522, now seen corresponding path program 1 times [2021-12-07 00:26:05,932 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:26:05,933 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1452071263] [2021-12-07 00:26:05,933 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:26:05,934 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:26:05,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:26:06,043 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:26:06,043 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:26:06,043 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1452071263] [2021-12-07 00:26:06,044 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1452071263] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:26:06,044 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:26:06,044 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:26:06,045 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1052174516] [2021-12-07 00:26:06,046 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:26:06,049 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:26:06,049 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:26:06,050 INFO L85 PathProgramCache]: Analyzing trace with hash 707442261, now seen corresponding path program 1 times [2021-12-07 00:26:06,050 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:26:06,050 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1445348088] [2021-12-07 00:26:06,050 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:26:06,050 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:26:06,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:26:06,067 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:26:06,067 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:26:06,067 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1445348088] [2021-12-07 00:26:06,067 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1445348088] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:26:06,067 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:26:06,068 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-07 00:26:06,068 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [165935264] [2021-12-07 00:26:06,068 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:26:06,069 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:26:06,069 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:26:06,091 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:26:06,092 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:26:06,093 INFO L87 Difference]: Start difference. First operand has 205 states, 204 states have (on average 1.5392156862745099) internal successors, (314), 204 states have internal predecessors, (314), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:26:06,118 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:26:06,118 INFO L93 Difference]: Finished difference Result 204 states and 299 transitions. [2021-12-07 00:26:06,119 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:26:06,124 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 204 states and 299 transitions. [2021-12-07 00:26:06,130 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 157 [2021-12-07 00:26:06,136 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 204 states to 198 states and 293 transitions. [2021-12-07 00:26:06,137 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 198 [2021-12-07 00:26:06,138 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 198 [2021-12-07 00:26:06,138 INFO L73 IsDeterministic]: Start isDeterministic. Operand 198 states and 293 transitions. [2021-12-07 00:26:06,140 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:26:06,140 INFO L681 BuchiCegarLoop]: Abstraction has 198 states and 293 transitions. [2021-12-07 00:26:06,152 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 198 states and 293 transitions. [2021-12-07 00:26:06,165 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 198 to 198. [2021-12-07 00:26:06,166 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 198 states, 198 states have (on average 1.47979797979798) internal successors, (293), 197 states have internal predecessors, (293), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:26:06,167 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 198 states to 198 states and 293 transitions. [2021-12-07 00:26:06,168 INFO L704 BuchiCegarLoop]: Abstraction has 198 states and 293 transitions. [2021-12-07 00:26:06,168 INFO L587 BuchiCegarLoop]: Abstraction has 198 states and 293 transitions. [2021-12-07 00:26:06,168 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-07 00:26:06,168 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 198 states and 293 transitions. [2021-12-07 00:26:06,171 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 157 [2021-12-07 00:26:06,171 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:26:06,171 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:26:06,172 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:26:06,172 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:26:06,173 INFO L791 eck$LassoCheckResult]: Stem: 615#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 601#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 421#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 422#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 609#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 514#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 488#L226-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 489#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 476#L334 assume !(0 == ~M_E~0); 477#L334-2 assume !(0 == ~T1_E~0); 565#L339-1 assume !(0 == ~T2_E~0); 559#L344-1 assume 0 == ~E_1~0;~E_1~0 := 1; 560#L349-1 assume !(0 == ~E_2~0); 486#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 487#L156 assume !(1 == ~m_pc~0); 429#L156-2 is_master_triggered_~__retres1~0#1 := 0; 428#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 581#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 534#L405 assume !(0 != activate_threads_~tmp~1#1); 518#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 519#L175 assume 1 == ~t1_pc~0; 578#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 520#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 521#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 567#L413 assume !(0 != activate_threads_~tmp___0~0#1); 568#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 611#L194 assume !(1 == ~t2_pc~0); 558#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 530#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 478#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 465#L421 assume !(0 != activate_threads_~tmp___1~0#1); 466#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 440#L367 assume !(1 == ~M_E~0); 441#L367-2 assume !(1 == ~T1_E~0); 585#L372-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 586#L377-1 assume !(1 == ~E_1~0); 460#L382-1 assume !(1 == ~E_2~0); 461#L387-1 assume { :end_inline_reset_delta_events } true; 452#L528-2 [2021-12-07 00:26:06,173 INFO L793 eck$LassoCheckResult]: Loop: 452#L528-2 assume !false; 539#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 513#L309 assume !false; 492#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 432#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 433#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 577#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 418#L276 assume !(0 != eval_~tmp~0#1); 420#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 442#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 535#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 602#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 569#L339-3 assume !(0 == ~T2_E~0); 570#L344-3 assume 0 == ~E_1~0;~E_1~0 := 1; 533#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 474#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 475#L156-9 assume !(1 == ~m_pc~0); 425#L156-11 is_master_triggered_~__retres1~0#1 := 0; 426#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 511#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 572#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 453#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 454#L175-9 assume 1 == ~t1_pc~0; 496#L176-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 443#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 444#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 566#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 596#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 597#L194-9 assume !(1 == ~t2_pc~0); 467#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 468#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 537#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 538#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 563#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 508#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 430#L367-5 assume !(1 == ~T1_E~0); 431#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 449#L377-3 assume 1 == ~E_1~0;~E_1~0 := 2; 450#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 471#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 564#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 480#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 462#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 463#L547 assume !(0 == start_simulation_~tmp~3#1); 587#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 598#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 505#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 506#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 484#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 485#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 501#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 451#L560 assume !(0 != start_simulation_~tmp___0~1#1); 452#L528-2 [2021-12-07 00:26:06,173 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:26:06,174 INFO L85 PathProgramCache]: Analyzing trace with hash 1357575776, now seen corresponding path program 1 times [2021-12-07 00:26:06,174 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:26:06,174 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [904473333] [2021-12-07 00:26:06,174 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:26:06,174 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:26:06,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:26:06,201 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:26:06,202 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:26:06,202 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [904473333] [2021-12-07 00:26:06,202 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [904473333] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:26:06,202 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:26:06,202 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:26:06,202 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1062297586] [2021-12-07 00:26:06,202 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:26:06,203 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:26:06,203 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:26:06,203 INFO L85 PathProgramCache]: Analyzing trace with hash -1486806721, now seen corresponding path program 1 times [2021-12-07 00:26:06,203 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:26:06,203 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1749637128] [2021-12-07 00:26:06,203 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:26:06,204 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:26:06,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:26:06,244 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:26:06,244 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:26:06,244 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1749637128] [2021-12-07 00:26:06,244 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1749637128] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:26:06,244 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:26:06,244 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:26:06,249 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [84843787] [2021-12-07 00:26:06,250 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:26:06,250 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:26:06,250 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:26:06,251 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:26:06,251 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:26:06,251 INFO L87 Difference]: Start difference. First operand 198 states and 293 transitions. cyclomatic complexity: 96 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:26:06,275 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:26:06,275 INFO L93 Difference]: Finished difference Result 198 states and 292 transitions. [2021-12-07 00:26:06,275 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:26:06,276 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 198 states and 292 transitions. [2021-12-07 00:26:06,279 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 157 [2021-12-07 00:26:06,282 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 198 states to 198 states and 292 transitions. [2021-12-07 00:26:06,282 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 198 [2021-12-07 00:26:06,283 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 198 [2021-12-07 00:26:06,283 INFO L73 IsDeterministic]: Start isDeterministic. Operand 198 states and 292 transitions. [2021-12-07 00:26:06,284 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:26:06,284 INFO L681 BuchiCegarLoop]: Abstraction has 198 states and 292 transitions. [2021-12-07 00:26:06,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 198 states and 292 transitions. [2021-12-07 00:26:06,292 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 198 to 198. [2021-12-07 00:26:06,293 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 198 states, 198 states have (on average 1.4747474747474747) internal successors, (292), 197 states have internal predecessors, (292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:26:06,294 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 198 states to 198 states and 292 transitions. [2021-12-07 00:26:06,294 INFO L704 BuchiCegarLoop]: Abstraction has 198 states and 292 transitions. [2021-12-07 00:26:06,294 INFO L587 BuchiCegarLoop]: Abstraction has 198 states and 292 transitions. [2021-12-07 00:26:06,295 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-07 00:26:06,295 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 198 states and 292 transitions. [2021-12-07 00:26:06,296 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 157 [2021-12-07 00:26:06,297 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:26:06,297 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:26:06,299 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:26:06,299 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:26:06,299 INFO L791 eck$LassoCheckResult]: Stem: 1018#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 1004#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 824#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 825#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1012#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 917#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 891#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 892#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 879#L334 assume !(0 == ~M_E~0); 880#L334-2 assume !(0 == ~T1_E~0); 968#L339-1 assume !(0 == ~T2_E~0); 962#L344-1 assume 0 == ~E_1~0;~E_1~0 := 1; 963#L349-1 assume !(0 == ~E_2~0); 889#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 890#L156 assume !(1 == ~m_pc~0); 832#L156-2 is_master_triggered_~__retres1~0#1 := 0; 831#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 984#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 937#L405 assume !(0 != activate_threads_~tmp~1#1); 921#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 922#L175 assume 1 == ~t1_pc~0; 981#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 923#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 924#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 970#L413 assume !(0 != activate_threads_~tmp___0~0#1); 971#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1014#L194 assume !(1 == ~t2_pc~0); 961#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 933#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 881#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 868#L421 assume !(0 != activate_threads_~tmp___1~0#1); 869#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 843#L367 assume !(1 == ~M_E~0); 844#L367-2 assume !(1 == ~T1_E~0); 988#L372-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 989#L377-1 assume !(1 == ~E_1~0); 863#L382-1 assume !(1 == ~E_2~0); 864#L387-1 assume { :end_inline_reset_delta_events } true; 855#L528-2 [2021-12-07 00:26:06,300 INFO L793 eck$LassoCheckResult]: Loop: 855#L528-2 assume !false; 942#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 916#L309 assume !false; 895#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 835#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 836#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 980#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 821#L276 assume !(0 != eval_~tmp~0#1); 823#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 845#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 938#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1005#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 972#L339-3 assume !(0 == ~T2_E~0); 973#L344-3 assume 0 == ~E_1~0;~E_1~0 := 1; 936#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 877#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 878#L156-9 assume !(1 == ~m_pc~0); 828#L156-11 is_master_triggered_~__retres1~0#1 := 0; 829#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 914#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 975#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 856#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 857#L175-9 assume 1 == ~t1_pc~0; 899#L176-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 846#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 847#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 969#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 999#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1000#L194-9 assume !(1 == ~t2_pc~0); 870#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 871#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 940#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 941#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 966#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 911#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 833#L367-5 assume !(1 == ~T1_E~0); 834#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 852#L377-3 assume 1 == ~E_1~0;~E_1~0 := 2; 853#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 874#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 967#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 883#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 865#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 866#L547 assume !(0 == start_simulation_~tmp~3#1); 990#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1001#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 908#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 909#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 887#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 888#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 904#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 854#L560 assume !(0 != start_simulation_~tmp___0~1#1); 855#L528-2 [2021-12-07 00:26:06,300 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:26:06,301 INFO L85 PathProgramCache]: Analyzing trace with hash 1082816162, now seen corresponding path program 1 times [2021-12-07 00:26:06,301 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:26:06,301 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1425648741] [2021-12-07 00:26:06,301 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:26:06,301 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:26:06,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:26:06,345 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:26:06,345 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:26:06,345 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1425648741] [2021-12-07 00:26:06,346 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1425648741] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:26:06,346 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:26:06,346 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:26:06,346 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1758881954] [2021-12-07 00:26:06,346 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:26:06,347 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:26:06,347 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:26:06,347 INFO L85 PathProgramCache]: Analyzing trace with hash -1486806721, now seen corresponding path program 2 times [2021-12-07 00:26:06,348 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:26:06,348 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [330480187] [2021-12-07 00:26:06,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:26:06,348 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:26:06,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:26:06,386 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:26:06,386 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:26:06,386 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [330480187] [2021-12-07 00:26:06,386 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [330480187] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:26:06,386 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:26:06,386 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:26:06,386 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1021422475] [2021-12-07 00:26:06,387 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:26:06,387 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:26:06,387 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:26:06,387 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-07 00:26:06,387 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-07 00:26:06,388 INFO L87 Difference]: Start difference. First operand 198 states and 292 transitions. cyclomatic complexity: 95 Second operand has 4 states, 4 states have (on average 9.5) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:26:06,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:26:06,465 INFO L93 Difference]: Finished difference Result 337 states and 494 transitions. [2021-12-07 00:26:06,465 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-07 00:26:06,466 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 337 states and 494 transitions. [2021-12-07 00:26:06,470 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 290 [2021-12-07 00:26:06,473 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 337 states to 337 states and 494 transitions. [2021-12-07 00:26:06,473 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 337 [2021-12-07 00:26:06,474 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 337 [2021-12-07 00:26:06,474 INFO L73 IsDeterministic]: Start isDeterministic. Operand 337 states and 494 transitions. [2021-12-07 00:26:06,476 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:26:06,476 INFO L681 BuchiCegarLoop]: Abstraction has 337 states and 494 transitions. [2021-12-07 00:26:06,477 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 337 states and 494 transitions. [2021-12-07 00:26:06,489 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 337 to 335. [2021-12-07 00:26:06,490 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 335 states, 335 states have (on average 1.4686567164179105) internal successors, (492), 334 states have internal predecessors, (492), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:26:06,492 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 335 states to 335 states and 492 transitions. [2021-12-07 00:26:06,492 INFO L704 BuchiCegarLoop]: Abstraction has 335 states and 492 transitions. [2021-12-07 00:26:06,492 INFO L587 BuchiCegarLoop]: Abstraction has 335 states and 492 transitions. [2021-12-07 00:26:06,492 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-07 00:26:06,492 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 335 states and 492 transitions. [2021-12-07 00:26:06,495 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 290 [2021-12-07 00:26:06,495 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:26:06,495 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:26:06,496 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:26:06,497 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:26:06,497 INFO L791 eck$LassoCheckResult]: Stem: 1588#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 1565#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1369#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1370#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1577#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 1467#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1440#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1441#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1427#L334 assume !(0 == ~M_E~0); 1428#L334-2 assume !(0 == ~T1_E~0); 1521#L339-1 assume !(0 == ~T2_E~0); 1515#L344-1 assume !(0 == ~E_1~0); 1516#L349-1 assume !(0 == ~E_2~0); 1438#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1439#L156 assume !(1 == ~m_pc~0); 1377#L156-2 is_master_triggered_~__retres1~0#1 := 0; 1376#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1538#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1488#L405 assume !(0 != activate_threads_~tmp~1#1); 1471#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1472#L175 assume 1 == ~t1_pc~0; 1535#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1473#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1474#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1523#L413 assume !(0 != activate_threads_~tmp___0~0#1); 1524#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1579#L194 assume !(1 == ~t2_pc~0); 1514#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1484#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1429#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1415#L421 assume !(0 != activate_threads_~tmp___1~0#1); 1416#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1389#L367 assume !(1 == ~M_E~0); 1390#L367-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1543#L372-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1544#L377-1 assume !(1 == ~E_1~0); 1410#L382-1 assume !(1 == ~E_2~0); 1411#L387-1 assume { :end_inline_reset_delta_events } true; 1402#L528-2 [2021-12-07 00:26:06,497 INFO L793 eck$LassoCheckResult]: Loop: 1402#L528-2 assume !false; 1494#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1466#L309 assume !false; 1444#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1381#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1382#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1595#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1593#L276 assume !(0 != eval_~tmp~0#1); 1592#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1489#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1490#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1590#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1525#L339-3 assume !(0 == ~T2_E~0); 1526#L344-3 assume !(0 == ~E_1~0); 1487#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1425#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1426#L156-9 assume 1 == ~m_pc~0; 1510#L157-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1374#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1464#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1528#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1403#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1404#L175-9 assume 1 == ~t1_pc~0; 1448#L176-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1449#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1687#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1686#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1685#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1684#L194-9 assume 1 == ~t2_pc~0; 1682#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1585#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1586#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1681#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1680#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1679#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1677#L367-5 assume !(1 == ~T1_E~0); 1380#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1430#L377-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1399#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1667#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1555#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1432#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1639#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 1563#L547 assume !(0 == start_simulation_~tmp~3#1); 1546#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1560#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1458#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1459#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 1436#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1437#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1454#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1401#L560 assume !(0 != start_simulation_~tmp___0~1#1); 1402#L528-2 [2021-12-07 00:26:06,498 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:26:06,498 INFO L85 PathProgramCache]: Analyzing trace with hash -1290770142, now seen corresponding path program 1 times [2021-12-07 00:26:06,498 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:26:06,498 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1953151788] [2021-12-07 00:26:06,498 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:26:06,499 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:26:06,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:26:06,534 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:26:06,534 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:26:06,534 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1953151788] [2021-12-07 00:26:06,534 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1953151788] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:26:06,534 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:26:06,534 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:26:06,535 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1821693283] [2021-12-07 00:26:06,535 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:26:06,535 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:26:06,535 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:26:06,536 INFO L85 PathProgramCache]: Analyzing trace with hash 23037699, now seen corresponding path program 1 times [2021-12-07 00:26:06,536 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:26:06,536 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1760062999] [2021-12-07 00:26:06,536 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:26:06,536 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:26:06,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:26:06,565 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:26:06,566 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:26:06,566 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1760062999] [2021-12-07 00:26:06,566 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1760062999] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:26:06,566 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:26:06,566 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:26:06,566 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [406572659] [2021-12-07 00:26:06,566 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:26:06,567 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:26:06,567 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:26:06,567 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-07 00:26:06,568 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-07 00:26:06,568 INFO L87 Difference]: Start difference. First operand 335 states and 492 transitions. cyclomatic complexity: 159 Second operand has 4 states, 4 states have (on average 9.5) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:26:06,642 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:26:06,642 INFO L93 Difference]: Finished difference Result 824 states and 1185 transitions. [2021-12-07 00:26:06,642 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-07 00:26:06,643 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 824 states and 1185 transitions. [2021-12-07 00:26:06,651 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 745 [2021-12-07 00:26:06,658 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 824 states to 824 states and 1185 transitions. [2021-12-07 00:26:06,658 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 824 [2021-12-07 00:26:06,660 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 824 [2021-12-07 00:26:06,660 INFO L73 IsDeterministic]: Start isDeterministic. Operand 824 states and 1185 transitions. [2021-12-07 00:26:06,661 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:26:06,661 INFO L681 BuchiCegarLoop]: Abstraction has 824 states and 1185 transitions. [2021-12-07 00:26:06,662 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 824 states and 1185 transitions. [2021-12-07 00:26:06,677 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 824 to 763. [2021-12-07 00:26:06,679 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 763 states, 763 states have (on average 1.4521625163826999) internal successors, (1108), 762 states have internal predecessors, (1108), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:26:06,681 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 763 states to 763 states and 1108 transitions. [2021-12-07 00:26:06,681 INFO L704 BuchiCegarLoop]: Abstraction has 763 states and 1108 transitions. [2021-12-07 00:26:06,681 INFO L587 BuchiCegarLoop]: Abstraction has 763 states and 1108 transitions. [2021-12-07 00:26:06,681 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-07 00:26:06,681 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 763 states and 1108 transitions. [2021-12-07 00:26:06,684 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 715 [2021-12-07 00:26:06,685 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:26:06,685 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:26:06,685 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:26:06,685 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:26:06,686 INFO L791 eck$LassoCheckResult]: Stem: 2790#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 2748#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2538#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2539#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2773#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 2635#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2606#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2607#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2594#L334 assume !(0 == ~M_E~0); 2595#L334-2 assume !(0 == ~T1_E~0); 2692#L339-1 assume !(0 == ~T2_E~0); 2686#L344-1 assume !(0 == ~E_1~0); 2687#L349-1 assume !(0 == ~E_2~0); 2604#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2605#L156 assume !(1 == ~m_pc~0); 2699#L156-2 is_master_triggered_~__retres1~0#1 := 0; 2727#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2711#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2657#L405 assume !(0 != activate_threads_~tmp~1#1); 2640#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2641#L175 assume !(1 == ~t1_pc~0); 2647#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2642#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2643#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2694#L413 assume !(0 != activate_threads_~tmp___0~0#1); 2697#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2775#L194 assume !(1 == ~t2_pc~0); 2684#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2653#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2598#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2583#L421 assume !(0 != activate_threads_~tmp___1~0#1); 2584#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2554#L367 assume !(1 == ~M_E~0); 2555#L367-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2777#L372-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3202#L377-1 assume !(1 == ~E_1~0); 2577#L382-1 assume !(1 == ~E_2~0); 2578#L387-1 assume { :end_inline_reset_delta_events } true; 3189#L528-2 [2021-12-07 00:26:06,686 INFO L793 eck$LassoCheckResult]: Loop: 3189#L528-2 assume !false; 3188#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2881#L309 assume !false; 2882#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2874#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2873#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2850#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2851#L276 assume !(0 != eval_~tmp~0#1); 2558#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2559#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2793#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2794#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3184#L339-3 assume !(0 == ~T2_E~0); 3266#L344-3 assume !(0 == ~E_1~0); 3265#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3264#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2679#L156-9 assume !(1 == ~m_pc~0); 2680#L156-11 is_master_triggered_~__retres1~0#1 := 0; 3231#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3230#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3229#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3228#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3227#L175-9 assume !(1 == ~t1_pc~0); 3226#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 3225#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3224#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3223#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3222#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3221#L194-9 assume 1 == ~t2_pc~0; 3219#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3218#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3217#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3216#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3215#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3214#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3213#L367-5 assume !(1 == ~T1_E~0); 2546#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3211#L377-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2566#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2589#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2691#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2770#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2579#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 2580#L547 assume !(0 == start_simulation_~tmp~3#1); 3155#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3156#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3195#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3194#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 3193#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3192#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3191#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3190#L560 assume !(0 != start_simulation_~tmp___0~1#1); 3189#L528-2 [2021-12-07 00:26:06,686 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:26:06,686 INFO L85 PathProgramCache]: Analyzing trace with hash -150418431, now seen corresponding path program 1 times [2021-12-07 00:26:06,686 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:26:06,687 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [780529855] [2021-12-07 00:26:06,687 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:26:06,687 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:26:06,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:26:06,709 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:26:06,709 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:26:06,709 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [780529855] [2021-12-07 00:26:06,709 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [780529855] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:26:06,709 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:26:06,709 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-07 00:26:06,709 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1940006078] [2021-12-07 00:26:06,710 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:26:06,710 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:26:06,710 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:26:06,710 INFO L85 PathProgramCache]: Analyzing trace with hash -1798923135, now seen corresponding path program 1 times [2021-12-07 00:26:06,710 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:26:06,710 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1619537902] [2021-12-07 00:26:06,710 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:26:06,711 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:26:06,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:26:06,731 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:26:06,731 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:26:06,731 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1619537902] [2021-12-07 00:26:06,731 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1619537902] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:26:06,731 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:26:06,731 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:26:06,731 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2062588195] [2021-12-07 00:26:06,732 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:26:06,732 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:26:06,732 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:26:06,732 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:26:06,732 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:26:06,732 INFO L87 Difference]: Start difference. First operand 763 states and 1108 transitions. cyclomatic complexity: 349 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 2 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:26:06,743 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:26:06,743 INFO L93 Difference]: Finished difference Result 761 states and 1088 transitions. [2021-12-07 00:26:06,743 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:26:06,744 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 761 states and 1088 transitions. [2021-12-07 00:26:06,748 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 715 [2021-12-07 00:26:06,758 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 761 states to 761 states and 1088 transitions. [2021-12-07 00:26:06,758 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 761 [2021-12-07 00:26:06,759 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 761 [2021-12-07 00:26:06,759 INFO L73 IsDeterministic]: Start isDeterministic. Operand 761 states and 1088 transitions. [2021-12-07 00:26:06,760 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:26:06,760 INFO L681 BuchiCegarLoop]: Abstraction has 761 states and 1088 transitions. [2021-12-07 00:26:06,761 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 761 states and 1088 transitions. [2021-12-07 00:26:06,766 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 761 to 425. [2021-12-07 00:26:06,766 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 425 states, 425 states have (on average 1.4188235294117648) internal successors, (603), 424 states have internal predecessors, (603), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:26:06,768 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 425 states to 425 states and 603 transitions. [2021-12-07 00:26:06,768 INFO L704 BuchiCegarLoop]: Abstraction has 425 states and 603 transitions. [2021-12-07 00:26:06,768 INFO L587 BuchiCegarLoop]: Abstraction has 425 states and 603 transitions. [2021-12-07 00:26:06,768 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-07 00:26:06,768 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 425 states and 603 transitions. [2021-12-07 00:26:06,770 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 381 [2021-12-07 00:26:06,770 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:26:06,770 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:26:06,770 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:26:06,771 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:26:06,771 INFO L791 eck$LassoCheckResult]: Stem: 4285#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 4261#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 4069#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4070#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4274#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 4162#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4134#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4135#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4121#L334 assume !(0 == ~M_E~0); 4122#L334-2 assume !(0 == ~T1_E~0); 4216#L339-1 assume !(0 == ~T2_E~0); 4209#L344-1 assume !(0 == ~E_1~0); 4210#L349-1 assume !(0 == ~E_2~0); 4132#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4133#L156 assume !(1 == ~m_pc~0); 4223#L156-2 is_master_triggered_~__retres1~0#1 := 0; 4245#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4235#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4184#L405 assume !(0 != activate_threads_~tmp~1#1); 4168#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4169#L175 assume !(1 == ~t1_pc~0); 4176#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4170#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4171#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4218#L413 assume !(0 != activate_threads_~tmp___0~0#1); 4219#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4276#L194 assume !(1 == ~t2_pc~0); 4208#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4180#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4123#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4110#L421 assume !(0 != activate_threads_~tmp___1~0#1); 4111#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4084#L367 assume !(1 == ~M_E~0); 4085#L367-2 assume !(1 == ~T1_E~0); 4239#L372-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4240#L377-1 assume !(1 == ~E_1~0); 4105#L382-1 assume !(1 == ~E_2~0); 4106#L387-1 assume { :end_inline_reset_delta_events } true; 4186#L528-2 [2021-12-07 00:26:06,771 INFO L793 eck$LassoCheckResult]: Loop: 4186#L528-2 assume !false; 4336#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4326#L309 assume !false; 4323#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4319#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4314#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4311#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4306#L276 assume !(0 != eval_~tmp~0#1); 4086#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4087#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4185#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4262#L334-5 assume !(0 == ~T1_E~0); 4220#L339-3 assume !(0 == ~T2_E~0); 4221#L344-3 assume !(0 == ~E_1~0); 4183#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4119#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4120#L156-9 assume !(1 == ~m_pc~0); 4073#L156-11 is_master_triggered_~__retres1~0#1 := 0; 4074#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4159#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4224#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4098#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4099#L175-9 assume !(1 == ~t1_pc~0); 4248#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 4088#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4089#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4217#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4254#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4255#L194-9 assume !(1 == ~t2_pc~0); 4112#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 4113#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4188#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4189#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4213#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4155#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4156#L367-5 assume !(1 == ~T1_E~0); 4124#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4094#L377-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4095#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4116#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4251#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4126#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4107#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 4108#L547 assume !(0 == start_simulation_~tmp~3#1); 4241#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4264#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4349#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4347#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 4345#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4343#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4341#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 4339#L560 assume !(0 != start_simulation_~tmp___0~1#1); 4186#L528-2 [2021-12-07 00:26:06,771 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:26:06,771 INFO L85 PathProgramCache]: Analyzing trace with hash -148571389, now seen corresponding path program 1 times [2021-12-07 00:26:06,771 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:26:06,772 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1230996351] [2021-12-07 00:26:06,772 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:26:06,772 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:26:06,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:26:06,793 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:26:06,793 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:26:06,793 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1230996351] [2021-12-07 00:26:06,793 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1230996351] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:26:06,793 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:26:06,794 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-07 00:26:06,794 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [273704550] [2021-12-07 00:26:06,794 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:26:06,794 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:26:06,794 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:26:06,794 INFO L85 PathProgramCache]: Analyzing trace with hash 1329295906, now seen corresponding path program 1 times [2021-12-07 00:26:06,795 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:26:06,795 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [121209301] [2021-12-07 00:26:06,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:26:06,795 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:26:06,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:26:06,820 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:26:06,820 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:26:06,820 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [121209301] [2021-12-07 00:26:06,820 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [121209301] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:26:06,821 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:26:06,821 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-07 00:26:06,821 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1154405318] [2021-12-07 00:26:06,821 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:26:06,821 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:26:06,821 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:26:06,822 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:26:06,822 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:26:06,822 INFO L87 Difference]: Start difference. First operand 425 states and 603 transitions. cyclomatic complexity: 180 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 2 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:26:06,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:26:06,831 INFO L93 Difference]: Finished difference Result 425 states and 592 transitions. [2021-12-07 00:26:06,831 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:26:06,832 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 425 states and 592 transitions. [2021-12-07 00:26:06,834 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 381 [2021-12-07 00:26:06,837 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 425 states to 425 states and 592 transitions. [2021-12-07 00:26:06,837 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 425 [2021-12-07 00:26:06,837 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 425 [2021-12-07 00:26:06,837 INFO L73 IsDeterministic]: Start isDeterministic. Operand 425 states and 592 transitions. [2021-12-07 00:26:06,838 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:26:06,838 INFO L681 BuchiCegarLoop]: Abstraction has 425 states and 592 transitions. [2021-12-07 00:26:06,838 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 425 states and 592 transitions. [2021-12-07 00:26:06,842 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 425 to 425. [2021-12-07 00:26:06,843 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 425 states, 425 states have (on average 1.3929411764705881) internal successors, (592), 424 states have internal predecessors, (592), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:26:06,844 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 425 states to 425 states and 592 transitions. [2021-12-07 00:26:06,844 INFO L704 BuchiCegarLoop]: Abstraction has 425 states and 592 transitions. [2021-12-07 00:26:06,844 INFO L587 BuchiCegarLoop]: Abstraction has 425 states and 592 transitions. [2021-12-07 00:26:06,844 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-07 00:26:06,844 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 425 states and 592 transitions. [2021-12-07 00:26:06,846 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 381 [2021-12-07 00:26:06,846 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:26:06,846 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:26:06,847 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:26:06,847 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:26:06,847 INFO L791 eck$LassoCheckResult]: Stem: 5138#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 5113#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 4928#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4929#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5127#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 5021#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4992#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4993#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4980#L334 assume !(0 == ~M_E~0); 4981#L334-2 assume !(0 == ~T1_E~0); 5073#L339-1 assume !(0 == ~T2_E~0); 5067#L344-1 assume !(0 == ~E_1~0); 5068#L349-1 assume !(0 == ~E_2~0); 4990#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4991#L156 assume !(1 == ~m_pc~0); 5080#L156-2 is_master_triggered_~__retres1~0#1 := 0; 5100#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5089#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5042#L405 assume !(0 != activate_threads_~tmp~1#1); 5026#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5027#L175 assume !(1 == ~t1_pc~0); 5034#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5028#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5029#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 5075#L413 assume !(0 != activate_threads_~tmp___0~0#1); 5076#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5129#L194 assume !(1 == ~t2_pc~0); 5066#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5038#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4982#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4969#L421 assume !(0 != activate_threads_~tmp___1~0#1); 4970#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4943#L367 assume !(1 == ~M_E~0); 4944#L367-2 assume !(1 == ~T1_E~0); 5093#L372-1 assume !(1 == ~T2_E~0); 5094#L377-1 assume !(1 == ~E_1~0); 4964#L382-1 assume !(1 == ~E_2~0); 4965#L387-1 assume { :end_inline_reset_delta_events } true; 4956#L528-2 [2021-12-07 00:26:06,847 INFO L793 eck$LassoCheckResult]: Loop: 4956#L528-2 assume !false; 5047#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5020#L309 assume !false; 4996#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4936#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4937#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 5086#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4925#L276 assume !(0 != eval_~tmp~0#1); 4927#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5349#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5348#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5347#L334-5 assume !(0 == ~T1_E~0); 5346#L339-3 assume !(0 == ~T2_E~0); 5344#L344-3 assume !(0 == ~E_1~0); 5342#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5340#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5338#L156-9 assume !(1 == ~m_pc~0); 5336#L156-11 is_master_triggered_~__retres1~0#1 := 0; 5334#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5332#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5081#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4957#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4958#L175-9 assume !(1 == ~t1_pc~0); 5103#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 4947#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4948#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 5074#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5108#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5109#L194-9 assume 1 == ~t2_pc~0; 5044#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4972#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5045#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5046#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5071#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5015#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4934#L367-5 assume !(1 == ~T1_E~0); 4935#L372-3 assume !(1 == ~T2_E~0); 4953#L377-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4954#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4975#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 5072#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4984#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4966#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 4967#L547 assume !(0 == start_simulation_~tmp~3#1); 5096#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 5110#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 5010#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 5011#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 4988#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4989#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5006#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 4955#L560 assume !(0 != start_simulation_~tmp___0~1#1); 4956#L528-2 [2021-12-07 00:26:06,847 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:26:06,847 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 1 times [2021-12-07 00:26:06,847 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:26:06,848 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1059065781] [2021-12-07 00:26:06,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:26:06,848 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:26:06,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:26:06,854 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 00:26:06,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:26:06,878 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 00:26:06,878 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:26:06,878 INFO L85 PathProgramCache]: Analyzing trace with hash 1898622529, now seen corresponding path program 1 times [2021-12-07 00:26:06,878 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:26:06,878 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1110695410] [2021-12-07 00:26:06,879 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:26:06,879 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:26:06,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:26:06,902 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:26:06,902 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:26:06,902 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1110695410] [2021-12-07 00:26:06,903 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1110695410] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:26:06,903 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:26:06,903 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-07 00:26:06,903 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1572784742] [2021-12-07 00:26:06,903 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:26:06,903 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:26:06,903 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:26:06,904 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-07 00:26:06,904 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-07 00:26:06,904 INFO L87 Difference]: Start difference. First operand 425 states and 592 transitions. cyclomatic complexity: 169 Second operand has 5 states, 5 states have (on average 10.4) internal successors, (52), 5 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:26:06,951 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:26:06,951 INFO L93 Difference]: Finished difference Result 709 states and 975 transitions. [2021-12-07 00:26:06,951 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-07 00:26:06,952 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 709 states and 975 transitions. [2021-12-07 00:26:06,955 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 660 [2021-12-07 00:26:06,959 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 709 states to 709 states and 975 transitions. [2021-12-07 00:26:06,959 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 709 [2021-12-07 00:26:06,959 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 709 [2021-12-07 00:26:06,959 INFO L73 IsDeterministic]: Start isDeterministic. Operand 709 states and 975 transitions. [2021-12-07 00:26:06,960 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:26:06,960 INFO L681 BuchiCegarLoop]: Abstraction has 709 states and 975 transitions. [2021-12-07 00:26:06,961 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 709 states and 975 transitions. [2021-12-07 00:26:06,966 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 709 to 434. [2021-12-07 00:26:06,966 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 434 states, 434 states have (on average 1.3847926267281105) internal successors, (601), 433 states have internal predecessors, (601), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:26:06,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 434 states to 434 states and 601 transitions. [2021-12-07 00:26:06,967 INFO L704 BuchiCegarLoop]: Abstraction has 434 states and 601 transitions. [2021-12-07 00:26:06,968 INFO L587 BuchiCegarLoop]: Abstraction has 434 states and 601 transitions. [2021-12-07 00:26:06,968 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-07 00:26:06,968 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 434 states and 601 transitions. [2021-12-07 00:26:06,969 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 390 [2021-12-07 00:26:06,969 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:26:06,969 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:26:06,970 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:26:06,970 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:26:06,970 INFO L791 eck$LassoCheckResult]: Stem: 6293#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 6262#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 6077#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6078#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6278#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 6168#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6141#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6142#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6129#L334 assume !(0 == ~M_E~0); 6130#L334-2 assume !(0 == ~T1_E~0); 6218#L339-1 assume !(0 == ~T2_E~0); 6212#L344-1 assume !(0 == ~E_1~0); 6213#L349-1 assume !(0 == ~E_2~0); 6139#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6140#L156 assume !(1 == ~m_pc~0); 6225#L156-2 is_master_triggered_~__retres1~0#1 := 0; 6247#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6237#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6187#L405 assume !(0 != activate_threads_~tmp~1#1); 6172#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6173#L175 assume !(1 == ~t1_pc~0); 6180#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6174#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6175#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6220#L413 assume !(0 != activate_threads_~tmp___0~0#1); 6221#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6280#L194 assume !(1 == ~t2_pc~0); 6211#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6184#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6131#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 6118#L421 assume !(0 != activate_threads_~tmp___1~0#1); 6119#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6092#L367 assume !(1 == ~M_E~0); 6093#L367-2 assume !(1 == ~T1_E~0); 6241#L372-1 assume !(1 == ~T2_E~0); 6242#L377-1 assume !(1 == ~E_1~0); 6113#L382-1 assume !(1 == ~E_2~0); 6114#L387-1 assume { :end_inline_reset_delta_events } true; 6189#L528-2 [2021-12-07 00:26:06,970 INFO L793 eck$LassoCheckResult]: Loop: 6189#L528-2 assume !false; 6443#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6277#L309 assume !false; 6145#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6085#L244 assume !(0 == ~m_st~0); 6087#L248 assume !(0 == ~t1_st~0); 6233#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 6265#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6321#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6318#L276 assume !(0 != eval_~tmp~0#1); 6094#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6095#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6188#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6263#L334-5 assume !(0 == ~T1_E~0); 6222#L339-3 assume !(0 == ~T2_E~0); 6223#L344-3 assume !(0 == ~E_1~0); 6186#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6127#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6128#L156-9 assume !(1 == ~m_pc~0); 6081#L156-11 is_master_triggered_~__retres1~0#1 := 0; 6082#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6165#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6226#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6106#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6107#L175-9 assume !(1 == ~t1_pc~0); 6250#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 6096#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6097#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6219#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6261#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6405#L194-9 assume !(1 == ~t2_pc~0); 6120#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 6121#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6191#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 6192#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6216#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6162#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6083#L367-5 assume !(1 == ~T1_E~0); 6084#L372-3 assume !(1 == ~T2_E~0); 6102#L377-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6103#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6124#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6217#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 6133#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6115#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 6116#L547 assume !(0 == start_simulation_~tmp~3#1); 6260#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6455#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 6453#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6452#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 6451#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6450#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6449#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 6447#L560 assume !(0 != start_simulation_~tmp___0~1#1); 6189#L528-2 [2021-12-07 00:26:06,971 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:26:06,971 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 2 times [2021-12-07 00:26:06,971 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:26:06,971 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1296678315] [2021-12-07 00:26:06,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:26:06,971 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:26:06,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:26:06,976 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 00:26:06,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:26:06,985 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 00:26:06,985 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:26:06,985 INFO L85 PathProgramCache]: Analyzing trace with hash 1822427257, now seen corresponding path program 1 times [2021-12-07 00:26:06,986 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:26:06,986 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [124159099] [2021-12-07 00:26:06,986 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:26:06,986 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:26:06,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:26:07,027 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:26:07,028 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:26:07,028 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [124159099] [2021-12-07 00:26:07,028 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [124159099] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:26:07,028 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:26:07,028 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-07 00:26:07,028 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1635989330] [2021-12-07 00:26:07,028 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:26:07,029 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:26:07,029 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:26:07,029 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-07 00:26:07,029 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-07 00:26:07,029 INFO L87 Difference]: Start difference. First operand 434 states and 601 transitions. cyclomatic complexity: 169 Second operand has 5 states, 5 states have (on average 10.8) internal successors, (54), 5 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:26:07,097 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:26:07,097 INFO L93 Difference]: Finished difference Result 953 states and 1311 transitions. [2021-12-07 00:26:07,098 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-07 00:26:07,099 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 953 states and 1311 transitions. [2021-12-07 00:26:07,105 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 909 [2021-12-07 00:26:07,113 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 953 states to 953 states and 1311 transitions. [2021-12-07 00:26:07,113 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 953 [2021-12-07 00:26:07,114 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 953 [2021-12-07 00:26:07,114 INFO L73 IsDeterministic]: Start isDeterministic. Operand 953 states and 1311 transitions. [2021-12-07 00:26:07,116 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:26:07,116 INFO L681 BuchiCegarLoop]: Abstraction has 953 states and 1311 transitions. [2021-12-07 00:26:07,117 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 953 states and 1311 transitions. [2021-12-07 00:26:07,132 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 953 to 455. [2021-12-07 00:26:07,133 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 455 states, 455 states have (on average 1.3604395604395605) internal successors, (619), 454 states have internal predecessors, (619), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:26:07,134 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 455 states to 455 states and 619 transitions. [2021-12-07 00:26:07,135 INFO L704 BuchiCegarLoop]: Abstraction has 455 states and 619 transitions. [2021-12-07 00:26:07,135 INFO L587 BuchiCegarLoop]: Abstraction has 455 states and 619 transitions. [2021-12-07 00:26:07,135 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-07 00:26:07,135 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 455 states and 619 transitions. [2021-12-07 00:26:07,137 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 411 [2021-12-07 00:26:07,137 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:26:07,137 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:26:07,138 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:26:07,138 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:26:07,139 INFO L791 eck$LassoCheckResult]: Stem: 7697#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 7672#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 7477#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7478#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7686#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 7569#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7542#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7543#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7530#L334 assume !(0 == ~M_E~0); 7531#L334-2 assume !(0 == ~T1_E~0); 7625#L339-1 assume !(0 == ~T2_E~0); 7619#L344-1 assume !(0 == ~E_1~0); 7620#L349-1 assume !(0 == ~E_2~0); 7540#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7541#L156 assume !(1 == ~m_pc~0); 7633#L156-2 is_master_triggered_~__retres1~0#1 := 0; 7656#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7645#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 7591#L405 assume !(0 != activate_threads_~tmp~1#1); 7573#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7574#L175 assume !(1 == ~t1_pc~0); 7581#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7575#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7576#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 7627#L413 assume !(0 != activate_threads_~tmp___0~0#1); 7628#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7688#L194 assume !(1 == ~t2_pc~0); 7618#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7585#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7532#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7518#L421 assume !(0 != activate_threads_~tmp___1~0#1); 7519#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7492#L367 assume !(1 == ~M_E~0); 7493#L367-2 assume !(1 == ~T1_E~0); 7649#L372-1 assume !(1 == ~T2_E~0); 7650#L377-1 assume !(1 == ~E_1~0); 7513#L382-1 assume !(1 == ~E_2~0); 7514#L387-1 assume { :end_inline_reset_delta_events } true; 7593#L528-2 [2021-12-07 00:26:07,139 INFO L793 eck$LassoCheckResult]: Loop: 7593#L528-2 assume !false; 7733#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7728#L309 assume !false; 7727#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7725#L244 assume !(0 == ~m_st~0); 7726#L248 assume !(0 == ~t1_st~0); 7723#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 7724#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7719#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7720#L276 assume !(0 != eval_~tmp~0#1); 7848#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7847#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7846#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7845#L334-5 assume !(0 == ~T1_E~0); 7844#L339-3 assume !(0 == ~T2_E~0); 7843#L344-3 assume !(0 == ~E_1~0); 7842#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7528#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7529#L156-9 assume !(1 == ~m_pc~0); 7613#L156-11 is_master_triggered_~__retres1~0#1 := 0; 7800#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7799#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 7798#L405-9 assume !(0 != activate_threads_~tmp~1#1); 7797#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7796#L175-9 assume !(1 == ~t1_pc~0); 7794#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 7792#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7790#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 7788#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7786#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7784#L194-9 assume 1 == ~t2_pc~0; 7781#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7779#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7777#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7775#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7773#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7770#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7768#L367-5 assume !(1 == ~T1_E~0); 7766#L372-3 assume !(1 == ~T2_E~0); 7764#L377-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7762#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7760#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7757#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7754#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7752#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 7750#L547 assume !(0 == start_simulation_~tmp~3#1); 7748#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7746#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7744#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7743#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 7742#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7741#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7740#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 7738#L560 assume !(0 != start_simulation_~tmp___0~1#1); 7593#L528-2 [2021-12-07 00:26:07,139 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:26:07,139 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 3 times [2021-12-07 00:26:07,140 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:26:07,140 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1271851685] [2021-12-07 00:26:07,140 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:26:07,140 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:26:07,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:26:07,147 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 00:26:07,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:26:07,158 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 00:26:07,159 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:26:07,159 INFO L85 PathProgramCache]: Analyzing trace with hash -607385448, now seen corresponding path program 1 times [2021-12-07 00:26:07,159 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:26:07,159 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1683774911] [2021-12-07 00:26:07,159 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:26:07,160 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:26:07,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:26:07,182 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:26:07,182 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:26:07,182 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1683774911] [2021-12-07 00:26:07,183 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1683774911] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:26:07,183 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:26:07,183 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:26:07,183 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1078714334] [2021-12-07 00:26:07,183 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:26:07,183 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-07 00:26:07,183 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:26:07,184 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:26:07,184 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:26:07,184 INFO L87 Difference]: Start difference. First operand 455 states and 619 transitions. cyclomatic complexity: 166 Second operand has 3 states, 3 states have (on average 18.0) internal successors, (54), 3 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:26:07,204 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:26:07,204 INFO L93 Difference]: Finished difference Result 703 states and 944 transitions. [2021-12-07 00:26:07,205 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:26:07,205 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 703 states and 944 transitions. [2021-12-07 00:26:07,210 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 657 [2021-12-07 00:26:07,215 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 703 states to 703 states and 944 transitions. [2021-12-07 00:26:07,215 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 703 [2021-12-07 00:26:07,216 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 703 [2021-12-07 00:26:07,216 INFO L73 IsDeterministic]: Start isDeterministic. Operand 703 states and 944 transitions. [2021-12-07 00:26:07,217 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:26:07,217 INFO L681 BuchiCegarLoop]: Abstraction has 703 states and 944 transitions. [2021-12-07 00:26:07,218 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 703 states and 944 transitions. [2021-12-07 00:26:07,227 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 703 to 668. [2021-12-07 00:26:07,228 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 668 states, 668 states have (on average 1.345808383233533) internal successors, (899), 667 states have internal predecessors, (899), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:26:07,230 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 668 states to 668 states and 899 transitions. [2021-12-07 00:26:07,230 INFO L704 BuchiCegarLoop]: Abstraction has 668 states and 899 transitions. [2021-12-07 00:26:07,230 INFO L587 BuchiCegarLoop]: Abstraction has 668 states and 899 transitions. [2021-12-07 00:26:07,230 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-07 00:26:07,230 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 668 states and 899 transitions. [2021-12-07 00:26:07,232 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 622 [2021-12-07 00:26:07,232 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:26:07,232 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:26:07,233 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:26:07,233 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:26:07,233 INFO L791 eck$LassoCheckResult]: Stem: 8885#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 8842#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 8641#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8642#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8868#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 8736#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8705#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8706#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8693#L334 assume !(0 == ~M_E~0); 8694#L334-2 assume !(0 == ~T1_E~0); 8787#L339-1 assume !(0 == ~T2_E~0); 8781#L344-1 assume !(0 == ~E_1~0); 8782#L349-1 assume !(0 == ~E_2~0); 8703#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8704#L156 assume !(1 == ~m_pc~0); 8794#L156-2 is_master_triggered_~__retres1~0#1 := 0; 8823#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8810#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8757#L405 assume !(0 != activate_threads_~tmp~1#1); 8743#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8744#L175 assume !(1 == ~t1_pc~0); 8748#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8745#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8746#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 8789#L413 assume !(0 != activate_threads_~tmp___0~0#1); 8792#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8871#L194 assume !(1 == ~t2_pc~0); 8780#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8753#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8697#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8682#L421 assume !(0 != activate_threads_~tmp___1~0#1); 8683#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8655#L367 assume !(1 == ~M_E~0); 8656#L367-2 assume !(1 == ~T1_E~0); 8814#L372-1 assume !(1 == ~T2_E~0); 8815#L377-1 assume !(1 == ~E_1~0); 8677#L382-1 assume !(1 == ~E_2~0); 8678#L387-1 assume { :end_inline_reset_delta_events } true; 8758#L528-2 assume !false; 9011#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9003#L309 [2021-12-07 00:26:07,234 INFO L793 eck$LassoCheckResult]: Loop: 9003#L309 assume !false; 8999#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 8995#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 8990#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 8986#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8981#L276 assume 0 != eval_~tmp~0#1; 8976#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 8971#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 8972#L281 assume !(0 == ~t1_st~0); 9010#L295 assume !(0 == ~t2_st~0); 9003#L309 [2021-12-07 00:26:07,234 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:26:07,234 INFO L85 PathProgramCache]: Analyzing trace with hash -985920349, now seen corresponding path program 1 times [2021-12-07 00:26:07,234 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:26:07,234 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [959606184] [2021-12-07 00:26:07,234 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:26:07,235 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:26:07,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:26:07,241 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 00:26:07,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:26:07,253 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 00:26:07,254 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:26:07,254 INFO L85 PathProgramCache]: Analyzing trace with hash 1417539670, now seen corresponding path program 1 times [2021-12-07 00:26:07,254 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:26:07,254 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1554549782] [2021-12-07 00:26:07,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:26:07,254 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:26:07,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:26:07,257 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 00:26:07,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:26:07,261 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 00:26:07,261 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:26:07,262 INFO L85 PathProgramCache]: Analyzing trace with hash -1345054088, now seen corresponding path program 1 times [2021-12-07 00:26:07,262 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:26:07,262 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1150655171] [2021-12-07 00:26:07,262 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:26:07,262 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:26:07,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:26:07,284 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:26:07,284 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:26:07,284 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1150655171] [2021-12-07 00:26:07,284 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1150655171] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:26:07,284 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:26:07,285 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:26:07,285 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1869623258] [2021-12-07 00:26:07,285 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:26:07,327 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:26:07,327 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:26:07,327 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:26:07,327 INFO L87 Difference]: Start difference. First operand 668 states and 899 transitions. cyclomatic complexity: 234 Second operand has 3 states, 3 states have (on average 16.666666666666668) internal successors, (50), 3 states have internal predecessors, (50), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:26:07,351 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:26:07,351 INFO L93 Difference]: Finished difference Result 1183 states and 1572 transitions. [2021-12-07 00:26:07,351 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:26:07,351 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1183 states and 1572 transitions. [2021-12-07 00:26:07,357 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 1041 [2021-12-07 00:26:07,363 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1183 states to 1183 states and 1572 transitions. [2021-12-07 00:26:07,363 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1183 [2021-12-07 00:26:07,364 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1183 [2021-12-07 00:26:07,364 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1183 states and 1572 transitions. [2021-12-07 00:26:07,366 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:26:07,366 INFO L681 BuchiCegarLoop]: Abstraction has 1183 states and 1572 transitions. [2021-12-07 00:26:07,367 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1183 states and 1572 transitions. [2021-12-07 00:26:07,377 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1183 to 1109. [2021-12-07 00:26:07,379 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1109 states, 1109 states have (on average 1.3345356176735799) internal successors, (1480), 1108 states have internal predecessors, (1480), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:26:07,382 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1109 states to 1109 states and 1480 transitions. [2021-12-07 00:26:07,382 INFO L704 BuchiCegarLoop]: Abstraction has 1109 states and 1480 transitions. [2021-12-07 00:26:07,382 INFO L587 BuchiCegarLoop]: Abstraction has 1109 states and 1480 transitions. [2021-12-07 00:26:07,382 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-07 00:26:07,382 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1109 states and 1480 transitions. [2021-12-07 00:26:07,386 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1002 [2021-12-07 00:26:07,386 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:26:07,386 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:26:07,387 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:26:07,387 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:26:07,387 INFO L791 eck$LassoCheckResult]: Stem: 10762#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 10708#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 10500#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10501#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10736#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 10593#L221-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 10594#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10712#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10551#L334 assume !(0 == ~M_E~0); 10552#L334-2 assume !(0 == ~T1_E~0); 11520#L339-1 assume !(0 == ~T2_E~0); 10649#L344-1 assume !(0 == ~E_1~0); 10650#L349-1 assume !(0 == ~E_2~0); 10693#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11518#L156 assume !(1 == ~m_pc~0); 10707#L156-2 is_master_triggered_~__retres1~0#1 := 0; 10687#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10674#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10675#L405 assume !(0 != activate_threads_~tmp~1#1); 11515#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11514#L175 assume !(1 == ~t1_pc~0); 11513#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11512#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11511#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 11510#L413 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10659#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10745#L194 assume !(1 == ~t2_pc~0); 10648#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10611#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10553#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10540#L421 assume !(0 != activate_threads_~tmp___1~0#1); 10541#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10514#L367 assume !(1 == ~M_E~0); 10515#L367-2 assume !(1 == ~T1_E~0); 11473#L372-1 assume !(1 == ~T2_E~0); 11470#L377-1 assume !(1 == ~E_1~0); 10535#L382-1 assume !(1 == ~E_2~0); 10536#L387-1 assume { :end_inline_reset_delta_events } true; 11469#L528-2 assume !false; 11467#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11461#L309 [2021-12-07 00:26:07,387 INFO L793 eck$LassoCheckResult]: Loop: 11461#L309 assume !false; 11459#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 11457#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 11456#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 11455#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 10860#L276 assume 0 != eval_~tmp~0#1; 10861#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 10849#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 10851#L281 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 11468#L298 assume !(0 != eval_~tmp_ndt_2~0#1); 11466#L295 assume !(0 == ~t2_st~0); 11461#L309 [2021-12-07 00:26:07,387 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:26:07,387 INFO L85 PathProgramCache]: Analyzing trace with hash -808857497, now seen corresponding path program 1 times [2021-12-07 00:26:07,388 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:26:07,388 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [10521445] [2021-12-07 00:26:07,388 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:26:07,388 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:26:07,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:26:07,399 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:26:07,399 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:26:07,399 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [10521445] [2021-12-07 00:26:07,399 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [10521445] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:26:07,399 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:26:07,399 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-07 00:26:07,399 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2084358939] [2021-12-07 00:26:07,399 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:26:07,400 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-07 00:26:07,400 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:26:07,400 INFO L85 PathProgramCache]: Analyzing trace with hash 993952052, now seen corresponding path program 1 times [2021-12-07 00:26:07,400 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:26:07,400 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1994058522] [2021-12-07 00:26:07,400 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:26:07,400 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:26:07,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:26:07,403 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 00:26:07,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:26:07,406 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 00:26:07,452 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:26:07,452 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:26:07,452 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:26:07,452 INFO L87 Difference]: Start difference. First operand 1109 states and 1480 transitions. cyclomatic complexity: 375 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:26:07,458 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:26:07,459 INFO L93 Difference]: Finished difference Result 935 states and 1252 transitions. [2021-12-07 00:26:07,459 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:26:07,459 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 935 states and 1252 transitions. [2021-12-07 00:26:07,472 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 889 [2021-12-07 00:26:07,476 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 935 states to 935 states and 1252 transitions. [2021-12-07 00:26:07,477 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 935 [2021-12-07 00:26:07,477 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 935 [2021-12-07 00:26:07,477 INFO L73 IsDeterministic]: Start isDeterministic. Operand 935 states and 1252 transitions. [2021-12-07 00:26:07,478 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:26:07,478 INFO L681 BuchiCegarLoop]: Abstraction has 935 states and 1252 transitions. [2021-12-07 00:26:07,479 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 935 states and 1252 transitions. [2021-12-07 00:26:07,488 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 935 to 935. [2021-12-07 00:26:07,489 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 935 states, 935 states have (on average 1.3390374331550803) internal successors, (1252), 934 states have internal predecessors, (1252), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:26:07,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 935 states to 935 states and 1252 transitions. [2021-12-07 00:26:07,491 INFO L704 BuchiCegarLoop]: Abstraction has 935 states and 1252 transitions. [2021-12-07 00:26:07,491 INFO L587 BuchiCegarLoop]: Abstraction has 935 states and 1252 transitions. [2021-12-07 00:26:07,491 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-07 00:26:07,492 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 935 states and 1252 transitions. [2021-12-07 00:26:07,495 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 889 [2021-12-07 00:26:07,495 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:26:07,495 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:26:07,495 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:26:07,495 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:26:07,495 INFO L791 eck$LassoCheckResult]: Stem: 12775#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 12739#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 12550#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12551#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12763#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 12641#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12613#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12614#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12601#L334 assume !(0 == ~M_E~0); 12602#L334-2 assume !(0 == ~T1_E~0); 12698#L339-1 assume !(0 == ~T2_E~0); 12692#L344-1 assume !(0 == ~E_1~0); 12693#L349-1 assume !(0 == ~E_2~0); 12611#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12612#L156 assume !(1 == ~m_pc~0); 12705#L156-2 is_master_triggered_~__retres1~0#1 := 0; 12726#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12714#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 12663#L405 assume !(0 != activate_threads_~tmp~1#1); 12646#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12647#L175 assume !(1 == ~t1_pc~0); 12654#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12648#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12649#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 12700#L413 assume !(0 != activate_threads_~tmp___0~0#1); 12701#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12767#L194 assume !(1 == ~t2_pc~0); 12691#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12658#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12603#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 12590#L421 assume !(0 != activate_threads_~tmp___1~0#1); 12591#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12564#L367 assume !(1 == ~M_E~0); 12565#L367-2 assume !(1 == ~T1_E~0); 12718#L372-1 assume !(1 == ~T2_E~0); 12719#L377-1 assume !(1 == ~E_1~0); 12585#L382-1 assume !(1 == ~E_2~0); 12586#L387-1 assume { :end_inline_reset_delta_events } true; 12666#L528-2 assume !false; 12858#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12853#L309 [2021-12-07 00:26:07,495 INFO L793 eck$LassoCheckResult]: Loop: 12853#L309 assume !false; 12852#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 12851#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 12850#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 12849#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12848#L276 assume 0 != eval_~tmp~0#1; 12847#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 12845#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 12846#L281 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 12860#L298 assume !(0 != eval_~tmp_ndt_2~0#1); 12857#L295 assume !(0 == ~t2_st~0); 12853#L309 [2021-12-07 00:26:07,496 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:26:07,496 INFO L85 PathProgramCache]: Analyzing trace with hash -985920349, now seen corresponding path program 2 times [2021-12-07 00:26:07,496 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:26:07,496 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1023240081] [2021-12-07 00:26:07,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:26:07,496 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:26:07,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:26:07,500 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 00:26:07,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:26:07,508 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 00:26:07,508 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:26:07,509 INFO L85 PathProgramCache]: Analyzing trace with hash 993952052, now seen corresponding path program 2 times [2021-12-07 00:26:07,509 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:26:07,509 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [337980767] [2021-12-07 00:26:07,509 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:26:07,509 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:26:07,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:26:07,511 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 00:26:07,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:26:07,514 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 00:26:07,514 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:26:07,514 INFO L85 PathProgramCache]: Analyzing trace with hash 1252891474, now seen corresponding path program 1 times [2021-12-07 00:26:07,514 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:26:07,515 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1907976719] [2021-12-07 00:26:07,515 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:26:07,515 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:26:07,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-07 00:26:07,530 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-07 00:26:07,530 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-07 00:26:07,530 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1907976719] [2021-12-07 00:26:07,530 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1907976719] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-07 00:26:07,530 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-07 00:26:07,530 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-07 00:26:07,530 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [74230300] [2021-12-07 00:26:07,530 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-07 00:26:07,578 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-07 00:26:07,578 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-07 00:26:07,579 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-07 00:26:07,579 INFO L87 Difference]: Start difference. First operand 935 states and 1252 transitions. cyclomatic complexity: 319 Second operand has 3 states, 2 states have (on average 25.5) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:26:07,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-07 00:26:07,608 INFO L93 Difference]: Finished difference Result 1647 states and 2195 transitions. [2021-12-07 00:26:07,608 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-07 00:26:07,609 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1647 states and 2195 transitions. [2021-12-07 00:26:07,619 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1596 [2021-12-07 00:26:07,628 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1647 states to 1647 states and 2195 transitions. [2021-12-07 00:26:07,628 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1647 [2021-12-07 00:26:07,629 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1647 [2021-12-07 00:26:07,629 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1647 states and 2195 transitions. [2021-12-07 00:26:07,631 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-07 00:26:07,631 INFO L681 BuchiCegarLoop]: Abstraction has 1647 states and 2195 transitions. [2021-12-07 00:26:07,632 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1647 states and 2195 transitions. [2021-12-07 00:26:07,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1647 to 1647. [2021-12-07 00:26:07,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1647 states, 1647 states have (on average 1.3327261687917427) internal successors, (2195), 1646 states have internal predecessors, (2195), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-07 00:26:07,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1647 states to 1647 states and 2195 transitions. [2021-12-07 00:26:07,654 INFO L704 BuchiCegarLoop]: Abstraction has 1647 states and 2195 transitions. [2021-12-07 00:26:07,654 INFO L587 BuchiCegarLoop]: Abstraction has 1647 states and 2195 transitions. [2021-12-07 00:26:07,654 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-07 00:26:07,654 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1647 states and 2195 transitions. [2021-12-07 00:26:07,660 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1596 [2021-12-07 00:26:07,660 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-07 00:26:07,660 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-07 00:26:07,660 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:26:07,660 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-07 00:26:07,660 INFO L791 eck$LassoCheckResult]: Stem: 15381#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 15347#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 15140#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15141#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15365#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 15233#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15203#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15204#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15191#L334 assume !(0 == ~M_E~0); 15192#L334-2 assume !(0 == ~T1_E~0); 15295#L339-1 assume !(0 == ~T2_E~0); 15288#L344-1 assume !(0 == ~E_1~0); 15289#L349-1 assume !(0 == ~E_2~0); 15201#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15202#L156 assume !(1 == ~m_pc~0); 15303#L156-2 is_master_triggered_~__retres1~0#1 := 0; 15327#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15315#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 15256#L405 assume !(0 != activate_threads_~tmp~1#1); 15238#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15239#L175 assume !(1 == ~t1_pc~0); 15247#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15240#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15241#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 15297#L413 assume !(0 != activate_threads_~tmp___0~0#1); 15298#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15369#L194 assume !(1 == ~t2_pc~0); 15286#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15251#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15193#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 15180#L421 assume !(0 != activate_threads_~tmp___1~0#1); 15181#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15154#L367 assume !(1 == ~M_E~0); 15155#L367-2 assume !(1 == ~T1_E~0); 15319#L372-1 assume !(1 == ~T2_E~0); 15320#L377-1 assume !(1 == ~E_1~0); 15175#L382-1 assume !(1 == ~E_2~0); 15176#L387-1 assume { :end_inline_reset_delta_events } true; 15259#L528-2 assume !false; 16516#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16513#L309 [2021-12-07 00:26:07,661 INFO L793 eck$LassoCheckResult]: Loop: 16513#L309 assume !false; 16511#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 16509#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 16505#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 16500#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16497#L276 assume 0 != eval_~tmp~0#1; 16495#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 16490#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 16491#L281 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 16523#L298 assume !(0 != eval_~tmp_ndt_2~0#1); 16521#L295 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 16515#L312 assume !(0 != eval_~tmp_ndt_3~0#1); 16513#L309 [2021-12-07 00:26:07,661 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:26:07,661 INFO L85 PathProgramCache]: Analyzing trace with hash -985920349, now seen corresponding path program 3 times [2021-12-07 00:26:07,661 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:26:07,661 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2026483751] [2021-12-07 00:26:07,661 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:26:07,661 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:26:07,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:26:07,666 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 00:26:07,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:26:07,672 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 00:26:07,673 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:26:07,673 INFO L85 PathProgramCache]: Analyzing trace with hash 747741784, now seen corresponding path program 1 times [2021-12-07 00:26:07,673 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:26:07,673 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2059476777] [2021-12-07 00:26:07,673 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:26:07,673 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:26:07,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:26:07,675 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 00:26:07,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:26:07,678 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 00:26:07,678 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-07 00:26:07,679 INFO L85 PathProgramCache]: Analyzing trace with hash 184929274, now seen corresponding path program 1 times [2021-12-07 00:26:07,679 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-07 00:26:07,679 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1250772848] [2021-12-07 00:26:07,679 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-07 00:26:07,679 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-07 00:26:07,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:26:07,684 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-07 00:26:07,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-07 00:26:07,691 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-07 00:26:08,165 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 07.12 12:26:08 BoogieIcfgContainer [2021-12-07 00:26:08,165 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-12-07 00:26:08,165 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-12-07 00:26:08,165 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-12-07 00:26:08,165 INFO L275 PluginConnector]: Witness Printer initialized [2021-12-07 00:26:08,166 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.12 12:26:05" (3/4) ... [2021-12-07 00:26:08,168 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-12-07 00:26:08,211 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66751a00-5c53-4330-b56f-b5f6ba4bb390/bin/uautomizer-DrprNOufMa/witness.graphml [2021-12-07 00:26:08,211 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-12-07 00:26:08,211 INFO L158 Benchmark]: Toolchain (without parser) took 3156.41ms. Allocated memory was 104.9MB in the beginning and 151.0MB in the end (delta: 46.1MB). Free memory was 78.8MB in the beginning and 73.5MB in the end (delta: 5.3MB). Peak memory consumption was 51.8MB. Max. memory is 16.1GB. [2021-12-07 00:26:08,212 INFO L158 Benchmark]: CDTParser took 0.13ms. Allocated memory is still 77.6MB. Free memory was 53.3MB in the beginning and 53.2MB in the end (delta: 49.5kB). There was no memory consumed. Max. memory is 16.1GB. [2021-12-07 00:26:08,212 INFO L158 Benchmark]: CACSL2BoogieTranslator took 212.69ms. Allocated memory is still 104.9MB. Free memory was 78.8MB in the beginning and 76.6MB in the end (delta: 2.2MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2021-12-07 00:26:08,212 INFO L158 Benchmark]: Boogie Procedure Inliner took 37.47ms. Allocated memory is still 104.9MB. Free memory was 76.3MB in the beginning and 73.6MB in the end (delta: 2.7MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-12-07 00:26:08,212 INFO L158 Benchmark]: Boogie Preprocessor took 28.18ms. Allocated memory is still 104.9MB. Free memory was 73.6MB in the beginning and 71.3MB in the end (delta: 2.3MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-12-07 00:26:08,213 INFO L158 Benchmark]: RCFGBuilder took 470.19ms. Allocated memory is still 104.9MB. Free memory was 71.3MB in the beginning and 80.8MB in the end (delta: -9.5MB). Peak memory consumption was 29.7MB. Max. memory is 16.1GB. [2021-12-07 00:26:08,213 INFO L158 Benchmark]: BuchiAutomizer took 2358.18ms. Allocated memory was 104.9MB in the beginning and 151.0MB in the end (delta: 46.1MB). Free memory was 80.3MB in the beginning and 77.6MB in the end (delta: 2.7MB). Peak memory consumption was 69.6MB. Max. memory is 16.1GB. [2021-12-07 00:26:08,213 INFO L158 Benchmark]: Witness Printer took 45.64ms. Allocated memory is still 151.0MB. Free memory was 76.7MB in the beginning and 73.5MB in the end (delta: 3.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-07 00:26:08,215 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.13ms. Allocated memory is still 77.6MB. Free memory was 53.3MB in the beginning and 53.2MB in the end (delta: 49.5kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 212.69ms. Allocated memory is still 104.9MB. Free memory was 78.8MB in the beginning and 76.6MB in the end (delta: 2.2MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 37.47ms. Allocated memory is still 104.9MB. Free memory was 76.3MB in the beginning and 73.6MB in the end (delta: 2.7MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 28.18ms. Allocated memory is still 104.9MB. Free memory was 73.6MB in the beginning and 71.3MB in the end (delta: 2.3MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 470.19ms. Allocated memory is still 104.9MB. Free memory was 71.3MB in the beginning and 80.8MB in the end (delta: -9.5MB). Peak memory consumption was 29.7MB. Max. memory is 16.1GB. * BuchiAutomizer took 2358.18ms. Allocated memory was 104.9MB in the beginning and 151.0MB in the end (delta: 46.1MB). Free memory was 80.3MB in the beginning and 77.6MB in the end (delta: 2.7MB). Peak memory consumption was 69.6MB. Max. memory is 16.1GB. * Witness Printer took 45.64ms. Allocated memory is still 151.0MB. Free memory was 76.7MB in the beginning and 73.5MB in the end (delta: 3.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 12 terminating modules (12 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.12 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 1647 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 2.3s and 13 iterations. TraceHistogramMax:1. Analysis of lassos took 1.3s. Construction of modules took 0.1s. Büchi inclusion checks took 0.2s. Highest rank in rank-based complementation 0. Minimization of det autom 12. Minimization of nondet autom 0. Automata minimization 0.2s AutomataMinimizationTime, 12 MinimizatonAttempts, 1281 StatesRemovedByMinimization, 7 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had 1647 states and ocurred in iteration 12. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 4248 SdHoareTripleChecker+Valid, 0.2s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 4248 mSDsluCounter, 6812 SdHoareTripleChecker+Invalid, 0.2s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 3242 mSDsCounter, 107 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 286 IncrementalHoareTripleChecker+Invalid, 393 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 107 mSolverCounterUnsat, 3570 mSDtfsCounter, 286 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc2 concLT0 SILN1 SILU0 SILI6 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 271]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {tmp_ndt_3=0, NULL=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6aba82ee=0, NULL=1, \result=0, tmp=0, \result=0, __retres1=0, tmp___1=0, T2_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5f963dd4=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3e28d43=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@636ffdf8=0, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@95512d1=0, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2936f69a=0, t1_pc=0, tmp_ndt_2=0, E_2=2, tmp___0=0, T1_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7139dbd0=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@57ecaad0=0, E_1=2, __retres1=0, M_E=2, __retres1=1, tmp_ndt_1=0, t2_i=1, tmp=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@565992be=0, \result=0, m_i=1, t1_st=0, __retres1=0, t2_pc=0, m_st=0, NULL=0, kernel_st=1, __retres1=0, tmp___0=0, t1_i=1, m_pc=0, \result=0, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 271]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int m_i ; [L32] int t1_i ; [L33] int t2_i ; [L34] int M_E = 2; [L35] int T1_E = 2; [L36] int T2_E = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; [L573] int __retres1 ; [L577] CALL init_model() [L487] m_i = 1 [L488] t1_i = 1 [L489] t2_i = 1 [L577] RET init_model() [L578] CALL start_simulation() [L514] int kernel_st ; [L515] int tmp ; [L516] int tmp___0 ; [L520] kernel_st = 0 [L521] FCALL update_channels() [L522] CALL init_threads() [L221] COND TRUE m_i == 1 [L222] m_st = 0 [L226] COND TRUE t1_i == 1 [L227] t1_st = 0 [L231] COND TRUE t2_i == 1 [L232] t2_st = 0 [L522] RET init_threads() [L523] CALL fire_delta_events() [L334] COND FALSE !(M_E == 0) [L339] COND FALSE !(T1_E == 0) [L344] COND FALSE !(T2_E == 0) [L349] COND FALSE !(E_1 == 0) [L354] COND FALSE !(E_2 == 0) [L523] RET fire_delta_events() [L524] CALL activate_threads() [L397] int tmp ; [L398] int tmp___0 ; [L399] int tmp___1 ; [L403] CALL, EXPR is_master_triggered() [L153] int __retres1 ; [L156] COND FALSE !(m_pc == 1) [L166] __retres1 = 0 [L168] return (__retres1); [L403] RET, EXPR is_master_triggered() [L403] tmp = is_master_triggered() [L405] COND FALSE !(\read(tmp)) [L411] CALL, EXPR is_transmit1_triggered() [L172] int __retres1 ; [L175] COND FALSE !(t1_pc == 1) [L185] __retres1 = 0 [L187] return (__retres1); [L411] RET, EXPR is_transmit1_triggered() [L411] tmp___0 = is_transmit1_triggered() [L413] COND FALSE !(\read(tmp___0)) [L419] CALL, EXPR is_transmit2_triggered() [L191] int __retres1 ; [L194] COND FALSE !(t2_pc == 1) [L204] __retres1 = 0 [L206] return (__retres1); [L419] RET, EXPR is_transmit2_triggered() [L419] tmp___1 = is_transmit2_triggered() [L421] COND FALSE !(\read(tmp___1)) [L524] RET activate_threads() [L525] CALL reset_delta_events() [L367] COND FALSE !(M_E == 1) [L372] COND FALSE !(T1_E == 1) [L377] COND FALSE !(T2_E == 1) [L382] COND FALSE !(E_1 == 1) [L387] COND FALSE !(E_2 == 1) [L525] RET reset_delta_events() [L528] COND TRUE 1 [L531] kernel_st = 1 [L532] CALL eval() [L267] int tmp ; Loop: [L271] COND TRUE 1 [L274] CALL, EXPR exists_runnable_thread() [L241] int __retres1 ; [L244] COND TRUE m_st == 0 [L245] __retres1 = 1 [L262] return (__retres1); [L274] RET, EXPR exists_runnable_thread() [L274] tmp = exists_runnable_thread() [L276] COND TRUE \read(tmp) [L281] COND TRUE m_st == 0 [L282] int tmp_ndt_1; [L283] tmp_ndt_1 = __VERIFIER_nondet_int() [L284] COND FALSE !(\read(tmp_ndt_1)) [L295] COND TRUE t1_st == 0 [L296] int tmp_ndt_2; [L297] tmp_ndt_2 = __VERIFIER_nondet_int() [L298] COND FALSE !(\read(tmp_ndt_2)) [L309] COND TRUE t2_st == 0 [L310] int tmp_ndt_3; [L311] tmp_ndt_3 = __VERIFIER_nondet_int() [L312] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-12-07 00:26:08,262 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_66751a00-5c53-4330-b56f-b5f6ba4bb390/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)