./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.04.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 839c364b Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8319a0d-1f41-44fc-88b4-21d0b049ce17/bin/uautomizer-DrprNOufMa/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8319a0d-1f41-44fc-88b4-21d0b049ce17/bin/uautomizer-DrprNOufMa/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8319a0d-1f41-44fc-88b4-21d0b049ce17/bin/uautomizer-DrprNOufMa/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8319a0d-1f41-44fc-88b4-21d0b049ce17/bin/uautomizer-DrprNOufMa/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.04.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8319a0d-1f41-44fc-88b4-21d0b049ce17/bin/uautomizer-DrprNOufMa/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8319a0d-1f41-44fc-88b4-21d0b049ce17/bin/uautomizer-DrprNOufMa --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 1de07d37d630bd073064bf436fb9512b72ab982b0eaf3fcb1582f689c57482fa --- Real Ultimate output --- This is Ultimate 0.2.2-hotfix-svcomp22-839c364 [2021-12-06 19:59:28,695 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-06 19:59:28,697 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-06 19:59:28,726 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-06 19:59:28,727 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-06 19:59:28,728 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-06 19:59:28,729 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-06 19:59:28,732 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-06 19:59:28,734 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-06 19:59:28,734 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-06 19:59:28,736 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-06 19:59:28,737 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-06 19:59:28,737 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-06 19:59:28,738 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-06 19:59:28,740 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-06 19:59:28,741 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-06 19:59:28,742 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-06 19:59:28,743 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-06 19:59:28,745 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-06 19:59:28,747 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-06 19:59:28,749 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-06 19:59:28,751 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-06 19:59:28,752 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-06 19:59:28,753 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-06 19:59:28,756 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-06 19:59:28,756 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-06 19:59:28,757 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-06 19:59:28,758 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-06 19:59:28,758 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-06 19:59:28,759 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-06 19:59:28,760 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-06 19:59:28,760 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-06 19:59:28,761 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-06 19:59:28,762 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-06 19:59:28,763 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-06 19:59:28,763 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-06 19:59:28,764 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-06 19:59:28,764 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-06 19:59:28,764 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-06 19:59:28,765 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-06 19:59:28,765 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-06 19:59:28,766 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8319a0d-1f41-44fc-88b4-21d0b049ce17/bin/uautomizer-DrprNOufMa/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-06 19:59:28,783 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-06 19:59:28,784 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-06 19:59:28,784 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-06 19:59:28,784 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-06 19:59:28,785 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-06 19:59:28,785 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-06 19:59:28,785 INFO L138 SettingsManager]: * Use SBE=true [2021-12-06 19:59:28,785 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-06 19:59:28,785 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-06 19:59:28,785 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-06 19:59:28,786 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-06 19:59:28,786 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-06 19:59:28,786 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-06 19:59:28,786 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-06 19:59:28,786 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-06 19:59:28,786 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-06 19:59:28,786 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-06 19:59:28,786 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-06 19:59:28,787 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-06 19:59:28,787 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-06 19:59:28,787 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-06 19:59:28,787 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-06 19:59:28,787 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-06 19:59:28,787 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-06 19:59:28,787 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-06 19:59:28,787 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-06 19:59:28,787 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-06 19:59:28,788 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-06 19:59:28,788 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-06 19:59:28,788 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-06 19:59:28,788 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-06 19:59:28,788 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-06 19:59:28,789 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-06 19:59:28,789 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8319a0d-1f41-44fc-88b4-21d0b049ce17/bin/uautomizer-DrprNOufMa/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8319a0d-1f41-44fc-88b4-21d0b049ce17/bin/uautomizer-DrprNOufMa Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1de07d37d630bd073064bf436fb9512b72ab982b0eaf3fcb1582f689c57482fa [2021-12-06 19:59:28,963 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-06 19:59:28,979 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-06 19:59:28,980 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-06 19:59:28,981 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-06 19:59:28,982 INFO L275 PluginConnector]: CDTParser initialized [2021-12-06 19:59:28,983 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8319a0d-1f41-44fc-88b4-21d0b049ce17/bin/uautomizer-DrprNOufMa/../../sv-benchmarks/c/systemc/transmitter.04.cil.c [2021-12-06 19:59:29,030 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8319a0d-1f41-44fc-88b4-21d0b049ce17/bin/uautomizer-DrprNOufMa/data/5bf4333b3/29a6bd62c7ea423581103fb7897738a8/FLAG157cf543d [2021-12-06 19:59:29,424 INFO L306 CDTParser]: Found 1 translation units. [2021-12-06 19:59:29,425 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8319a0d-1f41-44fc-88b4-21d0b049ce17/sv-benchmarks/c/systemc/transmitter.04.cil.c [2021-12-06 19:59:29,435 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8319a0d-1f41-44fc-88b4-21d0b049ce17/bin/uautomizer-DrprNOufMa/data/5bf4333b3/29a6bd62c7ea423581103fb7897738a8/FLAG157cf543d [2021-12-06 19:59:29,445 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8319a0d-1f41-44fc-88b4-21d0b049ce17/bin/uautomizer-DrprNOufMa/data/5bf4333b3/29a6bd62c7ea423581103fb7897738a8 [2021-12-06 19:59:29,448 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-06 19:59:29,449 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-06 19:59:29,450 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-06 19:59:29,450 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-06 19:59:29,453 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-06 19:59:29,453 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 07:59:29" (1/1) ... [2021-12-06 19:59:29,454 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@746ac5e7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:59:29, skipping insertion in model container [2021-12-06 19:59:29,454 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 07:59:29" (1/1) ... [2021-12-06 19:59:29,459 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-06 19:59:29,483 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-06 19:59:29,610 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8319a0d-1f41-44fc-88b4-21d0b049ce17/sv-benchmarks/c/systemc/transmitter.04.cil.c[706,719] [2021-12-06 19:59:29,667 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-06 19:59:29,675 INFO L203 MainTranslator]: Completed pre-run [2021-12-06 19:59:29,683 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8319a0d-1f41-44fc-88b4-21d0b049ce17/sv-benchmarks/c/systemc/transmitter.04.cil.c[706,719] [2021-12-06 19:59:29,708 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-06 19:59:29,720 INFO L208 MainTranslator]: Completed translation [2021-12-06 19:59:29,720 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:59:29 WrapperNode [2021-12-06 19:59:29,720 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-06 19:59:29,721 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-06 19:59:29,721 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-06 19:59:29,721 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-06 19:59:29,726 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:59:29" (1/1) ... [2021-12-06 19:59:29,733 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:59:29" (1/1) ... [2021-12-06 19:59:29,763 INFO L137 Inliner]: procedures = 36, calls = 42, calls flagged for inlining = 37, calls inlined = 70, statements flattened = 966 [2021-12-06 19:59:29,764 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-06 19:59:29,764 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-06 19:59:29,764 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-06 19:59:29,764 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-06 19:59:29,771 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:59:29" (1/1) ... [2021-12-06 19:59:29,771 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:59:29" (1/1) ... [2021-12-06 19:59:29,776 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:59:29" (1/1) ... [2021-12-06 19:59:29,776 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:59:29" (1/1) ... [2021-12-06 19:59:29,788 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:59:29" (1/1) ... [2021-12-06 19:59:29,800 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:59:29" (1/1) ... [2021-12-06 19:59:29,802 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:59:29" (1/1) ... [2021-12-06 19:59:29,807 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-06 19:59:29,808 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-06 19:59:29,808 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-06 19:59:29,808 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-06 19:59:29,809 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:59:29" (1/1) ... [2021-12-06 19:59:29,816 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 19:59:29,826 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8319a0d-1f41-44fc-88b4-21d0b049ce17/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 19:59:29,837 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8319a0d-1f41-44fc-88b4-21d0b049ce17/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 19:59:29,840 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8319a0d-1f41-44fc-88b4-21d0b049ce17/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-06 19:59:29,877 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-06 19:59:29,877 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-06 19:59:29,877 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-06 19:59:29,877 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-06 19:59:29,946 INFO L236 CfgBuilder]: Building ICFG [2021-12-06 19:59:29,948 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-06 19:59:30,461 INFO L277 CfgBuilder]: Performing block encoding [2021-12-06 19:59:30,470 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-06 19:59:30,471 INFO L301 CfgBuilder]: Removed 8 assume(true) statements. [2021-12-06 19:59:30,473 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 07:59:30 BoogieIcfgContainer [2021-12-06 19:59:30,473 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-06 19:59:30,474 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-06 19:59:30,474 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-06 19:59:30,476 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-06 19:59:30,477 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 19:59:30,477 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.12 07:59:29" (1/3) ... [2021-12-06 19:59:30,478 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@59655f28 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.12 07:59:30, skipping insertion in model container [2021-12-06 19:59:30,478 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 19:59:30,478 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:59:29" (2/3) ... [2021-12-06 19:59:30,479 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@59655f28 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.12 07:59:30, skipping insertion in model container [2021-12-06 19:59:30,479 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 19:59:30,479 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 07:59:30" (3/3) ... [2021-12-06 19:59:30,480 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.04.cil.c [2021-12-06 19:59:30,517 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-06 19:59:30,517 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-06 19:59:30,518 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-06 19:59:30,518 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-06 19:59:30,518 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-06 19:59:30,518 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-06 19:59:30,518 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-06 19:59:30,518 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-06 19:59:30,553 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 391 states, 390 states have (on average 1.5384615384615385) internal successors, (600), 390 states have internal predecessors, (600), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:30,582 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 322 [2021-12-06 19:59:30,583 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:59:30,583 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:59:30,591 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:30,591 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:30,591 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-06 19:59:30,593 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 391 states, 390 states have (on average 1.5384615384615385) internal successors, (600), 390 states have internal predecessors, (600), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:30,602 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 322 [2021-12-06 19:59:30,602 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:59:30,602 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:59:30,605 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:30,605 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:30,612 INFO L791 eck$LassoCheckResult]: Stem: 381#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 327#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 191#L739true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29#L334true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 55#L341true assume !(1 == ~m_i~0);~m_st~0 := 2; 364#L341-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 212#L346-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 117#L351-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 24#L356-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 108#L361-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32#L502true assume !(0 == ~M_E~0); 83#L502-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 18#L507-1true assume !(0 == ~T2_E~0); 56#L512-1true assume !(0 == ~T3_E~0); 314#L517-1true assume !(0 == ~T4_E~0); 12#L522-1true assume !(0 == ~E_1~0); 277#L527-1true assume !(0 == ~E_2~0); 121#L532-1true assume !(0 == ~E_3~0); 358#L537-1true assume !(0 == ~E_4~0); 136#L542-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 115#L238true assume 1 == ~m_pc~0; 320#L239true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 195#L249true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 159#L250true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 101#L615true assume !(0 != activate_threads_~tmp~1#1); 200#L615-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 89#L257true assume 1 == ~t1_pc~0; 323#L258true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 112#L268true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44#L269true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 193#L623true assume !(0 != activate_threads_~tmp___0~0#1); 25#L623-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 192#L276true assume !(1 == ~t2_pc~0); 279#L276-2true is_transmit2_triggered_~__retres1~2#1 := 0; 337#L287true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 214#L288true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 340#L631true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 356#L631-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 99#L295true assume 1 == ~t3_pc~0; 38#L296true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 92#L306true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 149#L307true activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 325#L639true assume !(0 != activate_threads_~tmp___2~0#1); 318#L639-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 372#L314true assume !(1 == ~t4_pc~0); 345#L314-2true is_transmit4_triggered_~__retres1~4#1 := 0; 142#L325true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 321#L326true activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 88#L647true assume !(0 != activate_threads_~tmp___3~0#1); 273#L647-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 386#L555true assume !(1 == ~M_E~0); 40#L555-2true assume !(1 == ~T1_E~0); 366#L560-1true assume !(1 == ~T2_E~0); 13#L565-1true assume !(1 == ~T3_E~0); 94#L570-1true assume !(1 == ~T4_E~0); 222#L575-1true assume !(1 == ~E_1~0); 292#L580-1true assume !(1 == ~E_2~0); 130#L585-1true assume 1 == ~E_3~0;~E_3~0 := 2; 31#L590-1true assume !(1 == ~E_4~0); 28#L595-1true assume { :end_inline_reset_delta_events } true; 179#L776-2true [2021-12-06 19:59:30,613 INFO L793 eck$LassoCheckResult]: Loop: 179#L776-2true assume !false; 20#L777true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 118#L477true assume !true; 379#L492true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 124#L334-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 75#L502-3true assume !(0 == ~M_E~0); 300#L502-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 312#L507-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 53#L512-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 392#L517-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 50#L522-3true assume 0 == ~E_1~0;~E_1~0 := 1; 90#L527-3true assume 0 == ~E_2~0;~E_2~0 := 1; 140#L532-3true assume 0 == ~E_3~0;~E_3~0 := 1; 264#L537-3true assume !(0 == ~E_4~0); 59#L542-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 84#L238-15true assume !(1 == ~m_pc~0); 113#L238-17true is_master_triggered_~__retres1~0#1 := 0; 309#L249-5true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 163#L250-5true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 230#L615-15true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 157#L615-17true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 210#L257-15true assume !(1 == ~t1_pc~0); 72#L257-17true is_transmit1_triggered_~__retres1~1#1 := 0; 334#L268-5true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 362#L269-5true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 305#L623-15true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 313#L623-17true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 367#L276-15true assume 1 == ~t2_pc~0; 253#L277-5true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 246#L287-5true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 188#L288-5true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 184#L631-15true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 288#L631-17true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26#L295-15true assume 1 == ~t3_pc~0; 304#L296-5true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 331#L306-5true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 155#L307-5true activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 165#L639-15true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 123#L639-17true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 164#L314-15true assume 1 == ~t4_pc~0; 282#L315-5true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 186#L325-5true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 252#L326-5true activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 317#L647-15true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 119#L647-17true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82#L555-3true assume 1 == ~M_E~0;~M_E~0 := 2; 196#L555-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 43#L560-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 306#L565-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 346#L570-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 289#L575-3true assume 1 == ~E_1~0;~E_1~0 := 2; 194#L580-3true assume !(1 == ~E_2~0); 390#L585-3true assume 1 == ~E_3~0;~E_3~0 := 2; 236#L590-3true assume 1 == ~E_4~0;~E_4~0 := 2; 271#L595-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 166#L374-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 71#L401-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 100#L402-1true start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 98#L795true assume !(0 == start_simulation_~tmp~3#1); 319#L795-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 110#L374-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 266#L401-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 248#L402-2true stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 171#L750true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 41#L757true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 272#L758true start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 276#L808true assume !(0 != start_simulation_~tmp___0~1#1); 179#L776-2true [2021-12-06 19:59:30,617 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:30,617 INFO L85 PathProgramCache]: Analyzing trace with hash 1110077256, now seen corresponding path program 1 times [2021-12-06 19:59:30,623 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:30,624 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1751014424] [2021-12-06 19:59:30,624 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:30,625 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:30,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:59:30,753 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:59:30,753 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:59:30,754 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1751014424] [2021-12-06 19:59:30,754 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1751014424] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:59:30,754 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:59:30,754 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:59:30,756 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1189378300] [2021-12-06 19:59:30,756 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:59:30,759 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 19:59:30,760 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:30,760 INFO L85 PathProgramCache]: Analyzing trace with hash 1190976846, now seen corresponding path program 1 times [2021-12-06 19:59:30,760 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:30,760 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [640829383] [2021-12-06 19:59:30,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:30,760 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:30,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:59:30,780 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:59:30,781 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:59:30,781 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [640829383] [2021-12-06 19:59:30,781 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [640829383] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:59:30,781 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:59:30,781 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 19:59:30,781 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [593196477] [2021-12-06 19:59:30,781 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:59:30,782 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:59:30,783 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:59:30,806 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 19:59:30,806 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 19:59:30,808 INFO L87 Difference]: Start difference. First operand has 391 states, 390 states have (on average 1.5384615384615385) internal successors, (600), 390 states have internal predecessors, (600), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:30,842 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:59:30,842 INFO L93 Difference]: Finished difference Result 390 states and 581 transitions. [2021-12-06 19:59:30,843 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 19:59:30,847 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 390 states and 581 transitions. [2021-12-06 19:59:30,851 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2021-12-06 19:59:30,857 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 390 states to 384 states and 575 transitions. [2021-12-06 19:59:30,858 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 384 [2021-12-06 19:59:30,859 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 384 [2021-12-06 19:59:30,859 INFO L73 IsDeterministic]: Start isDeterministic. Operand 384 states and 575 transitions. [2021-12-06 19:59:30,861 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:59:30,861 INFO L681 BuchiCegarLoop]: Abstraction has 384 states and 575 transitions. [2021-12-06 19:59:30,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 384 states and 575 transitions. [2021-12-06 19:59:30,893 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 384 to 384. [2021-12-06 19:59:30,894 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 384 states, 384 states have (on average 1.4973958333333333) internal successors, (575), 383 states have internal predecessors, (575), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:30,896 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 384 states to 384 states and 575 transitions. [2021-12-06 19:59:30,897 INFO L704 BuchiCegarLoop]: Abstraction has 384 states and 575 transitions. [2021-12-06 19:59:30,897 INFO L587 BuchiCegarLoop]: Abstraction has 384 states and 575 transitions. [2021-12-06 19:59:30,897 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-06 19:59:30,897 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 384 states and 575 transitions. [2021-12-06 19:59:30,899 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2021-12-06 19:59:30,899 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:59:30,899 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:59:30,902 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:30,902 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:30,902 INFO L791 eck$LassoCheckResult]: Stem: 1171#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 1140#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 790#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 791#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 915#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 1021#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 874#L346-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 875#L351-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 887#L356-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 888#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 933#L502 assume !(0 == ~M_E~0); 934#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 862#L507-1 assume !(0 == ~T2_E~0); 863#L512-1 assume !(0 == ~T3_E~0); 1023#L517-1 assume !(0 == ~T4_E~0); 844#L522-1 assume !(0 == ~E_1~0); 845#L527-1 assume !(0 == ~E_2~0); 1040#L532-1 assume !(0 == ~E_3~0); 1134#L537-1 assume !(0 == ~E_4~0); 1148#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1124#L238 assume 1 == ~m_pc~0; 1125#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 803#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 804#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1104#L615 assume !(0 != activate_threads_~tmp~1#1); 826#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 827#L257 assume 1 == ~t1_pc~0; 1082#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 942#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 977#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 797#L623 assume !(0 != activate_threads_~tmp___0~0#1); 798#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 792#L276 assume !(1 == ~t2_pc~0); 793#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1051#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 889#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 890#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1159#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1103#L295 assume 1 == ~t3_pc~0; 953#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 908#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1088#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1135#L639 assume !(0 != activate_threads_~tmp___2~0#1); 1128#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1129#L314 assume !(1 == ~t4_pc~0); 945#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 944#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1130#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1080#L647 assume !(0 != activate_threads_~tmp___3~0#1); 1034#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1035#L555 assume !(1 == ~M_E~0); 958#L555-2 assume !(1 == ~T1_E~0); 959#L560-1 assume !(1 == ~T2_E~0); 846#L565-1 assume !(1 == ~T3_E~0); 847#L570-1 assume !(1 == ~T4_E~0); 918#L575-1 assume !(1 == ~E_1~0); 919#L580-1 assume !(1 == ~E_2~0); 1081#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 920#L590-1 assume !(1 == ~E_4~0); 909#L595-1 assume { :end_inline_reset_delta_events } true; 910#L776-2 [2021-12-06 19:59:30,902 INFO L793 eck$LassoCheckResult]: Loop: 910#L776-2 assume !false; 878#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 879#L477 assume !false; 969#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 970#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 811#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 812#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 850#L416 assume !(0 != eval_~tmp~0#1); 852#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1138#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1065#L502-3 assume !(0 == ~M_E~0); 1066#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1092#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1014#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1015#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1000#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1001#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1083#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1017#L537-3 assume !(0 == ~E_4~0); 1018#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1027#L238-15 assume 1 == ~m_pc~0; 828#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 829#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1113#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 939#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 940#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 869#L257-15 assume !(1 == ~t1_pc~0); 870#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 1061#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1152#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1105#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1106#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1119#L276-15 assume 1 == ~t2_pc~0; 997#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 984#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 985#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1173#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1074#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 904#L295-15 assume !(1 == ~t3_pc~0); 905#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 1102#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1146#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1167#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1136#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1137#L314-15 assume 1 == ~t4_pc~0; 1056#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1057#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 995#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 996#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1123#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1073#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 805#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 806#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 974#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1108#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1075#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 799#L580-3 assume !(1 == ~E_2~0); 800#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 956#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 957#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1032#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 883#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1059#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 1098#L795 assume !(0 == start_simulation_~tmp~3#1); 1100#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1120#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 841#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 986#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 987#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 965#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 966#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1033#L808 assume !(0 != start_simulation_~tmp___0~1#1); 910#L776-2 [2021-12-06 19:59:30,903 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:30,903 INFO L85 PathProgramCache]: Analyzing trace with hash 1069402506, now seen corresponding path program 1 times [2021-12-06 19:59:30,903 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:30,903 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [444606780] [2021-12-06 19:59:30,903 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:30,904 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:30,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:59:30,935 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:59:30,935 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:59:30,935 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [444606780] [2021-12-06 19:59:30,936 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [444606780] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:59:30,936 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:59:30,936 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:59:30,936 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1776215760] [2021-12-06 19:59:30,936 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:59:30,937 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 19:59:30,937 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:30,937 INFO L85 PathProgramCache]: Analyzing trace with hash -1704108643, now seen corresponding path program 1 times [2021-12-06 19:59:30,937 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:30,937 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2087128042] [2021-12-06 19:59:30,938 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:30,938 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:30,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:59:30,989 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:59:30,989 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:59:30,989 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2087128042] [2021-12-06 19:59:30,989 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2087128042] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:59:30,990 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:59:30,990 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:59:30,990 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1386336714] [2021-12-06 19:59:30,990 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:59:30,990 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:59:30,990 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:59:30,991 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 19:59:30,991 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 19:59:30,991 INFO L87 Difference]: Start difference. First operand 384 states and 575 transitions. cyclomatic complexity: 192 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:31,005 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:59:31,005 INFO L93 Difference]: Finished difference Result 384 states and 574 transitions. [2021-12-06 19:59:31,005 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 19:59:31,006 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 384 states and 574 transitions. [2021-12-06 19:59:31,016 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2021-12-06 19:59:31,018 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 384 states to 384 states and 574 transitions. [2021-12-06 19:59:31,019 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 384 [2021-12-06 19:59:31,019 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 384 [2021-12-06 19:59:31,019 INFO L73 IsDeterministic]: Start isDeterministic. Operand 384 states and 574 transitions. [2021-12-06 19:59:31,020 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:59:31,020 INFO L681 BuchiCegarLoop]: Abstraction has 384 states and 574 transitions. [2021-12-06 19:59:31,021 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 384 states and 574 transitions. [2021-12-06 19:59:31,029 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 384 to 384. [2021-12-06 19:59:31,030 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 384 states, 384 states have (on average 1.4947916666666667) internal successors, (574), 383 states have internal predecessors, (574), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:31,031 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 384 states to 384 states and 574 transitions. [2021-12-06 19:59:31,031 INFO L704 BuchiCegarLoop]: Abstraction has 384 states and 574 transitions. [2021-12-06 19:59:31,031 INFO L587 BuchiCegarLoop]: Abstraction has 384 states and 574 transitions. [2021-12-06 19:59:31,031 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-06 19:59:31,031 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 384 states and 574 transitions. [2021-12-06 19:59:31,033 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2021-12-06 19:59:31,033 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:59:31,033 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:59:31,035 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:31,035 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:31,035 INFO L791 eck$LassoCheckResult]: Stem: 1946#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 1914#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1565#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1566#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1688#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 1794#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1649#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1650#L351-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1662#L356-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1663#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1708#L502 assume !(0 == ~M_E~0); 1709#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1637#L507-1 assume !(0 == ~T2_E~0); 1638#L512-1 assume !(0 == ~T3_E~0); 1797#L517-1 assume !(0 == ~T4_E~0); 1610#L522-1 assume !(0 == ~E_1~0); 1611#L527-1 assume !(0 == ~E_2~0); 1815#L532-1 assume !(0 == ~E_3~0); 1909#L537-1 assume !(0 == ~E_4~0); 1923#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1899#L238 assume 1 == ~m_pc~0; 1900#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1578#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1579#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1879#L615 assume !(0 != activate_threads_~tmp~1#1); 1597#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1598#L257 assume 1 == ~t1_pc~0; 1857#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1717#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1752#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1572#L623 assume !(0 != activate_threads_~tmp___0~0#1); 1573#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1567#L276 assume !(1 == ~t2_pc~0); 1568#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1825#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1664#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1665#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1933#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1876#L295 assume 1 == ~t3_pc~0; 1728#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1683#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1863#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1910#L639 assume !(0 != activate_threads_~tmp___2~0#1); 1902#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1903#L314 assume !(1 == ~t4_pc~0); 1720#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1719#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1905#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1855#L647 assume !(0 != activate_threads_~tmp___3~0#1); 1809#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1810#L555 assume !(1 == ~M_E~0); 1733#L555-2 assume !(1 == ~T1_E~0); 1734#L560-1 assume !(1 == ~T2_E~0); 1612#L565-1 assume !(1 == ~T3_E~0); 1613#L570-1 assume !(1 == ~T4_E~0); 1693#L575-1 assume !(1 == ~E_1~0); 1694#L580-1 assume !(1 == ~E_2~0); 1856#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1695#L590-1 assume !(1 == ~E_4~0); 1684#L595-1 assume { :end_inline_reset_delta_events } true; 1685#L776-2 [2021-12-06 19:59:31,035 INFO L793 eck$LassoCheckResult]: Loop: 1685#L776-2 assume !false; 1653#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1654#L477 assume !false; 1744#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1745#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1586#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1587#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1625#L416 assume !(0 != eval_~tmp~0#1); 1627#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1913#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1840#L502-3 assume !(0 == ~M_E~0); 1841#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1866#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1789#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1790#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1775#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1776#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1858#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1792#L537-3 assume !(0 == ~E_4~0); 1793#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1802#L238-15 assume 1 == ~m_pc~0; 1603#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1604#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1889#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1714#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1715#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1644#L257-15 assume !(1 == ~t1_pc~0); 1645#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 1836#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1927#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1880#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1881#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1894#L276-15 assume 1 == ~t2_pc~0; 1772#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1759#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1760#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1948#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1849#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1679#L295-15 assume !(1 == ~t3_pc~0); 1680#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 1878#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1921#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1942#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1911#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1912#L314-15 assume 1 == ~t4_pc~0; 1831#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1832#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1770#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1771#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1898#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1848#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1580#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1581#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1749#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1883#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1850#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1574#L580-3 assume !(1 == ~E_2~0); 1575#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1731#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1732#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1807#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1658#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1835#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 1873#L795 assume !(0 == start_simulation_~tmp~3#1); 1875#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1895#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1620#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1761#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 1762#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1742#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1743#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1808#L808 assume !(0 != start_simulation_~tmp___0~1#1); 1685#L776-2 [2021-12-06 19:59:31,036 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:31,036 INFO L85 PathProgramCache]: Analyzing trace with hash 193383500, now seen corresponding path program 1 times [2021-12-06 19:59:31,036 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:31,036 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1903084438] [2021-12-06 19:59:31,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:31,037 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:31,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:59:31,064 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:59:31,064 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:59:31,064 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1903084438] [2021-12-06 19:59:31,064 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1903084438] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:59:31,064 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:59:31,064 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:59:31,065 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1432191263] [2021-12-06 19:59:31,065 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:59:31,065 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 19:59:31,065 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:31,065 INFO L85 PathProgramCache]: Analyzing trace with hash -1704108643, now seen corresponding path program 2 times [2021-12-06 19:59:31,066 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:31,066 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [451327168] [2021-12-06 19:59:31,066 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:31,066 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:31,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:59:31,100 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:59:31,100 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:59:31,100 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [451327168] [2021-12-06 19:59:31,101 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [451327168] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:59:31,101 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:59:31,101 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:59:31,101 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1069289273] [2021-12-06 19:59:31,101 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:59:31,101 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:59:31,101 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:59:31,102 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 19:59:31,102 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 19:59:31,102 INFO L87 Difference]: Start difference. First operand 384 states and 574 transitions. cyclomatic complexity: 191 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:31,111 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:59:31,111 INFO L93 Difference]: Finished difference Result 384 states and 573 transitions. [2021-12-06 19:59:31,111 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 19:59:31,112 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 384 states and 573 transitions. [2021-12-06 19:59:31,114 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2021-12-06 19:59:31,117 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 384 states to 384 states and 573 transitions. [2021-12-06 19:59:31,117 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 384 [2021-12-06 19:59:31,117 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 384 [2021-12-06 19:59:31,117 INFO L73 IsDeterministic]: Start isDeterministic. Operand 384 states and 573 transitions. [2021-12-06 19:59:31,118 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:59:31,118 INFO L681 BuchiCegarLoop]: Abstraction has 384 states and 573 transitions. [2021-12-06 19:59:31,119 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 384 states and 573 transitions. [2021-12-06 19:59:31,123 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 384 to 384. [2021-12-06 19:59:31,124 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 384 states, 384 states have (on average 1.4921875) internal successors, (573), 383 states have internal predecessors, (573), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:31,125 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 384 states to 384 states and 573 transitions. [2021-12-06 19:59:31,126 INFO L704 BuchiCegarLoop]: Abstraction has 384 states and 573 transitions. [2021-12-06 19:59:31,126 INFO L587 BuchiCegarLoop]: Abstraction has 384 states and 573 transitions. [2021-12-06 19:59:31,126 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-06 19:59:31,126 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 384 states and 573 transitions. [2021-12-06 19:59:31,128 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2021-12-06 19:59:31,128 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:59:31,128 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:59:31,129 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:31,129 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:31,129 INFO L791 eck$LassoCheckResult]: Stem: 2721#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 2690#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2340#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2341#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2465#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 2571#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2424#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2425#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2437#L356-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2438#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2483#L502 assume !(0 == ~M_E~0); 2484#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2415#L507-1 assume !(0 == ~T2_E~0); 2416#L512-1 assume !(0 == ~T3_E~0); 2573#L517-1 assume !(0 == ~T4_E~0); 2394#L522-1 assume !(0 == ~E_1~0); 2395#L527-1 assume !(0 == ~E_2~0); 2590#L532-1 assume !(0 == ~E_3~0); 2684#L537-1 assume !(0 == ~E_4~0); 2698#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2674#L238 assume 1 == ~m_pc~0; 2675#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2353#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2354#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2654#L615 assume !(0 != activate_threads_~tmp~1#1); 2376#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2377#L257 assume 1 == ~t1_pc~0; 2632#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2492#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2527#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2347#L623 assume !(0 != activate_threads_~tmp___0~0#1); 2348#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2342#L276 assume !(1 == ~t2_pc~0); 2343#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2603#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2439#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2440#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2709#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2653#L295 assume 1 == ~t3_pc~0; 2503#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2458#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2638#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2685#L639 assume !(0 != activate_threads_~tmp___2~0#1); 2678#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2679#L314 assume !(1 == ~t4_pc~0); 2495#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2494#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2680#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2630#L647 assume !(0 != activate_threads_~tmp___3~0#1); 2584#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2585#L555 assume !(1 == ~M_E~0); 2508#L555-2 assume !(1 == ~T1_E~0); 2509#L560-1 assume !(1 == ~T2_E~0); 2396#L565-1 assume !(1 == ~T3_E~0); 2397#L570-1 assume !(1 == ~T4_E~0); 2468#L575-1 assume !(1 == ~E_1~0); 2469#L580-1 assume !(1 == ~E_2~0); 2631#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 2470#L590-1 assume !(1 == ~E_4~0); 2459#L595-1 assume { :end_inline_reset_delta_events } true; 2460#L776-2 [2021-12-06 19:59:31,129 INFO L793 eck$LassoCheckResult]: Loop: 2460#L776-2 assume !false; 2428#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2429#L477 assume !false; 2519#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2520#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2361#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2362#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2400#L416 assume !(0 != eval_~tmp~0#1); 2402#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2688#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2615#L502-3 assume !(0 == ~M_E~0); 2616#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2642#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2564#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2565#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2550#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2551#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2633#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2567#L537-3 assume !(0 == ~E_4~0); 2568#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2577#L238-15 assume 1 == ~m_pc~0; 2378#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2379#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2663#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2489#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2490#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2419#L257-15 assume !(1 == ~t1_pc~0); 2420#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 2611#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2702#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2655#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2656#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2669#L276-15 assume 1 == ~t2_pc~0; 2547#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2534#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2535#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2723#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2624#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2454#L295-15 assume !(1 == ~t3_pc~0); 2455#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 2652#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2696#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2717#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2686#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2687#L314-15 assume !(1 == ~t4_pc~0); 2608#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 2607#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2545#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2546#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2673#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2623#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2355#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2356#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2524#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2658#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2625#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2349#L580-3 assume !(1 == ~E_2~0); 2350#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2506#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2507#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2582#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2433#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2609#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 2648#L795 assume !(0 == start_simulation_~tmp~3#1); 2650#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2670#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2391#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2536#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 2537#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2515#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2516#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 2583#L808 assume !(0 != start_simulation_~tmp___0~1#1); 2460#L776-2 [2021-12-06 19:59:31,130 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:31,130 INFO L85 PathProgramCache]: Analyzing trace with hash -250517174, now seen corresponding path program 1 times [2021-12-06 19:59:31,130 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:31,130 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1732878192] [2021-12-06 19:59:31,130 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:31,130 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:31,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:59:31,151 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:59:31,152 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:59:31,152 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1732878192] [2021-12-06 19:59:31,152 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1732878192] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:59:31,152 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:59:31,152 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:59:31,153 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2088898794] [2021-12-06 19:59:31,153 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:59:31,153 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 19:59:31,154 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:31,154 INFO L85 PathProgramCache]: Analyzing trace with hash -2012547652, now seen corresponding path program 1 times [2021-12-06 19:59:31,154 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:31,154 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1862276781] [2021-12-06 19:59:31,154 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:31,154 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:31,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:59:31,193 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:59:31,193 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:59:31,193 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1862276781] [2021-12-06 19:59:31,193 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1862276781] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:59:31,193 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:59:31,193 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:59:31,193 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2011728449] [2021-12-06 19:59:31,194 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:59:31,194 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:59:31,194 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:59:31,194 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 19:59:31,194 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 19:59:31,195 INFO L87 Difference]: Start difference. First operand 384 states and 573 transitions. cyclomatic complexity: 190 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:31,203 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:59:31,203 INFO L93 Difference]: Finished difference Result 384 states and 572 transitions. [2021-12-06 19:59:31,203 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 19:59:31,204 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 384 states and 572 transitions. [2021-12-06 19:59:31,206 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2021-12-06 19:59:31,209 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 384 states to 384 states and 572 transitions. [2021-12-06 19:59:31,209 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 384 [2021-12-06 19:59:31,209 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 384 [2021-12-06 19:59:31,209 INFO L73 IsDeterministic]: Start isDeterministic. Operand 384 states and 572 transitions. [2021-12-06 19:59:31,210 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:59:31,210 INFO L681 BuchiCegarLoop]: Abstraction has 384 states and 572 transitions. [2021-12-06 19:59:31,210 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 384 states and 572 transitions. [2021-12-06 19:59:31,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 384 to 384. [2021-12-06 19:59:31,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 384 states, 384 states have (on average 1.4895833333333333) internal successors, (572), 383 states have internal predecessors, (572), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:31,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 384 states to 384 states and 572 transitions. [2021-12-06 19:59:31,216 INFO L704 BuchiCegarLoop]: Abstraction has 384 states and 572 transitions. [2021-12-06 19:59:31,216 INFO L587 BuchiCegarLoop]: Abstraction has 384 states and 572 transitions. [2021-12-06 19:59:31,216 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-06 19:59:31,216 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 384 states and 572 transitions. [2021-12-06 19:59:31,218 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2021-12-06 19:59:31,218 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:59:31,218 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:59:31,219 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:31,219 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:31,219 INFO L791 eck$LassoCheckResult]: Stem: 3496#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 3464#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3115#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3116#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3238#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 3346#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3199#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3200#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3212#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3213#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3258#L502 assume !(0 == ~M_E~0); 3259#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3187#L507-1 assume !(0 == ~T2_E~0); 3188#L512-1 assume !(0 == ~T3_E~0); 3347#L517-1 assume !(0 == ~T4_E~0); 3162#L522-1 assume !(0 == ~E_1~0); 3163#L527-1 assume !(0 == ~E_2~0); 3365#L532-1 assume !(0 == ~E_3~0); 3459#L537-1 assume !(0 == ~E_4~0); 3473#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3449#L238 assume 1 == ~m_pc~0; 3450#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3128#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3129#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3429#L615 assume !(0 != activate_threads_~tmp~1#1); 3147#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3148#L257 assume 1 == ~t1_pc~0; 3407#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3267#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3302#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3122#L623 assume !(0 != activate_threads_~tmp___0~0#1); 3123#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3117#L276 assume !(1 == ~t2_pc~0); 3118#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3375#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3214#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3215#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3483#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3426#L295 assume 1 == ~t3_pc~0; 3278#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3233#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3413#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3460#L639 assume !(0 != activate_threads_~tmp___2~0#1); 3452#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3453#L314 assume !(1 == ~t4_pc~0); 3270#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3269#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3455#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3405#L647 assume !(0 != activate_threads_~tmp___3~0#1); 3359#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3360#L555 assume !(1 == ~M_E~0); 3283#L555-2 assume !(1 == ~T1_E~0); 3284#L560-1 assume !(1 == ~T2_E~0); 3164#L565-1 assume !(1 == ~T3_E~0); 3165#L570-1 assume !(1 == ~T4_E~0); 3243#L575-1 assume !(1 == ~E_1~0); 3244#L580-1 assume !(1 == ~E_2~0); 3406#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 3245#L590-1 assume !(1 == ~E_4~0); 3234#L595-1 assume { :end_inline_reset_delta_events } true; 3235#L776-2 [2021-12-06 19:59:31,220 INFO L793 eck$LassoCheckResult]: Loop: 3235#L776-2 assume !false; 3203#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3204#L477 assume !false; 3294#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3295#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3136#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3137#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3175#L416 assume !(0 != eval_~tmp~0#1); 3177#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3463#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3390#L502-3 assume !(0 == ~M_E~0); 3391#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3416#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3339#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3340#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3325#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3326#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3408#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3342#L537-3 assume !(0 == ~E_4~0); 3343#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3352#L238-15 assume 1 == ~m_pc~0; 3153#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3154#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3439#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3264#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3265#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3194#L257-15 assume !(1 == ~t1_pc~0); 3195#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 3386#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3477#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3430#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3431#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3444#L276-15 assume 1 == ~t2_pc~0; 3322#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3309#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3310#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3498#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3399#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3229#L295-15 assume !(1 == ~t3_pc~0); 3230#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 3428#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3471#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3492#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3461#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3462#L314-15 assume 1 == ~t4_pc~0; 3381#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3382#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3320#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3321#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3448#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3398#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3130#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3131#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3299#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3433#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3400#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3124#L580-3 assume !(1 == ~E_2~0); 3125#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3281#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3282#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3358#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3208#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3385#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 3423#L795 assume !(0 == start_simulation_~tmp~3#1); 3425#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3445#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3172#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3311#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 3312#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3290#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3291#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 3356#L808 assume !(0 != start_simulation_~tmp___0~1#1); 3235#L776-2 [2021-12-06 19:59:31,220 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:31,220 INFO L85 PathProgramCache]: Analyzing trace with hash -1788857204, now seen corresponding path program 1 times [2021-12-06 19:59:31,220 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:31,220 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2032308686] [2021-12-06 19:59:31,221 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:31,221 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:31,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:59:31,245 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:59:31,245 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:59:31,245 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2032308686] [2021-12-06 19:59:31,245 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2032308686] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:59:31,246 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:59:31,246 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 19:59:31,246 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1013224687] [2021-12-06 19:59:31,246 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:59:31,246 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 19:59:31,247 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:31,247 INFO L85 PathProgramCache]: Analyzing trace with hash -1704108643, now seen corresponding path program 3 times [2021-12-06 19:59:31,247 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:31,247 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1883958544] [2021-12-06 19:59:31,247 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:31,247 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:31,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:59:31,285 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:59:31,285 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:59:31,285 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1883958544] [2021-12-06 19:59:31,285 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1883958544] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:59:31,286 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:59:31,286 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:59:31,286 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1476508429] [2021-12-06 19:59:31,286 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:59:31,286 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:59:31,286 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:59:31,287 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 19:59:31,287 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 19:59:31,287 INFO L87 Difference]: Start difference. First operand 384 states and 572 transitions. cyclomatic complexity: 189 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:31,301 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:59:31,301 INFO L93 Difference]: Finished difference Result 384 states and 567 transitions. [2021-12-06 19:59:31,302 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 19:59:31,302 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 384 states and 567 transitions. [2021-12-06 19:59:31,306 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2021-12-06 19:59:31,309 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 384 states to 384 states and 567 transitions. [2021-12-06 19:59:31,310 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 384 [2021-12-06 19:59:31,310 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 384 [2021-12-06 19:59:31,310 INFO L73 IsDeterministic]: Start isDeterministic. Operand 384 states and 567 transitions. [2021-12-06 19:59:31,311 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:59:31,311 INFO L681 BuchiCegarLoop]: Abstraction has 384 states and 567 transitions. [2021-12-06 19:59:31,312 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 384 states and 567 transitions. [2021-12-06 19:59:31,318 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 384 to 384. [2021-12-06 19:59:31,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 384 states, 384 states have (on average 1.4765625) internal successors, (567), 383 states have internal predecessors, (567), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:31,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 384 states to 384 states and 567 transitions. [2021-12-06 19:59:31,321 INFO L704 BuchiCegarLoop]: Abstraction has 384 states and 567 transitions. [2021-12-06 19:59:31,321 INFO L587 BuchiCegarLoop]: Abstraction has 384 states and 567 transitions. [2021-12-06 19:59:31,322 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-06 19:59:31,322 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 384 states and 567 transitions. [2021-12-06 19:59:31,324 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 319 [2021-12-06 19:59:31,324 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:59:31,324 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:59:31,326 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:31,326 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:31,326 INFO L791 eck$LassoCheckResult]: Stem: 4271#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 4240#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3890#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3891#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4015#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 4121#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3974#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3975#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3987#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3988#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4033#L502 assume !(0 == ~M_E~0); 4034#L502-2 assume !(0 == ~T1_E~0); 3965#L507-1 assume !(0 == ~T2_E~0); 3966#L512-1 assume !(0 == ~T3_E~0); 4123#L517-1 assume !(0 == ~T4_E~0); 3944#L522-1 assume !(0 == ~E_1~0); 3945#L527-1 assume !(0 == ~E_2~0); 4140#L532-1 assume !(0 == ~E_3~0); 4234#L537-1 assume !(0 == ~E_4~0); 4248#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4224#L238 assume 1 == ~m_pc~0; 4225#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3903#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3904#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4204#L615 assume !(0 != activate_threads_~tmp~1#1); 3926#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3927#L257 assume 1 == ~t1_pc~0; 4182#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4042#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4077#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3897#L623 assume !(0 != activate_threads_~tmp___0~0#1); 3898#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3892#L276 assume !(1 == ~t2_pc~0); 3893#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4153#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3989#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3990#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4259#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4203#L295 assume 1 == ~t3_pc~0; 4053#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4008#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4188#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4235#L639 assume !(0 != activate_threads_~tmp___2~0#1); 4228#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4229#L314 assume !(1 == ~t4_pc~0); 4045#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4044#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4230#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4180#L647 assume !(0 != activate_threads_~tmp___3~0#1); 4134#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4135#L555 assume !(1 == ~M_E~0); 4058#L555-2 assume !(1 == ~T1_E~0); 4059#L560-1 assume !(1 == ~T2_E~0); 3946#L565-1 assume !(1 == ~T3_E~0); 3947#L570-1 assume !(1 == ~T4_E~0); 4018#L575-1 assume !(1 == ~E_1~0); 4019#L580-1 assume !(1 == ~E_2~0); 4181#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 4020#L590-1 assume !(1 == ~E_4~0); 4009#L595-1 assume { :end_inline_reset_delta_events } true; 4010#L776-2 [2021-12-06 19:59:31,327 INFO L793 eck$LassoCheckResult]: Loop: 4010#L776-2 assume !false; 3978#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3979#L477 assume !false; 4069#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4070#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3911#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3912#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3950#L416 assume !(0 != eval_~tmp~0#1); 3952#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4238#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4165#L502-3 assume !(0 == ~M_E~0); 4166#L502-5 assume !(0 == ~T1_E~0); 4191#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4114#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4115#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4100#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4101#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4183#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4117#L537-3 assume !(0 == ~E_4~0); 4118#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4127#L238-15 assume 1 == ~m_pc~0; 3928#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3929#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4213#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4039#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4040#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3969#L257-15 assume !(1 == ~t1_pc~0); 3970#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 4161#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4252#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4205#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4206#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4219#L276-15 assume 1 == ~t2_pc~0; 4097#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4084#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4085#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4273#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4174#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4004#L295-15 assume !(1 == ~t3_pc~0); 4005#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 4202#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4246#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4267#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4236#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4237#L314-15 assume 1 == ~t4_pc~0; 4156#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4157#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4095#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4096#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4223#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4173#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3905#L555-5 assume !(1 == ~T1_E~0); 3906#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4074#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4208#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4175#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3899#L580-3 assume !(1 == ~E_2~0); 3900#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4056#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4057#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4132#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3983#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4159#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 4198#L795 assume !(0 == start_simulation_~tmp~3#1); 4200#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4220#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3941#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4086#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 4087#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4065#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4066#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 4133#L808 assume !(0 != start_simulation_~tmp___0~1#1); 4010#L776-2 [2021-12-06 19:59:31,327 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:31,327 INFO L85 PathProgramCache]: Analyzing trace with hash -1804375922, now seen corresponding path program 1 times [2021-12-06 19:59:31,327 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:31,328 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1602341975] [2021-12-06 19:59:31,328 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:31,328 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:31,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:59:31,355 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:59:31,355 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:59:31,356 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1602341975] [2021-12-06 19:59:31,356 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1602341975] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:59:31,356 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:59:31,356 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 19:59:31,356 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1596757642] [2021-12-06 19:59:31,357 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:59:31,357 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 19:59:31,357 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:31,357 INFO L85 PathProgramCache]: Analyzing trace with hash 680167841, now seen corresponding path program 1 times [2021-12-06 19:59:31,358 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:31,358 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [346484330] [2021-12-06 19:59:31,358 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:31,358 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:31,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:59:31,390 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:59:31,390 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:59:31,390 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [346484330] [2021-12-06 19:59:31,390 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [346484330] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:59:31,390 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:59:31,391 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:59:31,391 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1807008790] [2021-12-06 19:59:31,391 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:59:31,391 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:59:31,391 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:59:31,392 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 19:59:31,392 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 19:59:31,392 INFO L87 Difference]: Start difference. First operand 384 states and 567 transitions. cyclomatic complexity: 184 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:31,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:59:31,438 INFO L93 Difference]: Finished difference Result 694 states and 1012 transitions. [2021-12-06 19:59:31,439 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 19:59:31,439 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 694 states and 1012 transitions. [2021-12-06 19:59:31,444 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 629 [2021-12-06 19:59:31,448 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 694 states to 694 states and 1012 transitions. [2021-12-06 19:59:31,449 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 694 [2021-12-06 19:59:31,449 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 694 [2021-12-06 19:59:31,449 INFO L73 IsDeterministic]: Start isDeterministic. Operand 694 states and 1012 transitions. [2021-12-06 19:59:31,450 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:59:31,450 INFO L681 BuchiCegarLoop]: Abstraction has 694 states and 1012 transitions. [2021-12-06 19:59:31,451 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 694 states and 1012 transitions. [2021-12-06 19:59:31,459 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 694 to 658. [2021-12-06 19:59:31,460 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 658 states, 658 states have (on average 1.4635258358662615) internal successors, (963), 657 states have internal predecessors, (963), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:31,462 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 658 states to 658 states and 963 transitions. [2021-12-06 19:59:31,462 INFO L704 BuchiCegarLoop]: Abstraction has 658 states and 963 transitions. [2021-12-06 19:59:31,462 INFO L587 BuchiCegarLoop]: Abstraction has 658 states and 963 transitions. [2021-12-06 19:59:31,463 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-06 19:59:31,463 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 658 states and 963 transitions. [2021-12-06 19:59:31,465 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 593 [2021-12-06 19:59:31,465 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:59:31,465 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:59:31,466 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:31,466 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:31,466 INFO L791 eck$LassoCheckResult]: Stem: 5365#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 5328#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4975#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4976#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5096#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 5204#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5059#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5060#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5072#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5073#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5118#L502 assume !(0 == ~M_E~0); 5119#L502-2 assume !(0 == ~T1_E~0); 5047#L507-1 assume !(0 == ~T2_E~0); 5048#L512-1 assume !(0 == ~T3_E~0); 5207#L517-1 assume !(0 == ~T4_E~0); 5020#L522-1 assume !(0 == ~E_1~0); 5021#L527-1 assume !(0 == ~E_2~0); 5226#L532-1 assume !(0 == ~E_3~0); 5320#L537-1 assume !(0 == ~E_4~0); 5340#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5311#L238 assume !(1 == ~m_pc~0); 5312#L238-2 is_master_triggered_~__retres1~0#1 := 0; 4986#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4987#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5292#L615 assume !(0 != activate_threads_~tmp~1#1); 5007#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5008#L257 assume 1 == ~t1_pc~0; 5268#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5127#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5162#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4980#L623 assume !(0 != activate_threads_~tmp___0~0#1); 4981#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4977#L276 assume !(1 == ~t2_pc~0); 4978#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5235#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5074#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5075#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5352#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5289#L295 assume 1 == ~t3_pc~0; 5138#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5093#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5274#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5321#L639 assume !(0 != activate_threads_~tmp___2~0#1); 5313#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5314#L314 assume !(1 == ~t4_pc~0); 5130#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5129#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5316#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5266#L647 assume !(0 != activate_threads_~tmp___3~0#1); 5219#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5220#L555 assume !(1 == ~M_E~0); 5143#L555-2 assume !(1 == ~T1_E~0); 5144#L560-1 assume !(1 == ~T2_E~0); 5022#L565-1 assume !(1 == ~T3_E~0); 5023#L570-1 assume !(1 == ~T4_E~0); 5103#L575-1 assume !(1 == ~E_1~0); 5104#L580-1 assume !(1 == ~E_2~0); 5267#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 5105#L590-1 assume !(1 == ~E_4~0); 5094#L595-1 assume { :end_inline_reset_delta_events } true; 5095#L776-2 [2021-12-06 19:59:31,466 INFO L793 eck$LassoCheckResult]: Loop: 5095#L776-2 assume !false; 5063#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5064#L477 assume !false; 5154#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5155#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4994#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4995#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5035#L416 assume !(0 != eval_~tmp~0#1); 5037#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5324#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5250#L502-3 assume !(0 == ~M_E~0); 5251#L502-5 assume !(0 == ~T1_E~0); 5280#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5199#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5200#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5185#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5186#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5269#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5202#L537-3 assume !(0 == ~E_4~0); 5203#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5212#L238-15 assume !(1 == ~m_pc~0); 5262#L238-17 is_master_triggered_~__retres1~0#1 := 0; 5538#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5536#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5534#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5532#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5530#L257-15 assume 1 == ~t1_pc~0; 5527#L258-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5525#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5523#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5521#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5519#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5518#L276-15 assume 1 == ~t2_pc~0; 5516#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5515#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5514#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5513#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5512#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5511#L295-15 assume !(1 == ~t3_pc~0); 5507#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 5503#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5502#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5501#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5500#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5499#L314-15 assume 1 == ~t4_pc~0; 5497#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5496#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5495#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5494#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5492#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5490#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5488#L555-5 assume !(1 == ~T1_E~0); 5486#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5483#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5481#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5479#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5477#L580-3 assume !(1 == ~E_2~0); 5475#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5473#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5470#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5463#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5459#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5458#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 5454#L795 assume !(0 == start_simulation_~tmp~3#1); 5451#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5432#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5428#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5426#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 5424#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5423#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5421#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 5419#L808 assume !(0 != start_simulation_~tmp___0~1#1); 5095#L776-2 [2021-12-06 19:59:31,467 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:31,467 INFO L85 PathProgramCache]: Analyzing trace with hash -1404384723, now seen corresponding path program 1 times [2021-12-06 19:59:31,467 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:31,467 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1408103599] [2021-12-06 19:59:31,467 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:31,467 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:31,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:59:31,492 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:59:31,493 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:59:31,493 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1408103599] [2021-12-06 19:59:31,493 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1408103599] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:59:31,493 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:59:31,493 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:59:31,493 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1672371930] [2021-12-06 19:59:31,494 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:59:31,494 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 19:59:31,494 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:31,494 INFO L85 PathProgramCache]: Analyzing trace with hash 1286604385, now seen corresponding path program 1 times [2021-12-06 19:59:31,494 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:31,495 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1654676863] [2021-12-06 19:59:31,495 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:31,495 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:31,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:59:31,519 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:59:31,519 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:59:31,519 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1654676863] [2021-12-06 19:59:31,519 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1654676863] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:59:31,519 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:59:31,519 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:59:31,520 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1165860221] [2021-12-06 19:59:31,520 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:59:31,520 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:59:31,520 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:59:31,521 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 19:59:31,521 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 19:59:31,521 INFO L87 Difference]: Start difference. First operand 658 states and 963 transitions. cyclomatic complexity: 307 Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:31,620 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:59:31,620 INFO L93 Difference]: Finished difference Result 1490 states and 2153 transitions. [2021-12-06 19:59:31,620 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 19:59:31,621 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1490 states and 2153 transitions. [2021-12-06 19:59:31,630 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1382 [2021-12-06 19:59:31,639 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1490 states to 1490 states and 2153 transitions. [2021-12-06 19:59:31,639 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1490 [2021-12-06 19:59:31,640 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1490 [2021-12-06 19:59:31,640 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1490 states and 2153 transitions. [2021-12-06 19:59:31,642 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:59:31,642 INFO L681 BuchiCegarLoop]: Abstraction has 1490 states and 2153 transitions. [2021-12-06 19:59:31,644 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1490 states and 2153 transitions. [2021-12-06 19:59:31,671 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1490 to 1163. [2021-12-06 19:59:31,674 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1163 states, 1163 states have (on average 1.4557179707652623) internal successors, (1693), 1162 states have internal predecessors, (1693), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:31,678 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1163 states to 1163 states and 1693 transitions. [2021-12-06 19:59:31,678 INFO L704 BuchiCegarLoop]: Abstraction has 1163 states and 1693 transitions. [2021-12-06 19:59:31,678 INFO L587 BuchiCegarLoop]: Abstraction has 1163 states and 1693 transitions. [2021-12-06 19:59:31,678 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-06 19:59:31,679 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1163 states and 1693 transitions. [2021-12-06 19:59:31,685 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1098 [2021-12-06 19:59:31,685 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:59:31,685 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:59:31,687 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:31,687 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:31,687 INFO L791 eck$LassoCheckResult]: Stem: 7536#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 7491#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 7133#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7134#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7258#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 7367#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7217#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7218#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7230#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7231#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7276#L502 assume !(0 == ~M_E~0); 7277#L502-2 assume !(0 == ~T1_E~0); 7209#L507-1 assume !(0 == ~T2_E~0); 7210#L512-1 assume !(0 == ~T3_E~0); 7369#L517-1 assume !(0 == ~T4_E~0); 7188#L522-1 assume !(0 == ~E_1~0); 7189#L527-1 assume !(0 == ~E_2~0); 7386#L532-1 assume !(0 == ~E_3~0); 7482#L537-1 assume !(0 == ~E_4~0); 7500#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7473#L238 assume !(1 == ~m_pc~0); 7474#L238-2 is_master_triggered_~__retres1~0#1 := 0; 7146#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7147#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7452#L615 assume !(0 != activate_threads_~tmp~1#1); 7169#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7170#L257 assume !(1 == ~t1_pc~0); 7284#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7285#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7320#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7140#L623 assume !(0 != activate_threads_~tmp___0~0#1); 7141#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7135#L276 assume !(1 == ~t2_pc~0); 7136#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7398#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7232#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7233#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7515#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7450#L295 assume 1 == ~t3_pc~0; 7296#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7251#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7437#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7483#L639 assume !(0 != activate_threads_~tmp___2~0#1); 7476#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7477#L314 assume !(1 == ~t4_pc~0); 7288#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7287#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7478#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7427#L647 assume !(0 != activate_threads_~tmp___3~0#1); 7380#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7381#L555 assume !(1 == ~M_E~0); 7301#L555-2 assume !(1 == ~T1_E~0); 7302#L560-1 assume !(1 == ~T2_E~0); 7190#L565-1 assume !(1 == ~T3_E~0); 7191#L570-1 assume !(1 == ~T4_E~0); 7261#L575-1 assume !(1 == ~E_1~0); 7262#L580-1 assume !(1 == ~E_2~0); 7428#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 7263#L590-1 assume !(1 == ~E_4~0); 7252#L595-1 assume { :end_inline_reset_delta_events } true; 7253#L776-2 [2021-12-06 19:59:31,687 INFO L793 eck$LassoCheckResult]: Loop: 7253#L776-2 assume !false; 7221#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7222#L477 assume !false; 7312#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7313#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7152#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7153#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7194#L416 assume !(0 != eval_~tmp~0#1); 7196#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7486#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7411#L502-3 assume !(0 == ~M_E~0); 7412#L502-5 assume !(0 == ~T1_E~0); 7441#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7360#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7361#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7347#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7348#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7429#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7363#L537-3 assume !(0 == ~E_4~0); 7364#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7375#L238-15 assume !(1 == ~m_pc~0); 7423#L238-17 is_master_triggered_~__retres1~0#1 := 0; 7461#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7462#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7282#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7283#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7213#L257-15 assume !(1 == ~t1_pc~0); 7214#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 7406#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7505#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7453#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7454#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7467#L276-15 assume 1 == ~t2_pc~0; 7344#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7325#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7326#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7538#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7420#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7247#L295-15 assume !(1 == ~t3_pc~0); 7248#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 7449#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7497#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7528#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7484#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7485#L314-15 assume 1 == ~t4_pc~0; 7401#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7402#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7342#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7343#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7472#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7418#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7148#L555-5 assume !(1 == ~T1_E~0); 7149#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7317#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7456#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7421#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7142#L580-3 assume !(1 == ~E_2~0); 7143#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7299#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7300#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7377#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7226#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7404#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 7446#L795 assume !(0 == start_simulation_~tmp~3#1); 7448#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7468#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7182#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7330#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 7331#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7308#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7309#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 7378#L808 assume !(0 != start_simulation_~tmp___0~1#1); 7253#L776-2 [2021-12-06 19:59:31,688 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:31,688 INFO L85 PathProgramCache]: Analyzing trace with hash 1261932300, now seen corresponding path program 1 times [2021-12-06 19:59:31,688 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:31,688 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1712167699] [2021-12-06 19:59:31,688 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:31,688 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:31,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:59:31,721 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:59:31,721 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:59:31,721 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1712167699] [2021-12-06 19:59:31,721 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1712167699] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:59:31,721 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:59:31,721 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 19:59:31,721 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1062326562] [2021-12-06 19:59:31,721 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:59:31,722 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 19:59:31,722 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:31,722 INFO L85 PathProgramCache]: Analyzing trace with hash -21400384, now seen corresponding path program 1 times [2021-12-06 19:59:31,722 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:31,722 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1266039954] [2021-12-06 19:59:31,722 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:31,723 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:31,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:59:31,740 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:59:31,740 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:59:31,741 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1266039954] [2021-12-06 19:59:31,741 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1266039954] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:59:31,741 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:59:31,741 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:59:31,741 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1722026217] [2021-12-06 19:59:31,742 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:59:31,742 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:59:31,742 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:59:31,743 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-06 19:59:31,743 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-06 19:59:31,743 INFO L87 Difference]: Start difference. First operand 1163 states and 1693 transitions. cyclomatic complexity: 532 Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:31,866 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:59:31,866 INFO L93 Difference]: Finished difference Result 2972 states and 4330 transitions. [2021-12-06 19:59:31,867 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-06 19:59:31,867 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2972 states and 4330 transitions. [2021-12-06 19:59:31,891 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2850 [2021-12-06 19:59:31,914 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2972 states to 2972 states and 4330 transitions. [2021-12-06 19:59:31,914 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2972 [2021-12-06 19:59:31,918 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2972 [2021-12-06 19:59:31,918 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2972 states and 4330 transitions. [2021-12-06 19:59:31,923 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:59:31,924 INFO L681 BuchiCegarLoop]: Abstraction has 2972 states and 4330 transitions. [2021-12-06 19:59:31,927 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2972 states and 4330 transitions. [2021-12-06 19:59:31,949 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2972 to 1226. [2021-12-06 19:59:31,951 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1226 states, 1226 states have (on average 1.432300163132137) internal successors, (1756), 1225 states have internal predecessors, (1756), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:31,955 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1226 states to 1226 states and 1756 transitions. [2021-12-06 19:59:31,955 INFO L704 BuchiCegarLoop]: Abstraction has 1226 states and 1756 transitions. [2021-12-06 19:59:31,955 INFO L587 BuchiCegarLoop]: Abstraction has 1226 states and 1756 transitions. [2021-12-06 19:59:31,955 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-06 19:59:31,955 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1226 states and 1756 transitions. [2021-12-06 19:59:31,960 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1158 [2021-12-06 19:59:31,960 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:59:31,960 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:59:31,961 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:31,961 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:31,961 INFO L791 eck$LassoCheckResult]: Stem: 11722#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 11659#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 11281#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11282#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11402#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 11517#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11365#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11366#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11378#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11379#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11424#L502 assume !(0 == ~M_E~0); 11425#L502-2 assume !(0 == ~T1_E~0); 11354#L507-1 assume !(0 == ~T2_E~0); 11355#L512-1 assume !(0 == ~T3_E~0); 11520#L517-1 assume !(0 == ~T4_E~0); 11326#L522-1 assume !(0 == ~E_1~0); 11327#L527-1 assume !(0 == ~E_2~0); 11542#L532-1 assume !(0 == ~E_3~0); 11654#L537-1 assume !(0 == ~E_4~0); 11673#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11643#L238 assume !(1 == ~m_pc~0); 11644#L238-2 is_master_triggered_~__retres1~0#1 := 0; 11292#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11293#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 11620#L615 assume !(0 != activate_threads_~tmp~1#1); 11313#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11314#L257 assume !(1 == ~t1_pc~0); 11432#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11433#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11470#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 11286#L623 assume !(0 != activate_threads_~tmp___0~0#1); 11287#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11283#L276 assume !(1 == ~t2_pc~0); 11284#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11552#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11680#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 11689#L631 assume !(0 != activate_threads_~tmp___1~0#1); 11690#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11617#L295 assume 1 == ~t3_pc~0; 11444#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11399#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11598#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11655#L639 assume !(0 != activate_threads_~tmp___2~0#1); 11645#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11646#L314 assume !(1 == ~t4_pc~0); 11436#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11435#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11649#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11588#L647 assume !(0 != activate_threads_~tmp___3~0#1); 11534#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11535#L555 assume !(1 == ~M_E~0); 11449#L555-2 assume !(1 == ~T1_E~0); 11450#L560-1 assume !(1 == ~T2_E~0); 11328#L565-1 assume !(1 == ~T3_E~0); 11329#L570-1 assume !(1 == ~T4_E~0); 11409#L575-1 assume !(1 == ~E_1~0); 11410#L580-1 assume !(1 == ~E_2~0); 11589#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 11411#L590-1 assume !(1 == ~E_4~0); 11400#L595-1 assume { :end_inline_reset_delta_events } true; 11401#L776-2 [2021-12-06 19:59:31,962 INFO L793 eck$LassoCheckResult]: Loop: 11401#L776-2 assume !false; 11369#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11370#L477 assume !false; 11460#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 11461#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 11300#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 11301#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11342#L416 assume !(0 != eval_~tmp~0#1); 11344#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12497#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12495#L502-3 assume !(0 == ~M_E~0); 12493#L502-5 assume !(0 == ~T1_E~0); 12491#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12489#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12487#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12485#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12483#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12481#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12480#L537-3 assume !(0 == ~E_4~0); 11525#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11526#L238-15 assume !(1 == ~m_pc~0); 12467#L238-17 is_master_triggered_~__retres1~0#1 := 0; 12466#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12465#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 12464#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12463#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11361#L257-15 assume !(1 == ~t1_pc~0); 11362#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 12461#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11708#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 11621#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11622#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11637#L276-15 assume !(1 == ~t2_pc~0); 12453#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 12451#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12449#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12448#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 12412#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12410#L295-15 assume !(1 == ~t3_pc~0); 12406#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 12404#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12401#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12399#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12397#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12395#L314-15 assume 1 == ~t4_pc~0; 12389#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12388#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11492#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11493#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12332#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12331#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12330#L555-5 assume !(1 == ~T1_E~0); 11465#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11466#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12314#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11580#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11290#L580-3 assume !(1 == ~E_2~0); 11291#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11447#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11448#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 11532#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 11374#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 11561#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 11614#L795 assume !(0 == start_simulation_~tmp~3#1); 11616#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 11638#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 11336#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 11479#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 11480#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11456#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11457#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 11533#L808 assume !(0 != start_simulation_~tmp___0~1#1); 11401#L776-2 [2021-12-06 19:59:31,962 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:31,962 INFO L85 PathProgramCache]: Analyzing trace with hash 1127918794, now seen corresponding path program 1 times [2021-12-06 19:59:31,962 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:31,962 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [986159627] [2021-12-06 19:59:31,962 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:31,963 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:31,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:59:31,985 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:59:31,985 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:59:31,986 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [986159627] [2021-12-06 19:59:31,986 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [986159627] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:59:31,986 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:59:31,986 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:59:31,986 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1707296394] [2021-12-06 19:59:31,986 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:59:31,987 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 19:59:31,987 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:31,987 INFO L85 PathProgramCache]: Analyzing trace with hash -15775971, now seen corresponding path program 1 times [2021-12-06 19:59:31,987 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:31,988 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1178347451] [2021-12-06 19:59:31,988 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:31,988 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:31,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:59:32,020 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:59:32,020 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:59:32,020 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1178347451] [2021-12-06 19:59:32,021 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1178347451] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:59:32,021 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:59:32,021 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:59:32,021 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1249209208] [2021-12-06 19:59:32,021 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:59:32,022 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:59:32,022 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:59:32,022 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 19:59:32,022 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 19:59:32,022 INFO L87 Difference]: Start difference. First operand 1226 states and 1756 transitions. cyclomatic complexity: 532 Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:32,125 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:59:32,125 INFO L93 Difference]: Finished difference Result 2784 states and 3948 transitions. [2021-12-06 19:59:32,126 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 19:59:32,126 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2784 states and 3948 transitions. [2021-12-06 19:59:32,147 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2624 [2021-12-06 19:59:32,168 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2784 states to 2784 states and 3948 transitions. [2021-12-06 19:59:32,168 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2784 [2021-12-06 19:59:32,171 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2784 [2021-12-06 19:59:32,171 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2784 states and 3948 transitions. [2021-12-06 19:59:32,176 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:59:32,176 INFO L681 BuchiCegarLoop]: Abstraction has 2784 states and 3948 transitions. [2021-12-06 19:59:32,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2784 states and 3948 transitions. [2021-12-06 19:59:32,201 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2784 to 2201. [2021-12-06 19:59:32,205 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2201 states, 2201 states have (on average 1.4279872785097683) internal successors, (3143), 2200 states have internal predecessors, (3143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:32,210 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2201 states to 2201 states and 3143 transitions. [2021-12-06 19:59:32,211 INFO L704 BuchiCegarLoop]: Abstraction has 2201 states and 3143 transitions. [2021-12-06 19:59:32,211 INFO L587 BuchiCegarLoop]: Abstraction has 2201 states and 3143 transitions. [2021-12-06 19:59:32,211 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-06 19:59:32,211 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2201 states and 3143 transitions. [2021-12-06 19:59:32,219 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2132 [2021-12-06 19:59:32,219 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:59:32,219 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:59:32,220 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:32,220 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:32,220 INFO L791 eck$LassoCheckResult]: Stem: 15727#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 15673#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 15301#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15302#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15421#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 15540#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15385#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15386#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15398#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15399#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15443#L502 assume !(0 == ~M_E~0); 15444#L502-2 assume !(0 == ~T1_E~0); 15374#L507-1 assume !(0 == ~T2_E~0); 15375#L512-1 assume !(0 == ~T3_E~0); 15543#L517-1 assume !(0 == ~T4_E~0); 15346#L522-1 assume !(0 == ~E_1~0); 15347#L527-1 assume !(0 == ~E_2~0); 15561#L532-1 assume !(0 == ~E_3~0); 15665#L537-1 assume !(0 == ~E_4~0); 15688#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15654#L238 assume !(1 == ~m_pc~0); 15655#L238-2 is_master_triggered_~__retres1~0#1 := 0; 15312#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15313#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 15633#L615 assume !(0 != activate_threads_~tmp~1#1); 15333#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15334#L257 assume !(1 == ~t1_pc~0); 15451#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15452#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15490#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 15306#L623 assume !(0 != activate_threads_~tmp___0~0#1); 15307#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15303#L276 assume !(1 == ~t2_pc~0); 15304#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15570#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15400#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 15401#L631 assume !(0 != activate_threads_~tmp___1~0#1); 15704#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15629#L295 assume !(1 == ~t3_pc~0); 15417#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15418#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15612#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 15666#L639 assume !(0 != activate_threads_~tmp___2~0#1); 15656#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15657#L314 assume !(1 == ~t4_pc~0); 15456#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 15455#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15660#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15604#L647 assume !(0 != activate_threads_~tmp___3~0#1); 15555#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15556#L555 assume !(1 == ~M_E~0); 15470#L555-2 assume !(1 == ~T1_E~0); 15471#L560-1 assume !(1 == ~T2_E~0); 15348#L565-1 assume !(1 == ~T3_E~0); 15349#L570-1 assume !(1 == ~T4_E~0); 15428#L575-1 assume !(1 == ~E_1~0); 15429#L580-1 assume !(1 == ~E_2~0); 15605#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 15430#L590-1 assume !(1 == ~E_4~0); 15419#L595-1 assume { :end_inline_reset_delta_events } true; 15420#L776-2 [2021-12-06 19:59:32,220 INFO L793 eck$LassoCheckResult]: Loop: 15420#L776-2 assume !false; 15389#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15390#L477 assume !false; 15480#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 15481#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 15320#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 15321#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15362#L416 assume !(0 != eval_~tmp~0#1); 15364#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15669#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15588#L502-3 assume !(0 == ~M_E~0); 15589#L502-5 assume !(0 == ~T1_E~0); 15619#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15535#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15536#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15519#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15520#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15606#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15538#L537-3 assume !(0 == ~E_4~0); 15539#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15548#L238-15 assume !(1 == ~m_pc~0); 15600#L238-17 is_master_triggered_~__retres1~0#1 := 0; 15642#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15643#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 15449#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15450#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15381#L257-15 assume !(1 == ~t1_pc~0); 15382#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 17460#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17458#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 17456#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17454#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17452#L276-15 assume !(1 == ~t2_pc~0); 17448#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 17446#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17444#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 17442#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 17439#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17437#L295-15 assume !(1 == ~t3_pc~0); 16565#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 17434#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17433#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17432#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17431#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17430#L314-15 assume 1 == ~t4_pc~0; 17421#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17419#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17418#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17416#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17414#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17412#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17410#L555-5 assume !(1 == ~T1_E~0); 17408#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17405#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17403#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17401#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17399#L580-3 assume !(1 == ~E_2~0); 17397#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17395#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17394#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 17389#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 17386#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 17385#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 17382#L795 assume !(0 == start_simulation_~tmp~3#1); 15659#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 15649#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 15356#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 15500#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 15501#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15476#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15477#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 15554#L808 assume !(0 != start_simulation_~tmp___0~1#1); 15420#L776-2 [2021-12-06 19:59:32,221 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:32,221 INFO L85 PathProgramCache]: Analyzing trace with hash 1014532137, now seen corresponding path program 1 times [2021-12-06 19:59:32,221 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:32,221 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [402350716] [2021-12-06 19:59:32,221 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:32,221 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:32,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:59:32,245 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:59:32,245 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:59:32,245 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [402350716] [2021-12-06 19:59:32,245 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [402350716] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:59:32,245 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:59:32,246 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:59:32,246 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2024670080] [2021-12-06 19:59:32,246 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:59:32,246 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 19:59:32,246 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:32,247 INFO L85 PathProgramCache]: Analyzing trace with hash -15775971, now seen corresponding path program 2 times [2021-12-06 19:59:32,247 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:32,247 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1824973825] [2021-12-06 19:59:32,247 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:32,247 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:32,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:59:32,268 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:59:32,268 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:59:32,268 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1824973825] [2021-12-06 19:59:32,269 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1824973825] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:59:32,269 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:59:32,269 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:59:32,269 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1237508657] [2021-12-06 19:59:32,269 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:59:32,270 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:59:32,270 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:59:32,270 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 19:59:32,270 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 19:59:32,270 INFO L87 Difference]: Start difference. First operand 2201 states and 3143 transitions. cyclomatic complexity: 944 Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:32,337 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:59:32,338 INFO L93 Difference]: Finished difference Result 4500 states and 6391 transitions. [2021-12-06 19:59:32,338 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 19:59:32,338 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4500 states and 6391 transitions. [2021-12-06 19:59:32,364 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4372 [2021-12-06 19:59:32,388 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4500 states to 4500 states and 6391 transitions. [2021-12-06 19:59:32,389 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4500 [2021-12-06 19:59:32,392 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4500 [2021-12-06 19:59:32,392 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4500 states and 6391 transitions. [2021-12-06 19:59:32,397 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:59:32,397 INFO L681 BuchiCegarLoop]: Abstraction has 4500 states and 6391 transitions. [2021-12-06 19:59:32,400 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4500 states and 6391 transitions. [2021-12-06 19:59:32,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4500 to 2614. [2021-12-06 19:59:32,437 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2614 states, 2614 states have (on average 1.4154552410099464) internal successors, (3700), 2613 states have internal predecessors, (3700), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:32,444 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2614 states to 2614 states and 3700 transitions. [2021-12-06 19:59:32,444 INFO L704 BuchiCegarLoop]: Abstraction has 2614 states and 3700 transitions. [2021-12-06 19:59:32,444 INFO L587 BuchiCegarLoop]: Abstraction has 2614 states and 3700 transitions. [2021-12-06 19:59:32,444 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-06 19:59:32,445 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2614 states and 3700 transitions. [2021-12-06 19:59:32,450 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2500 [2021-12-06 19:59:32,451 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:59:32,451 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:59:32,452 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:32,452 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:32,452 INFO L791 eck$LassoCheckResult]: Stem: 22496#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 22410#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 22012#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22013#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22134#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 22250#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22096#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22097#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22109#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22110#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22155#L502 assume !(0 == ~M_E~0); 22156#L502-2 assume !(0 == ~T1_E~0); 22085#L507-1 assume !(0 == ~T2_E~0); 22086#L512-1 assume !(0 == ~T3_E~0); 22253#L517-1 assume !(0 == ~T4_E~0); 22057#L522-1 assume !(0 == ~E_1~0); 22058#L527-1 assume !(0 == ~E_2~0); 22272#L532-1 assume 0 == ~E_3~0;~E_3~0 := 1; 22403#L537-1 assume !(0 == ~E_4~0); 22470#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22389#L238 assume !(1 == ~m_pc~0); 22390#L238-2 is_master_triggered_~__retres1~0#1 := 0; 22023#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22024#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 22363#L615 assume !(0 != activate_threads_~tmp~1#1); 22364#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22328#L257 assume !(1 == ~t1_pc~0); 22329#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22385#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22386#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 22518#L623 assume !(0 != activate_threads_~tmp___0~0#1); 22118#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22119#L276 assume !(1 == ~t2_pc~0); 22281#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 22282#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22111#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 22112#L631 assume !(0 != activate_threads_~tmp___1~0#1); 22468#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22469#L295 assume !(1 == ~t3_pc~0); 22130#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22131#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22455#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 22456#L639 assume !(0 != activate_threads_~tmp___2~0#1); 22391#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22392#L314 assume !(1 == ~t4_pc~0); 22168#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22167#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22397#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 22398#L647 assume !(0 != activate_threads_~tmp___3~0#1); 22266#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22267#L555 assume !(1 == ~M_E~0); 22180#L555-2 assume !(1 == ~T1_E~0); 22181#L560-1 assume !(1 == ~T2_E~0); 22059#L565-1 assume !(1 == ~T3_E~0); 22060#L570-1 assume !(1 == ~T4_E~0); 22517#L575-1 assume !(1 == ~E_1~0); 22326#L580-1 assume !(1 == ~E_2~0); 22327#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 22143#L590-1 assume !(1 == ~E_4~0); 22132#L595-1 assume { :end_inline_reset_delta_events } true; 22133#L776-2 [2021-12-06 19:59:32,452 INFO L793 eck$LassoCheckResult]: Loop: 22133#L776-2 assume !false; 22100#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22101#L477 assume !false; 22190#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 22191#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 22031#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 22032#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 22073#L416 assume !(0 != eval_~tmp~0#1); 22075#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24521#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24520#L502-3 assume !(0 == ~M_E~0); 24519#L502-5 assume !(0 == ~T1_E~0); 24518#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 24517#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24516#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24515#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22330#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22331#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22437#L537-3 assume !(0 == ~E_4~0); 24504#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24501#L238-15 assume !(1 == ~m_pc~0); 24502#L238-17 is_master_triggered_~__retres1~0#1 := 0; 24485#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24486#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 24481#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24482#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24478#L257-15 assume !(1 == ~t1_pc~0); 23183#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 24473#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24474#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 24467#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 24468#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24462#L276-15 assume !(1 == ~t2_pc~0); 24464#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 24454#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24455#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 24449#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 24448#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24444#L295-15 assume !(1 == ~t3_pc~0); 23970#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 24441#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24442#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 22482#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22483#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24529#L314-15 assume 1 == ~t4_pc~0; 22288#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22289#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22503#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 22387#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22388#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22400#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22027#L555-5 assume !(1 == ~T1_E~0); 22028#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22368#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22369#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24526#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22021#L580-3 assume !(1 == ~E_2~0); 22022#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22178#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22179#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 22263#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 22105#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 22293#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 22356#L795 assume !(0 == start_simulation_~tmp~3#1); 22358#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 22382#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 22067#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 22210#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 22211#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24315#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22264#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 22265#L808 assume !(0 != start_simulation_~tmp___0~1#1); 22133#L776-2 [2021-12-06 19:59:32,452 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:32,452 INFO L85 PathProgramCache]: Analyzing trace with hash 1911925415, now seen corresponding path program 1 times [2021-12-06 19:59:32,453 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:32,453 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [6391128] [2021-12-06 19:59:32,453 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:32,453 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:32,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:59:32,471 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:59:32,471 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:59:32,471 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [6391128] [2021-12-06 19:59:32,471 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [6391128] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:59:32,471 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:59:32,472 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:59:32,472 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [672308384] [2021-12-06 19:59:32,472 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:59:32,472 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 19:59:32,472 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:32,473 INFO L85 PathProgramCache]: Analyzing trace with hash -15775971, now seen corresponding path program 3 times [2021-12-06 19:59:32,473 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:32,473 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [541026385] [2021-12-06 19:59:32,473 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:32,473 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:32,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:59:32,495 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:59:32,496 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:59:32,496 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [541026385] [2021-12-06 19:59:32,496 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [541026385] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:59:32,496 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:59:32,496 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:59:32,496 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1927310913] [2021-12-06 19:59:32,496 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:59:32,497 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:59:32,497 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:59:32,497 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 19:59:32,497 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 19:59:32,497 INFO L87 Difference]: Start difference. First operand 2614 states and 3700 transitions. cyclomatic complexity: 1088 Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:32,554 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:59:32,555 INFO L93 Difference]: Finished difference Result 4037 states and 5717 transitions. [2021-12-06 19:59:32,555 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 19:59:32,555 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4037 states and 5717 transitions. [2021-12-06 19:59:32,570 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3956 [2021-12-06 19:59:32,593 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4037 states to 4037 states and 5717 transitions. [2021-12-06 19:59:32,593 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4037 [2021-12-06 19:59:32,596 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4037 [2021-12-06 19:59:32,608 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4037 states and 5717 transitions. [2021-12-06 19:59:32,613 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:59:32,613 INFO L681 BuchiCegarLoop]: Abstraction has 4037 states and 5717 transitions. [2021-12-06 19:59:32,616 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4037 states and 5717 transitions. [2021-12-06 19:59:32,646 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4037 to 2201. [2021-12-06 19:59:32,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2201 states, 2201 states have (on average 1.408905043162199) internal successors, (3101), 2200 states have internal predecessors, (3101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:32,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2201 states to 2201 states and 3101 transitions. [2021-12-06 19:59:32,655 INFO L704 BuchiCegarLoop]: Abstraction has 2201 states and 3101 transitions. [2021-12-06 19:59:32,655 INFO L587 BuchiCegarLoop]: Abstraction has 2201 states and 3101 transitions. [2021-12-06 19:59:32,655 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-06 19:59:32,656 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2201 states and 3101 transitions. [2021-12-06 19:59:32,661 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2132 [2021-12-06 19:59:32,662 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:59:32,662 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:59:32,663 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:32,663 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:32,663 INFO L791 eck$LassoCheckResult]: Stem: 29102#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 29045#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 28673#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28674#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28793#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 28906#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28757#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28758#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28770#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28771#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28814#L502 assume !(0 == ~M_E~0); 28815#L502-2 assume !(0 == ~T1_E~0); 28746#L507-1 assume !(0 == ~T2_E~0); 28747#L512-1 assume !(0 == ~T3_E~0); 28909#L517-1 assume !(0 == ~T4_E~0); 28718#L522-1 assume !(0 == ~E_1~0); 28719#L527-1 assume !(0 == ~E_2~0); 28929#L532-1 assume !(0 == ~E_3~0); 29037#L537-1 assume !(0 == ~E_4~0); 29061#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29026#L238 assume !(1 == ~m_pc~0); 29027#L238-2 is_master_triggered_~__retres1~0#1 := 0; 28684#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28685#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 29006#L615 assume !(0 != activate_threads_~tmp~1#1); 28705#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28706#L257 assume !(1 == ~t1_pc~0); 28822#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28823#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28858#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 28678#L623 assume !(0 != activate_threads_~tmp___0~0#1); 28679#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28675#L276 assume !(1 == ~t2_pc~0); 28676#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 28939#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28772#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 28773#L631 assume !(0 != activate_threads_~tmp___1~0#1); 29076#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29002#L295 assume !(1 == ~t3_pc~0); 28789#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 28790#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28984#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 29038#L639 assume !(0 != activate_threads_~tmp___2~0#1); 29028#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29029#L314 assume !(1 == ~t4_pc~0); 28827#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 28826#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29032#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 28975#L647 assume !(0 != activate_threads_~tmp___3~0#1); 28922#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28923#L555 assume !(1 == ~M_E~0); 28839#L555-2 assume !(1 == ~T1_E~0); 28840#L560-1 assume !(1 == ~T2_E~0); 28720#L565-1 assume !(1 == ~T3_E~0); 28721#L570-1 assume !(1 == ~T4_E~0); 28800#L575-1 assume !(1 == ~E_1~0); 28801#L580-1 assume !(1 == ~E_2~0); 28976#L585-1 assume !(1 == ~E_3~0); 28802#L590-1 assume !(1 == ~E_4~0); 28791#L595-1 assume { :end_inline_reset_delta_events } true; 28792#L776-2 [2021-12-06 19:59:32,663 INFO L793 eck$LassoCheckResult]: Loop: 28792#L776-2 assume !false; 30076#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30068#L477 assume !false; 30064#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 30035#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 30031#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 30029#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 30026#L416 assume !(0 != eval_~tmp~0#1); 30027#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30754#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30751#L502-3 assume !(0 == ~M_E~0); 30749#L502-5 assume !(0 == ~T1_E~0); 30747#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30745#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30743#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30741#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30740#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30738#L532-3 assume !(0 == ~E_3~0); 30736#L537-3 assume !(0 == ~E_4~0); 30734#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30732#L238-15 assume !(1 == ~m_pc~0); 30731#L238-17 is_master_triggered_~__retres1~0#1 := 0; 30730#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30729#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 30728#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30727#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30725#L257-15 assume !(1 == ~t1_pc~0); 30487#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 30718#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30712#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 30711#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30710#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30708#L276-15 assume !(1 == ~t2_pc~0); 30704#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 30699#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30695#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 30694#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 30690#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28787#L295-15 assume !(1 == ~t3_pc~0); 28788#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 30630#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30628#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 30626#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30624#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30622#L314-15 assume 1 == ~t4_pc~0; 30619#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30618#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30616#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 30614#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30612#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30610#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 30606#L555-5 assume !(1 == ~T1_E~0); 28854#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28855#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29010#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28969#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28682#L580-3 assume !(1 == ~E_2~0); 28683#L585-3 assume !(1 == ~E_3~0); 28837#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28838#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 28920#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 28766#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 28949#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 28999#L795 assume !(0 == start_simulation_~tmp~3#1); 29001#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 29021#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 28728#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 30529#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 30502#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30501#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30500#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 30093#L808 assume !(0 != start_simulation_~tmp___0~1#1); 28792#L776-2 [2021-12-06 19:59:32,664 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:32,664 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 1 times [2021-12-06 19:59:32,664 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:32,664 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2121629145] [2021-12-06 19:59:32,664 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:32,664 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:32,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:59:32,672 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 19:59:32,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:59:32,708 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 19:59:32,708 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:32,709 INFO L85 PathProgramCache]: Analyzing trace with hash 91145761, now seen corresponding path program 1 times [2021-12-06 19:59:32,709 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:32,709 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [94685765] [2021-12-06 19:59:32,709 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:32,709 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:32,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:59:32,735 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:59:32,735 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:59:32,735 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [94685765] [2021-12-06 19:59:32,735 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [94685765] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:59:32,736 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:59:32,736 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:59:32,736 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1010771228] [2021-12-06 19:59:32,736 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:59:32,737 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:59:32,737 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:59:32,737 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 19:59:32,737 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 19:59:32,738 INFO L87 Difference]: Start difference. First operand 2201 states and 3101 transitions. cyclomatic complexity: 902 Second operand has 3 states, 3 states have (on average 24.0) internal successors, (72), 3 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:32,787 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:59:32,788 INFO L93 Difference]: Finished difference Result 3747 states and 5242 transitions. [2021-12-06 19:59:32,788 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 19:59:32,789 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3747 states and 5242 transitions. [2021-12-06 19:59:32,806 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3632 [2021-12-06 19:59:32,829 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3747 states to 3747 states and 5242 transitions. [2021-12-06 19:59:32,829 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3747 [2021-12-06 19:59:32,833 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3747 [2021-12-06 19:59:32,833 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3747 states and 5242 transitions. [2021-12-06 19:59:32,839 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:59:32,839 INFO L681 BuchiCegarLoop]: Abstraction has 3747 states and 5242 transitions. [2021-12-06 19:59:32,842 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3747 states and 5242 transitions. [2021-12-06 19:59:32,875 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3747 to 3743. [2021-12-06 19:59:32,882 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3743 states, 3743 states have (on average 1.3994122361741919) internal successors, (5238), 3742 states have internal predecessors, (5238), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:32,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3743 states to 3743 states and 5238 transitions. [2021-12-06 19:59:32,889 INFO L704 BuchiCegarLoop]: Abstraction has 3743 states and 5238 transitions. [2021-12-06 19:59:32,889 INFO L587 BuchiCegarLoop]: Abstraction has 3743 states and 5238 transitions. [2021-12-06 19:59:32,889 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-06 19:59:32,889 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3743 states and 5238 transitions. [2021-12-06 19:59:32,898 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3628 [2021-12-06 19:59:32,898 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:59:32,898 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:59:32,899 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:32,899 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:32,900 INFO L791 eck$LassoCheckResult]: Stem: 35081#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 35010#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 34627#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34628#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34750#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 34863#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34710#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34711#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34723#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34724#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34767#L502 assume !(0 == ~M_E~0); 34768#L502-2 assume !(0 == ~T1_E~0); 34702#L507-1 assume !(0 == ~T2_E~0); 34703#L512-1 assume !(0 == ~T3_E~0); 34865#L517-1 assume !(0 == ~T4_E~0); 34681#L522-1 assume !(0 == ~E_1~0); 34682#L527-1 assume 0 == ~E_2~0;~E_2~0 := 1; 34884#L532-1 assume !(0 == ~E_3~0); 34999#L537-1 assume !(0 == ~E_4~0); 35111#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35110#L238 assume !(1 == ~m_pc~0); 35109#L238-2 is_master_triggered_~__retres1~0#1 := 0; 35108#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35107#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 35106#L615 assume !(0 != activate_threads_~tmp~1#1); 34663#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34664#L257 assume !(1 == ~t1_pc~0); 34934#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 35104#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35103#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 35102#L623 assume !(0 != activate_threads_~tmp___0~0#1); 35101#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34629#L276 assume !(1 == ~t2_pc~0); 34630#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 34898#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34725#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 34726#L631 assume !(0 != activate_threads_~tmp___1~0#1); 35061#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34962#L295 assume !(1 == ~t3_pc~0); 34742#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 34743#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34944#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 35117#L639 assume !(0 != activate_threads_~tmp___2~0#1); 35116#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35073#L314 assume !(1 == ~t4_pc~0); 35074#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 35034#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34993#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 34994#L647 assume !(0 != activate_threads_~tmp___3~0#1); 34877#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34878#L555 assume !(1 == ~M_E~0); 35087#L555-2 assume !(1 == ~T1_E~0); 35098#L560-1 assume !(1 == ~T2_E~0); 35097#L565-1 assume !(1 == ~T3_E~0); 35096#L570-1 assume !(1 == ~T4_E~0); 35095#L575-1 assume !(1 == ~E_1~0); 34932#L580-1 assume 1 == ~E_2~0;~E_2~0 := 2; 34933#L585-1 assume !(1 == ~E_3~0); 34755#L590-1 assume !(1 == ~E_4~0); 34744#L595-1 assume { :end_inline_reset_delta_events } true; 34745#L776-2 [2021-12-06 19:59:32,900 INFO L793 eck$LassoCheckResult]: Loop: 34745#L776-2 assume !false; 34714#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34715#L477 assume !false; 34804#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 34805#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 34648#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 34649#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 34687#L416 assume !(0 != eval_~tmp~0#1); 34689#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 38350#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 38348#L502-3 assume !(0 == ~M_E~0); 38346#L502-5 assume !(0 == ~T1_E~0); 38344#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38342#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38331#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 38330#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 38327#L527-3 assume !(0 == ~E_2~0); 38326#L532-3 assume !(0 == ~E_3~0); 38325#L537-3 assume !(0 == ~E_4~0); 38323#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38321#L238-15 assume !(1 == ~m_pc~0); 38320#L238-17 is_master_triggered_~__retres1~0#1 := 0; 34975#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34976#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 34773#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 34774#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34704#L257-15 assume !(1 == ~t1_pc~0); 34705#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 34906#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35025#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 34967#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34968#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34981#L276-15 assume 1 == ~t2_pc~0; 35070#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38223#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38221#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 38193#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38191#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38189#L295-15 assume !(1 == ~t3_pc~0); 37658#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 38186#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38184#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 38182#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38180#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38178#L314-15 assume 1 == ~t4_pc~0; 38174#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 38172#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38170#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 38168#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 38166#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38164#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 38162#L555-5 assume !(1 == ~T1_E~0); 38160#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38158#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38156#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 38154#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 38153#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38151#L585-3 assume !(1 == ~E_3~0); 38150#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 38149#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 38145#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 38141#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 38139#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 34957#L795 assume !(0 == start_simulation_~tmp~3#1); 34959#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 34982#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 34676#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 34823#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 34824#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34800#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34801#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 34874#L808 assume !(0 != start_simulation_~tmp___0~1#1); 34745#L776-2 [2021-12-06 19:59:32,900 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:32,900 INFO L85 PathProgramCache]: Analyzing trace with hash -1231104977, now seen corresponding path program 1 times [2021-12-06 19:59:32,900 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:32,900 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1784722576] [2021-12-06 19:59:32,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:32,900 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:32,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:59:32,929 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:59:32,929 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:59:32,929 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1784722576] [2021-12-06 19:59:32,929 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1784722576] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:59:32,929 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:59:32,929 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 19:59:32,929 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2086223862] [2021-12-06 19:59:32,929 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:59:32,929 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 19:59:32,930 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:32,930 INFO L85 PathProgramCache]: Analyzing trace with hash 1147264452, now seen corresponding path program 1 times [2021-12-06 19:59:32,930 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:32,930 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [870981079] [2021-12-06 19:59:32,930 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:32,930 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:32,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:59:32,953 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:59:32,953 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:59:32,953 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [870981079] [2021-12-06 19:59:32,953 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [870981079] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:59:32,954 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:59:32,954 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 19:59:32,954 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1242790455] [2021-12-06 19:59:32,954 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:59:32,954 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:59:32,954 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:59:32,954 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 19:59:32,954 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 19:59:32,955 INFO L87 Difference]: Start difference. First operand 3743 states and 5238 transitions. cyclomatic complexity: 1497 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:32,980 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:59:32,981 INFO L93 Difference]: Finished difference Result 2102 states and 2906 transitions. [2021-12-06 19:59:32,981 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 19:59:32,981 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2102 states and 2906 transitions. [2021-12-06 19:59:32,988 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2036 [2021-12-06 19:59:32,995 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2102 states to 2102 states and 2906 transitions. [2021-12-06 19:59:32,995 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2102 [2021-12-06 19:59:32,997 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2102 [2021-12-06 19:59:32,997 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2102 states and 2906 transitions. [2021-12-06 19:59:32,999 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:59:32,999 INFO L681 BuchiCegarLoop]: Abstraction has 2102 states and 2906 transitions. [2021-12-06 19:59:33,001 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2102 states and 2906 transitions. [2021-12-06 19:59:33,019 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2102 to 2102. [2021-12-06 19:59:33,023 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2102 states, 2102 states have (on average 1.3824928639391056) internal successors, (2906), 2101 states have internal predecessors, (2906), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:33,027 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2102 states to 2102 states and 2906 transitions. [2021-12-06 19:59:33,027 INFO L704 BuchiCegarLoop]: Abstraction has 2102 states and 2906 transitions. [2021-12-06 19:59:33,027 INFO L587 BuchiCegarLoop]: Abstraction has 2102 states and 2906 transitions. [2021-12-06 19:59:33,027 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-06 19:59:33,027 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2102 states and 2906 transitions. [2021-12-06 19:59:33,032 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2036 [2021-12-06 19:59:33,032 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:59:33,032 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:59:33,033 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:33,033 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:33,033 INFO L791 eck$LassoCheckResult]: Stem: 40897#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 40839#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 40481#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40482#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 40599#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 40711#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40564#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40565#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40577#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40578#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40620#L502 assume !(0 == ~M_E~0); 40621#L502-2 assume !(0 == ~T1_E~0); 40553#L507-1 assume !(0 == ~T2_E~0); 40554#L512-1 assume !(0 == ~T3_E~0); 40714#L517-1 assume !(0 == ~T4_E~0); 40526#L522-1 assume !(0 == ~E_1~0); 40527#L527-1 assume !(0 == ~E_2~0); 40734#L532-1 assume !(0 == ~E_3~0); 40832#L537-1 assume !(0 == ~E_4~0); 40852#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40822#L238 assume !(1 == ~m_pc~0); 40823#L238-2 is_master_triggered_~__retres1~0#1 := 0; 40492#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40493#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 40803#L615 assume !(0 != activate_threads_~tmp~1#1); 40513#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40514#L257 assume !(1 == ~t1_pc~0); 40628#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 40629#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40664#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 40486#L623 assume !(0 != activate_threads_~tmp___0~0#1); 40487#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40483#L276 assume !(1 == ~t2_pc~0); 40484#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 40743#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40579#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 40580#L631 assume !(0 != activate_threads_~tmp___1~0#1); 40867#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40799#L295 assume !(1 == ~t3_pc~0); 40595#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 40596#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40786#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 40833#L639 assume !(0 != activate_threads_~tmp___2~0#1); 40824#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40825#L314 assume !(1 == ~t4_pc~0); 40633#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 40632#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40827#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 40779#L647 assume !(0 != activate_threads_~tmp___3~0#1); 40728#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40729#L555 assume !(1 == ~M_E~0); 40645#L555-2 assume !(1 == ~T1_E~0); 40646#L560-1 assume !(1 == ~T2_E~0); 40528#L565-1 assume !(1 == ~T3_E~0); 40529#L570-1 assume !(1 == ~T4_E~0); 40606#L575-1 assume !(1 == ~E_1~0); 40607#L580-1 assume !(1 == ~E_2~0); 40780#L585-1 assume !(1 == ~E_3~0); 40608#L590-1 assume !(1 == ~E_4~0); 40597#L595-1 assume { :end_inline_reset_delta_events } true; 40598#L776-2 [2021-12-06 19:59:33,033 INFO L793 eck$LassoCheckResult]: Loop: 40598#L776-2 assume !false; 40568#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40569#L477 assume !false; 40655#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 40656#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 40500#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 40501#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 40541#L416 assume !(0 != eval_~tmp~0#1); 40543#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40836#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40760#L502-3 assume !(0 == ~M_E~0); 40761#L502-5 assume !(0 == ~T1_E~0); 40789#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 40706#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40707#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40691#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 40692#L527-3 assume !(0 == ~E_2~0); 40781#L532-3 assume !(0 == ~E_3~0); 40709#L537-3 assume !(0 == ~E_4~0); 40710#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40720#L238-15 assume !(1 == ~m_pc~0); 40773#L238-17 is_master_triggered_~__retres1~0#1 := 0; 40820#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42571#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 42570#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 42569#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42530#L257-15 assume !(1 == ~t1_pc~0); 42403#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 40856#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40857#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 40804#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40805#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40816#L276-15 assume !(1 == ~t2_pc~0); 40689#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 40672#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40673#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 40902#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 40903#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40593#L295-15 assume !(1 == ~t3_pc~0); 40594#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 42479#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42478#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 42477#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 42476#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42475#L314-15 assume 1 == ~t4_pc~0; 42473#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 42472#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42471#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 42470#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 42469#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42468#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 42467#L555-5 assume !(1 == ~T1_E~0); 42357#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42356#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42355#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 42354#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 42353#L580-3 assume !(1 == ~E_2~0); 42352#L585-3 assume !(1 == ~E_3~0); 40643#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 40644#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 40726#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 40573#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 40752#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 40796#L795 assume !(0 == start_simulation_~tmp~3#1); 40798#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 40817#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 40536#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 40674#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 40675#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40651#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40652#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 40727#L808 assume !(0 != start_simulation_~tmp___0~1#1); 40598#L776-2 [2021-12-06 19:59:33,033 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:33,034 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 2 times [2021-12-06 19:59:33,034 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:33,034 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [493315406] [2021-12-06 19:59:33,034 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:33,034 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:33,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:59:33,040 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 19:59:33,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:59:33,057 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 19:59:33,057 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:33,057 INFO L85 PathProgramCache]: Analyzing trace with hash 131820511, now seen corresponding path program 1 times [2021-12-06 19:59:33,057 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:33,057 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1072798684] [2021-12-06 19:59:33,058 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:33,058 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:33,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:59:33,080 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:59:33,080 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:59:33,080 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1072798684] [2021-12-06 19:59:33,080 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1072798684] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:59:33,080 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:59:33,081 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 19:59:33,081 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1342689425] [2021-12-06 19:59:33,081 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:59:33,081 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:59:33,081 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:59:33,081 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-06 19:59:33,081 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-06 19:59:33,082 INFO L87 Difference]: Start difference. First operand 2102 states and 2906 transitions. cyclomatic complexity: 806 Second operand has 5 states, 5 states have (on average 14.4) internal successors, (72), 5 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:33,161 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:59:33,161 INFO L93 Difference]: Finished difference Result 3666 states and 4994 transitions. [2021-12-06 19:59:33,162 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-06 19:59:33,162 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3666 states and 4994 transitions. [2021-12-06 19:59:33,179 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3596 [2021-12-06 19:59:33,197 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3666 states to 3666 states and 4994 transitions. [2021-12-06 19:59:33,197 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3666 [2021-12-06 19:59:33,200 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3666 [2021-12-06 19:59:33,200 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3666 states and 4994 transitions. [2021-12-06 19:59:33,205 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:59:33,205 INFO L681 BuchiCegarLoop]: Abstraction has 3666 states and 4994 transitions. [2021-12-06 19:59:33,209 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3666 states and 4994 transitions. [2021-12-06 19:59:33,248 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3666 to 2126. [2021-12-06 19:59:33,252 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2126 states, 2126 states have (on average 1.3781749764816558) internal successors, (2930), 2125 states have internal predecessors, (2930), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:33,257 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2126 states to 2126 states and 2930 transitions. [2021-12-06 19:59:33,257 INFO L704 BuchiCegarLoop]: Abstraction has 2126 states and 2930 transitions. [2021-12-06 19:59:33,257 INFO L587 BuchiCegarLoop]: Abstraction has 2126 states and 2930 transitions. [2021-12-06 19:59:33,257 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-06 19:59:33,257 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2126 states and 2930 transitions. [2021-12-06 19:59:33,264 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2060 [2021-12-06 19:59:33,264 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:59:33,264 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:59:33,265 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:33,265 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:33,265 INFO L791 eck$LassoCheckResult]: Stem: 46704#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 46636#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 46265#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46266#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46382#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 46494#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46347#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46348#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46360#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46361#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46403#L502 assume !(0 == ~M_E~0); 46404#L502-2 assume !(0 == ~T1_E~0); 46336#L507-1 assume !(0 == ~T2_E~0); 46337#L512-1 assume !(0 == ~T3_E~0); 46497#L517-1 assume !(0 == ~T4_E~0); 46310#L522-1 assume !(0 == ~E_1~0); 46311#L527-1 assume !(0 == ~E_2~0); 46517#L532-1 assume !(0 == ~E_3~0); 46628#L537-1 assume !(0 == ~E_4~0); 46652#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46616#L238 assume !(1 == ~m_pc~0); 46617#L238-2 is_master_triggered_~__retres1~0#1 := 0; 46276#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46277#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 46594#L615 assume !(0 != activate_threads_~tmp~1#1); 46297#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46298#L257 assume !(1 == ~t1_pc~0); 46411#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46412#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46447#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 46270#L623 assume !(0 != activate_threads_~tmp___0~0#1); 46271#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46267#L276 assume !(1 == ~t2_pc~0); 46268#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 46526#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46362#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 46363#L631 assume !(0 != activate_threads_~tmp___1~0#1); 46667#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46590#L295 assume !(1 == ~t3_pc~0); 46378#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 46379#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46574#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 46629#L639 assume !(0 != activate_threads_~tmp___2~0#1); 46618#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46619#L314 assume !(1 == ~t4_pc~0); 46416#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 46415#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46622#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 46567#L647 assume !(0 != activate_threads_~tmp___3~0#1); 46509#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46510#L555 assume !(1 == ~M_E~0); 46428#L555-2 assume !(1 == ~T1_E~0); 46429#L560-1 assume !(1 == ~T2_E~0); 46312#L565-1 assume !(1 == ~T3_E~0); 46313#L570-1 assume !(1 == ~T4_E~0); 46389#L575-1 assume !(1 == ~E_1~0); 46390#L580-1 assume !(1 == ~E_2~0); 46568#L585-1 assume !(1 == ~E_3~0); 46391#L590-1 assume !(1 == ~E_4~0); 46380#L595-1 assume { :end_inline_reset_delta_events } true; 46381#L776-2 [2021-12-06 19:59:33,265 INFO L793 eck$LassoCheckResult]: Loop: 46381#L776-2 assume !false; 47962#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47958#L477 assume !false; 47516#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 47514#L374 assume !(0 == ~m_st~0); 47487#L378 assume !(0 == ~t1_st~0); 47486#L382 assume !(0 == ~t2_st~0); 47485#L386 assume !(0 == ~t3_st~0); 47368#L390 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 47361#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 47358#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 47354#L416 assume !(0 != eval_~tmp~0#1); 47355#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 48212#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 48211#L502-3 assume !(0 == ~M_E~0); 48210#L502-5 assume !(0 == ~T1_E~0); 48209#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 48208#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46717#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 46474#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 46475#L527-3 assume !(0 == ~E_2~0); 46569#L532-3 assume !(0 == ~E_3~0); 46492#L537-3 assume !(0 == ~E_4~0); 46493#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46502#L238-15 assume !(1 == ~m_pc~0); 46561#L238-17 is_master_triggered_~__retres1~0#1 := 0; 46603#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46604#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 46690#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 46683#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46684#L257-15 assume !(1 == ~t1_pc~0); 48085#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 48146#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48145#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 48144#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 48143#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 48142#L276-15 assume !(1 == ~t2_pc~0); 48140#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 48139#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48138#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 48137#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 48136#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48135#L295-15 assume !(1 == ~t3_pc~0); 47685#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 48134#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48133#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 48132#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 48131#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48130#L314-15 assume 1 == ~t4_pc~0; 48128#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 48127#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48126#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 48125#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 48124#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48123#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 48122#L555-5 assume !(1 == ~T1_E~0); 48121#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48120#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 48119#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 48118#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 48117#L580-3 assume !(1 == ~E_2~0); 48115#L585-3 assume !(1 == ~E_3~0); 48114#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 48113#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 48110#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 48106#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 48104#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 48103#L795 assume !(0 == start_simulation_~tmp~3#1); 48100#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 47981#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 47977#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 47975#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 47973#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 47972#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 47971#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 47970#L808 assume !(0 != start_simulation_~tmp___0~1#1); 46381#L776-2 [2021-12-06 19:59:33,266 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:33,266 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 3 times [2021-12-06 19:59:33,266 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:33,266 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [679305035] [2021-12-06 19:59:33,266 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:33,266 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:33,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:59:33,272 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 19:59:33,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:59:33,284 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 19:59:33,284 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:33,284 INFO L85 PathProgramCache]: Analyzing trace with hash -2111704621, now seen corresponding path program 1 times [2021-12-06 19:59:33,285 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:33,285 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1016264113] [2021-12-06 19:59:33,285 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:33,285 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:33,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:59:33,325 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:59:33,325 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:59:33,325 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1016264113] [2021-12-06 19:59:33,325 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1016264113] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:59:33,325 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:59:33,325 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 19:59:33,325 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [282551292] [2021-12-06 19:59:33,326 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:59:33,326 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:59:33,326 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:59:33,326 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-06 19:59:33,326 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-06 19:59:33,326 INFO L87 Difference]: Start difference. First operand 2126 states and 2930 transitions. cyclomatic complexity: 806 Second operand has 5 states, 5 states have (on average 15.2) internal successors, (76), 5 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:33,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:59:33,423 INFO L93 Difference]: Finished difference Result 4194 states and 5727 transitions. [2021-12-06 19:59:33,423 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-06 19:59:33,424 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4194 states and 5727 transitions. [2021-12-06 19:59:33,436 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4128 [2021-12-06 19:59:33,445 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4194 states to 4194 states and 5727 transitions. [2021-12-06 19:59:33,445 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4194 [2021-12-06 19:59:33,447 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4194 [2021-12-06 19:59:33,447 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4194 states and 5727 transitions. [2021-12-06 19:59:33,451 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:59:33,451 INFO L681 BuchiCegarLoop]: Abstraction has 4194 states and 5727 transitions. [2021-12-06 19:59:33,454 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4194 states and 5727 transitions. [2021-12-06 19:59:33,476 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4194 to 2186. [2021-12-06 19:59:33,479 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2186 states, 2186 states have (on average 1.360018298261665) internal successors, (2973), 2185 states have internal predecessors, (2973), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:33,482 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2186 states to 2186 states and 2973 transitions. [2021-12-06 19:59:33,483 INFO L704 BuchiCegarLoop]: Abstraction has 2186 states and 2973 transitions. [2021-12-06 19:59:33,483 INFO L587 BuchiCegarLoop]: Abstraction has 2186 states and 2973 transitions. [2021-12-06 19:59:33,483 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-06 19:59:33,483 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2186 states and 2973 transitions. [2021-12-06 19:59:33,487 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2120 [2021-12-06 19:59:33,487 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:59:33,487 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:59:33,488 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:33,488 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:33,488 INFO L791 eck$LassoCheckResult]: Stem: 53051#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 52983#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 52598#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 52599#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 52720#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 52835#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 52681#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 52682#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 52694#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 52695#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 52737#L502 assume !(0 == ~M_E~0); 52738#L502-2 assume !(0 == ~T1_E~0); 52673#L507-1 assume !(0 == ~T2_E~0); 52674#L512-1 assume !(0 == ~T3_E~0); 52837#L517-1 assume !(0 == ~T4_E~0); 52653#L522-1 assume !(0 == ~E_1~0); 52654#L527-1 assume !(0 == ~E_2~0); 52860#L532-1 assume !(0 == ~E_3~0); 52971#L537-1 assume !(0 == ~E_4~0); 52996#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52960#L238 assume !(1 == ~m_pc~0); 52961#L238-2 is_master_triggered_~__retres1~0#1 := 0; 52611#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52612#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 52936#L615 assume !(0 != activate_threads_~tmp~1#1); 52634#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52635#L257 assume !(1 == ~t1_pc~0); 52745#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 52746#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52783#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 52605#L623 assume !(0 != activate_threads_~tmp___0~0#1); 52606#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52600#L276 assume !(1 == ~t2_pc~0); 52601#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 52874#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52696#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 52697#L631 assume !(0 != activate_threads_~tmp___1~0#1); 53014#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52935#L295 assume !(1 == ~t3_pc~0); 52712#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 52713#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52920#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 52973#L639 assume !(0 != activate_threads_~tmp___2~0#1); 52964#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 52965#L314 assume !(1 == ~t4_pc~0); 52750#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 52749#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 52966#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 52912#L647 assume !(0 != activate_threads_~tmp___3~0#1); 52851#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52852#L555 assume !(1 == ~M_E~0); 52762#L555-2 assume !(1 == ~T1_E~0); 52763#L560-1 assume !(1 == ~T2_E~0); 52655#L565-1 assume !(1 == ~T3_E~0); 52656#L570-1 assume !(1 == ~T4_E~0); 52723#L575-1 assume !(1 == ~E_1~0); 52724#L580-1 assume !(1 == ~E_2~0); 52913#L585-1 assume !(1 == ~E_3~0); 52725#L590-1 assume !(1 == ~E_4~0); 52714#L595-1 assume { :end_inline_reset_delta_events } true; 52715#L776-2 [2021-12-06 19:59:33,488 INFO L793 eck$LassoCheckResult]: Loop: 52715#L776-2 assume !false; 53906#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53903#L477 assume !false; 53902#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 53898#L374 assume !(0 == ~m_st~0); 53899#L378 assume !(0 == ~t1_st~0); 53901#L382 assume !(0 == ~t2_st~0); 53896#L386 assume !(0 == ~t3_st~0); 53897#L390 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 53900#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 53494#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 53495#L416 assume !(0 != eval_~tmp~0#1); 54227#L492 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 54226#L334-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 54225#L502-3 assume !(0 == ~M_E~0); 54224#L502-5 assume !(0 == ~T1_E~0); 54223#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 54222#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54221#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 54220#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 54219#L527-3 assume !(0 == ~E_2~0); 54218#L532-3 assume !(0 == ~E_3~0); 54217#L537-3 assume !(0 == ~E_4~0); 52844#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52845#L238-15 assume !(1 == ~m_pc~0); 52905#L238-17 is_master_triggered_~__retres1~0#1 := 0; 54006#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54005#L250-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 54004#L615-15 assume !(0 != activate_threads_~tmp~1#1); 54003#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54002#L257-15 assume !(1 == ~t1_pc~0); 53875#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 53999#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53997#L269-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 53995#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 53993#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53992#L276-15 assume !(1 == ~t2_pc~0); 53989#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 53987#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53985#L288-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 53983#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 53980#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53978#L295-15 assume !(1 == ~t3_pc~0); 53667#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 53975#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53973#L307-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 53971#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53969#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53968#L314-15 assume 1 == ~t4_pc~0; 53965#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53963#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53961#L326-5 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 53959#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 53957#L647-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53954#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 53952#L555-5 assume !(1 == ~T1_E~0); 53950#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 53948#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53946#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 53944#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 53942#L580-3 assume !(1 == ~E_2~0); 53940#L585-3 assume !(1 == ~E_3~0); 53938#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53936#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 53932#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 53928#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 53926#L402-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 53924#L795 assume !(0 == start_simulation_~tmp~3#1); 53922#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 53919#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 53916#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 53915#L402-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 53914#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 53913#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 53911#L758 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 53909#L808 assume !(0 != start_simulation_~tmp___0~1#1); 52715#L776-2 [2021-12-06 19:59:33,489 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:33,489 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 4 times [2021-12-06 19:59:33,489 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:33,489 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [366858558] [2021-12-06 19:59:33,489 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:33,489 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:33,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:59:33,507 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 19:59:33,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:59:33,517 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 19:59:33,518 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:33,518 INFO L85 PathProgramCache]: Analyzing trace with hash -172542575, now seen corresponding path program 1 times [2021-12-06 19:59:33,518 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:33,518 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [313804438] [2021-12-06 19:59:33,518 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:33,518 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:33,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:59:33,535 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:59:33,535 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:59:33,535 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [313804438] [2021-12-06 19:59:33,535 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [313804438] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:59:33,535 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:59:33,535 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:59:33,535 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1421729174] [2021-12-06 19:59:33,536 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:59:33,536 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 19:59:33,536 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:59:33,536 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 19:59:33,536 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 19:59:33,537 INFO L87 Difference]: Start difference. First operand 2186 states and 2973 transitions. cyclomatic complexity: 789 Second operand has 3 states, 3 states have (on average 25.333333333333332) internal successors, (76), 3 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:33,566 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:59:33,566 INFO L93 Difference]: Finished difference Result 3576 states and 4783 transitions. [2021-12-06 19:59:33,567 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 19:59:33,567 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3576 states and 4783 transitions. [2021-12-06 19:59:33,576 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3508 [2021-12-06 19:59:33,587 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3576 states to 3576 states and 4783 transitions. [2021-12-06 19:59:33,587 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3576 [2021-12-06 19:59:33,589 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3576 [2021-12-06 19:59:33,590 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3576 states and 4783 transitions. [2021-12-06 19:59:33,592 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:59:33,592 INFO L681 BuchiCegarLoop]: Abstraction has 3576 states and 4783 transitions. [2021-12-06 19:59:33,595 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3576 states and 4783 transitions. [2021-12-06 19:59:33,628 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3576 to 3452. [2021-12-06 19:59:33,632 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3452 states, 3452 states have (on average 1.3409617612977984) internal successors, (4629), 3451 states have internal predecessors, (4629), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:33,638 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3452 states to 3452 states and 4629 transitions. [2021-12-06 19:59:33,638 INFO L704 BuchiCegarLoop]: Abstraction has 3452 states and 4629 transitions. [2021-12-06 19:59:33,638 INFO L587 BuchiCegarLoop]: Abstraction has 3452 states and 4629 transitions. [2021-12-06 19:59:33,638 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-06 19:59:33,638 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3452 states and 4629 transitions. [2021-12-06 19:59:33,646 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3384 [2021-12-06 19:59:33,646 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:59:33,646 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:59:33,647 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:33,647 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:33,647 INFO L791 eck$LassoCheckResult]: Stem: 58796#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 58726#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 58366#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 58367#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 58486#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 58599#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 58449#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 58450#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 58462#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 58463#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 58505#L502 assume !(0 == ~M_E~0); 58506#L502-2 assume !(0 == ~T1_E~0); 58441#L507-1 assume !(0 == ~T2_E~0); 58442#L512-1 assume !(0 == ~T3_E~0); 58600#L517-1 assume !(0 == ~T4_E~0); 58417#L522-1 assume !(0 == ~E_1~0); 58418#L527-1 assume !(0 == ~E_2~0); 58620#L532-1 assume !(0 == ~E_3~0); 58717#L537-1 assume !(0 == ~E_4~0); 58743#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 58707#L238 assume !(1 == ~m_pc~0); 58708#L238-2 is_master_triggered_~__retres1~0#1 := 0; 58379#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58380#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 58687#L615 assume !(0 != activate_threads_~tmp~1#1); 58400#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 58401#L257 assume !(1 == ~t1_pc~0); 58513#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 58514#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 58549#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 58373#L623 assume !(0 != activate_threads_~tmp___0~0#1); 58374#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 58368#L276 assume !(1 == ~t2_pc~0); 58369#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 58632#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58464#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 58465#L631 assume !(0 != activate_threads_~tmp___1~0#1); 58757#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 58684#L295 assume !(1 == ~t3_pc~0); 58480#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 58481#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58671#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 58718#L639 assume !(0 != activate_threads_~tmp___2~0#1); 58711#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58712#L314 assume !(1 == ~t4_pc~0); 58518#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 58517#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58713#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 58661#L647 assume !(0 != activate_threads_~tmp___3~0#1); 58613#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 58614#L555 assume !(1 == ~M_E~0); 58531#L555-2 assume !(1 == ~T1_E~0); 58532#L560-1 assume !(1 == ~T2_E~0); 58419#L565-1 assume !(1 == ~T3_E~0); 58420#L570-1 assume !(1 == ~T4_E~0); 58491#L575-1 assume !(1 == ~E_1~0); 58492#L580-1 assume !(1 == ~E_2~0); 58662#L585-1 assume !(1 == ~E_3~0); 58493#L590-1 assume !(1 == ~E_4~0); 58482#L595-1 assume { :end_inline_reset_delta_events } true; 58483#L776-2 assume !false; 61620#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 61616#L477 [2021-12-06 19:59:33,647 INFO L793 eck$LassoCheckResult]: Loop: 61616#L477 assume !false; 61614#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 61612#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 61609#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 61607#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 61605#L416 assume 0 != eval_~tmp~0#1; 61589#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 58790#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 58791#L421 assume !(0 == ~t1_st~0); 61146#L435 assume !(0 == ~t2_st~0); 61519#L449 assume !(0 == ~t3_st~0); 58811#L463 assume !(0 == ~t4_st~0); 61616#L477 [2021-12-06 19:59:33,647 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:33,647 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 1 times [2021-12-06 19:59:33,647 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:33,647 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1368042209] [2021-12-06 19:59:33,648 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:33,648 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:33,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:59:33,653 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 19:59:33,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:59:33,663 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 19:59:33,664 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:33,664 INFO L85 PathProgramCache]: Analyzing trace with hash 839567500, now seen corresponding path program 1 times [2021-12-06 19:59:33,664 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:33,664 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [691135633] [2021-12-06 19:59:33,664 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:33,664 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:33,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:59:33,666 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 19:59:33,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:59:33,669 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 19:59:33,669 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:33,669 INFO L85 PathProgramCache]: Analyzing trace with hash -1729123880, now seen corresponding path program 1 times [2021-12-06 19:59:33,669 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:33,669 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [3280581] [2021-12-06 19:59:33,670 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:33,670 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:33,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:59:33,687 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:59:33,687 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:59:33,688 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [3280581] [2021-12-06 19:59:33,688 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [3280581] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:59:33,688 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:59:33,688 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:59:33,688 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [677957818] [2021-12-06 19:59:33,688 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:59:33,750 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:59:33,750 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 19:59:33,750 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 19:59:33,750 INFO L87 Difference]: Start difference. First operand 3452 states and 4629 transitions. cyclomatic complexity: 1180 Second operand has 3 states, 3 states have (on average 24.666666666666668) internal successors, (74), 3 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:33,808 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:59:33,808 INFO L93 Difference]: Finished difference Result 6396 states and 8469 transitions. [2021-12-06 19:59:33,808 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 19:59:33,809 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6396 states and 8469 transitions. [2021-12-06 19:59:33,834 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6266 [2021-12-06 19:59:33,857 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6396 states to 6396 states and 8469 transitions. [2021-12-06 19:59:33,857 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6396 [2021-12-06 19:59:33,862 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6396 [2021-12-06 19:59:33,862 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6396 states and 8469 transitions. [2021-12-06 19:59:33,866 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:59:33,867 INFO L681 BuchiCegarLoop]: Abstraction has 6396 states and 8469 transitions. [2021-12-06 19:59:33,872 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6396 states and 8469 transitions. [2021-12-06 19:59:33,931 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6396 to 6176. [2021-12-06 19:59:33,937 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6176 states, 6176 states have (on average 1.3272344559585492) internal successors, (8197), 6175 states have internal predecessors, (8197), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:33,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6176 states to 6176 states and 8197 transitions. [2021-12-06 19:59:33,948 INFO L704 BuchiCegarLoop]: Abstraction has 6176 states and 8197 transitions. [2021-12-06 19:59:33,948 INFO L587 BuchiCegarLoop]: Abstraction has 6176 states and 8197 transitions. [2021-12-06 19:59:33,948 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-06 19:59:33,948 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6176 states and 8197 transitions. [2021-12-06 19:59:33,962 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6046 [2021-12-06 19:59:33,962 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:59:33,962 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:59:33,962 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:33,963 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:33,963 INFO L791 eck$LassoCheckResult]: Stem: 68747#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 68639#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 68222#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 68223#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 68343#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 68464#L341-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 68720#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 68619#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 68620#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 68601#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 68602#L502 assume !(0 == ~M_E~0); 68536#L502-2 assume !(0 == ~T1_E~0); 68537#L507-1 assume !(0 == ~T2_E~0); 68466#L512-1 assume !(0 == ~T3_E~0); 68467#L517-1 assume !(0 == ~T4_E~0); 68275#L522-1 assume !(0 == ~E_1~0); 68276#L527-1 assume !(0 == ~E_2~0); 68627#L532-1 assume !(0 == ~E_3~0); 68628#L537-1 assume !(0 == ~E_4~0); 68656#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68657#L238 assume !(1 == ~m_pc~0); 68718#L238-2 is_master_triggered_~__retres1~0#1 := 0; 68719#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68711#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 68712#L615 assume !(0 != activate_threads_~tmp~1#1); 68258#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68259#L257 assume !(1 == ~t1_pc~0); 68372#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 68373#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68409#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 68410#L623 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 68230#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68224#L276 assume !(1 == ~t2_pc~0); 68225#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 68666#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68667#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 68678#L631 assume !(0 != activate_threads_~tmp___1~0#1); 68679#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68576#L295 assume !(1 == ~t3_pc~0); 68577#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 68559#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68560#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 68629#L639 assume !(0 != activate_threads_~tmp___2~0#1); 68630#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68738#L314 assume !(1 == ~t4_pc~0); 68739#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 68670#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68671#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 68544#L647 assume !(0 != activate_threads_~tmp___3~0#1); 68545#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68754#L555 assume !(1 == ~M_E~0); 68755#L555-2 assume !(1 == ~T1_E~0); 68734#L560-1 assume !(1 == ~T2_E~0); 68735#L565-1 assume !(1 == ~T3_E~0); 68562#L570-1 assume !(1 == ~T4_E~0); 68563#L575-1 assume !(1 == ~E_1~0); 68546#L580-1 assume !(1 == ~E_2~0); 68547#L585-1 assume !(1 == ~E_3~0); 68350#L590-1 assume !(1 == ~E_4~0); 68351#L595-1 assume { :end_inline_reset_delta_events } true; 69043#L776-2 assume !false; 69044#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 70642#L477 [2021-12-06 19:59:33,963 INFO L793 eck$LassoCheckResult]: Loop: 70642#L477 assume !false; 70641#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 70640#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 69026#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 69027#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 70638#L416 assume 0 != eval_~tmp~0#1; 69009#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 69006#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 69008#L421 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 70631#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 69052#L435 assume !(0 == ~t2_st~0); 69049#L449 assume !(0 == ~t3_st~0); 70644#L463 assume !(0 == ~t4_st~0); 70642#L477 [2021-12-06 19:59:33,963 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:33,963 INFO L85 PathProgramCache]: Analyzing trace with hash 995820945, now seen corresponding path program 1 times [2021-12-06 19:59:33,963 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:33,963 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1137866508] [2021-12-06 19:59:33,963 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:33,964 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:33,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:59:33,977 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:59:33,977 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:59:33,977 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1137866508] [2021-12-06 19:59:33,977 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1137866508] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:59:33,977 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:59:33,977 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:59:33,977 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1201305296] [2021-12-06 19:59:33,977 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:59:33,978 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 19:59:33,978 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:33,978 INFO L85 PathProgramCache]: Analyzing trace with hash 109617948, now seen corresponding path program 1 times [2021-12-06 19:59:33,978 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:33,978 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [798124322] [2021-12-06 19:59:33,978 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:33,978 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:33,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:59:33,981 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 19:59:33,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:59:33,983 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 19:59:34,047 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:59:34,047 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 19:59:34,047 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 19:59:34,047 INFO L87 Difference]: Start difference. First operand 6176 states and 8197 transitions. cyclomatic complexity: 2024 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:34,076 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:59:34,076 INFO L93 Difference]: Finished difference Result 6118 states and 8120 transitions. [2021-12-06 19:59:34,077 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 19:59:34,077 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6118 states and 8120 transitions. [2021-12-06 19:59:34,098 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6046 [2021-12-06 19:59:34,113 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6118 states to 6118 states and 8120 transitions. [2021-12-06 19:59:34,114 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6118 [2021-12-06 19:59:34,116 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6118 [2021-12-06 19:59:34,116 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6118 states and 8120 transitions. [2021-12-06 19:59:34,119 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:59:34,119 INFO L681 BuchiCegarLoop]: Abstraction has 6118 states and 8120 transitions. [2021-12-06 19:59:34,122 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6118 states and 8120 transitions. [2021-12-06 19:59:34,158 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6118 to 6118. [2021-12-06 19:59:34,165 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6118 states, 6118 states have (on average 1.3272311212814645) internal successors, (8120), 6117 states have internal predecessors, (8120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:34,176 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6118 states to 6118 states and 8120 transitions. [2021-12-06 19:59:34,177 INFO L704 BuchiCegarLoop]: Abstraction has 6118 states and 8120 transitions. [2021-12-06 19:59:34,177 INFO L587 BuchiCegarLoop]: Abstraction has 6118 states and 8120 transitions. [2021-12-06 19:59:34,177 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-06 19:59:34,177 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6118 states and 8120 transitions. [2021-12-06 19:59:34,190 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6046 [2021-12-06 19:59:34,190 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:59:34,190 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:59:34,191 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:34,191 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:34,191 INFO L791 eck$LassoCheckResult]: Stem: 80976#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 80898#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 80522#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 80523#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 80639#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 80755#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 80605#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 80606#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 80618#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 80619#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 80660#L502 assume !(0 == ~M_E~0); 80661#L502-2 assume !(0 == ~T1_E~0); 80594#L507-1 assume !(0 == ~T2_E~0); 80595#L512-1 assume !(0 == ~T3_E~0); 80758#L517-1 assume !(0 == ~T4_E~0); 80567#L522-1 assume !(0 == ~E_1~0); 80568#L527-1 assume !(0 == ~E_2~0); 80783#L532-1 assume !(0 == ~E_3~0); 80892#L537-1 assume !(0 == ~E_4~0); 80915#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 80883#L238 assume !(1 == ~m_pc~0); 80884#L238-2 is_master_triggered_~__retres1~0#1 := 0; 80533#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 80534#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 80862#L615 assume !(0 != activate_threads_~tmp~1#1); 80554#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 80555#L257 assume !(1 == ~t1_pc~0); 80668#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 80669#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 80705#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 80527#L623 assume !(0 != activate_threads_~tmp___0~0#1); 80528#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 80524#L276 assume !(1 == ~t2_pc~0); 80525#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 80793#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 80620#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 80621#L631 assume !(0 != activate_threads_~tmp___1~0#1); 80932#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 80858#L295 assume !(1 == ~t3_pc~0); 80635#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 80636#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 80839#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 80893#L639 assume !(0 != activate_threads_~tmp___2~0#1); 80885#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 80886#L314 assume !(1 == ~t4_pc~0); 80674#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 80673#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 80888#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 80832#L647 assume !(0 != activate_threads_~tmp___3~0#1); 80773#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 80774#L555 assume !(1 == ~M_E~0); 80686#L555-2 assume !(1 == ~T1_E~0); 80687#L560-1 assume !(1 == ~T2_E~0); 80569#L565-1 assume !(1 == ~T3_E~0); 80570#L570-1 assume !(1 == ~T4_E~0); 80646#L575-1 assume !(1 == ~E_1~0); 80647#L580-1 assume !(1 == ~E_2~0); 80833#L585-1 assume !(1 == ~E_3~0); 80648#L590-1 assume !(1 == ~E_4~0); 80637#L595-1 assume { :end_inline_reset_delta_events } true; 80638#L776-2 assume !false; 82044#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 82045#L477 [2021-12-06 19:59:34,191 INFO L793 eck$LassoCheckResult]: Loop: 82045#L477 assume !false; 82366#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 82028#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 82027#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 82025#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 82026#L416 assume 0 != eval_~tmp~0#1; 82354#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 82352#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 82012#L421 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 82009#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 82011#L435 assume !(0 == ~t2_st~0); 82057#L449 assume !(0 == ~t3_st~0); 82051#L463 assume !(0 == ~t4_st~0); 82045#L477 [2021-12-06 19:59:34,191 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:34,192 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 2 times [2021-12-06 19:59:34,192 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:34,192 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1553168876] [2021-12-06 19:59:34,192 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:34,192 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:34,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:59:34,199 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 19:59:34,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:59:34,214 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 19:59:34,214 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:34,214 INFO L85 PathProgramCache]: Analyzing trace with hash 109617948, now seen corresponding path program 2 times [2021-12-06 19:59:34,214 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:34,215 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1564974219] [2021-12-06 19:59:34,215 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:34,215 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:34,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:59:34,217 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 19:59:34,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:59:34,221 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 19:59:34,222 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:34,222 INFO L85 PathProgramCache]: Analyzing trace with hash 2084563792, now seen corresponding path program 1 times [2021-12-06 19:59:34,222 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:34,222 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2083867530] [2021-12-06 19:59:34,222 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:34,222 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:34,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:59:34,241 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:59:34,242 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:59:34,242 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2083867530] [2021-12-06 19:59:34,242 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2083867530] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:59:34,242 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:59:34,242 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:59:34,242 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2066143454] [2021-12-06 19:59:34,242 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:59:34,304 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:59:34,305 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 19:59:34,305 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 19:59:34,306 INFO L87 Difference]: Start difference. First operand 6118 states and 8120 transitions. cyclomatic complexity: 2005 Second operand has 3 states, 3 states have (on average 25.0) internal successors, (75), 3 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:34,366 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:59:34,366 INFO L93 Difference]: Finished difference Result 9420 states and 12442 transitions. [2021-12-06 19:59:34,367 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 19:59:34,367 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9420 states and 12442 transitions. [2021-12-06 19:59:34,402 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 9340 [2021-12-06 19:59:34,421 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9420 states to 9420 states and 12442 transitions. [2021-12-06 19:59:34,421 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9420 [2021-12-06 19:59:34,426 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9420 [2021-12-06 19:59:34,426 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9420 states and 12442 transitions. [2021-12-06 19:59:34,429 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:59:34,430 INFO L681 BuchiCegarLoop]: Abstraction has 9420 states and 12442 transitions. [2021-12-06 19:59:34,435 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9420 states and 12442 transitions. [2021-12-06 19:59:34,489 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9420 to 9420. [2021-12-06 19:59:34,497 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9420 states, 9420 states have (on average 1.3208067940552017) internal successors, (12442), 9419 states have internal predecessors, (12442), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:34,532 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9420 states to 9420 states and 12442 transitions. [2021-12-06 19:59:34,533 INFO L704 BuchiCegarLoop]: Abstraction has 9420 states and 12442 transitions. [2021-12-06 19:59:34,533 INFO L587 BuchiCegarLoop]: Abstraction has 9420 states and 12442 transitions. [2021-12-06 19:59:34,533 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-06 19:59:34,533 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9420 states and 12442 transitions. [2021-12-06 19:59:34,549 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 9340 [2021-12-06 19:59:34,549 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:59:34,549 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:59:34,549 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:34,549 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:34,549 INFO L791 eck$LassoCheckResult]: Stem: 96526#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 96444#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 96068#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 96069#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 96184#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 96301#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 96150#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 96151#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 96163#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 96164#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 96205#L502 assume !(0 == ~M_E~0); 96206#L502-2 assume !(0 == ~T1_E~0); 96139#L507-1 assume !(0 == ~T2_E~0); 96140#L512-1 assume !(0 == ~T3_E~0); 96304#L517-1 assume !(0 == ~T4_E~0); 96113#L522-1 assume !(0 == ~E_1~0); 96114#L527-1 assume !(0 == ~E_2~0); 96326#L532-1 assume !(0 == ~E_3~0); 96434#L537-1 assume !(0 == ~E_4~0); 96462#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 96421#L238 assume !(1 == ~m_pc~0); 96422#L238-2 is_master_triggered_~__retres1~0#1 := 0; 96079#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 96080#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 96399#L615 assume !(0 != activate_threads_~tmp~1#1); 96100#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 96101#L257 assume !(1 == ~t1_pc~0); 96213#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 96214#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 96251#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 96073#L623 assume !(0 != activate_threads_~tmp___0~0#1); 96074#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 96070#L276 assume !(1 == ~t2_pc~0); 96071#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 96335#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 96165#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 96166#L631 assume !(0 != activate_threads_~tmp___1~0#1); 96477#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 96396#L295 assume !(1 == ~t3_pc~0); 96180#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 96181#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 96379#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 96435#L639 assume !(0 != activate_threads_~tmp___2~0#1); 96423#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 96424#L314 assume !(1 == ~t4_pc~0); 96218#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 96217#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 96429#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 96372#L647 assume !(0 != activate_threads_~tmp___3~0#1); 96318#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 96319#L555 assume !(1 == ~M_E~0); 96232#L555-2 assume !(1 == ~T1_E~0); 96233#L560-1 assume !(1 == ~T2_E~0); 96115#L565-1 assume !(1 == ~T3_E~0); 96116#L570-1 assume !(1 == ~T4_E~0); 96191#L575-1 assume !(1 == ~E_1~0); 96192#L580-1 assume !(1 == ~E_2~0); 96373#L585-1 assume !(1 == ~E_3~0); 96193#L590-1 assume !(1 == ~E_4~0); 96182#L595-1 assume { :end_inline_reset_delta_events } true; 96183#L776-2 assume !false; 101147#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 101143#L477 [2021-12-06 19:59:34,550 INFO L793 eck$LassoCheckResult]: Loop: 101143#L477 assume !false; 101141#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 101138#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 101136#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 101134#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 101133#L416 assume 0 != eval_~tmp~0#1; 101132#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 101130#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 101120#L421 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 100398#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 100960#L435 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 100955#L452 assume !(0 != eval_~tmp_ndt_3~0#1); 100951#L449 assume !(0 == ~t3_st~0); 100947#L463 assume !(0 == ~t4_st~0); 101143#L477 [2021-12-06 19:59:34,550 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:34,550 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 3 times [2021-12-06 19:59:34,550 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:34,550 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [607003578] [2021-12-06 19:59:34,550 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:34,550 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:34,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:59:34,555 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 19:59:34,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:59:34,565 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 19:59:34,566 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:34,566 INFO L85 PathProgramCache]: Analyzing trace with hash -901553796, now seen corresponding path program 1 times [2021-12-06 19:59:34,566 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:34,566 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [414965013] [2021-12-06 19:59:34,566 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:34,566 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:34,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:59:34,568 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 19:59:34,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:59:34,571 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 19:59:34,571 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:34,571 INFO L85 PathProgramCache]: Analyzing trace with hash 192225224, now seen corresponding path program 1 times [2021-12-06 19:59:34,571 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:34,571 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1240661038] [2021-12-06 19:59:34,572 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:34,572 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:34,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:59:34,588 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:59:34,588 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:59:34,589 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1240661038] [2021-12-06 19:59:34,589 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1240661038] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:59:34,589 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:59:34,589 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:59:34,589 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1215578462] [2021-12-06 19:59:34,589 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:59:34,660 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:59:34,660 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 19:59:34,660 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 19:59:34,660 INFO L87 Difference]: Start difference. First operand 9420 states and 12442 transitions. cyclomatic complexity: 3025 Second operand has 3 states, 3 states have (on average 25.333333333333332) internal successors, (76), 3 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:34,732 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:59:34,732 INFO L93 Difference]: Finished difference Result 17038 states and 22432 transitions. [2021-12-06 19:59:34,732 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 19:59:34,733 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17038 states and 22432 transitions. [2021-12-06 19:59:34,790 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 16942 [2021-12-06 19:59:34,824 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17038 states to 17038 states and 22432 transitions. [2021-12-06 19:59:34,824 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17038 [2021-12-06 19:59:34,832 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17038 [2021-12-06 19:59:34,832 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17038 states and 22432 transitions. [2021-12-06 19:59:34,846 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:59:34,846 INFO L681 BuchiCegarLoop]: Abstraction has 17038 states and 22432 transitions. [2021-12-06 19:59:34,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17038 states and 22432 transitions. [2021-12-06 19:59:34,964 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17038 to 16686. [2021-12-06 19:59:34,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16686 states, 16686 states have (on average 1.3175116864437253) internal successors, (21984), 16685 states have internal predecessors, (21984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:35,005 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16686 states to 16686 states and 21984 transitions. [2021-12-06 19:59:35,005 INFO L704 BuchiCegarLoop]: Abstraction has 16686 states and 21984 transitions. [2021-12-06 19:59:35,005 INFO L587 BuchiCegarLoop]: Abstraction has 16686 states and 21984 transitions. [2021-12-06 19:59:35,005 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-06 19:59:35,005 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16686 states and 21984 transitions. [2021-12-06 19:59:35,058 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 16590 [2021-12-06 19:59:35,059 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:59:35,059 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:59:35,059 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:35,059 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:35,059 INFO L791 eck$LassoCheckResult]: Stem: 123019#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 122916#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 122534#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 122535#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 122650#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 122766#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 122616#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 122617#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 122629#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 122630#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 122671#L502 assume !(0 == ~M_E~0); 122672#L502-2 assume !(0 == ~T1_E~0); 122605#L507-1 assume !(0 == ~T2_E~0); 122606#L512-1 assume !(0 == ~T3_E~0); 122769#L517-1 assume !(0 == ~T4_E~0); 122579#L522-1 assume !(0 == ~E_1~0); 122580#L527-1 assume !(0 == ~E_2~0); 122789#L532-1 assume !(0 == ~E_3~0); 122909#L537-1 assume !(0 == ~E_4~0); 122935#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 122896#L238 assume !(1 == ~m_pc~0); 122897#L238-2 is_master_triggered_~__retres1~0#1 := 0; 122545#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 122546#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 122870#L615 assume !(0 != activate_threads_~tmp~1#1); 122566#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 122567#L257 assume !(1 == ~t1_pc~0); 122679#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 122680#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 122717#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 122539#L623 assume !(0 != activate_threads_~tmp___0~0#1); 122540#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 122536#L276 assume !(1 == ~t2_pc~0); 122537#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 122799#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 122631#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 122632#L631 assume !(0 != activate_threads_~tmp___1~0#1); 122955#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 122865#L295 assume !(1 == ~t3_pc~0); 122646#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 122647#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 122847#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 122910#L639 assume !(0 != activate_threads_~tmp___2~0#1); 122898#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 122899#L314 assume !(1 == ~t4_pc~0); 122684#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 122683#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 122904#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 122839#L647 assume !(0 != activate_threads_~tmp___3~0#1); 122782#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 122783#L555 assume !(1 == ~M_E~0); 122698#L555-2 assume !(1 == ~T1_E~0); 122699#L560-1 assume !(1 == ~T2_E~0); 122581#L565-1 assume !(1 == ~T3_E~0); 122582#L570-1 assume !(1 == ~T4_E~0); 122657#L575-1 assume !(1 == ~E_1~0); 122658#L580-1 assume !(1 == ~E_2~0); 122840#L585-1 assume !(1 == ~E_3~0); 122659#L590-1 assume !(1 == ~E_4~0); 122648#L595-1 assume { :end_inline_reset_delta_events } true; 122649#L776-2 assume !false; 130866#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 130858#L477 [2021-12-06 19:59:35,060 INFO L793 eck$LassoCheckResult]: Loop: 130858#L477 assume !false; 130859#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 130848#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 130849#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 130840#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 130841#L416 assume 0 != eval_~tmp~0#1; 130833#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 130834#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 130827#L421 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 130824#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 130826#L435 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 130911#L452 assume !(0 != eval_~tmp_ndt_3~0#1); 130904#L449 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 130905#L466 assume !(0 != eval_~tmp_ndt_4~0#1); 131612#L463 assume !(0 == ~t4_st~0); 130858#L477 [2021-12-06 19:59:35,060 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:35,060 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 4 times [2021-12-06 19:59:35,060 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:35,060 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [170687203] [2021-12-06 19:59:35,060 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:35,060 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:35,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:59:35,066 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 19:59:35,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:59:35,077 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 19:59:35,077 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:35,077 INFO L85 PathProgramCache]: Analyzing trace with hash 2116454956, now seen corresponding path program 1 times [2021-12-06 19:59:35,077 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:35,077 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1531332484] [2021-12-06 19:59:35,077 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:35,078 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:35,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:59:35,080 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 19:59:35,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:59:35,082 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 19:59:35,083 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:35,083 INFO L85 PathProgramCache]: Analyzing trace with hash 1663866208, now seen corresponding path program 1 times [2021-12-06 19:59:35,083 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:35,083 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [515326372] [2021-12-06 19:59:35,083 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:35,083 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:35,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:59:35,100 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:59:35,100 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:59:35,100 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [515326372] [2021-12-06 19:59:35,100 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [515326372] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:59:35,100 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:59:35,101 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 19:59:35,101 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [260838254] [2021-12-06 19:59:35,101 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:59:35,183 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:59:35,184 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 19:59:35,184 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 19:59:35,184 INFO L87 Difference]: Start difference. First operand 16686 states and 21984 transitions. cyclomatic complexity: 5301 Second operand has 3 states, 2 states have (on average 38.5) internal successors, (77), 3 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:35,303 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 19:59:35,303 INFO L93 Difference]: Finished difference Result 31602 states and 41476 transitions. [2021-12-06 19:59:35,303 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 19:59:35,303 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31602 states and 41476 transitions. [2021-12-06 19:59:35,445 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 31474 [2021-12-06 19:59:35,515 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31602 states to 31602 states and 41476 transitions. [2021-12-06 19:59:35,515 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31602 [2021-12-06 19:59:35,528 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31602 [2021-12-06 19:59:35,528 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31602 states and 41476 transitions. [2021-12-06 19:59:35,541 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:59:35,541 INFO L681 BuchiCegarLoop]: Abstraction has 31602 states and 41476 transitions. [2021-12-06 19:59:35,555 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31602 states and 41476 transitions. [2021-12-06 19:59:35,770 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31602 to 31602. [2021-12-06 19:59:35,790 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31602 states, 31602 states have (on average 1.3124485792038478) internal successors, (41476), 31601 states have internal predecessors, (41476), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:59:35,843 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31602 states to 31602 states and 41476 transitions. [2021-12-06 19:59:35,843 INFO L704 BuchiCegarLoop]: Abstraction has 31602 states and 41476 transitions. [2021-12-06 19:59:35,843 INFO L587 BuchiCegarLoop]: Abstraction has 31602 states and 41476 transitions. [2021-12-06 19:59:35,843 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-06 19:59:35,843 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31602 states and 41476 transitions. [2021-12-06 19:59:35,919 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 31474 [2021-12-06 19:59:35,919 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 19:59:35,919 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 19:59:35,920 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:35,920 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:59:35,921 INFO L791 eck$LassoCheckResult]: Stem: 171315#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 171223#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 170830#L739 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 170831#L334 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 170945#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 171062#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 170911#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 170912#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 170924#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 170925#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 170967#L502 assume !(0 == ~M_E~0); 170968#L502-2 assume !(0 == ~T1_E~0); 170900#L507-1 assume !(0 == ~T2_E~0); 170901#L512-1 assume !(0 == ~T3_E~0); 171065#L517-1 assume !(0 == ~T4_E~0); 170875#L522-1 assume !(0 == ~E_1~0); 170876#L527-1 assume !(0 == ~E_2~0); 171087#L532-1 assume !(0 == ~E_3~0); 171213#L537-1 assume !(0 == ~E_4~0); 171242#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 171200#L238 assume !(1 == ~m_pc~0); 171201#L238-2 is_master_triggered_~__retres1~0#1 := 0; 170841#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 170842#L250 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 171173#L615 assume !(0 != activate_threads_~tmp~1#1); 170862#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 170863#L257 assume !(1 == ~t1_pc~0); 170975#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 170976#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 171012#L269 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 170835#L623 assume !(0 != activate_threads_~tmp___0~0#1); 170836#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 170832#L276 assume !(1 == ~t2_pc~0); 170833#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 171098#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 170926#L288 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 170927#L631 assume !(0 != activate_threads_~tmp___1~0#1); 171259#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 171169#L295 assume !(1 == ~t3_pc~0); 170941#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 170942#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 171148#L307 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 171214#L639 assume !(0 != activate_threads_~tmp___2~0#1); 171202#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 171203#L314 assume !(1 == ~t4_pc~0); 170980#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 170979#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 171206#L326 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 171140#L647 assume !(0 != activate_threads_~tmp___3~0#1); 171079#L647-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 171080#L555 assume !(1 == ~M_E~0); 170993#L555-2 assume !(1 == ~T1_E~0); 170994#L560-1 assume !(1 == ~T2_E~0); 170877#L565-1 assume !(1 == ~T3_E~0); 170878#L570-1 assume !(1 == ~T4_E~0); 170952#L575-1 assume !(1 == ~E_1~0); 170953#L580-1 assume !(1 == ~E_2~0); 171141#L585-1 assume !(1 == ~E_3~0); 170954#L590-1 assume !(1 == ~E_4~0); 170943#L595-1 assume { :end_inline_reset_delta_events } true; 170944#L776-2 assume !false; 182551#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 182552#L477 [2021-12-06 19:59:35,921 INFO L793 eck$LassoCheckResult]: Loop: 182552#L477 assume !false; 194174#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 194172#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 194171#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 194170#L402 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 194169#L416 assume 0 != eval_~tmp~0#1; 194167#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 194166#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 180455#L421 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 180051#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 180052#L435 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 191171#L452 assume !(0 != eval_~tmp_ndt_3~0#1); 191170#L449 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 190912#L466 assume !(0 != eval_~tmp_ndt_4~0#1); 191169#L463 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 191160#L480 assume !(0 != eval_~tmp_ndt_5~0#1); 182552#L477 [2021-12-06 19:59:35,921 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:35,921 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 5 times [2021-12-06 19:59:35,921 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:35,921 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1339181250] [2021-12-06 19:59:35,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:35,922 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:35,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:59:35,927 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 19:59:35,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:59:35,938 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 19:59:35,938 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:35,939 INFO L85 PathProgramCache]: Analyzing trace with hash 1185593964, now seen corresponding path program 1 times [2021-12-06 19:59:35,939 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:35,939 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1158706179] [2021-12-06 19:59:35,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:35,939 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:35,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:59:35,942 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 19:59:35,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:59:35,944 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 19:59:35,945 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:59:35,945 INFO L85 PathProgramCache]: Analyzing trace with hash 40244664, now seen corresponding path program 1 times [2021-12-06 19:59:35,945 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:59:35,945 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [66563229] [2021-12-06 19:59:35,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:59:35,945 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:59:35,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:59:35,951 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 19:59:35,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 19:59:35,964 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 19:59:36,765 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 06.12 07:59:36 BoogieIcfgContainer [2021-12-06 19:59:36,765 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-12-06 19:59:36,765 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-12-06 19:59:36,765 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-12-06 19:59:36,766 INFO L275 PluginConnector]: Witness Printer initialized [2021-12-06 19:59:36,766 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 07:59:30" (3/4) ... [2021-12-06 19:59:36,767 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-12-06 19:59:36,808 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8319a0d-1f41-44fc-88b4-21d0b049ce17/bin/uautomizer-DrprNOufMa/witness.graphml [2021-12-06 19:59:36,808 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-12-06 19:59:36,809 INFO L158 Benchmark]: Toolchain (without parser) took 7359.96ms. Allocated memory was 115.3MB in the beginning and 570.4MB in the end (delta: 455.1MB). Free memory was 79.9MB in the beginning and 276.7MB in the end (delta: -196.8MB). Peak memory consumption was 258.9MB. Max. memory is 16.1GB. [2021-12-06 19:59:36,809 INFO L158 Benchmark]: CDTParser took 0.12ms. Allocated memory is still 79.7MB. Free memory was 53.2MB in the beginning and 53.1MB in the end (delta: 30.2kB). There was no memory consumed. Max. memory is 16.1GB. [2021-12-06 19:59:36,809 INFO L158 Benchmark]: CACSL2BoogieTranslator took 270.64ms. Allocated memory is still 115.3MB. Free memory was 79.7MB in the beginning and 86.3MB in the end (delta: -6.6MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2021-12-06 19:59:36,810 INFO L158 Benchmark]: Boogie Procedure Inliner took 42.79ms. Allocated memory is still 115.3MB. Free memory was 86.3MB in the beginning and 82.4MB in the end (delta: 3.9MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-06 19:59:36,810 INFO L158 Benchmark]: Boogie Preprocessor took 42.68ms. Allocated memory is still 115.3MB. Free memory was 82.4MB in the beginning and 78.8MB in the end (delta: 3.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-06 19:59:36,811 INFO L158 Benchmark]: RCFGBuilder took 665.41ms. Allocated memory is still 115.3MB. Free memory was 78.8MB in the beginning and 43.8MB in the end (delta: 35.1MB). Peak memory consumption was 35.7MB. Max. memory is 16.1GB. [2021-12-06 19:59:36,811 INFO L158 Benchmark]: BuchiAutomizer took 6291.47ms. Allocated memory was 115.3MB in the beginning and 570.4MB in the end (delta: 455.1MB). Free memory was 43.2MB in the beginning and 280.8MB in the end (delta: -237.6MB). Peak memory consumption was 295.1MB. Max. memory is 16.1GB. [2021-12-06 19:59:36,811 INFO L158 Benchmark]: Witness Printer took 42.76ms. Allocated memory is still 570.4MB. Free memory was 280.8MB in the beginning and 276.7MB in the end (delta: 4.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-06 19:59:36,812 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.12ms. Allocated memory is still 79.7MB. Free memory was 53.2MB in the beginning and 53.1MB in the end (delta: 30.2kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 270.64ms. Allocated memory is still 115.3MB. Free memory was 79.7MB in the beginning and 86.3MB in the end (delta: -6.6MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 42.79ms. Allocated memory is still 115.3MB. Free memory was 86.3MB in the beginning and 82.4MB in the end (delta: 3.9MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 42.68ms. Allocated memory is still 115.3MB. Free memory was 82.4MB in the beginning and 78.8MB in the end (delta: 3.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 665.41ms. Allocated memory is still 115.3MB. Free memory was 78.8MB in the beginning and 43.8MB in the end (delta: 35.1MB). Peak memory consumption was 35.7MB. Max. memory is 16.1GB. * BuchiAutomizer took 6291.47ms. Allocated memory was 115.3MB in the beginning and 570.4MB in the end (delta: 455.1MB). Free memory was 43.2MB in the beginning and 280.8MB in the end (delta: -237.6MB). Peak memory consumption was 295.1MB. Max. memory is 16.1GB. * Witness Printer took 42.76ms. Allocated memory is still 570.4MB. Free memory was 280.8MB in the beginning and 276.7MB in the end (delta: 4.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 21 terminating modules (21 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.21 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 31602 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 6.2s and 22 iterations. TraceHistogramMax:1. Analysis of lassos took 2.4s. Construction of modules took 0.4s. Büchi inclusion checks took 0.8s. Highest rank in rank-based complementation 0. Minimization of det autom 21. Minimization of nondet autom 0. Automata minimization 1.2s AutomataMinimizationTime, 21 MinimizatonAttempts, 10662 StatesRemovedByMinimization, 12 NontrivialMinimizations. Non-live state removal took 0.8s Buchi closure took 0.0s. Biggest automaton had 31602 states and ocurred in iteration 21. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 15676 SdHoareTripleChecker+Valid, 0.6s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 15676 mSDsluCounter, 24935 SdHoareTripleChecker+Invalid, 0.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 12263 mSDsCounter, 254 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 596 IncrementalHoareTripleChecker+Invalid, 850 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 254 mSolverCounterUnsat, 12672 mSDtfsCounter, 596 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc4 concLT0 SILN1 SILU0 SILI12 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 411]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {tmp_ndt_3=0, NULL=0, t3_st=0, NULL=1, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7845e9e2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@10d527a3=0, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7a1eeb1f=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3e6304c6=0, tmp_ndt_2=0, t4_i=1, \result=0, E_3=2, t4_pc=0, E_1=2, tmp_ndt_1=0, __retres1=1, tmp=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7968db1a=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@398cd485=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@73681360=0, m_st=0, NULL=0, t3_pc=0, tmp___3=0, __retres1=0, tmp___0=0, __retres1=0, tmp___2=0, m_pc=0, \result=0, \result=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@211f7269=0, \result=0, \result=0, tmp___1=0, __retres1=0, T2_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@468e98ae=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@16e0938e=0, tmp=0, t1_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@332857af=0, E_2=2, tmp___0=0, E_4=2, T1_E=2, __retres1=0, M_E=2, t2_i=1, T4_E=2, \result=0, t3_i=1, t4_st=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@12cbf28c=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@21af4a87=0, t1_st=0, __retres1=0, t2_pc=0, tmp_ndt_5=0, __retres1=0, tmp_ndt_4=0, kernel_st=1, T3_E=2, t1_i=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 411]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int m_i ; [L36] int t1_i ; [L37] int t2_i ; [L38] int t3_i ; [L39] int t4_i ; [L40] int M_E = 2; [L41] int T1_E = 2; [L42] int T2_E = 2; [L43] int T3_E = 2; [L44] int T4_E = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; [L821] int __retres1 ; [L825] CALL init_model() [L733] m_i = 1 [L734] t1_i = 1 [L735] t2_i = 1 [L736] t3_i = 1 [L737] t4_i = 1 [L825] RET init_model() [L826] CALL start_simulation() [L762] int kernel_st ; [L763] int tmp ; [L764] int tmp___0 ; [L768] kernel_st = 0 [L769] FCALL update_channels() [L770] CALL init_threads() [L341] COND TRUE m_i == 1 [L342] m_st = 0 [L346] COND TRUE t1_i == 1 [L347] t1_st = 0 [L351] COND TRUE t2_i == 1 [L352] t2_st = 0 [L356] COND TRUE t3_i == 1 [L357] t3_st = 0 [L361] COND TRUE t4_i == 1 [L362] t4_st = 0 [L770] RET init_threads() [L771] CALL fire_delta_events() [L502] COND FALSE !(M_E == 0) [L507] COND FALSE !(T1_E == 0) [L512] COND FALSE !(T2_E == 0) [L517] COND FALSE !(T3_E == 0) [L522] COND FALSE !(T4_E == 0) [L527] COND FALSE !(E_1 == 0) [L532] COND FALSE !(E_2 == 0) [L537] COND FALSE !(E_3 == 0) [L542] COND FALSE !(E_4 == 0) [L771] RET fire_delta_events() [L772] CALL activate_threads() [L605] int tmp ; [L606] int tmp___0 ; [L607] int tmp___1 ; [L608] int tmp___2 ; [L609] int tmp___3 ; [L613] CALL, EXPR is_master_triggered() [L235] int __retres1 ; [L238] COND FALSE !(m_pc == 1) [L248] __retres1 = 0 [L250] return (__retres1); [L613] RET, EXPR is_master_triggered() [L613] tmp = is_master_triggered() [L615] COND FALSE !(\read(tmp)) [L621] CALL, EXPR is_transmit1_triggered() [L254] int __retres1 ; [L257] COND FALSE !(t1_pc == 1) [L267] __retres1 = 0 [L269] return (__retres1); [L621] RET, EXPR is_transmit1_triggered() [L621] tmp___0 = is_transmit1_triggered() [L623] COND FALSE !(\read(tmp___0)) [L629] CALL, EXPR is_transmit2_triggered() [L273] int __retres1 ; [L276] COND FALSE !(t2_pc == 1) [L286] __retres1 = 0 [L288] return (__retres1); [L629] RET, EXPR is_transmit2_triggered() [L629] tmp___1 = is_transmit2_triggered() [L631] COND FALSE !(\read(tmp___1)) [L637] CALL, EXPR is_transmit3_triggered() [L292] int __retres1 ; [L295] COND FALSE !(t3_pc == 1) [L305] __retres1 = 0 [L307] return (__retres1); [L637] RET, EXPR is_transmit3_triggered() [L637] tmp___2 = is_transmit3_triggered() [L639] COND FALSE !(\read(tmp___2)) [L645] CALL, EXPR is_transmit4_triggered() [L311] int __retres1 ; [L314] COND FALSE !(t4_pc == 1) [L324] __retres1 = 0 [L326] return (__retres1); [L645] RET, EXPR is_transmit4_triggered() [L645] tmp___3 = is_transmit4_triggered() [L647] COND FALSE !(\read(tmp___3)) [L772] RET activate_threads() [L773] CALL reset_delta_events() [L555] COND FALSE !(M_E == 1) [L560] COND FALSE !(T1_E == 1) [L565] COND FALSE !(T2_E == 1) [L570] COND FALSE !(T3_E == 1) [L575] COND FALSE !(T4_E == 1) [L580] COND FALSE !(E_1 == 1) [L585] COND FALSE !(E_2 == 1) [L590] COND FALSE !(E_3 == 1) [L595] COND FALSE !(E_4 == 1) [L773] RET reset_delta_events() [L776] COND TRUE 1 [L779] kernel_st = 1 [L780] CALL eval() [L407] int tmp ; Loop: [L411] COND TRUE 1 [L414] CALL, EXPR exists_runnable_thread() [L371] int __retres1 ; [L374] COND TRUE m_st == 0 [L375] __retres1 = 1 [L402] return (__retres1); [L414] RET, EXPR exists_runnable_thread() [L414] tmp = exists_runnable_thread() [L416] COND TRUE \read(tmp) [L421] COND TRUE m_st == 0 [L422] int tmp_ndt_1; [L423] tmp_ndt_1 = __VERIFIER_nondet_int() [L424] COND FALSE !(\read(tmp_ndt_1)) [L435] COND TRUE t1_st == 0 [L436] int tmp_ndt_2; [L437] tmp_ndt_2 = __VERIFIER_nondet_int() [L438] COND FALSE !(\read(tmp_ndt_2)) [L449] COND TRUE t2_st == 0 [L450] int tmp_ndt_3; [L451] tmp_ndt_3 = __VERIFIER_nondet_int() [L452] COND FALSE !(\read(tmp_ndt_3)) [L463] COND TRUE t3_st == 0 [L464] int tmp_ndt_4; [L465] tmp_ndt_4 = __VERIFIER_nondet_int() [L466] COND FALSE !(\read(tmp_ndt_4)) [L477] COND TRUE t4_st == 0 [L478] int tmp_ndt_5; [L479] tmp_ndt_5 = __VERIFIER_nondet_int() [L480] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-12-06 19:59:36,855 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8319a0d-1f41-44fc-88b4-21d0b049ce17/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)