./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.06.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 839c364b Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ab77971-ef11-4f75-af24-bd2dcc5fc51c/bin/uautomizer-DrprNOufMa/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ab77971-ef11-4f75-af24-bd2dcc5fc51c/bin/uautomizer-DrprNOufMa/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ab77971-ef11-4f75-af24-bd2dcc5fc51c/bin/uautomizer-DrprNOufMa/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ab77971-ef11-4f75-af24-bd2dcc5fc51c/bin/uautomizer-DrprNOufMa/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.06.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ab77971-ef11-4f75-af24-bd2dcc5fc51c/bin/uautomizer-DrprNOufMa/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ab77971-ef11-4f75-af24-bd2dcc5fc51c/bin/uautomizer-DrprNOufMa --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bbfdf3f22061e77485b28b33d06a9820d2c4b7aa22afc378a1743c2d746b69df --- Real Ultimate output --- This is Ultimate 0.2.2-hotfix-svcomp22-839c364 [2021-12-06 22:09:19,633 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-06 22:09:19,635 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-06 22:09:19,663 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-06 22:09:19,664 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-06 22:09:19,665 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-06 22:09:19,667 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-06 22:09:19,669 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-06 22:09:19,671 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-06 22:09:19,672 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-06 22:09:19,673 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-06 22:09:19,675 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-06 22:09:19,675 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-06 22:09:19,676 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-06 22:09:19,678 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-06 22:09:19,679 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-06 22:09:19,680 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-06 22:09:19,681 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-06 22:09:19,684 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-06 22:09:19,686 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-06 22:09:19,688 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-06 22:09:19,689 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-06 22:09:19,690 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-06 22:09:19,691 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-06 22:09:19,695 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-06 22:09:19,695 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-06 22:09:19,696 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-06 22:09:19,697 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-06 22:09:19,697 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-06 22:09:19,698 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-06 22:09:19,699 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-06 22:09:19,700 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-06 22:09:19,700 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-06 22:09:19,701 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-06 22:09:19,702 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-06 22:09:19,702 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-06 22:09:19,703 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-06 22:09:19,703 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-06 22:09:19,703 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-06 22:09:19,703 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-06 22:09:19,704 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-06 22:09:19,705 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ab77971-ef11-4f75-af24-bd2dcc5fc51c/bin/uautomizer-DrprNOufMa/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-06 22:09:19,727 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-06 22:09:19,727 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-06 22:09:19,727 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-06 22:09:19,727 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-06 22:09:19,728 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-06 22:09:19,729 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-06 22:09:19,729 INFO L138 SettingsManager]: * Use SBE=true [2021-12-06 22:09:19,729 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-06 22:09:19,729 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-06 22:09:19,729 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-06 22:09:19,730 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-06 22:09:19,730 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-06 22:09:19,730 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-06 22:09:19,730 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-06 22:09:19,730 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-06 22:09:19,730 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-06 22:09:19,731 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-06 22:09:19,731 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-06 22:09:19,731 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-06 22:09:19,731 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-06 22:09:19,731 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-06 22:09:19,731 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-06 22:09:19,731 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-06 22:09:19,731 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-06 22:09:19,731 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-06 22:09:19,732 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-06 22:09:19,732 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-06 22:09:19,732 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-06 22:09:19,732 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-06 22:09:19,732 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-06 22:09:19,732 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-06 22:09:19,733 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-06 22:09:19,734 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-06 22:09:19,734 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ab77971-ef11-4f75-af24-bd2dcc5fc51c/bin/uautomizer-DrprNOufMa/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ab77971-ef11-4f75-af24-bd2dcc5fc51c/bin/uautomizer-DrprNOufMa Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bbfdf3f22061e77485b28b33d06a9820d2c4b7aa22afc378a1743c2d746b69df [2021-12-06 22:09:19,923 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-06 22:09:19,938 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-06 22:09:19,940 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-06 22:09:19,941 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-06 22:09:19,941 INFO L275 PluginConnector]: CDTParser initialized [2021-12-06 22:09:19,942 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ab77971-ef11-4f75-af24-bd2dcc5fc51c/bin/uautomizer-DrprNOufMa/../../sv-benchmarks/c/systemc/transmitter.06.cil.c [2021-12-06 22:09:19,982 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ab77971-ef11-4f75-af24-bd2dcc5fc51c/bin/uautomizer-DrprNOufMa/data/a0deb396a/82e0ec1483ae4d8a939ff5964eb428e3/FLAG27f1e4a00 [2021-12-06 22:09:20,398 INFO L306 CDTParser]: Found 1 translation units. [2021-12-06 22:09:20,399 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ab77971-ef11-4f75-af24-bd2dcc5fc51c/sv-benchmarks/c/systemc/transmitter.06.cil.c [2021-12-06 22:09:20,408 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ab77971-ef11-4f75-af24-bd2dcc5fc51c/bin/uautomizer-DrprNOufMa/data/a0deb396a/82e0ec1483ae4d8a939ff5964eb428e3/FLAG27f1e4a00 [2021-12-06 22:09:20,763 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ab77971-ef11-4f75-af24-bd2dcc5fc51c/bin/uautomizer-DrprNOufMa/data/a0deb396a/82e0ec1483ae4d8a939ff5964eb428e3 [2021-12-06 22:09:20,765 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-06 22:09:20,767 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-06 22:09:20,768 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-06 22:09:20,768 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-06 22:09:20,771 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-06 22:09:20,771 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 10:09:20" (1/1) ... [2021-12-06 22:09:20,772 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7b87dff1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 10:09:20, skipping insertion in model container [2021-12-06 22:09:20,772 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 10:09:20" (1/1) ... [2021-12-06 22:09:20,777 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-06 22:09:20,805 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-06 22:09:20,908 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ab77971-ef11-4f75-af24-bd2dcc5fc51c/sv-benchmarks/c/systemc/transmitter.06.cil.c[706,719] [2021-12-06 22:09:20,969 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-06 22:09:20,979 INFO L203 MainTranslator]: Completed pre-run [2021-12-06 22:09:20,988 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ab77971-ef11-4f75-af24-bd2dcc5fc51c/sv-benchmarks/c/systemc/transmitter.06.cil.c[706,719] [2021-12-06 22:09:21,018 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-06 22:09:21,032 INFO L208 MainTranslator]: Completed translation [2021-12-06 22:09:21,032 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 10:09:21 WrapperNode [2021-12-06 22:09:21,032 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-06 22:09:21,033 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-06 22:09:21,033 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-06 22:09:21,033 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-06 22:09:21,038 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 10:09:21" (1/1) ... [2021-12-06 22:09:21,046 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 10:09:21" (1/1) ... [2021-12-06 22:09:21,093 INFO L137 Inliner]: procedures = 40, calls = 48, calls flagged for inlining = 43, calls inlined = 104, statements flattened = 1522 [2021-12-06 22:09:21,093 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-06 22:09:21,094 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-06 22:09:21,094 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-06 22:09:21,094 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-06 22:09:21,103 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 10:09:21" (1/1) ... [2021-12-06 22:09:21,103 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 10:09:21" (1/1) ... [2021-12-06 22:09:21,112 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 10:09:21" (1/1) ... [2021-12-06 22:09:21,112 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 10:09:21" (1/1) ... [2021-12-06 22:09:21,135 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 10:09:21" (1/1) ... [2021-12-06 22:09:21,155 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 10:09:21" (1/1) ... [2021-12-06 22:09:21,159 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 10:09:21" (1/1) ... [2021-12-06 22:09:21,168 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-06 22:09:21,168 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-06 22:09:21,169 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-06 22:09:21,169 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-06 22:09:21,170 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 10:09:21" (1/1) ... [2021-12-06 22:09:21,178 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 22:09:21,189 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ab77971-ef11-4f75-af24-bd2dcc5fc51c/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 22:09:21,201 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ab77971-ef11-4f75-af24-bd2dcc5fc51c/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 22:09:21,207 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ab77971-ef11-4f75-af24-bd2dcc5fc51c/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-06 22:09:21,234 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-06 22:09:21,234 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-06 22:09:21,235 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-06 22:09:21,235 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-06 22:09:21,300 INFO L236 CfgBuilder]: Building ICFG [2021-12-06 22:09:21,301 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-06 22:09:21,922 INFO L277 CfgBuilder]: Performing block encoding [2021-12-06 22:09:21,935 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-06 22:09:21,935 INFO L301 CfgBuilder]: Removed 10 assume(true) statements. [2021-12-06 22:09:21,939 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 10:09:21 BoogieIcfgContainer [2021-12-06 22:09:21,939 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-06 22:09:21,940 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-06 22:09:21,940 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-06 22:09:21,942 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-06 22:09:21,943 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 22:09:21,943 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.12 10:09:20" (1/3) ... [2021-12-06 22:09:21,944 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@246b2609 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.12 10:09:21, skipping insertion in model container [2021-12-06 22:09:21,944 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 22:09:21,944 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 10:09:21" (2/3) ... [2021-12-06 22:09:21,944 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@246b2609 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.12 10:09:21, skipping insertion in model container [2021-12-06 22:09:21,944 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 22:09:21,944 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 10:09:21" (3/3) ... [2021-12-06 22:09:21,945 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.06.cil.c [2021-12-06 22:09:21,976 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-06 22:09:21,976 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-06 22:09:21,976 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-06 22:09:21,977 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-06 22:09:21,977 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-06 22:09:21,977 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-06 22:09:21,977 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-06 22:09:21,977 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-06 22:09:22,005 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 633 states, 632 states have (on average 1.5284810126582278) internal successors, (966), 632 states have internal predecessors, (966), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:22,044 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 540 [2021-12-06 22:09:22,044 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:09:22,044 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:09:22,054 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:22,054 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:22,054 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-06 22:09:22,056 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 633 states, 632 states have (on average 1.5284810126582278) internal successors, (966), 632 states have internal predecessors, (966), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:22,065 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 540 [2021-12-06 22:09:22,065 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:09:22,065 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:09:22,069 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:22,069 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:22,075 INFO L791 eck$LassoCheckResult]: Stem: 625#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 513#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 414#L987true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5#L454true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3#L461true assume !(1 == ~m_i~0);~m_st~0 := 2; 340#L461-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 555#L466-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 610#L471-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 45#L476-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 272#L481-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 130#L486-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 54#L491-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 525#L670true assume !(0 == ~M_E~0); 301#L670-2true assume !(0 == ~T1_E~0); 251#L675-1true assume !(0 == ~T2_E~0); 338#L680-1true assume !(0 == ~T3_E~0); 432#L685-1true assume !(0 == ~T4_E~0); 306#L690-1true assume !(0 == ~T5_E~0); 609#L695-1true assume !(0 == ~T6_E~0); 384#L700-1true assume 0 == ~E_1~0;~E_1~0 := 1; 373#L705-1true assume !(0 == ~E_2~0); 547#L710-1true assume !(0 == ~E_3~0); 249#L715-1true assume !(0 == ~E_4~0); 192#L720-1true assume !(0 == ~E_5~0); 234#L725-1true assume !(0 == ~E_6~0); 275#L730-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 405#L320true assume 1 == ~m_pc~0; 222#L321true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 153#L331true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 498#L332true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 131#L825true assume !(0 != activate_threads_~tmp~1#1); 447#L825-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 134#L339true assume !(1 == ~t1_pc~0); 420#L339-2true is_transmit1_triggered_~__retres1~1#1 := 0; 121#L350true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 388#L351true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 57#L833true assume !(0 != activate_threads_~tmp___0~0#1); 537#L833-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14#L358true assume 1 == ~t2_pc~0; 588#L359true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 511#L369true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 303#L370true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 238#L841true assume !(0 != activate_threads_~tmp___1~0#1); 128#L841-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 452#L377true assume !(1 == ~t3_pc~0); 320#L377-2true is_transmit3_triggered_~__retres1~3#1 := 0; 330#L388true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 317#L389true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 133#L849true assume !(0 != activate_threads_~tmp___2~0#1); 335#L849-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 101#L396true assume 1 == ~t4_pc~0; 443#L397true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15#L407true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 607#L408true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 263#L857true assume !(0 != activate_threads_~tmp___3~0#1); 85#L857-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 122#L415true assume 1 == ~t5_pc~0; 324#L416true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 276#L426true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 583#L427true activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 423#L865true assume !(0 != activate_threads_~tmp___4~0#1); 35#L865-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 321#L434true assume !(1 == ~t6_pc~0); 214#L434-2true is_transmit6_triggered_~__retres1~6#1 := 0; 351#L445true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 604#L446true activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 352#L873true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 139#L873-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 535#L743true assume !(1 == ~M_E~0); 80#L743-2true assume !(1 == ~T1_E~0); 484#L748-1true assume !(1 == ~T2_E~0); 268#L753-1true assume !(1 == ~T3_E~0); 389#L758-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 458#L763-1true assume !(1 == ~T5_E~0); 552#L768-1true assume !(1 == ~T6_E~0); 136#L773-1true assume !(1 == ~E_1~0); 623#L778-1true assume !(1 == ~E_2~0); 126#L783-1true assume !(1 == ~E_3~0); 597#L788-1true assume !(1 == ~E_4~0); 336#L793-1true assume !(1 == ~E_5~0); 293#L798-1true assume 1 == ~E_6~0;~E_6~0 := 2; 65#L803-1true assume { :end_inline_reset_delta_events } true; 243#L1024-2true [2021-12-06 22:09:22,077 INFO L793 eck$LassoCheckResult]: Loop: 243#L1024-2true assume !false; 471#L1025true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 459#L645true assume false; 589#L660true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 367#L454-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 61#L670-3true assume 0 == ~M_E~0;~M_E~0 := 1; 228#L670-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 150#L675-3true assume !(0 == ~T2_E~0); 426#L680-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 333#L685-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 603#L690-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 558#L695-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 346#L700-3true assume 0 == ~E_1~0;~E_1~0 := 1; 632#L705-3true assume 0 == ~E_2~0;~E_2~0 := 1; 93#L710-3true assume 0 == ~E_3~0;~E_3~0 := 1; 379#L715-3true assume !(0 == ~E_4~0); 240#L720-3true assume 0 == ~E_5~0;~E_5~0 := 1; 307#L725-3true assume 0 == ~E_6~0;~E_6~0 := 1; 495#L730-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 137#L320-21true assume 1 == ~m_pc~0; 456#L321-7true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 530#L331-7true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 185#L332-7true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 473#L825-21true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 441#L825-23true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 99#L339-21true assume !(1 == ~t1_pc~0); 265#L339-23true is_transmit1_triggered_~__retres1~1#1 := 0; 620#L350-7true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86#L351-7true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 26#L833-21true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 74#L833-23true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 580#L358-21true assume !(1 == ~t2_pc~0); 104#L358-23true is_transmit2_triggered_~__retres1~2#1 := 0; 66#L369-7true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 242#L370-7true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 395#L841-21true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 87#L841-23true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 464#L377-21true assume 1 == ~t3_pc~0; 561#L378-7true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 262#L388-7true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 357#L389-7true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 281#L849-21true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 167#L849-23true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 294#L396-21true assume !(1 == ~t4_pc~0); 184#L396-23true is_transmit4_triggered_~__retres1~4#1 := 0; 223#L407-7true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 165#L408-7true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18#L857-21true assume !(0 != activate_threads_~tmp___3~0#1); 297#L857-23true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 151#L415-21true assume 1 == ~t5_pc~0; 507#L416-7true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 425#L426-7true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77#L427-7true activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 219#L865-21true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 195#L865-23true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 374#L434-21true assume !(1 == ~t6_pc~0); 30#L434-23true is_transmit6_triggered_~__retres1~6#1 := 0; 419#L445-7true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 431#L446-7true activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 147#L873-21true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 256#L873-23true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 144#L743-3true assume 1 == ~M_E~0;~M_E~0 := 2; 491#L743-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 554#L748-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 257#L753-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 209#L758-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 161#L763-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 522#L768-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 465#L773-3true assume !(1 == ~E_1~0); 112#L778-3true assume 1 == ~E_2~0;~E_2~0 := 2; 260#L783-3true assume 1 == ~E_3~0;~E_3~0 := 2; 571#L788-3true assume 1 == ~E_4~0;~E_4~0 := 2; 516#L793-3true assume 1 == ~E_5~0;~E_5~0 := 2; 529#L798-3true assume 1 == ~E_6~0;~E_6~0 := 2; 299#L803-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 107#L504-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 391#L541-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 203#L542-1true start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 434#L1043true assume !(0 == start_simulation_~tmp~3#1); 429#L1043-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 258#L504-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 323#L541-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 236#L542-2true stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 226#L998true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 59#L1005true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 140#L1006true start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 218#L1056true assume !(0 != start_simulation_~tmp___0~1#1); 243#L1024-2true [2021-12-06 22:09:22,081 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:22,082 INFO L85 PathProgramCache]: Analyzing trace with hash -1010496615, now seen corresponding path program 1 times [2021-12-06 22:09:22,088 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:22,088 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [326226948] [2021-12-06 22:09:22,089 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:22,089 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:22,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:22,229 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:22,230 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:22,230 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [326226948] [2021-12-06 22:09:22,231 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [326226948] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:22,231 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:22,231 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:09:22,233 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [347488408] [2021-12-06 22:09:22,234 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:22,238 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:09:22,239 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:22,239 INFO L85 PathProgramCache]: Analyzing trace with hash -243567112, now seen corresponding path program 1 times [2021-12-06 22:09:22,240 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:22,240 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1151862925] [2021-12-06 22:09:22,240 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:22,240 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:22,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:22,279 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:22,280 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:22,280 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1151862925] [2021-12-06 22:09:22,280 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1151862925] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:22,280 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:22,281 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 22:09:22,281 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [759103944] [2021-12-06 22:09:22,281 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:22,282 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:09:22,283 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:09:22,314 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:09:22,314 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:09:22,317 INFO L87 Difference]: Start difference. First operand has 633 states, 632 states have (on average 1.5284810126582278) internal successors, (966), 632 states have internal predecessors, (966), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:22,402 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:09:22,402 INFO L93 Difference]: Finished difference Result 632 states and 943 transitions. [2021-12-06 22:09:22,403 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:09:22,408 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 632 states and 943 transitions. [2021-12-06 22:09:22,418 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2021-12-06 22:09:22,431 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 632 states to 626 states and 937 transitions. [2021-12-06 22:09:22,432 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 626 [2021-12-06 22:09:22,434 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 626 [2021-12-06 22:09:22,435 INFO L73 IsDeterministic]: Start isDeterministic. Operand 626 states and 937 transitions. [2021-12-06 22:09:22,440 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:09:22,440 INFO L681 BuchiCegarLoop]: Abstraction has 626 states and 937 transitions. [2021-12-06 22:09:22,454 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 626 states and 937 transitions. [2021-12-06 22:09:22,487 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 626 to 626. [2021-12-06 22:09:22,489 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 626 states, 626 states have (on average 1.4968051118210863) internal successors, (937), 625 states have internal predecessors, (937), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:22,492 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 937 transitions. [2021-12-06 22:09:22,492 INFO L704 BuchiCegarLoop]: Abstraction has 626 states and 937 transitions. [2021-12-06 22:09:22,493 INFO L587 BuchiCegarLoop]: Abstraction has 626 states and 937 transitions. [2021-12-06 22:09:22,493 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-06 22:09:22,493 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 626 states and 937 transitions. [2021-12-06 22:09:22,496 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2021-12-06 22:09:22,496 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:09:22,497 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:09:22,499 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:22,500 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:22,500 INFO L791 eck$LassoCheckResult]: Stem: 1899#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 1882#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1834#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1278#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1274#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 1275#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1790#L466-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1893#L471-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1370#L476-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1371#L481-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1523#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1387#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1388#L670 assume !(0 == ~M_E~0); 1758#L670-2 assume !(0 == ~T1_E~0); 1706#L675-1 assume !(0 == ~T2_E~0); 1707#L680-1 assume !(0 == ~T3_E~0); 1788#L685-1 assume !(0 == ~T4_E~0); 1761#L690-1 assume !(0 == ~T5_E~0); 1762#L695-1 assume !(0 == ~T6_E~0); 1820#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 1812#L705-1 assume !(0 == ~E_2~0); 1813#L710-1 assume !(0 == ~E_3~0); 1705#L715-1 assume !(0 == ~E_4~0); 1629#L720-1 assume !(0 == ~E_5~0); 1630#L725-1 assume !(0 == ~E_6~0); 1683#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1730#L320 assume 1 == ~m_pc~0; 1671#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1565#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1566#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1524#L825 assume !(0 != activate_threads_~tmp~1#1); 1525#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1530#L339 assume !(1 == ~t1_pc~0); 1531#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1508#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1509#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1390#L833 assume !(0 != activate_threads_~tmp___0~0#1); 1391#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1299#L358 assume 1 == ~t2_pc~0; 1300#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1808#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1759#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1687#L841 assume !(0 != activate_threads_~tmp___1~0#1); 1521#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1522#L377 assume !(1 == ~t3_pc~0); 1774#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1775#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1770#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1528#L849 assume !(0 != activate_threads_~tmp___2~0#1); 1529#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1474#L396 assume 1 == ~t4_pc~0; 1475#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1302#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1303#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1721#L857 assume !(0 != activate_threads_~tmp___3~0#1); 1443#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1444#L415 assume 1 == ~t5_pc~0; 1510#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1555#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1731#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1838#L865 assume !(0 != activate_threads_~tmp___4~0#1); 1345#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1346#L434 assume !(1 == ~t6_pc~0); 1660#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1661#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1800#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1801#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1541#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1542#L743 assume !(1 == ~M_E~0); 1435#L743-2 assume !(1 == ~T1_E~0); 1436#L748-1 assume !(1 == ~T2_E~0); 1724#L753-1 assume !(1 == ~T3_E~0); 1725#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1824#L763-1 assume !(1 == ~T5_E~0); 1856#L768-1 assume !(1 == ~T6_E~0); 1536#L773-1 assume !(1 == ~E_1~0); 1537#L778-1 assume !(1 == ~E_2~0); 1516#L783-1 assume !(1 == ~E_3~0); 1517#L788-1 assume !(1 == ~E_4~0); 1786#L793-1 assume !(1 == ~E_5~0); 1751#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 1407#L803-1 assume { :end_inline_reset_delta_events } true; 1408#L1024-2 [2021-12-06 22:09:22,501 INFO L793 eck$LassoCheckResult]: Loop: 1408#L1024-2 assume !false; 1693#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1748#L645 assume !false; 1625#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1626#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1353#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1830#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1863#L556 assume !(0 != eval_~tmp~0#1); 1897#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1807#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1401#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1402#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1562#L675-3 assume !(0 == ~T2_E~0); 1563#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1783#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1784#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1894#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1794#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1795#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1456#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1457#L715-3 assume !(0 == ~E_4~0); 1688#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1689#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1763#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1538#L320-21 assume 1 == ~m_pc~0; 1539#L321-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1686#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1612#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1613#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1848#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1469#L339-21 assume !(1 == ~t1_pc~0); 1470#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 1573#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1445#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1327#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1328#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1427#L358-21 assume !(1 == ~t2_pc~0); 1481#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 1409#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1410#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1692#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1446#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1447#L377-21 assume 1 == ~t3_pc~0; 1859#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1718#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1719#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1739#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1584#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1585#L396-21 assume 1 == ~t4_pc~0; 1752#L397-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1611#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1582#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1309#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 1310#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1560#L415-21 assume 1 == ~t5_pc~0; 1561#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1535#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1431#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1432#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1632#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1633#L434-21 assume !(1 == ~t6_pc~0); 1332#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 1333#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1835#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1556#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1557#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1551#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1552#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1872#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1714#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1652#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1575#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1576#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1860#L773-3 assume !(1 == ~E_1~0); 1494#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1495#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1717#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1884#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1885#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1756#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1485#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1381#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1645#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 1646#L1043 assume !(0 == start_simulation_~tmp~3#1); 1839#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1715#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1502#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1684#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 1673#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1395#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1396#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1543#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 1408#L1024-2 [2021-12-06 22:09:22,502 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:22,502 INFO L85 PathProgramCache]: Analyzing trace with hash -1849530277, now seen corresponding path program 1 times [2021-12-06 22:09:22,502 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:22,503 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1856326631] [2021-12-06 22:09:22,503 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:22,503 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:22,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:22,561 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:22,562 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:22,562 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1856326631] [2021-12-06 22:09:22,562 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1856326631] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:22,562 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:22,563 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:09:22,563 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1404501111] [2021-12-06 22:09:22,563 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:22,563 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:09:22,564 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:22,564 INFO L85 PathProgramCache]: Analyzing trace with hash 2030983010, now seen corresponding path program 1 times [2021-12-06 22:09:22,564 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:22,564 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [937896407] [2021-12-06 22:09:22,564 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:22,564 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:22,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:22,627 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:22,627 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:22,627 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [937896407] [2021-12-06 22:09:22,627 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [937896407] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:22,628 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:22,628 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:09:22,628 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2090892789] [2021-12-06 22:09:22,628 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:22,629 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:09:22,629 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:09:22,629 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:09:22,630 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:09:22,630 INFO L87 Difference]: Start difference. First operand 626 states and 937 transitions. cyclomatic complexity: 312 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:22,672 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:09:22,672 INFO L93 Difference]: Finished difference Result 626 states and 936 transitions. [2021-12-06 22:09:22,672 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:09:22,673 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 626 states and 936 transitions. [2021-12-06 22:09:22,677 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2021-12-06 22:09:22,683 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 626 states to 626 states and 936 transitions. [2021-12-06 22:09:22,683 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 626 [2021-12-06 22:09:22,684 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 626 [2021-12-06 22:09:22,684 INFO L73 IsDeterministic]: Start isDeterministic. Operand 626 states and 936 transitions. [2021-12-06 22:09:22,685 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:09:22,685 INFO L681 BuchiCegarLoop]: Abstraction has 626 states and 936 transitions. [2021-12-06 22:09:22,686 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 626 states and 936 transitions. [2021-12-06 22:09:22,696 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 626 to 626. [2021-12-06 22:09:22,697 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 626 states, 626 states have (on average 1.4952076677316295) internal successors, (936), 625 states have internal predecessors, (936), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:22,700 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 936 transitions. [2021-12-06 22:09:22,700 INFO L704 BuchiCegarLoop]: Abstraction has 626 states and 936 transitions. [2021-12-06 22:09:22,700 INFO L587 BuchiCegarLoop]: Abstraction has 626 states and 936 transitions. [2021-12-06 22:09:22,700 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-06 22:09:22,700 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 626 states and 936 transitions. [2021-12-06 22:09:22,703 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2021-12-06 22:09:22,703 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:09:22,703 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:09:22,705 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:22,705 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:22,705 INFO L791 eck$LassoCheckResult]: Stem: 3158#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 3141#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 3093#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2537#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2533#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 2534#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3049#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3152#L471-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2629#L476-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2630#L481-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2782#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2647#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2648#L670 assume !(0 == ~M_E~0); 3017#L670-2 assume !(0 == ~T1_E~0); 2965#L675-1 assume !(0 == ~T2_E~0); 2966#L680-1 assume !(0 == ~T3_E~0); 3047#L685-1 assume !(0 == ~T4_E~0); 3021#L690-1 assume !(0 == ~T5_E~0); 3022#L695-1 assume !(0 == ~T6_E~0); 3079#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 3071#L705-1 assume !(0 == ~E_2~0); 3072#L710-1 assume !(0 == ~E_3~0); 2964#L715-1 assume !(0 == ~E_4~0); 2888#L720-1 assume !(0 == ~E_5~0); 2889#L725-1 assume !(0 == ~E_6~0); 2942#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2989#L320 assume 1 == ~m_pc~0; 2930#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2824#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2825#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2783#L825 assume !(0 != activate_threads_~tmp~1#1); 2784#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2790#L339 assume !(1 == ~t1_pc~0); 2791#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2767#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2768#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2649#L833 assume !(0 != activate_threads_~tmp___0~0#1); 2650#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2558#L358 assume 1 == ~t2_pc~0; 2559#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3067#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3018#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2946#L841 assume !(0 != activate_threads_~tmp___1~0#1); 2780#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2781#L377 assume !(1 == ~t3_pc~0); 3033#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3034#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3029#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2787#L849 assume !(0 != activate_threads_~tmp___2~0#1); 2788#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2735#L396 assume 1 == ~t4_pc~0; 2736#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2561#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2562#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2980#L857 assume !(0 != activate_threads_~tmp___3~0#1); 2702#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2703#L415 assume 1 == ~t5_pc~0; 2770#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2814#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2990#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3097#L865 assume !(0 != activate_threads_~tmp___4~0#1); 2604#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2605#L434 assume !(1 == ~t6_pc~0); 2920#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2921#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3059#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3060#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2800#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2801#L743 assume !(1 == ~M_E~0); 2694#L743-2 assume !(1 == ~T1_E~0); 2695#L748-1 assume !(1 == ~T2_E~0); 2984#L753-1 assume !(1 == ~T3_E~0); 2985#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3083#L763-1 assume !(1 == ~T5_E~0); 3115#L768-1 assume !(1 == ~T6_E~0); 2798#L773-1 assume !(1 == ~E_1~0); 2799#L778-1 assume !(1 == ~E_2~0); 2775#L783-1 assume !(1 == ~E_3~0); 2776#L788-1 assume !(1 == ~E_4~0); 3045#L793-1 assume !(1 == ~E_5~0); 3010#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 2668#L803-1 assume { :end_inline_reset_delta_events } true; 2669#L1024-2 [2021-12-06 22:09:22,706 INFO L793 eck$LassoCheckResult]: Loop: 2669#L1024-2 assume !false; 2952#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3007#L645 assume !false; 2884#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2885#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2612#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3089#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3124#L556 assume !(0 != eval_~tmp~0#1); 3156#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3066#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2662#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2663#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2821#L675-3 assume !(0 == ~T2_E~0); 2822#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3042#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3043#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3153#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3051#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3052#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2715#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2716#L715-3 assume !(0 == ~E_4~0); 2947#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2948#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3020#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2793#L320-21 assume 1 == ~m_pc~0; 2794#L321-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2945#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2871#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2872#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3106#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2728#L339-21 assume !(1 == ~t1_pc~0); 2729#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 2832#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2704#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2586#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2587#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2686#L358-21 assume !(1 == ~t2_pc~0); 2740#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 2666#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2667#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2951#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2705#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2706#L377-21 assume !(1 == ~t3_pc~0); 3062#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 2977#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2978#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2998#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2843#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2844#L396-21 assume 1 == ~t4_pc~0; 3011#L397-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2870#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2841#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2568#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 2569#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2819#L415-21 assume 1 == ~t5_pc~0; 2820#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2797#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2690#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2691#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2891#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2892#L434-21 assume !(1 == ~t6_pc~0); 2593#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 2594#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3095#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2815#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2816#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2810#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2811#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3131#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2973#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2911#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2834#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2835#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3119#L773-3 assume !(1 == ~E_1~0); 2753#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2754#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2976#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3143#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3144#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3016#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2744#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2640#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2904#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 2905#L1043 assume !(0 == start_simulation_~tmp~3#1); 3098#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2974#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2761#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2944#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 2932#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2654#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2655#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 2802#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 2669#L1024-2 [2021-12-06 22:09:22,706 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:22,707 INFO L85 PathProgramCache]: Analyzing trace with hash 227806621, now seen corresponding path program 1 times [2021-12-06 22:09:22,707 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:22,707 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1384864821] [2021-12-06 22:09:22,707 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:22,707 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:22,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:22,739 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:22,739 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:22,740 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1384864821] [2021-12-06 22:09:22,740 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1384864821] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:22,740 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:22,740 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:09:22,741 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [78310413] [2021-12-06 22:09:22,741 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:22,741 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:09:22,742 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:22,742 INFO L85 PathProgramCache]: Analyzing trace with hash 300645953, now seen corresponding path program 1 times [2021-12-06 22:09:22,742 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:22,742 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1568361625] [2021-12-06 22:09:22,743 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:22,743 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:22,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:22,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:22,800 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:22,800 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1568361625] [2021-12-06 22:09:22,800 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1568361625] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:22,800 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:22,800 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:09:22,800 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1080489667] [2021-12-06 22:09:22,800 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:22,801 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:09:22,801 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:09:22,801 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:09:22,801 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:09:22,802 INFO L87 Difference]: Start difference. First operand 626 states and 936 transitions. cyclomatic complexity: 311 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:22,816 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:09:22,816 INFO L93 Difference]: Finished difference Result 626 states and 935 transitions. [2021-12-06 22:09:22,817 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:09:22,817 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 626 states and 935 transitions. [2021-12-06 22:09:22,821 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2021-12-06 22:09:22,825 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 626 states to 626 states and 935 transitions. [2021-12-06 22:09:22,825 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 626 [2021-12-06 22:09:22,826 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 626 [2021-12-06 22:09:22,826 INFO L73 IsDeterministic]: Start isDeterministic. Operand 626 states and 935 transitions. [2021-12-06 22:09:22,827 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:09:22,827 INFO L681 BuchiCegarLoop]: Abstraction has 626 states and 935 transitions. [2021-12-06 22:09:22,828 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 626 states and 935 transitions. [2021-12-06 22:09:22,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 626 to 626. [2021-12-06 22:09:22,835 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 626 states, 626 states have (on average 1.4936102236421724) internal successors, (935), 625 states have internal predecessors, (935), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:22,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 935 transitions. [2021-12-06 22:09:22,837 INFO L704 BuchiCegarLoop]: Abstraction has 626 states and 935 transitions. [2021-12-06 22:09:22,837 INFO L587 BuchiCegarLoop]: Abstraction has 626 states and 935 transitions. [2021-12-06 22:09:22,837 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-06 22:09:22,837 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 626 states and 935 transitions. [2021-12-06 22:09:22,839 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2021-12-06 22:09:22,839 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:09:22,839 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:09:22,841 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:22,841 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:22,841 INFO L791 eck$LassoCheckResult]: Stem: 4417#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 4400#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 4352#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3796#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3792#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 3793#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4307#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4411#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3886#L476-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3887#L481-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4041#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3905#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3906#L670 assume !(0 == ~M_E~0); 4276#L670-2 assume !(0 == ~T1_E~0); 4224#L675-1 assume !(0 == ~T2_E~0); 4225#L680-1 assume !(0 == ~T3_E~0); 4306#L685-1 assume !(0 == ~T4_E~0); 4279#L690-1 assume !(0 == ~T5_E~0); 4280#L695-1 assume !(0 == ~T6_E~0); 4338#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 4330#L705-1 assume !(0 == ~E_2~0); 4331#L710-1 assume !(0 == ~E_3~0); 4222#L715-1 assume !(0 == ~E_4~0); 4145#L720-1 assume !(0 == ~E_5~0); 4146#L725-1 assume !(0 == ~E_6~0); 4201#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4248#L320 assume 1 == ~m_pc~0; 4189#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4083#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4084#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4042#L825 assume !(0 != activate_threads_~tmp~1#1); 4043#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4048#L339 assume !(1 == ~t1_pc~0); 4049#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4026#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4027#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3908#L833 assume !(0 != activate_threads_~tmp___0~0#1); 3909#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3817#L358 assume 1 == ~t2_pc~0; 3818#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4326#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4277#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4205#L841 assume !(0 != activate_threads_~tmp___1~0#1); 4037#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4038#L377 assume !(1 == ~t3_pc~0); 4292#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4293#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4288#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4046#L849 assume !(0 != activate_threads_~tmp___2~0#1); 4047#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3992#L396 assume 1 == ~t4_pc~0; 3993#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3820#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3821#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4239#L857 assume !(0 != activate_threads_~tmp___3~0#1); 3961#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3962#L415 assume 1 == ~t5_pc~0; 4028#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4071#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4249#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4356#L865 assume !(0 != activate_threads_~tmp___4~0#1); 3863#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3864#L434 assume !(1 == ~t6_pc~0); 4178#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4179#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4318#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4319#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4059#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4060#L743 assume !(1 == ~M_E~0); 3953#L743-2 assume !(1 == ~T1_E~0); 3954#L748-1 assume !(1 == ~T2_E~0); 4242#L753-1 assume !(1 == ~T3_E~0); 4243#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4342#L763-1 assume !(1 == ~T5_E~0); 4374#L768-1 assume !(1 == ~T6_E~0); 4052#L773-1 assume !(1 == ~E_1~0); 4053#L778-1 assume !(1 == ~E_2~0); 4034#L783-1 assume !(1 == ~E_3~0); 4035#L788-1 assume !(1 == ~E_4~0); 4304#L793-1 assume !(1 == ~E_5~0); 4269#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 3925#L803-1 assume { :end_inline_reset_delta_events } true; 3926#L1024-2 [2021-12-06 22:09:22,841 INFO L793 eck$LassoCheckResult]: Loop: 3926#L1024-2 assume !false; 4211#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4266#L645 assume !false; 4143#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4144#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 3871#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4348#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4381#L556 assume !(0 != eval_~tmp~0#1); 4415#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4325#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3917#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3918#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4078#L675-3 assume !(0 == ~T2_E~0); 4079#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4301#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4302#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4412#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4310#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4311#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3974#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3975#L715-3 assume !(0 == ~E_4~0); 4206#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4207#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4281#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4054#L320-21 assume 1 == ~m_pc~0; 4055#L321-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4204#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4130#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4131#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4365#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3987#L339-21 assume !(1 == ~t1_pc~0); 3988#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 4091#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3963#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3845#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3846#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3945#L358-21 assume 1 == ~t2_pc~0; 4051#L359-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3927#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3928#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4210#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3964#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3965#L377-21 assume !(1 == ~t3_pc~0); 4321#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 4237#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4238#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4257#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4102#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4103#L396-21 assume !(1 == ~t4_pc~0); 4128#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 4129#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4100#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3827#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 3828#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4080#L415-21 assume 1 == ~t5_pc~0; 4081#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4058#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3949#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3950#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4150#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4151#L434-21 assume 1 == ~t6_pc~0; 4162#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3853#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4354#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4074#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4075#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4069#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4070#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4390#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4232#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4170#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4093#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4094#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4378#L773-3 assume !(1 == ~E_1~0); 4012#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4013#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4235#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4402#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4403#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4275#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4003#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 3899#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4163#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 4164#L1043 assume !(0 == start_simulation_~tmp~3#1); 4357#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4233#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4021#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4203#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 4191#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3913#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3914#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 4061#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 3926#L1024-2 [2021-12-06 22:09:22,842 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:22,842 INFO L85 PathProgramCache]: Analyzing trace with hash -1506297829, now seen corresponding path program 1 times [2021-12-06 22:09:22,842 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:22,842 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1291609399] [2021-12-06 22:09:22,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:22,842 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:22,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:22,864 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:22,865 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:22,865 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1291609399] [2021-12-06 22:09:22,865 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1291609399] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:22,865 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:22,865 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:09:22,865 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1647306182] [2021-12-06 22:09:22,865 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:22,866 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:09:22,866 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:22,866 INFO L85 PathProgramCache]: Analyzing trace with hash -1901181918, now seen corresponding path program 1 times [2021-12-06 22:09:22,866 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:22,867 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [851778675] [2021-12-06 22:09:22,867 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:22,867 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:22,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:22,898 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:22,899 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:22,899 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [851778675] [2021-12-06 22:09:22,899 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [851778675] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:22,899 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:22,899 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:09:22,899 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2038286666] [2021-12-06 22:09:22,899 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:22,900 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:09:22,900 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:09:22,900 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:09:22,900 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:09:22,900 INFO L87 Difference]: Start difference. First operand 626 states and 935 transitions. cyclomatic complexity: 310 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:22,912 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:09:22,912 INFO L93 Difference]: Finished difference Result 626 states and 934 transitions. [2021-12-06 22:09:22,913 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:09:22,913 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 626 states and 934 transitions. [2021-12-06 22:09:22,917 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2021-12-06 22:09:22,921 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 626 states to 626 states and 934 transitions. [2021-12-06 22:09:22,921 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 626 [2021-12-06 22:09:22,921 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 626 [2021-12-06 22:09:22,921 INFO L73 IsDeterministic]: Start isDeterministic. Operand 626 states and 934 transitions. [2021-12-06 22:09:22,922 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:09:22,922 INFO L681 BuchiCegarLoop]: Abstraction has 626 states and 934 transitions. [2021-12-06 22:09:22,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 626 states and 934 transitions. [2021-12-06 22:09:22,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 626 to 626. [2021-12-06 22:09:22,939 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 626 states, 626 states have (on average 1.4920127795527156) internal successors, (934), 625 states have internal predecessors, (934), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:22,941 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 934 transitions. [2021-12-06 22:09:22,941 INFO L704 BuchiCegarLoop]: Abstraction has 626 states and 934 transitions. [2021-12-06 22:09:22,941 INFO L587 BuchiCegarLoop]: Abstraction has 626 states and 934 transitions. [2021-12-06 22:09:22,941 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-06 22:09:22,941 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 626 states and 934 transitions. [2021-12-06 22:09:22,944 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2021-12-06 22:09:22,944 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:09:22,944 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:09:22,945 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:22,945 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:22,945 INFO L791 eck$LassoCheckResult]: Stem: 5676#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 5659#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 5611#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5055#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5051#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 5052#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5566#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5670#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5145#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5146#L481-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5300#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5164#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5165#L670 assume !(0 == ~M_E~0); 5535#L670-2 assume !(0 == ~T1_E~0); 5483#L675-1 assume !(0 == ~T2_E~0); 5484#L680-1 assume !(0 == ~T3_E~0); 5565#L685-1 assume !(0 == ~T4_E~0); 5538#L690-1 assume !(0 == ~T5_E~0); 5539#L695-1 assume !(0 == ~T6_E~0); 5597#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 5589#L705-1 assume !(0 == ~E_2~0); 5590#L710-1 assume !(0 == ~E_3~0); 5481#L715-1 assume !(0 == ~E_4~0); 5404#L720-1 assume !(0 == ~E_5~0); 5405#L725-1 assume !(0 == ~E_6~0); 5460#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5507#L320 assume 1 == ~m_pc~0; 5448#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5342#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5343#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5301#L825 assume !(0 != activate_threads_~tmp~1#1); 5302#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5307#L339 assume !(1 == ~t1_pc~0); 5308#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5285#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5286#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5167#L833 assume !(0 != activate_threads_~tmp___0~0#1); 5168#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5076#L358 assume 1 == ~t2_pc~0; 5077#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5585#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5536#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5464#L841 assume !(0 != activate_threads_~tmp___1~0#1); 5296#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5297#L377 assume !(1 == ~t3_pc~0); 5551#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5552#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5547#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5305#L849 assume !(0 != activate_threads_~tmp___2~0#1); 5306#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5251#L396 assume 1 == ~t4_pc~0; 5252#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5079#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5080#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5498#L857 assume !(0 != activate_threads_~tmp___3~0#1); 5220#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5221#L415 assume 1 == ~t5_pc~0; 5287#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5330#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5508#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5615#L865 assume !(0 != activate_threads_~tmp___4~0#1); 5122#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5123#L434 assume !(1 == ~t6_pc~0); 5437#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5438#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5577#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5578#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5318#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5319#L743 assume !(1 == ~M_E~0); 5212#L743-2 assume !(1 == ~T1_E~0); 5213#L748-1 assume !(1 == ~T2_E~0); 5501#L753-1 assume !(1 == ~T3_E~0); 5502#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5601#L763-1 assume !(1 == ~T5_E~0); 5633#L768-1 assume !(1 == ~T6_E~0); 5311#L773-1 assume !(1 == ~E_1~0); 5312#L778-1 assume !(1 == ~E_2~0); 5293#L783-1 assume !(1 == ~E_3~0); 5294#L788-1 assume !(1 == ~E_4~0); 5563#L793-1 assume !(1 == ~E_5~0); 5528#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 5184#L803-1 assume { :end_inline_reset_delta_events } true; 5185#L1024-2 [2021-12-06 22:09:22,946 INFO L793 eck$LassoCheckResult]: Loop: 5185#L1024-2 assume !false; 5470#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5525#L645 assume !false; 5402#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5403#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5130#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5607#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5640#L556 assume !(0 != eval_~tmp~0#1); 5674#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5584#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5176#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5177#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5337#L675-3 assume !(0 == ~T2_E~0); 5338#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5560#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5561#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5671#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5569#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5570#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5233#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5234#L715-3 assume !(0 == ~E_4~0); 5465#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5466#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5540#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5313#L320-21 assume 1 == ~m_pc~0; 5314#L321-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5463#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5389#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5390#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5624#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5246#L339-21 assume 1 == ~t1_pc~0; 5248#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5350#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5222#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5104#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5105#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5204#L358-21 assume !(1 == ~t2_pc~0); 5258#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 5186#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5187#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5469#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5223#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5224#L377-21 assume 1 == ~t3_pc~0; 5636#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5496#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5497#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5516#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5361#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5362#L396-21 assume 1 == ~t4_pc~0; 5529#L397-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5388#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5359#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5086#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 5087#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5339#L415-21 assume !(1 == ~t5_pc~0); 5316#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 5317#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5208#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5209#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5409#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5410#L434-21 assume !(1 == ~t6_pc~0); 5111#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 5112#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5613#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5333#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5334#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5328#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5329#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5649#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5491#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5429#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5352#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5353#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5637#L773-3 assume !(1 == ~E_1~0); 5271#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5272#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5494#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5661#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5662#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5534#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5262#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5158#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5422#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 5423#L1043 assume !(0 == start_simulation_~tmp~3#1); 5616#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5492#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5280#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5462#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 5450#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5172#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5173#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 5320#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 5185#L1024-2 [2021-12-06 22:09:22,946 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:22,946 INFO L85 PathProgramCache]: Analyzing trace with hash 1901446621, now seen corresponding path program 1 times [2021-12-06 22:09:22,946 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:22,947 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1995726592] [2021-12-06 22:09:22,947 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:22,947 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:22,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:22,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:22,966 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:22,966 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1995726592] [2021-12-06 22:09:22,967 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1995726592] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:22,967 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:22,967 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:09:22,967 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [72021509] [2021-12-06 22:09:22,967 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:22,967 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:09:22,968 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:22,968 INFO L85 PathProgramCache]: Analyzing trace with hash 734577762, now seen corresponding path program 1 times [2021-12-06 22:09:22,968 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:22,968 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [871139024] [2021-12-06 22:09:22,968 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:22,968 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:22,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:22,994 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:22,994 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:22,995 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [871139024] [2021-12-06 22:09:22,995 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [871139024] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:22,995 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:22,995 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:09:22,995 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1216432559] [2021-12-06 22:09:22,995 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:22,995 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:09:22,996 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:09:22,996 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:09:22,996 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:09:22,996 INFO L87 Difference]: Start difference. First operand 626 states and 934 transitions. cyclomatic complexity: 309 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:23,007 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:09:23,007 INFO L93 Difference]: Finished difference Result 626 states and 933 transitions. [2021-12-06 22:09:23,008 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:09:23,008 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 626 states and 933 transitions. [2021-12-06 22:09:23,012 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2021-12-06 22:09:23,015 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 626 states to 626 states and 933 transitions. [2021-12-06 22:09:23,015 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 626 [2021-12-06 22:09:23,016 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 626 [2021-12-06 22:09:23,016 INFO L73 IsDeterministic]: Start isDeterministic. Operand 626 states and 933 transitions. [2021-12-06 22:09:23,017 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:09:23,017 INFO L681 BuchiCegarLoop]: Abstraction has 626 states and 933 transitions. [2021-12-06 22:09:23,018 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 626 states and 933 transitions. [2021-12-06 22:09:23,023 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 626 to 626. [2021-12-06 22:09:23,024 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 626 states, 626 states have (on average 1.4904153354632588) internal successors, (933), 625 states have internal predecessors, (933), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:23,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 933 transitions. [2021-12-06 22:09:23,026 INFO L704 BuchiCegarLoop]: Abstraction has 626 states and 933 transitions. [2021-12-06 22:09:23,027 INFO L587 BuchiCegarLoop]: Abstraction has 626 states and 933 transitions. [2021-12-06 22:09:23,027 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-06 22:09:23,027 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 626 states and 933 transitions. [2021-12-06 22:09:23,029 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2021-12-06 22:09:23,029 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:09:23,029 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:09:23,030 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:23,030 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:23,030 INFO L791 eck$LassoCheckResult]: Stem: 6935#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 6918#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 6870#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6314#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6310#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 6311#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6826#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6929#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6404#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6405#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6559#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6423#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6424#L670 assume !(0 == ~M_E~0); 6794#L670-2 assume !(0 == ~T1_E~0); 6742#L675-1 assume !(0 == ~T2_E~0); 6743#L680-1 assume !(0 == ~T3_E~0); 6824#L685-1 assume !(0 == ~T4_E~0); 6797#L690-1 assume !(0 == ~T5_E~0); 6798#L695-1 assume !(0 == ~T6_E~0); 6856#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 6848#L705-1 assume !(0 == ~E_2~0); 6849#L710-1 assume !(0 == ~E_3~0); 6740#L715-1 assume !(0 == ~E_4~0); 6663#L720-1 assume !(0 == ~E_5~0); 6664#L725-1 assume !(0 == ~E_6~0); 6719#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6766#L320 assume 1 == ~m_pc~0; 6707#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6601#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6602#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6560#L825 assume !(0 != activate_threads_~tmp~1#1); 6561#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6566#L339 assume !(1 == ~t1_pc~0); 6567#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6544#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6545#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6426#L833 assume !(0 != activate_threads_~tmp___0~0#1); 6427#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6335#L358 assume 1 == ~t2_pc~0; 6336#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6844#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6795#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6723#L841 assume !(0 != activate_threads_~tmp___1~0#1); 6557#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6558#L377 assume !(1 == ~t3_pc~0); 6810#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6811#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6806#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6564#L849 assume !(0 != activate_threads_~tmp___2~0#1); 6565#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6510#L396 assume 1 == ~t4_pc~0; 6511#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6338#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6339#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6757#L857 assume !(0 != activate_threads_~tmp___3~0#1); 6479#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6480#L415 assume 1 == ~t5_pc~0; 6546#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6591#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6767#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6874#L865 assume !(0 != activate_threads_~tmp___4~0#1); 6381#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6382#L434 assume !(1 == ~t6_pc~0); 6696#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6697#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6836#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6837#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6577#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6578#L743 assume !(1 == ~M_E~0); 6471#L743-2 assume !(1 == ~T1_E~0); 6472#L748-1 assume !(1 == ~T2_E~0); 6760#L753-1 assume !(1 == ~T3_E~0); 6761#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6860#L763-1 assume !(1 == ~T5_E~0); 6892#L768-1 assume !(1 == ~T6_E~0); 6572#L773-1 assume !(1 == ~E_1~0); 6573#L778-1 assume !(1 == ~E_2~0); 6552#L783-1 assume !(1 == ~E_3~0); 6553#L788-1 assume !(1 == ~E_4~0); 6822#L793-1 assume !(1 == ~E_5~0); 6787#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 6443#L803-1 assume { :end_inline_reset_delta_events } true; 6444#L1024-2 [2021-12-06 22:09:23,031 INFO L793 eck$LassoCheckResult]: Loop: 6444#L1024-2 assume !false; 6729#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6784#L645 assume !false; 6661#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 6662#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6389#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6866#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6899#L556 assume !(0 != eval_~tmp~0#1); 6933#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6843#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6437#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6438#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6598#L675-3 assume !(0 == ~T2_E~0); 6599#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6819#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6820#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6930#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6828#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6829#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6492#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6493#L715-3 assume !(0 == ~E_4~0); 6724#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6725#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6799#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6574#L320-21 assume !(1 == ~m_pc~0); 6576#L320-23 is_master_triggered_~__retres1~0#1 := 0; 6722#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6648#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6649#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6884#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6505#L339-21 assume !(1 == ~t1_pc~0); 6506#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 6609#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6481#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6363#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6364#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6463#L358-21 assume !(1 == ~t2_pc~0); 6517#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 6445#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6446#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6728#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6482#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6483#L377-21 assume 1 == ~t3_pc~0; 6896#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6755#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6756#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6775#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6620#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6621#L396-21 assume 1 == ~t4_pc~0; 6788#L397-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6647#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6618#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6345#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 6346#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6596#L415-21 assume 1 == ~t5_pc~0; 6597#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6571#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6467#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6468#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6668#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6669#L434-21 assume !(1 == ~t6_pc~0); 6368#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 6369#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6871#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6592#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6593#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6587#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6588#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6908#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6750#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6687#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6611#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6612#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6895#L773-3 assume !(1 == ~E_1~0); 6530#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6531#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6753#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6920#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6921#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6792#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 6521#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6417#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6681#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 6682#L1043 assume !(0 == start_simulation_~tmp~3#1); 6875#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 6751#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6538#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6720#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 6709#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6431#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6432#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 6579#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 6444#L1024-2 [2021-12-06 22:09:23,031 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:23,031 INFO L85 PathProgramCache]: Analyzing trace with hash -482478117, now seen corresponding path program 1 times [2021-12-06 22:09:23,031 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:23,031 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1308664334] [2021-12-06 22:09:23,032 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:23,032 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:23,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:23,049 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:23,049 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:23,049 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1308664334] [2021-12-06 22:09:23,049 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1308664334] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:23,049 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:23,050 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:09:23,050 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [258482990] [2021-12-06 22:09:23,050 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:23,050 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:09:23,050 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:23,050 INFO L85 PathProgramCache]: Analyzing trace with hash -426171263, now seen corresponding path program 1 times [2021-12-06 22:09:23,051 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:23,051 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [591289097] [2021-12-06 22:09:23,051 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:23,051 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:23,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:23,074 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:23,074 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:23,074 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [591289097] [2021-12-06 22:09:23,074 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [591289097] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:23,074 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:23,075 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:09:23,075 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [953314632] [2021-12-06 22:09:23,075 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:23,075 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:09:23,075 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:09:23,075 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:09:23,076 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:09:23,076 INFO L87 Difference]: Start difference. First operand 626 states and 933 transitions. cyclomatic complexity: 308 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:23,086 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:09:23,086 INFO L93 Difference]: Finished difference Result 626 states and 932 transitions. [2021-12-06 22:09:23,087 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:09:23,087 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 626 states and 932 transitions. [2021-12-06 22:09:23,090 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2021-12-06 22:09:23,094 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 626 states to 626 states and 932 transitions. [2021-12-06 22:09:23,094 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 626 [2021-12-06 22:09:23,094 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 626 [2021-12-06 22:09:23,094 INFO L73 IsDeterministic]: Start isDeterministic. Operand 626 states and 932 transitions. [2021-12-06 22:09:23,095 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:09:23,095 INFO L681 BuchiCegarLoop]: Abstraction has 626 states and 932 transitions. [2021-12-06 22:09:23,096 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 626 states and 932 transitions. [2021-12-06 22:09:23,102 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 626 to 626. [2021-12-06 22:09:23,103 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 626 states, 626 states have (on average 1.488817891373802) internal successors, (932), 625 states have internal predecessors, (932), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:23,105 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 932 transitions. [2021-12-06 22:09:23,105 INFO L704 BuchiCegarLoop]: Abstraction has 626 states and 932 transitions. [2021-12-06 22:09:23,105 INFO L587 BuchiCegarLoop]: Abstraction has 626 states and 932 transitions. [2021-12-06 22:09:23,105 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-06 22:09:23,105 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 626 states and 932 transitions. [2021-12-06 22:09:23,107 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2021-12-06 22:09:23,107 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:09:23,107 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:09:23,108 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:23,109 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:23,109 INFO L791 eck$LassoCheckResult]: Stem: 8194#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 8177#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 8129#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7573#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7569#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 7570#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8085#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8188#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7665#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7666#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7818#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 7683#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7684#L670 assume !(0 == ~M_E~0); 8053#L670-2 assume !(0 == ~T1_E~0); 8001#L675-1 assume !(0 == ~T2_E~0); 8002#L680-1 assume !(0 == ~T3_E~0); 8083#L685-1 assume !(0 == ~T4_E~0); 8057#L690-1 assume !(0 == ~T5_E~0); 8058#L695-1 assume !(0 == ~T6_E~0); 8115#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 8107#L705-1 assume !(0 == ~E_2~0); 8108#L710-1 assume !(0 == ~E_3~0); 8000#L715-1 assume !(0 == ~E_4~0); 7924#L720-1 assume !(0 == ~E_5~0); 7925#L725-1 assume !(0 == ~E_6~0); 7978#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8025#L320 assume 1 == ~m_pc~0; 7966#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 7860#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7861#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7819#L825 assume !(0 != activate_threads_~tmp~1#1); 7820#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7826#L339 assume !(1 == ~t1_pc~0); 7827#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7803#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7804#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7685#L833 assume !(0 != activate_threads_~tmp___0~0#1); 7686#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7594#L358 assume 1 == ~t2_pc~0; 7595#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8103#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8054#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7982#L841 assume !(0 != activate_threads_~tmp___1~0#1); 7816#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7817#L377 assume !(1 == ~t3_pc~0); 8069#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8070#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8065#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7823#L849 assume !(0 != activate_threads_~tmp___2~0#1); 7824#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7769#L396 assume 1 == ~t4_pc~0; 7770#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7597#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7598#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8016#L857 assume !(0 != activate_threads_~tmp___3~0#1); 7738#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7739#L415 assume 1 == ~t5_pc~0; 7806#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7850#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8026#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8133#L865 assume !(0 != activate_threads_~tmp___4~0#1); 7640#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7641#L434 assume !(1 == ~t6_pc~0); 7955#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7956#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8095#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8096#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7836#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7837#L743 assume !(1 == ~M_E~0); 7730#L743-2 assume !(1 == ~T1_E~0); 7731#L748-1 assume !(1 == ~T2_E~0); 8019#L753-1 assume !(1 == ~T3_E~0); 8020#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8119#L763-1 assume !(1 == ~T5_E~0); 8151#L768-1 assume !(1 == ~T6_E~0); 7834#L773-1 assume !(1 == ~E_1~0); 7835#L778-1 assume !(1 == ~E_2~0); 7811#L783-1 assume !(1 == ~E_3~0); 7812#L788-1 assume !(1 == ~E_4~0); 8081#L793-1 assume !(1 == ~E_5~0); 8046#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 7704#L803-1 assume { :end_inline_reset_delta_events } true; 7705#L1024-2 [2021-12-06 22:09:23,109 INFO L793 eck$LassoCheckResult]: Loop: 7705#L1024-2 assume !false; 7988#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8043#L645 assume !false; 7920#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7921#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7648#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8125#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8160#L556 assume !(0 != eval_~tmp~0#1); 8192#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8102#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7696#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7697#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7857#L675-3 assume !(0 == ~T2_E~0); 7858#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8078#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8079#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8189#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8089#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8090#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7751#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7752#L715-3 assume !(0 == ~E_4~0); 7983#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7984#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8056#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7829#L320-21 assume 1 == ~m_pc~0; 7830#L321-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 7981#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7907#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7908#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8142#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7764#L339-21 assume !(1 == ~t1_pc~0); 7765#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 7868#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7740#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7622#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7623#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7722#L358-21 assume !(1 == ~t2_pc~0); 7776#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 7702#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7703#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7987#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7741#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7742#L377-21 assume !(1 == ~t3_pc~0); 8098#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 8013#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8014#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8034#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7879#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7880#L396-21 assume !(1 == ~t4_pc~0); 7905#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 7906#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7877#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7604#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 7605#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7855#L415-21 assume 1 == ~t5_pc~0; 7856#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7833#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7726#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7727#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7927#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7928#L434-21 assume 1 == ~t6_pc~0; 7939#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7630#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8131#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7851#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7852#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7846#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7847#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8167#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8009#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7947#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7870#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7871#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8155#L773-3 assume !(1 == ~E_1~0); 7789#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7790#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8012#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8179#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8180#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8052#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7780#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7676#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7940#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 7941#L1043 assume !(0 == start_simulation_~tmp~3#1); 8134#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8010#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7797#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7980#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 7968#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7690#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7691#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 7838#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 7705#L1024-2 [2021-12-06 22:09:23,109 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:23,109 INFO L85 PathProgramCache]: Analyzing trace with hash -559378915, now seen corresponding path program 1 times [2021-12-06 22:09:23,110 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:23,110 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1633842416] [2021-12-06 22:09:23,110 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:23,110 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:23,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:23,135 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:23,135 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:23,135 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1633842416] [2021-12-06 22:09:23,135 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1633842416] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:23,135 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:23,135 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:09:23,135 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [869631814] [2021-12-06 22:09:23,136 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:23,136 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:09:23,136 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:23,136 INFO L85 PathProgramCache]: Analyzing trace with hash -1893431359, now seen corresponding path program 1 times [2021-12-06 22:09:23,136 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:23,136 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [387308172] [2021-12-06 22:09:23,137 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:23,137 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:23,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:23,169 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:23,169 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:23,169 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [387308172] [2021-12-06 22:09:23,169 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [387308172] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:23,170 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:23,170 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:09:23,170 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1164836112] [2021-12-06 22:09:23,170 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:23,170 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:09:23,170 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:09:23,170 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 22:09:23,171 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 22:09:23,171 INFO L87 Difference]: Start difference. First operand 626 states and 932 transitions. cyclomatic complexity: 307 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:23,259 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:09:23,259 INFO L93 Difference]: Finished difference Result 1125 states and 1674 transitions. [2021-12-06 22:09:23,259 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 22:09:23,260 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1125 states and 1674 transitions. [2021-12-06 22:09:23,268 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1022 [2021-12-06 22:09:23,276 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1125 states to 1125 states and 1674 transitions. [2021-12-06 22:09:23,276 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1125 [2021-12-06 22:09:23,278 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1125 [2021-12-06 22:09:23,278 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1125 states and 1674 transitions. [2021-12-06 22:09:23,280 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:09:23,280 INFO L681 BuchiCegarLoop]: Abstraction has 1125 states and 1674 transitions. [2021-12-06 22:09:23,281 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1125 states and 1674 transitions. [2021-12-06 22:09:23,302 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1125 to 1123. [2021-12-06 22:09:23,305 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1123 states, 1123 states have (on average 1.4888691006233303) internal successors, (1672), 1122 states have internal predecessors, (1672), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:23,309 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1123 states to 1123 states and 1672 transitions. [2021-12-06 22:09:23,309 INFO L704 BuchiCegarLoop]: Abstraction has 1123 states and 1672 transitions. [2021-12-06 22:09:23,309 INFO L587 BuchiCegarLoop]: Abstraction has 1123 states and 1672 transitions. [2021-12-06 22:09:23,309 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-06 22:09:23,309 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1123 states and 1672 transitions. [2021-12-06 22:09:23,315 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1022 [2021-12-06 22:09:23,316 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:09:23,316 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:09:23,317 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:23,317 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:23,317 INFO L791 eck$LassoCheckResult]: Stem: 10016#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 9987#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 9923#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9334#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9330#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 9331#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9862#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10002#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9424#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9425#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9583#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 9443#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9444#L670 assume !(0 == ~M_E~0); 9829#L670-2 assume !(0 == ~T1_E~0); 9773#L675-1 assume !(0 == ~T2_E~0); 9774#L680-1 assume !(0 == ~T3_E~0); 9861#L685-1 assume !(0 == ~T4_E~0); 9832#L690-1 assume !(0 == ~T5_E~0); 9833#L695-1 assume !(0 == ~T6_E~0); 9902#L700-1 assume !(0 == ~E_1~0); 9894#L705-1 assume !(0 == ~E_2~0); 9895#L710-1 assume !(0 == ~E_3~0); 9771#L715-1 assume !(0 == ~E_4~0); 9690#L720-1 assume !(0 == ~E_5~0); 9691#L725-1 assume !(0 == ~E_6~0); 9749#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9799#L320 assume 1 == ~m_pc~0; 9735#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9626#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9627#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9584#L825 assume !(0 != activate_threads_~tmp~1#1); 9585#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9590#L339 assume !(1 == ~t1_pc~0); 9591#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9568#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9569#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9446#L833 assume !(0 != activate_threads_~tmp___0~0#1); 9447#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9355#L358 assume 1 == ~t2_pc~0; 9356#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9889#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9830#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9753#L841 assume !(0 != activate_threads_~tmp___1~0#1); 9579#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9580#L377 assume !(1 == ~t3_pc~0); 9845#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9846#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9841#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9588#L849 assume !(0 != activate_threads_~tmp___2~0#1); 9589#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9533#L396 assume 1 == ~t4_pc~0; 9534#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9358#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9359#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9788#L857 assume !(0 != activate_threads_~tmp___3~0#1); 9502#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9503#L415 assume 1 == ~t5_pc~0; 9570#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9614#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9800#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9928#L865 assume !(0 != activate_threads_~tmp___4~0#1); 9401#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9402#L434 assume !(1 == ~t6_pc~0); 9724#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9725#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9875#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9876#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9602#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9603#L743 assume !(1 == ~M_E~0); 9491#L743-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9492#L748-1 assume !(1 == ~T2_E~0); 10066#L753-1 assume !(1 == ~T3_E~0); 10065#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10064#L763-1 assume !(1 == ~T5_E~0); 10063#L768-1 assume !(1 == ~T6_E~0); 10062#L773-1 assume !(1 == ~E_1~0); 9595#L778-1 assume !(1 == ~E_2~0); 10061#L783-1 assume !(1 == ~E_3~0); 10058#L788-1 assume !(1 == ~E_4~0); 10056#L793-1 assume !(1 == ~E_5~0); 10054#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 9463#L803-1 assume { :end_inline_reset_delta_events } true; 9464#L1024-2 [2021-12-06 22:09:23,318 INFO L793 eck$LassoCheckResult]: Loop: 9464#L1024-2 assume !false; 9965#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9817#L645 assume !false; 9688#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 9689#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 9409#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 9960#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9961#L556 assume !(0 != eval_~tmp~0#1); 10010#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10011#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9455#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9456#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10019#L675-3 assume !(0 == ~T2_E~0); 10452#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10451#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10450#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10449#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10448#L700-3 assume !(0 == ~E_1~0); 10447#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10446#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10445#L715-3 assume !(0 == ~E_4~0); 10444#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10443#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10442#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10441#L320-21 assume 1 == ~m_pc~0; 10439#L321-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 10438#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10437#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 10436#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10435#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10434#L339-21 assume !(1 == ~t1_pc~0); 10432#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 10431#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10430#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10429#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10428#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10427#L358-21 assume 1 == ~t2_pc~0; 10425#L359-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10424#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10423#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10422#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10421#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10420#L377-21 assume !(1 == ~t3_pc~0); 10418#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 10417#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10416#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10415#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10414#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10413#L396-21 assume 1 == ~t4_pc~0; 10411#L397-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10410#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10409#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10408#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 10407#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10406#L415-21 assume 1 == ~t5_pc~0; 10404#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10403#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10402#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10401#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10400#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10399#L434-21 assume !(1 == ~t6_pc~0); 10397#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 10396#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10395#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10394#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10393#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10392#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10391#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9976#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10390#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10389#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10388#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10387#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10386#L773-3 assume !(1 == ~E_1~0); 9957#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10385#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10384#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10383#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10382#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10381#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 9544#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 9437#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10208#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 10204#L1043 assume !(0 == start_simulation_~tmp~3#1); 10203#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10199#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10193#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10190#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 10189#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9451#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9452#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 9604#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 9464#L1024-2 [2021-12-06 22:09:23,318 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:23,318 INFO L85 PathProgramCache]: Analyzing trace with hash -389969507, now seen corresponding path program 1 times [2021-12-06 22:09:23,318 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:23,319 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [540860517] [2021-12-06 22:09:23,319 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:23,319 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:23,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:23,343 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:23,344 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:23,344 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [540860517] [2021-12-06 22:09:23,344 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [540860517] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:23,344 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:23,344 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 22:09:23,344 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2139263179] [2021-12-06 22:09:23,344 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:23,345 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:09:23,345 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:23,345 INFO L85 PathProgramCache]: Analyzing trace with hash 2026999844, now seen corresponding path program 1 times [2021-12-06 22:09:23,345 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:23,345 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [326294880] [2021-12-06 22:09:23,345 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:23,345 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:23,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:23,373 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:23,373 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:23,373 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [326294880] [2021-12-06 22:09:23,373 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [326294880] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:23,373 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:23,374 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 22:09:23,374 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [708045463] [2021-12-06 22:09:23,374 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:23,374 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:09:23,374 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:09:23,375 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:09:23,375 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:09:23,375 INFO L87 Difference]: Start difference. First operand 1123 states and 1672 transitions. cyclomatic complexity: 551 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:23,426 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:09:23,427 INFO L93 Difference]: Finished difference Result 1638 states and 2408 transitions. [2021-12-06 22:09:23,427 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:09:23,428 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1638 states and 2408 transitions. [2021-12-06 22:09:23,439 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1536 [2021-12-06 22:09:23,451 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1638 states to 1638 states and 2408 transitions. [2021-12-06 22:09:23,452 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1638 [2021-12-06 22:09:23,453 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1638 [2021-12-06 22:09:23,453 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1638 states and 2408 transitions. [2021-12-06 22:09:23,456 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:09:23,456 INFO L681 BuchiCegarLoop]: Abstraction has 1638 states and 2408 transitions. [2021-12-06 22:09:23,458 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1638 states and 2408 transitions. [2021-12-06 22:09:23,489 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1638 to 1587. [2021-12-06 22:09:23,492 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1587 states, 1587 states have (on average 1.4732199117832387) internal successors, (2338), 1586 states have internal predecessors, (2338), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:23,498 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1587 states to 1587 states and 2338 transitions. [2021-12-06 22:09:23,498 INFO L704 BuchiCegarLoop]: Abstraction has 1587 states and 2338 transitions. [2021-12-06 22:09:23,498 INFO L587 BuchiCegarLoop]: Abstraction has 1587 states and 2338 transitions. [2021-12-06 22:09:23,498 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-06 22:09:23,498 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1587 states and 2338 transitions. [2021-12-06 22:09:23,507 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1486 [2021-12-06 22:09:23,507 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:09:23,507 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:09:23,508 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:23,509 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:23,509 INFO L791 eck$LassoCheckResult]: Stem: 12780#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 12743#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 12679#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12104#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12100#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 12101#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12618#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12761#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12193#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12194#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12345#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12212#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12213#L670 assume !(0 == ~M_E~0); 12581#L670-2 assume !(0 == ~T1_E~0); 12529#L675-1 assume !(0 == ~T2_E~0); 12530#L680-1 assume !(0 == ~T3_E~0); 12617#L685-1 assume !(0 == ~T4_E~0); 12584#L690-1 assume !(0 == ~T5_E~0); 12585#L695-1 assume !(0 == ~T6_E~0); 12656#L700-1 assume !(0 == ~E_1~0); 12646#L705-1 assume !(0 == ~E_2~0); 12647#L710-1 assume !(0 == ~E_3~0); 12527#L715-1 assume !(0 == ~E_4~0); 12449#L720-1 assume !(0 == ~E_5~0); 12450#L725-1 assume !(0 == ~E_6~0); 12506#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12553#L320 assume !(1 == ~m_pc~0); 12676#L320-2 is_master_triggered_~__retres1~0#1 := 0; 12386#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12387#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12346#L825 assume !(0 != activate_threads_~tmp~1#1); 12347#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12352#L339 assume !(1 == ~t1_pc~0); 12353#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12330#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12331#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12215#L833 assume !(0 != activate_threads_~tmp___0~0#1); 12216#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12125#L358 assume 1 == ~t2_pc~0; 12126#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12641#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12582#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12510#L841 assume !(0 != activate_threads_~tmp___1~0#1); 12341#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12342#L377 assume !(1 == ~t3_pc~0); 12601#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12602#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12597#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12350#L849 assume !(0 != activate_threads_~tmp___2~0#1); 12351#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12298#L396 assume 1 == ~t4_pc~0; 12299#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12128#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12129#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12543#L857 assume !(0 != activate_threads_~tmp___3~0#1); 12268#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12269#L415 assume 1 == ~t5_pc~0; 12332#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12374#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12554#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12683#L865 assume !(0 != activate_threads_~tmp___4~0#1); 12171#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12172#L434 assume !(1 == ~t6_pc~0); 12483#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12484#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12630#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12631#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12362#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12363#L743 assume !(1 == ~M_E~0); 12260#L743-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12261#L748-1 assume !(1 == ~T2_E~0); 12547#L753-1 assume !(1 == ~T3_E~0); 12548#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12660#L763-1 assume !(1 == ~T5_E~0); 12707#L768-1 assume !(1 == ~T6_E~0); 12356#L773-1 assume !(1 == ~E_1~0); 12357#L778-1 assume !(1 == ~E_2~0); 12338#L783-1 assume !(1 == ~E_3~0); 12339#L788-1 assume !(1 == ~E_4~0); 12615#L793-1 assume !(1 == ~E_5~0); 12574#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 12232#L803-1 assume { :end_inline_reset_delta_events } true; 12233#L1024-2 [2021-12-06 22:09:23,509 INFO L793 eck$LassoCheckResult]: Loop: 12233#L1024-2 assume !false; 12516#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12708#L645 assume !false; 12447#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 12448#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 12178#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 12716#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12717#L556 assume !(0 != eval_~tmp~0#1); 12783#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12640#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12224#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12225#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12381#L675-3 assume !(0 == ~T2_E~0); 12382#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12612#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12613#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13543#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12622#L700-3 assume !(0 == ~E_1~0); 12623#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12281#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12282#L715-3 assume !(0 == ~E_4~0); 12511#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12512#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12586#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12358#L320-21 assume !(1 == ~m_pc~0); 12359#L320-23 is_master_triggered_~__retres1~0#1 := 0; 12509#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12434#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12435#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12693#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12293#L339-21 assume !(1 == ~t1_pc~0); 12294#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 12394#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12270#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12153#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12154#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12252#L358-21 assume !(1 == ~t2_pc~0); 12305#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 12234#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12235#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12515#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12271#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12272#L377-21 assume 1 == ~t3_pc~0; 12711#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12541#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12542#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12562#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12405#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12406#L396-21 assume !(1 == ~t4_pc~0); 12432#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 12433#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12403#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12135#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 12136#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12383#L415-21 assume 1 == ~t5_pc~0; 12384#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12361#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12256#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12257#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12454#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12455#L434-21 assume !(1 == ~t6_pc~0); 12160#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 12161#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12681#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12377#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12378#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12372#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12373#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12732#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12536#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12474#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12396#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12397#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12712#L773-3 assume !(1 == ~E_1~0); 12318#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12319#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12539#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12745#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12746#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12580#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 12309#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 12206#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 12467#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 12468#L1043 assume !(0 == start_simulation_~tmp~3#1); 12684#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 12537#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 12325#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 12508#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 12494#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12220#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12221#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 12364#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 12233#L1024-2 [2021-12-06 22:09:23,509 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:23,510 INFO L85 PathProgramCache]: Analyzing trace with hash -382218948, now seen corresponding path program 1 times [2021-12-06 22:09:23,510 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:23,510 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [313622002] [2021-12-06 22:09:23,510 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:23,510 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:23,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:23,537 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:23,538 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:23,538 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [313622002] [2021-12-06 22:09:23,538 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [313622002] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:23,538 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:23,538 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:09:23,538 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [414847268] [2021-12-06 22:09:23,538 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:23,539 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:09:23,539 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:23,539 INFO L85 PathProgramCache]: Analyzing trace with hash 32830498, now seen corresponding path program 1 times [2021-12-06 22:09:23,539 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:23,539 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1695184096] [2021-12-06 22:09:23,540 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:23,540 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:23,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:23,566 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:23,566 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:23,567 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1695184096] [2021-12-06 22:09:23,567 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1695184096] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:23,567 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:23,567 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 22:09:23,567 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [845016242] [2021-12-06 22:09:23,567 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:23,567 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:09:23,567 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:09:23,568 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 22:09:23,568 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 22:09:23,568 INFO L87 Difference]: Start difference. First operand 1587 states and 2338 transitions. cyclomatic complexity: 754 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:23,709 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:09:23,709 INFO L93 Difference]: Finished difference Result 3887 states and 5663 transitions. [2021-12-06 22:09:23,710 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 22:09:23,710 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3887 states and 5663 transitions. [2021-12-06 22:09:23,735 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 3725 [2021-12-06 22:09:23,757 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3887 states to 3887 states and 5663 transitions. [2021-12-06 22:09:23,757 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3887 [2021-12-06 22:09:23,760 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3887 [2021-12-06 22:09:23,760 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3887 states and 5663 transitions. [2021-12-06 22:09:23,765 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:09:23,765 INFO L681 BuchiCegarLoop]: Abstraction has 3887 states and 5663 transitions. [2021-12-06 22:09:23,768 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3887 states and 5663 transitions. [2021-12-06 22:09:23,812 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3887 to 2894. [2021-12-06 22:09:23,816 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2894 states, 2894 states have (on average 1.4647546648237733) internal successors, (4239), 2893 states have internal predecessors, (4239), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:23,825 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2894 states to 2894 states and 4239 transitions. [2021-12-06 22:09:23,825 INFO L704 BuchiCegarLoop]: Abstraction has 2894 states and 4239 transitions. [2021-12-06 22:09:23,825 INFO L587 BuchiCegarLoop]: Abstraction has 2894 states and 4239 transitions. [2021-12-06 22:09:23,825 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-06 22:09:23,825 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2894 states and 4239 transitions. [2021-12-06 22:09:23,835 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2793 [2021-12-06 22:09:23,835 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:09:23,835 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:09:23,836 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:23,836 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:23,837 INFO L791 eck$LassoCheckResult]: Stem: 18281#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 18239#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 18173#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17590#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17586#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 17587#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18113#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18259#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17679#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17680#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17832#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17697#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17698#L670 assume !(0 == ~M_E~0); 18072#L670-2 assume !(0 == ~T1_E~0); 18018#L675-1 assume !(0 == ~T2_E~0); 18019#L680-1 assume !(0 == ~T3_E~0); 18111#L685-1 assume !(0 == ~T4_E~0); 18076#L690-1 assume !(0 == ~T5_E~0); 18077#L695-1 assume !(0 == ~T6_E~0); 18147#L700-1 assume !(0 == ~E_1~0); 18137#L705-1 assume !(0 == ~E_2~0); 18138#L710-1 assume !(0 == ~E_3~0); 18017#L715-1 assume !(0 == ~E_4~0); 17943#L720-1 assume !(0 == ~E_5~0); 17944#L725-1 assume !(0 == ~E_6~0); 17995#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18042#L320 assume !(1 == ~m_pc~0); 18170#L320-2 is_master_triggered_~__retres1~0#1 := 0; 17876#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17877#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 17833#L825 assume !(0 != activate_threads_~tmp~1#1); 17834#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17842#L339 assume !(1 == ~t1_pc~0); 17843#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 17817#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17818#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17699#L833 assume !(0 != activate_threads_~tmp___0~0#1); 17700#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17611#L358 assume !(1 == ~t2_pc~0); 17612#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18133#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18073#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17999#L841 assume !(0 != activate_threads_~tmp___1~0#1); 17830#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17831#L377 assume !(1 == ~t3_pc~0); 18092#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 18093#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18088#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 17837#L849 assume !(0 != activate_threads_~tmp___2~0#1); 17838#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17784#L396 assume 1 == ~t4_pc~0; 17785#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17613#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17614#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18032#L857 assume !(0 != activate_threads_~tmp___3~0#1); 17754#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17755#L415 assume 1 == ~t5_pc~0; 17819#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17866#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18043#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18178#L865 assume !(0 != activate_threads_~tmp___4~0#1); 17655#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17656#L434 assume !(1 == ~t6_pc~0); 17974#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17975#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18123#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18124#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17852#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17853#L743 assume !(1 == ~M_E~0); 17746#L743-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17747#L748-1 assume !(1 == ~T2_E~0); 18224#L753-1 assume !(1 == ~T3_E~0); 18151#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18152#L763-1 assume !(1 == ~T5_E~0); 18257#L768-1 assume !(1 == ~T6_E~0); 18258#L773-1 assume !(1 == ~E_1~0); 17850#L778-1 assume !(1 == ~E_2~0); 18280#L783-1 assume !(1 == ~E_3~0); 18271#L788-1 assume !(1 == ~E_4~0); 18272#L793-1 assume !(1 == ~E_5~0); 18064#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 18065#L803-1 assume { :end_inline_reset_delta_events } true; 20109#L1024-2 [2021-12-06 22:09:23,837 INFO L793 eck$LassoCheckResult]: Loop: 20109#L1024-2 assume !false; 20100#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20093#L645 assume !false; 20090#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 20087#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 20079#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 20077#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 20071#L556 assume !(0 != eval_~tmp~0#1); 18270#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18132#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17710#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17711#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17873#L675-3 assume !(0 == ~T2_E~0); 17874#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18105#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18106#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18263#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18117#L700-3 assume !(0 == ~E_1~0); 18118#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17768#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17769#L715-3 assume !(0 == ~E_4~0); 18000#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18001#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18075#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17845#L320-21 assume !(1 == ~m_pc~0); 17846#L320-23 is_master_triggered_~__retres1~0#1 := 0; 17998#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17926#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 17927#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18190#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17779#L339-21 assume !(1 == ~t1_pc~0); 17780#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 17884#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17756#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17634#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17635#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17736#L358-21 assume !(1 == ~t2_pc~0); 17791#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 17716#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17717#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 18004#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17757#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17758#L377-21 assume 1 == ~t3_pc~0; 18210#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18029#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18030#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18052#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17896#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17897#L396-21 assume 1 == ~t4_pc~0; 18066#L397-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17925#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17893#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17622#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 17623#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17871#L415-21 assume 1 == ~t5_pc~0; 17872#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17848#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17742#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17743#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17946#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17947#L434-21 assume 1 == ~t6_pc~0; 17958#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17643#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18176#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20358#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20357#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20356#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20355#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18226#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20354#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20353#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20352#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20351#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20350#L773-3 assume !(1 == ~E_1~0); 18209#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20344#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20343#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20342#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20341#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 20340#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 20243#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 20237#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 20236#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 20221#L1043 assume !(0 == start_simulation_~tmp~3#1); 20219#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 20210#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 20204#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 20202#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 20201#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20192#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20187#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 20114#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 20109#L1024-2 [2021-12-06 22:09:23,837 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:23,838 INFO L85 PathProgramCache]: Analyzing trace with hash -1657321637, now seen corresponding path program 1 times [2021-12-06 22:09:23,838 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:23,838 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [809467754] [2021-12-06 22:09:23,838 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:23,838 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:23,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:23,864 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:23,864 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:23,864 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [809467754] [2021-12-06 22:09:23,865 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [809467754] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:23,865 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:23,865 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 22:09:23,865 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1320965920] [2021-12-06 22:09:23,865 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:23,866 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:09:23,866 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:23,866 INFO L85 PathProgramCache]: Analyzing trace with hash 388958564, now seen corresponding path program 1 times [2021-12-06 22:09:23,867 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:23,867 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2123853686] [2021-12-06 22:09:23,867 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:23,867 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:23,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:23,898 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:23,899 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:23,899 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2123853686] [2021-12-06 22:09:23,899 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2123853686] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:23,899 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:23,899 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 22:09:23,899 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1715669196] [2021-12-06 22:09:23,899 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:23,900 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:09:23,900 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:09:23,900 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:09:23,900 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:09:23,900 INFO L87 Difference]: Start difference. First operand 2894 states and 4239 transitions. cyclomatic complexity: 1348 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:23,953 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:09:23,953 INFO L93 Difference]: Finished difference Result 5348 states and 7795 transitions. [2021-12-06 22:09:23,954 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:09:23,954 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5348 states and 7795 transitions. [2021-12-06 22:09:23,973 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5234 [2021-12-06 22:09:24,002 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5348 states to 5348 states and 7795 transitions. [2021-12-06 22:09:24,003 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5348 [2021-12-06 22:09:24,007 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5348 [2021-12-06 22:09:24,007 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5348 states and 7795 transitions. [2021-12-06 22:09:24,012 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:09:24,012 INFO L681 BuchiCegarLoop]: Abstraction has 5348 states and 7795 transitions. [2021-12-06 22:09:24,016 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5348 states and 7795 transitions. [2021-12-06 22:09:24,092 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5348 to 5336. [2021-12-06 22:09:24,099 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5336 states, 5336 states have (on average 1.4585832083958021) internal successors, (7783), 5335 states have internal predecessors, (7783), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:24,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5336 states to 5336 states and 7783 transitions. [2021-12-06 22:09:24,113 INFO L704 BuchiCegarLoop]: Abstraction has 5336 states and 7783 transitions. [2021-12-06 22:09:24,113 INFO L587 BuchiCegarLoop]: Abstraction has 5336 states and 7783 transitions. [2021-12-06 22:09:24,113 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-06 22:09:24,113 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5336 states and 7783 transitions. [2021-12-06 22:09:24,126 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5222 [2021-12-06 22:09:24,126 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:09:24,126 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:09:24,127 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:24,127 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:24,128 INFO L791 eck$LassoCheckResult]: Stem: 26571#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 26517#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 26445#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25841#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25837#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 25838#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26384#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26542#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25931#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25932#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26086#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25949#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25950#L670 assume !(0 == ~M_E~0); 26339#L670-2 assume !(0 == ~T1_E~0); 26278#L675-1 assume !(0 == ~T2_E~0); 26279#L680-1 assume !(0 == ~T3_E~0); 26382#L685-1 assume !(0 == ~T4_E~0); 26343#L690-1 assume !(0 == ~T5_E~0); 26344#L695-1 assume !(0 == ~T6_E~0); 26421#L700-1 assume !(0 == ~E_1~0); 26410#L705-1 assume !(0 == ~E_2~0); 26411#L710-1 assume !(0 == ~E_3~0); 26277#L715-1 assume !(0 == ~E_4~0); 26196#L720-1 assume !(0 == ~E_5~0); 26197#L725-1 assume !(0 == ~E_6~0); 26252#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26305#L320 assume !(1 == ~m_pc~0); 26440#L320-2 is_master_triggered_~__retres1~0#1 := 0; 26129#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26130#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 26087#L825 assume !(0 != activate_threads_~tmp~1#1); 26088#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26094#L339 assume !(1 == ~t1_pc~0); 26095#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26070#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26071#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 25951#L833 assume !(0 != activate_threads_~tmp___0~0#1); 25952#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25862#L358 assume !(1 == ~t2_pc~0); 25863#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26404#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26340#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 26258#L841 assume !(0 != activate_threads_~tmp___1~0#1); 26084#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26085#L377 assume !(1 == ~t3_pc~0); 26359#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26360#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26355#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 26091#L849 assume !(0 != activate_threads_~tmp___2~0#1); 26092#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26035#L396 assume !(1 == ~t4_pc~0); 26036#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 25864#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25865#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26292#L857 assume !(0 != activate_threads_~tmp___3~0#1); 26005#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26006#L415 assume 1 == ~t5_pc~0; 26072#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26119#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26306#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26452#L865 assume !(0 != activate_threads_~tmp___4~0#1); 25907#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25908#L434 assume !(1 == ~t6_pc~0); 26227#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 26228#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26396#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26397#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26104#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26105#L743 assume !(1 == ~M_E~0); 25997#L743-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25998#L748-1 assume !(1 == ~T2_E~0); 29778#L753-1 assume !(1 == ~T3_E~0); 29777#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29776#L763-1 assume !(1 == ~T5_E~0); 29775#L768-1 assume !(1 == ~T6_E~0); 29774#L773-1 assume !(1 == ~E_1~0); 26100#L778-1 assume !(1 == ~E_2~0); 29773#L783-1 assume !(1 == ~E_3~0); 29772#L788-1 assume !(1 == ~E_4~0); 29771#L793-1 assume !(1 == ~E_5~0); 29770#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 29769#L803-1 assume { :end_inline_reset_delta_events } true; 29768#L1024-2 [2021-12-06 22:09:24,128 INFO L793 eck$LassoCheckResult]: Loop: 29768#L1024-2 assume !false; 29767#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29763#L645 assume !false; 29762#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 29761#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 29754#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 29753#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 29751#L556 assume !(0 != eval_~tmp~0#1); 29752#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30293#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30292#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30291#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30290#L675-3 assume !(0 == ~T2_E~0); 30289#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30288#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30287#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30286#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30285#L700-3 assume !(0 == ~E_1~0); 30284#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30283#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30282#L715-3 assume !(0 == ~E_4~0); 30281#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30280#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30279#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30278#L320-21 assume !(1 == ~m_pc~0); 30277#L320-23 is_master_triggered_~__retres1~0#1 := 0; 30276#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30275#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 30274#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30273#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30272#L339-21 assume !(1 == ~t1_pc~0); 30270#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 30269#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30268#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 30266#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30264#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29241#L358-21 assume !(1 == ~t2_pc~0); 29239#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 29237#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29235#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 29233#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29231#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29229#L377-21 assume !(1 == ~t3_pc~0); 29226#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 29224#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29222#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 29220#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29218#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29216#L396-21 assume !(1 == ~t4_pc~0); 29200#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 29127#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29116#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 29113#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 29111#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29109#L415-21 assume 1 == ~t5_pc~0; 29106#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29104#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29102#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29100#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29098#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29096#L434-21 assume !(1 == ~t6_pc~0); 29093#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 29091#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29089#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29086#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29084#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29082#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29080#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29078#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29076#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29073#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29071#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29069#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29067#L773-3 assume !(1 == ~E_1~0); 29065#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 29063#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 29061#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29059#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29057#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29055#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 29046#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 29041#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 29039#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 29035#L1043 assume !(0 == start_simulation_~tmp~3#1); 29034#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 29027#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 29012#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 28947#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 28943#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 28942#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28595#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 28596#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 29768#L1024-2 [2021-12-06 22:09:24,128 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:24,128 INFO L85 PathProgramCache]: Analyzing trace with hash -738347014, now seen corresponding path program 1 times [2021-12-06 22:09:24,128 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:24,129 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1465665013] [2021-12-06 22:09:24,129 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:24,129 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:24,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:24,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:24,148 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:24,148 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1465665013] [2021-12-06 22:09:24,148 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1465665013] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:24,148 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:24,148 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 22:09:24,148 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1463465316] [2021-12-06 22:09:24,148 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:24,149 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:09:24,149 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:24,149 INFO L85 PathProgramCache]: Analyzing trace with hash -1697506559, now seen corresponding path program 1 times [2021-12-06 22:09:24,149 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:24,149 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1992060332] [2021-12-06 22:09:24,149 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:24,149 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:24,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:24,171 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:24,172 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:24,172 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1992060332] [2021-12-06 22:09:24,172 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1992060332] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:24,172 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:24,172 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 22:09:24,172 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [8991155] [2021-12-06 22:09:24,172 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:24,172 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:09:24,172 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:09:24,173 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:09:24,173 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:09:24,173 INFO L87 Difference]: Start difference. First operand 5336 states and 7783 transitions. cyclomatic complexity: 2453 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:24,246 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:09:24,246 INFO L93 Difference]: Finished difference Result 9905 states and 14394 transitions. [2021-12-06 22:09:24,246 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:09:24,247 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9905 states and 14394 transitions. [2021-12-06 22:09:24,277 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 9752 [2021-12-06 22:09:24,323 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9905 states to 9905 states and 14394 transitions. [2021-12-06 22:09:24,324 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9905 [2021-12-06 22:09:24,330 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9905 [2021-12-06 22:09:24,330 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9905 states and 14394 transitions. [2021-12-06 22:09:24,339 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:09:24,339 INFO L681 BuchiCegarLoop]: Abstraction has 9905 states and 14394 transitions. [2021-12-06 22:09:24,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9905 states and 14394 transitions. [2021-12-06 22:09:24,464 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9905 to 9881. [2021-12-06 22:09:24,481 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9881 states, 9881 states have (on average 1.4543062443072563) internal successors, (14370), 9880 states have internal predecessors, (14370), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:24,515 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9881 states to 9881 states and 14370 transitions. [2021-12-06 22:09:24,515 INFO L704 BuchiCegarLoop]: Abstraction has 9881 states and 14370 transitions. [2021-12-06 22:09:24,515 INFO L587 BuchiCegarLoop]: Abstraction has 9881 states and 14370 transitions. [2021-12-06 22:09:24,515 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-06 22:09:24,515 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9881 states and 14370 transitions. [2021-12-06 22:09:24,567 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 9728 [2021-12-06 22:09:24,567 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:09:24,567 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:09:24,569 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:24,569 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:24,570 INFO L791 eck$LassoCheckResult]: Stem: 41798#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 41752#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 41682#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41091#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41087#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 41088#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41616#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41776#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41180#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 41181#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41333#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41198#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41199#L670 assume !(0 == ~M_E~0); 41578#L670-2 assume !(0 == ~T1_E~0); 41522#L675-1 assume !(0 == ~T2_E~0); 41523#L680-1 assume !(0 == ~T3_E~0); 41614#L685-1 assume !(0 == ~T4_E~0); 41582#L690-1 assume !(0 == ~T5_E~0); 41583#L695-1 assume !(0 == ~T6_E~0); 41656#L700-1 assume !(0 == ~E_1~0); 41644#L705-1 assume !(0 == ~E_2~0); 41645#L710-1 assume !(0 == ~E_3~0); 41521#L715-1 assume !(0 == ~E_4~0); 41442#L720-1 assume !(0 == ~E_5~0); 41443#L725-1 assume !(0 == ~E_6~0); 41499#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41547#L320 assume !(1 == ~m_pc~0); 41677#L320-2 is_master_triggered_~__retres1~0#1 := 0; 41374#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41375#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 41334#L825 assume !(0 != activate_threads_~tmp~1#1); 41335#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41341#L339 assume !(1 == ~t1_pc~0); 41342#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 41319#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41320#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 41200#L833 assume !(0 != activate_threads_~tmp___0~0#1); 41201#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41112#L358 assume !(1 == ~t2_pc~0); 41113#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 41639#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41579#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 41503#L841 assume !(0 != activate_threads_~tmp___1~0#1); 41331#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41332#L377 assume !(1 == ~t3_pc~0); 41598#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41599#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41597#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 41337#L849 assume !(0 != activate_threads_~tmp___2~0#1); 41338#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41288#L396 assume !(1 == ~t4_pc~0); 41289#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 41114#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41115#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 41536#L857 assume !(0 != activate_threads_~tmp___3~0#1); 41256#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41257#L415 assume !(1 == ~t5_pc~0); 41322#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 41365#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41548#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 41687#L865 assume !(0 != activate_threads_~tmp___4~0#1); 41156#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41157#L434 assume !(1 == ~t6_pc~0); 41477#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 41478#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41627#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41628#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 41351#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41352#L743 assume !(1 == ~M_E~0); 41247#L743-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 41248#L748-1 assume !(1 == ~T2_E~0); 48325#L753-1 assume !(1 == ~T3_E~0); 48323#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 48321#L763-1 assume !(1 == ~T5_E~0); 48319#L768-1 assume !(1 == ~T6_E~0); 48316#L773-1 assume !(1 == ~E_1~0); 41349#L778-1 assume !(1 == ~E_2~0); 48313#L783-1 assume !(1 == ~E_3~0); 48311#L788-1 assume !(1 == ~E_4~0); 48309#L793-1 assume !(1 == ~E_5~0); 48307#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 48056#L803-1 assume { :end_inline_reset_delta_events } true; 48055#L1024-2 [2021-12-06 22:09:24,570 INFO L793 eck$LassoCheckResult]: Loop: 48055#L1024-2 assume !false; 44933#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44929#L645 assume !false; 44921#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 44922#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 47990#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 44762#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 44763#L556 assume !(0 != eval_~tmp~0#1); 47967#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 48298#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 48296#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 48294#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 48292#L675-3 assume !(0 == ~T2_E~0); 48290#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 48288#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 48286#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 48284#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 48282#L700-3 assume !(0 == ~E_1~0); 48280#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 48278#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 48276#L715-3 assume !(0 == ~E_4~0); 48274#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 48272#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 48270#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48268#L320-21 assume !(1 == ~m_pc~0); 48266#L320-23 is_master_triggered_~__retres1~0#1 := 0; 48264#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48262#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 48260#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 48258#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48256#L339-21 assume !(1 == ~t1_pc~0); 48253#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 48250#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48248#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 48246#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 48244#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 48242#L358-21 assume !(1 == ~t2_pc~0); 47904#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 48240#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48238#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 48236#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 48234#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48232#L377-21 assume !(1 == ~t3_pc~0); 48229#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 48226#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48224#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 48222#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 48220#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48218#L396-21 assume !(1 == ~t4_pc~0); 48216#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 48214#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48212#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 48210#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 48208#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48206#L415-21 assume !(1 == ~t5_pc~0); 48204#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 48202#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48200#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 48198#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 48196#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48194#L434-21 assume 1 == ~t6_pc~0; 48192#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 48188#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 48186#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 48184#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 48182#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48180#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 48178#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 48176#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48174#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 48172#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 48170#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 48168#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 48164#L773-3 assume !(1 == ~E_1~0); 48163#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 48155#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 48153#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 48151#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 48150#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 48149#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 48144#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 48139#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 48137#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 48075#L1043 assume !(0 == start_simulation_~tmp~3#1); 48071#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 44990#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 44983#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 44978#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 44975#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44971#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 44972#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 48057#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 48055#L1024-2 [2021-12-06 22:09:24,571 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:24,571 INFO L85 PathProgramCache]: Analyzing trace with hash -99562535, now seen corresponding path program 1 times [2021-12-06 22:09:24,571 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:24,571 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [45747716] [2021-12-06 22:09:24,571 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:24,571 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:24,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:24,609 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:24,609 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:24,609 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [45747716] [2021-12-06 22:09:24,609 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [45747716] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:24,609 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:24,609 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 22:09:24,609 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [407884189] [2021-12-06 22:09:24,609 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:24,610 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:09:24,610 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:24,610 INFO L85 PathProgramCache]: Analyzing trace with hash -2093160511, now seen corresponding path program 1 times [2021-12-06 22:09:24,610 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:24,610 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1345875498] [2021-12-06 22:09:24,610 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:24,611 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:24,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:24,634 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:24,635 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:24,635 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1345875498] [2021-12-06 22:09:24,635 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1345875498] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:24,635 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:24,635 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 22:09:24,635 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2056323943] [2021-12-06 22:09:24,636 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:24,636 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:09:24,636 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:09:24,637 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-06 22:09:24,637 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-06 22:09:24,637 INFO L87 Difference]: Start difference. First operand 9881 states and 14370 transitions. cyclomatic complexity: 4501 Second operand has 5 states, 5 states have (on average 16.4) internal successors, (82), 5 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:24,839 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:09:24,840 INFO L93 Difference]: Finished difference Result 22638 states and 33255 transitions. [2021-12-06 22:09:24,840 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-06 22:09:24,840 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22638 states and 33255 transitions. [2021-12-06 22:09:24,919 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 22316 [2021-12-06 22:09:24,971 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22638 states to 22638 states and 33255 transitions. [2021-12-06 22:09:24,971 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22638 [2021-12-06 22:09:25,004 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22638 [2021-12-06 22:09:25,004 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22638 states and 33255 transitions. [2021-12-06 22:09:25,019 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:09:25,019 INFO L681 BuchiCegarLoop]: Abstraction has 22638 states and 33255 transitions. [2021-12-06 22:09:25,033 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22638 states and 33255 transitions. [2021-12-06 22:09:25,164 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22638 to 10304. [2021-12-06 22:09:25,174 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10304 states, 10304 states have (on average 1.435656055900621) internal successors, (14793), 10303 states have internal predecessors, (14793), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:25,194 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10304 states to 10304 states and 14793 transitions. [2021-12-06 22:09:25,194 INFO L704 BuchiCegarLoop]: Abstraction has 10304 states and 14793 transitions. [2021-12-06 22:09:25,195 INFO L587 BuchiCegarLoop]: Abstraction has 10304 states and 14793 transitions. [2021-12-06 22:09:25,195 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-06 22:09:25,195 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10304 states and 14793 transitions. [2021-12-06 22:09:25,233 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 10148 [2021-12-06 22:09:25,233 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:09:25,233 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:09:25,234 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:25,234 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:25,234 INFO L791 eck$LassoCheckResult]: Stem: 74536#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 74431#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 74321#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 73625#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 73621#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 73622#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 74223#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 74471#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 73714#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 73715#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 73885#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 73734#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 73735#L670 assume !(0 == ~M_E~0); 74161#L670-2 assume !(0 == ~T1_E~0); 74092#L675-1 assume !(0 == ~T2_E~0); 74093#L680-1 assume !(0 == ~T3_E~0); 74220#L685-1 assume !(0 == ~T4_E~0); 74171#L690-1 assume !(0 == ~T5_E~0); 74172#L695-1 assume !(0 == ~T6_E~0); 74286#L700-1 assume !(0 == ~E_1~0); 74270#L705-1 assume !(0 == ~E_2~0); 74271#L710-1 assume !(0 == ~E_3~0); 74091#L715-1 assume !(0 == ~E_4~0); 74006#L720-1 assume !(0 == ~E_5~0); 74007#L725-1 assume !(0 == ~E_6~0); 74066#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 74123#L320 assume !(1 == ~m_pc~0); 74312#L320-2 is_master_triggered_~__retres1~0#1 := 0; 73932#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 73933#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 73886#L825 assume !(0 != activate_threads_~tmp~1#1); 73887#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 73895#L339 assume !(1 == ~t1_pc~0); 73896#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 73868#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 73869#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 73736#L833 assume !(0 != activate_threads_~tmp___0~0#1); 73737#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 73646#L358 assume !(1 == ~t2_pc~0); 73647#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 74259#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 74167#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 74072#L841 assume !(0 != activate_threads_~tmp___1~0#1); 73883#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 73884#L377 assume !(1 == ~t3_pc~0); 74195#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 74196#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 74191#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 73890#L849 assume !(0 != activate_threads_~tmp___2~0#1); 73891#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 73830#L396 assume !(1 == ~t4_pc~0); 73831#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 73648#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 73649#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 74111#L857 assume !(0 != activate_threads_~tmp___3~0#1); 73796#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 73797#L415 assume !(1 == ~t5_pc~0); 73872#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 73919#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 74124#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 74326#L865 assume !(0 != activate_threads_~tmp___4~0#1); 73690#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 73691#L434 assume !(1 == ~t6_pc~0); 74042#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 74043#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 74237#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 74238#L873 assume !(0 != activate_threads_~tmp___5~0#1); 73904#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 73905#L743 assume !(1 == ~M_E~0); 73785#L743-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 73786#L748-1 assume !(1 == ~T2_E~0); 74114#L753-1 assume !(1 == ~T3_E~0); 74115#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 74367#L763-1 assume !(1 == ~T5_E~0); 74368#L768-1 assume !(1 == ~T6_E~0); 73902#L773-1 assume !(1 == ~E_1~0); 73903#L778-1 assume !(1 == ~E_2~0); 73877#L783-1 assume !(1 == ~E_3~0); 73878#L788-1 assume !(1 == ~E_4~0); 81445#L793-1 assume !(1 == ~E_5~0); 81444#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 73756#L803-1 assume { :end_inline_reset_delta_events } true; 73757#L1024-2 [2021-12-06 22:09:25,235 INFO L793 eck$LassoCheckResult]: Loop: 73757#L1024-2 assume !false; 74383#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 74149#L645 assume !false; 74002#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 74003#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 73697#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 74307#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 74378#L556 assume !(0 != eval_~tmp~0#1); 74539#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 82812#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 82811#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 82810#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 82809#L675-3 assume !(0 == ~T2_E~0); 82808#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 82807#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 82806#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 82805#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 82804#L700-3 assume !(0 == ~E_1~0); 82803#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 82802#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 82801#L715-3 assume !(0 == ~E_4~0); 82800#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 82799#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 82798#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 82797#L320-21 assume !(1 == ~m_pc~0); 82796#L320-23 is_master_triggered_~__retres1~0#1 := 0; 82795#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82794#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 82793#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 82792#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 82791#L339-21 assume !(1 == ~t1_pc~0); 82789#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 82788#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82787#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 82786#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 82785#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 82784#L358-21 assume !(1 == ~t2_pc~0); 80763#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 82783#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 82782#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 82781#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 82780#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 82779#L377-21 assume !(1 == ~t3_pc~0); 82777#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 82776#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 82775#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 82774#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 82773#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 82772#L396-21 assume !(1 == ~t4_pc~0); 82771#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 82770#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 82769#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 82768#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 82767#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 82766#L415-21 assume !(1 == ~t5_pc~0); 82765#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 82764#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 82763#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 82762#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 82761#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 82760#L434-21 assume !(1 == ~t6_pc~0); 82759#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 82757#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 82755#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 82753#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 82751#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82750#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 82749#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 81783#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 82701#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 82699#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 82697#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 82696#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 82694#L773-3 assume !(1 == ~E_1~0); 81603#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 82691#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 82689#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 82687#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 82686#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 82684#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 82679#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 82674#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 82672#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 82669#L1043 assume !(0 == start_simulation_~tmp~3#1); 82668#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 82665#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 82660#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 82659#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 82658#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 82657#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 82656#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 82655#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 73757#L1024-2 [2021-12-06 22:09:25,235 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:25,235 INFO L85 PathProgramCache]: Analyzing trace with hash -1120630889, now seen corresponding path program 1 times [2021-12-06 22:09:25,235 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:25,235 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [710848809] [2021-12-06 22:09:25,235 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:25,235 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:25,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:25,255 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:25,255 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:25,255 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [710848809] [2021-12-06 22:09:25,255 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [710848809] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:25,255 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:25,255 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 22:09:25,256 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [16983095] [2021-12-06 22:09:25,256 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:25,256 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:09:25,256 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:25,256 INFO L85 PathProgramCache]: Analyzing trace with hash -1683658978, now seen corresponding path program 1 times [2021-12-06 22:09:25,257 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:25,257 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [786274493] [2021-12-06 22:09:25,257 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:25,257 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:25,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:25,284 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:25,285 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:25,285 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [786274493] [2021-12-06 22:09:25,285 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [786274493] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:25,285 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:25,285 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 22:09:25,285 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [280678131] [2021-12-06 22:09:25,285 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:25,285 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:09:25,285 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:09:25,286 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:09:25,286 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:09:25,286 INFO L87 Difference]: Start difference. First operand 10304 states and 14793 transitions. cyclomatic complexity: 4501 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:25,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:09:25,315 INFO L93 Difference]: Finished difference Result 10298 states and 14716 transitions. [2021-12-06 22:09:25,315 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:09:25,316 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10298 states and 14716 transitions. [2021-12-06 22:09:25,345 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 10148 [2021-12-06 22:09:25,366 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10298 states to 10298 states and 14716 transitions. [2021-12-06 22:09:25,367 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10298 [2021-12-06 22:09:25,372 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10298 [2021-12-06 22:09:25,372 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10298 states and 14716 transitions. [2021-12-06 22:09:25,377 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:09:25,377 INFO L681 BuchiCegarLoop]: Abstraction has 10298 states and 14716 transitions. [2021-12-06 22:09:25,384 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10298 states and 14716 transitions. [2021-12-06 22:09:25,470 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10298 to 7072. [2021-12-06 22:09:25,478 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7072 states, 7072 states have (on average 1.4294400452488687) internal successors, (10109), 7071 states have internal predecessors, (10109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:25,492 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7072 states to 7072 states and 10109 transitions. [2021-12-06 22:09:25,493 INFO L704 BuchiCegarLoop]: Abstraction has 7072 states and 10109 transitions. [2021-12-06 22:09:25,493 INFO L587 BuchiCegarLoop]: Abstraction has 7072 states and 10109 transitions. [2021-12-06 22:09:25,493 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-06 22:09:25,493 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7072 states and 10109 transitions. [2021-12-06 22:09:25,513 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6944 [2021-12-06 22:09:25,513 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:09:25,513 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:09:25,515 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:25,515 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:25,515 INFO L791 eck$LassoCheckResult]: Stem: 94926#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 94876#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 94813#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 94236#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 94232#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 94233#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 94754#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 94897#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 94322#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 94323#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 94477#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 94341#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 94342#L670 assume !(0 == ~M_E~0); 94717#L670-2 assume !(0 == ~T1_E~0); 94661#L675-1 assume !(0 == ~T2_E~0); 94662#L680-1 assume !(0 == ~T3_E~0); 94753#L685-1 assume !(0 == ~T4_E~0); 94720#L690-1 assume !(0 == ~T5_E~0); 94721#L695-1 assume !(0 == ~T6_E~0); 94789#L700-1 assume !(0 == ~E_1~0); 94778#L705-1 assume !(0 == ~E_2~0); 94779#L710-1 assume !(0 == ~E_3~0); 94659#L715-1 assume !(0 == ~E_4~0); 94581#L720-1 assume !(0 == ~E_5~0); 94582#L725-1 assume !(0 == ~E_6~0); 94638#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 94687#L320 assume !(1 == ~m_pc~0); 94810#L320-2 is_master_triggered_~__retres1~0#1 := 0; 94516#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 94517#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 94478#L825 assume !(0 != activate_threads_~tmp~1#1); 94479#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 94483#L339 assume !(1 == ~t1_pc~0); 94484#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 94463#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 94464#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 94344#L833 assume !(0 != activate_threads_~tmp___0~0#1); 94345#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 94257#L358 assume !(1 == ~t2_pc~0); 94258#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 94772#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 94718#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 94642#L841 assume !(0 != activate_threads_~tmp___1~0#1); 94473#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 94474#L377 assume !(1 == ~t3_pc~0); 94736#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 94737#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 94732#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 94481#L849 assume !(0 != activate_threads_~tmp___2~0#1); 94482#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 94430#L396 assume !(1 == ~t4_pc~0); 94431#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 94259#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 94260#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 94676#L857 assume !(0 != activate_threads_~tmp___3~0#1); 94398#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 94399#L415 assume !(1 == ~t5_pc~0); 94465#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 94505#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 94688#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 94818#L865 assume !(0 != activate_threads_~tmp___4~0#1); 94300#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 94301#L434 assume !(1 == ~t6_pc~0); 94615#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 94616#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 94916#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 94766#L873 assume !(0 != activate_threads_~tmp___5~0#1); 94493#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 94494#L743 assume !(1 == ~M_E~0); 94390#L743-2 assume !(1 == ~T1_E~0); 94391#L748-1 assume !(1 == ~T2_E~0); 94679#L753-1 assume !(1 == ~T3_E~0); 94680#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 94792#L763-1 assume !(1 == ~T5_E~0); 94841#L768-1 assume !(1 == ~T6_E~0); 94487#L773-1 assume !(1 == ~E_1~0); 94488#L778-1 assume !(1 == ~E_2~0); 94470#L783-1 assume !(1 == ~E_3~0); 94471#L788-1 assume !(1 == ~E_4~0); 94751#L793-1 assume !(1 == ~E_5~0); 94710#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 94361#L803-1 assume { :end_inline_reset_delta_events } true; 94362#L1024-2 [2021-12-06 22:09:25,515 INFO L793 eck$LassoCheckResult]: Loop: 94362#L1024-2 assume !false; 98294#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 98286#L645 assume !false; 98283#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 98280#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 98271#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 98268#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 98266#L556 assume !(0 != eval_~tmp~0#1); 94913#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 94771#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 94353#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 94354#L670-5 assume !(0 == ~T1_E~0); 94512#L675-3 assume !(0 == ~T2_E~0); 94513#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 94746#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 94747#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 94901#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 94757#L700-3 assume !(0 == ~E_1~0); 94758#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 94413#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 94414#L715-3 assume !(0 == ~E_4~0); 94643#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 94644#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 94722#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 94489#L320-21 assume !(1 == ~m_pc~0); 94490#L320-23 is_master_triggered_~__retres1~0#1 := 0; 94641#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 94566#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 94567#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 94828#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 94425#L339-21 assume 1 == ~t1_pc~0; 94427#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 94524#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 101226#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 94282#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 94283#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 98692#L358-21 assume !(1 == ~t2_pc~0); 98687#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 98682#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 98676#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 98670#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 98664#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 98590#L377-21 assume 1 == ~t3_pc~0; 98587#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 98584#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 98582#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 98580#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 98578#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 98576#L396-21 assume !(1 == ~t4_pc~0); 98574#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 98572#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 98569#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 98567#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 98565#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 98563#L415-21 assume !(1 == ~t5_pc~0); 98561#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 98559#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 98556#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 98554#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 98552#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 98470#L434-21 assume !(1 == ~t6_pc~0); 98466#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 98464#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 98462#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 98460#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 98457#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 98455#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 98453#L743-5 assume !(1 == ~T1_E~0); 98451#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 98449#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 98446#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 98444#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 98442#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 98438#L773-3 assume !(1 == ~E_1~0); 98436#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 98434#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 98432#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 98422#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 98384#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 98381#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 98369#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 98351#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 98342#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 98332#L1043 assume !(0 == start_simulation_~tmp~3#1); 98329#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 98317#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 98312#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 98311#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 98310#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 98308#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 98306#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 98304#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 94362#L1024-2 [2021-12-06 22:09:25,516 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:25,516 INFO L85 PathProgramCache]: Analyzing trace with hash -1707436903, now seen corresponding path program 1 times [2021-12-06 22:09:25,516 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:25,516 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1844544162] [2021-12-06 22:09:25,516 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:25,516 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:25,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:25,546 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:25,546 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:25,546 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1844544162] [2021-12-06 22:09:25,546 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1844544162] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:25,546 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:25,546 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:09:25,546 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [720474285] [2021-12-06 22:09:25,547 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:25,547 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:09:25,547 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:25,547 INFO L85 PathProgramCache]: Analyzing trace with hash 1604629988, now seen corresponding path program 1 times [2021-12-06 22:09:25,547 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:25,548 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1355276533] [2021-12-06 22:09:25,548 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:25,548 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:25,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:25,572 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:25,572 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:25,572 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1355276533] [2021-12-06 22:09:25,572 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1355276533] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:25,572 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:25,572 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:09:25,573 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1281497341] [2021-12-06 22:09:25,573 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:25,573 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:09:25,573 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:09:25,573 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 22:09:25,574 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 22:09:25,574 INFO L87 Difference]: Start difference. First operand 7072 states and 10109 transitions. cyclomatic complexity: 3045 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:25,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:09:25,669 INFO L93 Difference]: Finished difference Result 15151 states and 21603 transitions. [2021-12-06 22:09:25,669 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 22:09:25,670 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15151 states and 21603 transitions. [2021-12-06 22:09:25,727 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14912 [2021-12-06 22:09:25,764 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15151 states to 15151 states and 21603 transitions. [2021-12-06 22:09:25,764 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15151 [2021-12-06 22:09:25,773 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15151 [2021-12-06 22:09:25,773 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15151 states and 21603 transitions. [2021-12-06 22:09:25,781 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:09:25,781 INFO L681 BuchiCegarLoop]: Abstraction has 15151 states and 21603 transitions. [2021-12-06 22:09:25,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15151 states and 21603 transitions. [2021-12-06 22:09:25,912 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15151 to 8158. [2021-12-06 22:09:25,922 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8158 states, 8158 states have (on average 1.426084824711939) internal successors, (11634), 8157 states have internal predecessors, (11634), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:25,941 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8158 states to 8158 states and 11634 transitions. [2021-12-06 22:09:25,941 INFO L704 BuchiCegarLoop]: Abstraction has 8158 states and 11634 transitions. [2021-12-06 22:09:25,941 INFO L587 BuchiCegarLoop]: Abstraction has 8158 states and 11634 transitions. [2021-12-06 22:09:25,942 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-06 22:09:25,942 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8158 states and 11634 transitions. [2021-12-06 22:09:25,961 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7968 [2021-12-06 22:09:25,962 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:09:25,962 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:09:25,963 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:25,963 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:25,963 INFO L791 eck$LassoCheckResult]: Stem: 117246#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 117176#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 117092#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 116469#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 116465#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 116466#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 117017#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 117207#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 116555#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 116556#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 116708#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 116574#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 116575#L670 assume !(0 == ~M_E~0); 116969#L670-2 assume !(0 == ~T1_E~0); 116906#L675-1 assume !(0 == ~T2_E~0); 116907#L680-1 assume !(0 == ~T3_E~0); 117014#L685-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 116972#L690-1 assume !(0 == ~T5_E~0); 116973#L695-1 assume !(0 == ~T6_E~0); 117060#L700-1 assume !(0 == ~E_1~0); 117061#L705-1 assume !(0 == ~E_2~0); 117198#L710-1 assume !(0 == ~E_3~0); 116903#L715-1 assume !(0 == ~E_4~0); 116904#L720-1 assume !(0 == ~E_5~0); 116880#L725-1 assume !(0 == ~E_6~0); 116881#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 117086#L320 assume !(1 == ~m_pc~0); 117087#L320-2 is_master_triggered_~__retres1~0#1 := 0; 116753#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 116754#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 116709#L825 assume !(0 != activate_threads_~tmp~1#1); 116710#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 116714#L339 assume !(1 == ~t1_pc~0); 116715#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 116694#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 116695#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 116577#L833 assume !(0 != activate_threads_~tmp___0~0#1); 116578#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 116490#L358 assume !(1 == ~t2_pc~0); 116491#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 117263#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 116970#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 116885#L841 assume !(0 != activate_threads_~tmp___1~0#1); 116704#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 116705#L377 assume !(1 == ~t3_pc~0); 116986#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 116987#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 116981#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 116982#L849 assume !(0 != activate_threads_~tmp___2~0#1); 117010#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 117011#L396 assume !(1 == ~t4_pc~0); 117260#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 116492#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 116493#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 117259#L857 assume !(0 != activate_threads_~tmp___3~0#1); 116632#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 116633#L415 assume !(1 == ~t5_pc~0); 116696#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 116937#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 116938#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 117099#L865 assume !(0 != activate_threads_~tmp___4~0#1); 117100#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 116988#L434 assume !(1 == ~t6_pc~0); 116989#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 117255#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 117256#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 117032#L873 assume !(0 != activate_threads_~tmp___5~0#1); 117033#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 117187#L743 assume !(1 == ~M_E~0); 117188#L743-2 assume !(1 == ~T1_E~0); 117257#L748-1 assume !(1 == ~T2_E~0); 116929#L753-1 assume !(1 == ~T3_E~0); 116930#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 117068#L763-1 assume !(1 == ~T5_E~0); 117131#L768-1 assume !(1 == ~T6_E~0); 116720#L773-1 assume !(1 == ~E_1~0); 116721#L778-1 assume !(1 == ~E_2~0); 116701#L783-1 assume !(1 == ~E_3~0); 116702#L788-1 assume !(1 == ~E_4~0); 117012#L793-1 assume !(1 == ~E_5~0); 116961#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 116594#L803-1 assume { :end_inline_reset_delta_events } true; 116595#L1024-2 [2021-12-06 22:09:25,964 INFO L793 eck$LassoCheckResult]: Loop: 116595#L1024-2 assume !false; 117145#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 116957#L645 assume !false; 117132#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 119787#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 119779#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 119777#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 119774#L556 assume !(0 != eval_~tmp~0#1); 119775#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 123323#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 123322#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 123321#L670-5 assume !(0 == ~T1_E~0); 123320#L675-3 assume !(0 == ~T2_E~0); 123319#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 123317#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 123316#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 123315#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 123314#L700-3 assume !(0 == ~E_1~0); 123313#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 123312#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 123311#L715-3 assume !(0 == ~E_4~0); 123310#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 123309#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 123308#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 123307#L320-21 assume !(1 == ~m_pc~0); 123306#L320-23 is_master_triggered_~__retres1~0#1 := 0; 123305#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 123304#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 123303#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 123302#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 123301#L339-21 assume !(1 == ~t1_pc~0); 123299#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 123298#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 123297#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 123296#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 123295#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 123294#L358-21 assume !(1 == ~t2_pc~0); 122925#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 123293#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 123292#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 123291#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 123290#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 123289#L377-21 assume !(1 == ~t3_pc~0); 123287#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 123286#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 123285#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 123284#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 123283#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 123282#L396-21 assume !(1 == ~t4_pc~0); 123281#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 123280#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 123279#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 123278#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 123277#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 123276#L415-21 assume !(1 == ~t5_pc~0); 123275#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 123274#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 123273#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 123272#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 123271#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 123270#L434-21 assume !(1 == ~t6_pc~0); 123269#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 123267#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 123265#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 123263#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 123261#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 123260#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 123259#L743-5 assume !(1 == ~T1_E~0); 123258#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 123257#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 123255#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 123254#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 123252#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 123250#L773-3 assume !(1 == ~E_1~0); 123248#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 123246#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 123244#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 123241#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 123239#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 123237#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 123228#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 123223#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 123221#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 123162#L1043 assume !(0 == start_simulation_~tmp~3#1); 123160#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 123151#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 123145#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 123144#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 123143#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 123141#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 123139#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 123137#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 116595#L1024-2 [2021-12-06 22:09:25,964 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:25,964 INFO L85 PathProgramCache]: Analyzing trace with hash -975469477, now seen corresponding path program 1 times [2021-12-06 22:09:25,964 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:25,964 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [7568903] [2021-12-06 22:09:25,964 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:25,964 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:25,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:25,984 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:25,984 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:25,985 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [7568903] [2021-12-06 22:09:25,985 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [7568903] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:25,985 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:25,985 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:09:25,985 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [482833540] [2021-12-06 22:09:25,985 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:25,985 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:09:25,986 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:25,986 INFO L85 PathProgramCache]: Analyzing trace with hash 1694018850, now seen corresponding path program 1 times [2021-12-06 22:09:25,986 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:25,986 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [106674014] [2021-12-06 22:09:25,986 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:25,987 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:25,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:26,016 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:26,016 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:26,016 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [106674014] [2021-12-06 22:09:26,016 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [106674014] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:26,016 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:26,016 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 22:09:26,016 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1034166095] [2021-12-06 22:09:26,017 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:26,017 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:09:26,017 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:09:26,018 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 22:09:26,018 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 22:09:26,018 INFO L87 Difference]: Start difference. First operand 8158 states and 11634 transitions. cyclomatic complexity: 3484 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:26,059 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:09:26,059 INFO L93 Difference]: Finished difference Result 7072 states and 10059 transitions. [2021-12-06 22:09:26,060 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:09:26,060 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7072 states and 10059 transitions. [2021-12-06 22:09:26,084 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6944 [2021-12-06 22:09:26,100 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7072 states to 7072 states and 10059 transitions. [2021-12-06 22:09:26,100 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7072 [2021-12-06 22:09:26,104 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7072 [2021-12-06 22:09:26,104 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7072 states and 10059 transitions. [2021-12-06 22:09:26,108 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:09:26,108 INFO L681 BuchiCegarLoop]: Abstraction has 7072 states and 10059 transitions. [2021-12-06 22:09:26,112 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7072 states and 10059 transitions. [2021-12-06 22:09:26,161 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7072 to 7072. [2021-12-06 22:09:26,167 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7072 states, 7072 states have (on average 1.4223699095022624) internal successors, (10059), 7071 states have internal predecessors, (10059), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:26,181 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7072 states to 7072 states and 10059 transitions. [2021-12-06 22:09:26,181 INFO L704 BuchiCegarLoop]: Abstraction has 7072 states and 10059 transitions. [2021-12-06 22:09:26,181 INFO L587 BuchiCegarLoop]: Abstraction has 7072 states and 10059 transitions. [2021-12-06 22:09:26,181 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-06 22:09:26,181 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7072 states and 10059 transitions. [2021-12-06 22:09:26,199 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6944 [2021-12-06 22:09:26,199 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:09:26,199 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:09:26,200 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:26,201 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:26,201 INFO L791 eck$LassoCheckResult]: Stem: 132433#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 132385#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 132309#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 131711#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 131707#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 131708#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 132236#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 132407#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 131799#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 131800#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 131955#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 131818#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 131819#L670 assume !(0 == ~M_E~0); 132196#L670-2 assume !(0 == ~T1_E~0); 132141#L675-1 assume !(0 == ~T2_E~0); 132142#L680-1 assume !(0 == ~T3_E~0); 132235#L685-1 assume !(0 == ~T4_E~0); 132199#L690-1 assume !(0 == ~T5_E~0); 132200#L695-1 assume !(0 == ~T6_E~0); 132279#L700-1 assume !(0 == ~E_1~0); 132267#L705-1 assume !(0 == ~E_2~0); 132268#L710-1 assume !(0 == ~E_3~0); 132139#L715-1 assume !(0 == ~E_4~0); 132061#L720-1 assume !(0 == ~E_5~0); 132062#L725-1 assume !(0 == ~E_6~0); 132118#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 132165#L320 assume !(1 == ~m_pc~0); 132302#L320-2 is_master_triggered_~__retres1~0#1 := 0; 131997#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 131998#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 131956#L825 assume !(0 != activate_threads_~tmp~1#1); 131957#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 131961#L339 assume !(1 == ~t1_pc~0); 131962#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 131941#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 131942#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 131821#L833 assume !(0 != activate_threads_~tmp___0~0#1); 131822#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 131732#L358 assume !(1 == ~t2_pc~0); 131733#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 132262#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 132197#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 132122#L841 assume !(0 != activate_threads_~tmp___1~0#1); 131953#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 131954#L377 assume !(1 == ~t3_pc~0); 132218#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 132219#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 132214#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 131959#L849 assume !(0 != activate_threads_~tmp___2~0#1); 131960#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 131910#L396 assume !(1 == ~t4_pc~0); 131911#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 131734#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 131735#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 132156#L857 assume !(0 != activate_threads_~tmp___3~0#1); 131879#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 131880#L415 assume !(1 == ~t5_pc~0); 131943#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 131988#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 132166#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 132314#L865 assume !(0 != activate_threads_~tmp___4~0#1); 131777#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 131778#L434 assume !(1 == ~t6_pc~0); 132095#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 132096#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 132425#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 132251#L873 assume !(0 != activate_threads_~tmp___5~0#1); 131974#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 131975#L743 assume !(1 == ~M_E~0); 131869#L743-2 assume !(1 == ~T1_E~0); 131870#L748-1 assume !(1 == ~T2_E~0); 132159#L753-1 assume !(1 == ~T3_E~0); 132160#L758-1 assume !(1 == ~T4_E~0); 132282#L763-1 assume !(1 == ~T5_E~0); 132341#L768-1 assume !(1 == ~T6_E~0); 131967#L773-1 assume !(1 == ~E_1~0); 131968#L778-1 assume !(1 == ~E_2~0); 131948#L783-1 assume !(1 == ~E_3~0); 131949#L788-1 assume !(1 == ~E_4~0); 132233#L793-1 assume !(1 == ~E_5~0); 132189#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 131838#L803-1 assume { :end_inline_reset_delta_events } true; 131839#L1024-2 [2021-12-06 22:09:26,201 INFO L793 eck$LassoCheckResult]: Loop: 131839#L1024-2 assume !false; 134240#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 134234#L645 assume !false; 134231#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 134229#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 134221#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 134219#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 134216#L556 assume !(0 != eval_~tmp~0#1); 134217#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 138538#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 138536#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 138534#L670-5 assume !(0 == ~T1_E~0); 138532#L675-3 assume !(0 == ~T2_E~0); 138530#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 138528#L685-3 assume !(0 == ~T4_E~0); 138526#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 138524#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 138522#L700-3 assume !(0 == ~E_1~0); 138520#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 138518#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 138516#L715-3 assume !(0 == ~E_4~0); 138513#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 138510#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 138507#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 138504#L320-21 assume !(1 == ~m_pc~0); 138501#L320-23 is_master_triggered_~__retres1~0#1 := 0; 138498#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 138493#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 138488#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 138485#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 138482#L339-21 assume 1 == ~t1_pc~0; 138478#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 138472#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 138467#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 138461#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 138455#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 134513#L358-21 assume !(1 == ~t2_pc~0); 134511#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 134509#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 134505#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 134503#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 134501#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 134499#L377-21 assume 1 == ~t3_pc~0; 134496#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 134493#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 134489#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 134487#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 134485#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 134480#L396-21 assume !(1 == ~t4_pc~0); 134476#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 134472#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 134471#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 134470#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 134469#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 134468#L415-21 assume !(1 == ~t5_pc~0); 134467#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 134466#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 134465#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 134464#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 134463#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 134462#L434-21 assume !(1 == ~t6_pc~0); 134459#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 134457#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 134456#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 134455#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 134452#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 134449#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 134447#L743-5 assume !(1 == ~T1_E~0); 134445#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 134443#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 134441#L758-3 assume !(1 == ~T4_E~0); 134439#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 134436#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 134434#L773-3 assume !(1 == ~E_1~0); 134432#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 134430#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 134428#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 134427#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 134426#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 134425#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 134421#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 134417#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 134416#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 134271#L1043 assume !(0 == start_simulation_~tmp~3#1); 134269#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 134260#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 134254#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 134252#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 134249#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 134247#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 134245#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 134243#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 131839#L1024-2 [2021-12-06 22:09:26,202 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:26,202 INFO L85 PathProgramCache]: Analyzing trace with hash -2100463913, now seen corresponding path program 1 times [2021-12-06 22:09:26,202 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:26,202 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [777291413] [2021-12-06 22:09:26,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:26,202 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:26,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:26,226 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:26,226 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:26,226 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [777291413] [2021-12-06 22:09:26,226 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [777291413] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:26,226 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:26,227 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:09:26,227 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2042575683] [2021-12-06 22:09:26,227 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:26,227 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:09:26,227 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:26,227 INFO L85 PathProgramCache]: Analyzing trace with hash -1632448928, now seen corresponding path program 1 times [2021-12-06 22:09:26,228 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:26,228 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [214695629] [2021-12-06 22:09:26,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:26,228 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:26,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:26,247 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:26,247 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:26,248 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [214695629] [2021-12-06 22:09:26,248 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [214695629] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:26,248 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:26,248 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:09:26,248 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [537748980] [2021-12-06 22:09:26,248 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:26,248 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:09:26,248 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:09:26,249 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 22:09:26,249 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 22:09:26,249 INFO L87 Difference]: Start difference. First operand 7072 states and 10059 transitions. cyclomatic complexity: 2995 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:26,376 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:09:26,376 INFO L93 Difference]: Finished difference Result 14266 states and 20124 transitions. [2021-12-06 22:09:26,376 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 22:09:26,377 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14266 states and 20124 transitions. [2021-12-06 22:09:26,414 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14012 [2021-12-06 22:09:26,436 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14266 states to 14266 states and 20124 transitions. [2021-12-06 22:09:26,437 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14266 [2021-12-06 22:09:26,441 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14266 [2021-12-06 22:09:26,442 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14266 states and 20124 transitions. [2021-12-06 22:09:26,447 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:09:26,447 INFO L681 BuchiCegarLoop]: Abstraction has 14266 states and 20124 transitions. [2021-12-06 22:09:26,453 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14266 states and 20124 transitions. [2021-12-06 22:09:26,513 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14266 to 7891. [2021-12-06 22:09:26,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7891 states, 7891 states have (on average 1.4116081611962996) internal successors, (11139), 7890 states have internal predecessors, (11139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:26,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7891 states to 7891 states and 11139 transitions. [2021-12-06 22:09:26,530 INFO L704 BuchiCegarLoop]: Abstraction has 7891 states and 11139 transitions. [2021-12-06 22:09:26,530 INFO L587 BuchiCegarLoop]: Abstraction has 7891 states and 11139 transitions. [2021-12-06 22:09:26,530 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-06 22:09:26,530 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7891 states and 11139 transitions. [2021-12-06 22:09:26,545 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7704 [2021-12-06 22:09:26,546 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:09:26,546 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:09:26,547 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:26,547 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:26,547 INFO L791 eck$LassoCheckResult]: Stem: 153841#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 153771#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 153689#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 153059#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 153055#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 153056#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 153615#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 153799#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 153145#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 153146#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 153301#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 153164#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 153165#L670 assume !(0 == ~M_E~0); 153560#L670-2 assume !(0 == ~T1_E~0); 153498#L675-1 assume !(0 == ~T2_E~0); 153499#L680-1 assume !(0 == ~T3_E~0); 153614#L685-1 assume !(0 == ~T4_E~0); 153566#L690-1 assume !(0 == ~T5_E~0); 153567#L695-1 assume !(0 == ~T6_E~0); 153658#L700-1 assume !(0 == ~E_1~0); 153647#L705-1 assume !(0 == ~E_2~0); 153648#L710-1 assume !(0 == ~E_3~0); 153495#L715-1 assume !(0 == ~E_4~0); 153413#L720-1 assume !(0 == ~E_5~0); 153414#L725-1 assume 0 == ~E_6~0;~E_6~0 := 1; 153473#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 153683#L320 assume !(1 == ~m_pc~0); 153684#L320-2 is_master_triggered_~__retres1~0#1 := 0; 153346#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 153347#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 153875#L825 assume !(0 != activate_threads_~tmp~1#1); 153712#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 153713#L339 assume !(1 == ~t1_pc~0); 153517#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 153518#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 153661#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 153662#L833 assume !(0 != activate_threads_~tmp___0~0#1); 153782#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 153783#L358 assume !(1 == ~t2_pc~0); 153640#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 153641#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 153769#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 153478#L841 assume !(0 != activate_threads_~tmp___1~0#1); 153297#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 153298#L377 assume !(1 == ~t3_pc~0); 153593#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 153594#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 153588#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 153589#L849 assume !(0 != activate_threads_~tmp___2~0#1); 153610#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 153611#L396 assume !(1 == ~t4_pc~0); 153870#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 153082#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 153083#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 153869#L857 assume !(0 != activate_threads_~tmp___3~0#1); 153220#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 153221#L415 assume !(1 == ~t5_pc~0); 153331#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 153332#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 153818#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 153819#L865 assume !(0 != activate_threads_~tmp___4~0#1); 153123#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 153124#L434 assume !(1 == ~t6_pc~0); 153868#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 153873#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 153872#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 153863#L873 assume !(0 != activate_threads_~tmp___5~0#1); 153862#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 153861#L743 assume !(1 == ~M_E~0); 153860#L743-2 assume !(1 == ~T1_E~0); 153859#L748-1 assume !(1 == ~T2_E~0); 153858#L753-1 assume !(1 == ~T3_E~0); 153857#L758-1 assume !(1 == ~T4_E~0); 153856#L763-1 assume !(1 == ~T5_E~0); 153855#L768-1 assume !(1 == ~T6_E~0); 153854#L773-1 assume !(1 == ~E_1~0); 153853#L778-1 assume !(1 == ~E_2~0); 153852#L783-1 assume !(1 == ~E_3~0); 153851#L788-1 assume !(1 == ~E_4~0); 153850#L793-1 assume !(1 == ~E_5~0); 153849#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 153184#L803-1 assume { :end_inline_reset_delta_events } true; 153185#L1024-2 [2021-12-06 22:09:26,547 INFO L793 eck$LassoCheckResult]: Loop: 153185#L1024-2 assume !false; 158121#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 158114#L645 assume !false; 158112#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 158110#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 158102#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 157352#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 157345#L556 assume !(0 != eval_~tmp~0#1); 157346#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 158345#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 158343#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 158341#L670-5 assume !(0 == ~T1_E~0); 158339#L675-3 assume !(0 == ~T2_E~0); 158337#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 158335#L685-3 assume !(0 == ~T4_E~0); 158333#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 158331#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 158329#L700-3 assume !(0 == ~E_1~0); 158327#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 158325#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 158323#L715-3 assume !(0 == ~E_4~0); 158321#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 158318#L725-3 assume !(0 == ~E_6~0); 158319#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 160523#L320-21 assume !(1 == ~m_pc~0); 160521#L320-23 is_master_triggered_~__retres1~0#1 := 0; 160518#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 160516#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 160514#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 160512#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 160510#L339-21 assume !(1 == ~t1_pc~0); 160507#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 160504#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 160502#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 160500#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 160498#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 158418#L358-21 assume !(1 == ~t2_pc~0); 158416#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 158414#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 158412#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 158410#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 158408#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 158404#L377-21 assume 1 == ~t3_pc~0; 158402#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 158400#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 158399#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 158398#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 158390#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 158388#L396-21 assume !(1 == ~t4_pc~0); 158386#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 158384#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 158382#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 158380#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 158378#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 158376#L415-21 assume !(1 == ~t5_pc~0); 158371#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 158369#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 158367#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 158359#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 158357#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 158355#L434-21 assume !(1 == ~t6_pc~0); 158277#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 158348#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 158347#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 158346#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 158344#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 158342#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 158340#L743-5 assume !(1 == ~T1_E~0); 158338#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 158336#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 158334#L758-3 assume !(1 == ~T4_E~0); 158332#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 158330#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 158328#L773-3 assume !(1 == ~E_1~0); 158326#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 158324#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 158322#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 158320#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 158256#L798-3 assume !(1 == ~E_6~0); 158252#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 158243#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 158239#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 158237#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 158155#L1043 assume !(0 == start_simulation_~tmp~3#1); 158152#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 158145#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 158139#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 158135#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 158133#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 158131#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 158127#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 158124#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 153185#L1024-2 [2021-12-06 22:09:26,547 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:26,547 INFO L85 PathProgramCache]: Analyzing trace with hash 1760774297, now seen corresponding path program 1 times [2021-12-06 22:09:26,547 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:26,548 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [526953903] [2021-12-06 22:09:26,548 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:26,548 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:26,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:26,565 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:26,566 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:26,566 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [526953903] [2021-12-06 22:09:26,566 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [526953903] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:26,566 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:26,566 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:09:26,566 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [166683409] [2021-12-06 22:09:26,566 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:26,566 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:09:26,566 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:26,566 INFO L85 PathProgramCache]: Analyzing trace with hash 1084617531, now seen corresponding path program 1 times [2021-12-06 22:09:26,567 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:26,567 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [102835019] [2021-12-06 22:09:26,567 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:26,567 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:26,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:26,587 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:26,587 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:26,587 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [102835019] [2021-12-06 22:09:26,587 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [102835019] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:26,587 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:26,587 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 22:09:26,587 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1625721959] [2021-12-06 22:09:26,587 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:26,587 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:09:26,588 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:09:26,588 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 22:09:26,588 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 22:09:26,588 INFO L87 Difference]: Start difference. First operand 7891 states and 11139 transitions. cyclomatic complexity: 3256 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:26,650 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:09:26,650 INFO L93 Difference]: Finished difference Result 9997 states and 14096 transitions. [2021-12-06 22:09:26,651 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 22:09:26,651 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9997 states and 14096 transitions. [2021-12-06 22:09:26,675 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 9852 [2021-12-06 22:09:26,692 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9997 states to 9997 states and 14096 transitions. [2021-12-06 22:09:26,692 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9997 [2021-12-06 22:09:26,696 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9997 [2021-12-06 22:09:26,696 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9997 states and 14096 transitions. [2021-12-06 22:09:26,701 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:09:26,702 INFO L681 BuchiCegarLoop]: Abstraction has 9997 states and 14096 transitions. [2021-12-06 22:09:26,706 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9997 states and 14096 transitions. [2021-12-06 22:09:26,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9997 to 6805. [2021-12-06 22:09:26,761 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6805 states, 6805 states have (on average 1.4054371785451873) internal successors, (9564), 6804 states have internal predecessors, (9564), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:26,773 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6805 states to 6805 states and 9564 transitions. [2021-12-06 22:09:26,773 INFO L704 BuchiCegarLoop]: Abstraction has 6805 states and 9564 transitions. [2021-12-06 22:09:26,773 INFO L587 BuchiCegarLoop]: Abstraction has 6805 states and 9564 transitions. [2021-12-06 22:09:26,773 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-06 22:09:26,773 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6805 states and 9564 transitions. [2021-12-06 22:09:26,801 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6680 [2021-12-06 22:09:26,801 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:09:26,801 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:09:26,802 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:26,802 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:26,802 INFO L791 eck$LassoCheckResult]: Stem: 171637#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 171594#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 171537#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 170959#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 170955#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 170956#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 171482#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 171612#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 171049#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 171050#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 171198#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 171067#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 171068#L670 assume !(0 == ~M_E~0); 171442#L670-2 assume !(0 == ~T1_E~0); 171387#L675-1 assume !(0 == ~T2_E~0); 171388#L680-1 assume !(0 == ~T3_E~0); 171480#L685-1 assume !(0 == ~T4_E~0); 171446#L690-1 assume !(0 == ~T5_E~0); 171447#L695-1 assume !(0 == ~T6_E~0); 171518#L700-1 assume !(0 == ~E_1~0); 171507#L705-1 assume !(0 == ~E_2~0); 171508#L710-1 assume !(0 == ~E_3~0); 171386#L715-1 assume !(0 == ~E_4~0); 171309#L720-1 assume !(0 == ~E_5~0); 171310#L725-1 assume !(0 == ~E_6~0); 171364#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 171412#L320 assume !(1 == ~m_pc~0); 171534#L320-2 is_master_triggered_~__retres1~0#1 := 0; 171240#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 171241#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 171199#L825 assume !(0 != activate_threads_~tmp~1#1); 171200#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 171206#L339 assume !(1 == ~t1_pc~0); 171207#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 171184#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 171185#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 171069#L833 assume !(0 != activate_threads_~tmp___0~0#1); 171070#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 170980#L358 assume !(1 == ~t2_pc~0); 170981#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 171501#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 171443#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 171368#L841 assume !(0 != activate_threads_~tmp___1~0#1); 171196#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 171197#L377 assume !(1 == ~t3_pc~0); 171463#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 171464#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 171462#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 171203#L849 assume !(0 != activate_threads_~tmp___2~0#1); 171204#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 171155#L396 assume !(1 == ~t4_pc~0); 171156#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 170982#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 170983#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 171401#L857 assume !(0 != activate_threads_~tmp___3~0#1); 171122#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 171123#L415 assume !(1 == ~t5_pc~0); 171187#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 171229#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 171413#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 171544#L865 assume !(0 != activate_threads_~tmp___4~0#1); 171025#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 171026#L434 assume !(1 == ~t6_pc~0); 171343#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 171344#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 171493#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 171494#L873 assume !(0 != activate_threads_~tmp___5~0#1); 171215#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 171216#L743 assume !(1 == ~M_E~0); 171114#L743-2 assume !(1 == ~T1_E~0); 171115#L748-1 assume !(1 == ~T2_E~0); 171406#L753-1 assume !(1 == ~T3_E~0); 171407#L758-1 assume !(1 == ~T4_E~0); 171521#L763-1 assume !(1 == ~T5_E~0); 171564#L768-1 assume !(1 == ~T6_E~0); 171213#L773-1 assume !(1 == ~E_1~0); 171214#L778-1 assume !(1 == ~E_2~0); 171191#L783-1 assume !(1 == ~E_3~0); 171192#L788-1 assume !(1 == ~E_4~0); 171477#L793-1 assume !(1 == ~E_5~0); 171435#L798-1 assume !(1 == ~E_6~0); 171088#L803-1 assume { :end_inline_reset_delta_events } true; 171089#L1024-2 [2021-12-06 22:09:26,802 INFO L793 eck$LassoCheckResult]: Loop: 171089#L1024-2 assume !false; 175662#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 175646#L645 assume !false; 175640#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 175461#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 175454#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 175420#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 175412#L556 assume !(0 != eval_~tmp~0#1); 175413#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 176993#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 176992#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 176991#L670-5 assume !(0 == ~T1_E~0); 176990#L675-3 assume !(0 == ~T2_E~0); 176989#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 176988#L685-3 assume !(0 == ~T4_E~0); 176987#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 176986#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 176985#L700-3 assume !(0 == ~E_1~0); 176984#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 176983#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 176982#L715-3 assume !(0 == ~E_4~0); 176981#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 176980#L725-3 assume !(0 == ~E_6~0); 176979#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 176978#L320-21 assume !(1 == ~m_pc~0); 176977#L320-23 is_master_triggered_~__retres1~0#1 := 0; 176976#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 176975#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 176974#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 176972#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 176970#L339-21 assume !(1 == ~t1_pc~0); 176967#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 176910#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 176908#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 176906#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 176904#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 176117#L358-21 assume !(1 == ~t2_pc~0); 176116#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 176030#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 176023#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 176017#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 176006#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 176003#L377-21 assume !(1 == ~t3_pc~0); 176000#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 175998#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 175996#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 175994#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 175992#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 175989#L396-21 assume !(1 == ~t4_pc~0); 175987#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 175985#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 175983#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 175981#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 175979#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 175976#L415-21 assume !(1 == ~t5_pc~0); 175974#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 175972#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 175960#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 175955#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 175950#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 175946#L434-21 assume !(1 == ~t6_pc~0); 175940#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 175936#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 175933#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 175928#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 175927#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 175926#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 175925#L743-5 assume !(1 == ~T1_E~0); 175924#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 175922#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 175920#L758-3 assume !(1 == ~T4_E~0); 175918#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 175917#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 175916#L773-3 assume !(1 == ~E_1~0); 175915#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 175913#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 175911#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 175909#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 175907#L798-3 assume !(1 == ~E_6~0); 175905#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 175894#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 175889#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 175887#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 175825#L1043 assume !(0 == start_simulation_~tmp~3#1); 175823#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 175816#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 175810#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 175779#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 175773#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 175767#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 175760#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 175756#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 171089#L1024-2 [2021-12-06 22:09:26,803 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:26,803 INFO L85 PathProgramCache]: Analyzing trace with hash -2100463851, now seen corresponding path program 1 times [2021-12-06 22:09:26,803 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:26,803 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1659772206] [2021-12-06 22:09:26,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:26,803 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:26,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:26,809 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:09:26,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:26,847 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:09:26,847 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:26,847 INFO L85 PathProgramCache]: Analyzing trace with hash -645719526, now seen corresponding path program 1 times [2021-12-06 22:09:26,847 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:26,847 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1560652536] [2021-12-06 22:09:26,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:26,848 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:26,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:26,870 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:26,871 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:26,871 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1560652536] [2021-12-06 22:09:26,871 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1560652536] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:26,871 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:26,871 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 22:09:26,871 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1037114823] [2021-12-06 22:09:26,871 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:26,872 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:09:26,872 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:09:26,872 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-06 22:09:26,872 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-06 22:09:26,872 INFO L87 Difference]: Start difference. First operand 6805 states and 9564 transitions. cyclomatic complexity: 2767 Second operand has 5 states, 5 states have (on average 18.4) internal successors, (92), 5 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:26,957 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:09:26,957 INFO L93 Difference]: Finished difference Result 12165 states and 16868 transitions. [2021-12-06 22:09:26,958 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-06 22:09:26,958 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12165 states and 16868 transitions. [2021-12-06 22:09:26,991 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 12000 [2021-12-06 22:09:27,010 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12165 states to 12165 states and 16868 transitions. [2021-12-06 22:09:27,010 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12165 [2021-12-06 22:09:27,016 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12165 [2021-12-06 22:09:27,016 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12165 states and 16868 transitions. [2021-12-06 22:09:27,024 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:09:27,025 INFO L681 BuchiCegarLoop]: Abstraction has 12165 states and 16868 transitions. [2021-12-06 22:09:27,031 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12165 states and 16868 transitions. [2021-12-06 22:09:27,077 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12165 to 6853. [2021-12-06 22:09:27,082 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6853 states, 6853 states have (on average 1.4025974025974026) internal successors, (9612), 6852 states have internal predecessors, (9612), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:27,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6853 states to 6853 states and 9612 transitions. [2021-12-06 22:09:27,092 INFO L704 BuchiCegarLoop]: Abstraction has 6853 states and 9612 transitions. [2021-12-06 22:09:27,092 INFO L587 BuchiCegarLoop]: Abstraction has 6853 states and 9612 transitions. [2021-12-06 22:09:27,092 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-06 22:09:27,092 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6853 states and 9612 transitions. [2021-12-06 22:09:27,107 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6728 [2021-12-06 22:09:27,107 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:09:27,107 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:09:27,108 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:27,108 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:27,108 INFO L791 eck$LassoCheckResult]: Stem: 190658#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 190602#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 190532#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 189945#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 189941#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 189942#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 190470#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 190635#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 190032#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 190033#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 190182#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 190051#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 190052#L670 assume !(0 == ~M_E~0); 190432#L670-2 assume !(0 == ~T1_E~0); 190373#L675-1 assume !(0 == ~T2_E~0); 190374#L680-1 assume !(0 == ~T3_E~0); 190468#L685-1 assume !(0 == ~T4_E~0); 190436#L690-1 assume !(0 == ~T5_E~0); 190437#L695-1 assume !(0 == ~T6_E~0); 190504#L700-1 assume !(0 == ~E_1~0); 190495#L705-1 assume !(0 == ~E_2~0); 190496#L710-1 assume !(0 == ~E_3~0); 190372#L715-1 assume !(0 == ~E_4~0); 190290#L720-1 assume !(0 == ~E_5~0); 190291#L725-1 assume !(0 == ~E_6~0); 190348#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 190399#L320 assume !(1 == ~m_pc~0); 190529#L320-2 is_master_triggered_~__retres1~0#1 := 0; 190224#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 190225#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 190183#L825 assume !(0 != activate_threads_~tmp~1#1); 190184#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 190191#L339 assume !(1 == ~t1_pc~0); 190192#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 190168#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 190169#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 190053#L833 assume !(0 != activate_threads_~tmp___0~0#1); 190054#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 189966#L358 assume !(1 == ~t2_pc~0); 189967#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 190489#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 190433#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 190353#L841 assume !(0 != activate_threads_~tmp___1~0#1); 190180#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 190181#L377 assume !(1 == ~t3_pc~0); 190453#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 190454#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 190452#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 190186#L849 assume !(0 != activate_threads_~tmp___2~0#1); 190187#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 190139#L396 assume !(1 == ~t4_pc~0); 190140#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 189968#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 189969#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 190389#L857 assume !(0 != activate_threads_~tmp___3~0#1); 190105#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 190106#L415 assume !(1 == ~t5_pc~0); 190171#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 190214#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 190400#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 190539#L865 assume !(0 != activate_threads_~tmp___4~0#1); 190008#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 190009#L434 assume !(1 == ~t6_pc~0); 190323#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 190324#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 190480#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 190481#L873 assume !(0 != activate_threads_~tmp___5~0#1); 190200#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 190201#L743 assume !(1 == ~M_E~0); 190098#L743-2 assume !(1 == ~T1_E~0); 190099#L748-1 assume !(1 == ~T2_E~0); 190392#L753-1 assume !(1 == ~T3_E~0); 190393#L758-1 assume !(1 == ~T4_E~0); 190507#L763-1 assume !(1 == ~T5_E~0); 190567#L768-1 assume !(1 == ~T6_E~0); 190198#L773-1 assume !(1 == ~E_1~0); 190199#L778-1 assume !(1 == ~E_2~0); 190175#L783-1 assume !(1 == ~E_3~0); 190176#L788-1 assume !(1 == ~E_4~0); 190466#L793-1 assume !(1 == ~E_5~0); 190422#L798-1 assume !(1 == ~E_6~0); 190072#L803-1 assume { :end_inline_reset_delta_events } true; 190073#L1024-2 [2021-12-06 22:09:27,108 INFO L793 eck$LassoCheckResult]: Loop: 190073#L1024-2 assume !false; 193457#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 193087#L645 assume !false; 192991#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 192634#L504 assume !(0 == ~m_st~0); 192629#L508 assume !(0 == ~t1_st~0); 192630#L512 assume !(0 == ~t2_st~0); 192632#L516 assume !(0 == ~t3_st~0); 192627#L520 assume !(0 == ~t4_st~0); 192628#L524 assume !(0 == ~t5_st~0); 192631#L528 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 192633#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 192621#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 192622#L556 assume !(0 != eval_~tmp~0#1); 193695#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 193693#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 193691#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 193689#L670-5 assume !(0 == ~T1_E~0); 193687#L675-3 assume !(0 == ~T2_E~0); 193685#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 193683#L685-3 assume !(0 == ~T4_E~0); 193681#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 193679#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 193677#L700-3 assume !(0 == ~E_1~0); 193675#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 193673#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 193671#L715-3 assume !(0 == ~E_4~0); 193669#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 193667#L725-3 assume !(0 == ~E_6~0); 193665#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 193663#L320-21 assume !(1 == ~m_pc~0); 193661#L320-23 is_master_triggered_~__retres1~0#1 := 0; 193659#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 193657#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 193655#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 193653#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 193651#L339-21 assume 1 == ~t1_pc~0; 193648#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 193645#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 193643#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 193641#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 193639#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 193636#L358-21 assume !(1 == ~t2_pc~0); 193635#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 193634#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 193633#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 193632#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 193631#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 193630#L377-21 assume !(1 == ~t3_pc~0); 193628#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 193627#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 193626#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 193625#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 193624#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 193623#L396-21 assume !(1 == ~t4_pc~0); 193622#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 193621#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 193620#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 193619#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 193618#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 193617#L415-21 assume !(1 == ~t5_pc~0); 193616#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 193615#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 193614#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 193613#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 193612#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 193611#L434-21 assume !(1 == ~t6_pc~0); 193609#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 193608#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 193607#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 193606#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 193605#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 193604#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 193603#L743-5 assume !(1 == ~T1_E~0); 193602#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 193601#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 193600#L758-3 assume !(1 == ~T4_E~0); 193599#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 193598#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 193597#L773-3 assume !(1 == ~E_1~0); 193596#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 193595#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 193594#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 193593#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 193592#L798-3 assume !(1 == ~E_6~0); 193591#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 193587#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 193582#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 193580#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 193576#L1043 assume !(0 == start_simulation_~tmp~3#1); 193541#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 193538#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 193532#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 193524#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 193476#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 193471#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 193469#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 193467#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 190073#L1024-2 [2021-12-06 22:09:27,109 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:27,109 INFO L85 PathProgramCache]: Analyzing trace with hash -2100463851, now seen corresponding path program 2 times [2021-12-06 22:09:27,109 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:27,109 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [789123807] [2021-12-06 22:09:27,109 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:27,109 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:27,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:27,116 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:09:27,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:27,133 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:09:27,134 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:27,134 INFO L85 PathProgramCache]: Analyzing trace with hash -461444470, now seen corresponding path program 1 times [2021-12-06 22:09:27,134 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:27,134 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [626921210] [2021-12-06 22:09:27,134 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:27,134 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:27,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:27,152 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:27,153 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:27,153 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [626921210] [2021-12-06 22:09:27,153 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [626921210] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:27,153 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:27,153 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:09:27,153 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2016219515] [2021-12-06 22:09:27,153 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:27,153 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:09:27,153 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:09:27,154 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:09:27,154 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:09:27,154 INFO L87 Difference]: Start difference. First operand 6853 states and 9612 transitions. cyclomatic complexity: 2767 Second operand has 3 states, 3 states have (on average 32.666666666666664) internal successors, (98), 3 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:27,216 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:09:27,217 INFO L93 Difference]: Finished difference Result 12493 states and 17305 transitions. [2021-12-06 22:09:27,217 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:09:27,217 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12493 states and 17305 transitions. [2021-12-06 22:09:27,252 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 12284 [2021-12-06 22:09:27,273 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12493 states to 12493 states and 17305 transitions. [2021-12-06 22:09:27,273 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12493 [2021-12-06 22:09:27,277 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12493 [2021-12-06 22:09:27,277 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12493 states and 17305 transitions. [2021-12-06 22:09:27,281 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:09:27,281 INFO L681 BuchiCegarLoop]: Abstraction has 12493 states and 17305 transitions. [2021-12-06 22:09:27,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12493 states and 17305 transitions. [2021-12-06 22:09:27,344 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12493 to 12453. [2021-12-06 22:09:27,352 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12453 states, 12453 states have (on average 1.3864129125511926) internal successors, (17265), 12452 states have internal predecessors, (17265), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:27,376 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12453 states to 12453 states and 17265 transitions. [2021-12-06 22:09:27,376 INFO L704 BuchiCegarLoop]: Abstraction has 12453 states and 17265 transitions. [2021-12-06 22:09:27,376 INFO L587 BuchiCegarLoop]: Abstraction has 12453 states and 17265 transitions. [2021-12-06 22:09:27,376 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-06 22:09:27,376 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12453 states and 17265 transitions. [2021-12-06 22:09:27,406 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 12252 [2021-12-06 22:09:27,406 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:09:27,406 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:09:27,408 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:27,408 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:27,408 INFO L791 eck$LassoCheckResult]: Stem: 210059#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 209994#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 209903#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 209297#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 209293#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 209294#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 209836#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 210024#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 209384#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 209385#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 209541#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 209403#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 209404#L670 assume !(0 == ~M_E~0); 209796#L670-2 assume !(0 == ~T1_E~0); 209735#L675-1 assume !(0 == ~T2_E~0); 209736#L680-1 assume !(0 == ~T3_E~0); 209835#L685-1 assume !(0 == ~T4_E~0); 209799#L690-1 assume !(0 == ~T5_E~0); 209800#L695-1 assume !(0 == ~T6_E~0); 209878#L700-1 assume !(0 == ~E_1~0); 209867#L705-1 assume !(0 == ~E_2~0); 209868#L710-1 assume !(0 == ~E_3~0); 209733#L715-1 assume !(0 == ~E_4~0); 209652#L720-1 assume !(0 == ~E_5~0); 209653#L725-1 assume !(0 == ~E_6~0); 209712#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 209763#L320 assume !(1 == ~m_pc~0); 209898#L320-2 is_master_triggered_~__retres1~0#1 := 0; 209585#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 209586#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 209542#L825 assume !(0 != activate_threads_~tmp~1#1); 209543#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 209548#L339 assume !(1 == ~t1_pc~0); 209549#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 209907#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 209881#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 209406#L833 assume !(0 != activate_threads_~tmp___0~0#1); 209407#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 210089#L358 assume !(1 == ~t2_pc~0); 209861#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 209862#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 209992#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 210087#L841 assume !(0 != activate_threads_~tmp___1~0#1); 210086#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 210085#L377 assume !(1 == ~t3_pc~0); 209817#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 209818#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 209825#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 209546#L849 assume !(0 != activate_threads_~tmp___2~0#1); 209547#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 209492#L396 assume !(1 == ~t4_pc~0); 209493#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 209320#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 209321#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 210079#L857 assume !(0 != activate_threads_~tmp___3~0#1); 210078#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 210077#L415 assume !(1 == ~t5_pc~0); 209571#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 209572#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 210039#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 209910#L865 assume !(0 != activate_threads_~tmp___4~0#1); 209361#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 209362#L434 assume !(1 == ~t6_pc~0); 209688#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 209689#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 209850#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 210070#L873 assume !(0 != activate_threads_~tmp___5~0#1); 209559#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 209560#L743 assume !(1 == ~M_E~0); 209452#L743-2 assume !(1 == ~T1_E~0); 209453#L748-1 assume !(1 == ~T2_E~0); 209973#L753-1 assume !(1 == ~T3_E~0); 210068#L758-1 assume !(1 == ~T4_E~0); 210067#L763-1 assume !(1 == ~T5_E~0); 210066#L768-1 assume !(1 == ~T6_E~0); 210065#L773-1 assume !(1 == ~E_1~0); 209553#L778-1 assume !(1 == ~E_2~0); 209534#L783-1 assume !(1 == ~E_3~0); 209535#L788-1 assume !(1 == ~E_4~0); 209833#L793-1 assume !(1 == ~E_5~0); 209789#L798-1 assume !(1 == ~E_6~0); 209423#L803-1 assume { :end_inline_reset_delta_events } true; 209424#L1024-2 [2021-12-06 22:09:27,408 INFO L793 eck$LassoCheckResult]: Loop: 209424#L1024-2 assume !false; 215157#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 215152#L645 assume !false; 215151#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 215150#L504 assume !(0 == ~m_st~0); 215145#L508 assume !(0 == ~t1_st~0); 215146#L512 assume !(0 == ~t2_st~0); 215148#L516 assume !(0 == ~t3_st~0); 215143#L520 assume !(0 == ~t4_st~0); 215144#L524 assume !(0 == ~t5_st~0); 215147#L528 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 215149#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 215109#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 215110#L556 assume !(0 != eval_~tmp~0#1); 216154#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 216150#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 216146#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 216142#L670-5 assume !(0 == ~T1_E~0); 216138#L675-3 assume !(0 == ~T2_E~0); 216134#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 216130#L685-3 assume !(0 == ~T4_E~0); 216126#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 216122#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 216118#L700-3 assume !(0 == ~E_1~0); 216114#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 216110#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 216106#L715-3 assume !(0 == ~E_4~0); 216102#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 216098#L725-3 assume !(0 == ~E_6~0); 216094#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 216090#L320-21 assume !(1 == ~m_pc~0); 216086#L320-23 is_master_triggered_~__retres1~0#1 := 0; 216082#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 216078#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 216074#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 216071#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 216067#L339-21 assume !(1 == ~t1_pc~0); 216064#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 216062#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 216057#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 215983#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 215984#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 215490#L358-21 assume !(1 == ~t2_pc~0); 215483#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 215478#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 215473#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 215468#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 215464#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 215459#L377-21 assume 1 == ~t3_pc~0; 215446#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 215443#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 215441#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 215439#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 215437#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 215435#L396-21 assume !(1 == ~t4_pc~0); 215433#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 215430#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 215428#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 215426#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 215415#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 215410#L415-21 assume !(1 == ~t5_pc~0); 215405#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 215367#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 215364#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 215362#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 215360#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 215358#L434-21 assume !(1 == ~t6_pc~0); 215355#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 215353#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 215341#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 215334#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 215327#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 215321#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 215313#L743-5 assume !(1 == ~T1_E~0); 215306#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 215299#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 215290#L758-3 assume !(1 == ~T4_E~0); 215280#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 215275#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 215243#L773-3 assume !(1 == ~E_1~0); 215241#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 215240#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 215199#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 215196#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 215194#L798-3 assume !(1 == ~E_6~0); 215192#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 215187#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 215182#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 215180#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 215177#L1043 assume !(0 == start_simulation_~tmp~3#1); 215176#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 215173#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 215168#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 215167#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 215166#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 215165#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 215164#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 215162#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 209424#L1024-2 [2021-12-06 22:09:27,409 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:27,409 INFO L85 PathProgramCache]: Analyzing trace with hash -2100463851, now seen corresponding path program 3 times [2021-12-06 22:09:27,409 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:27,409 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [170334750] [2021-12-06 22:09:27,409 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:27,409 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:27,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:27,417 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:09:27,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:27,434 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:09:27,434 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:27,434 INFO L85 PathProgramCache]: Analyzing trace with hash -1206348790, now seen corresponding path program 1 times [2021-12-06 22:09:27,435 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:27,435 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1722409678] [2021-12-06 22:09:27,435 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:27,435 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:27,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:27,482 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:27,483 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:27,483 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1722409678] [2021-12-06 22:09:27,483 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1722409678] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:27,483 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:27,483 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 22:09:27,483 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1764232901] [2021-12-06 22:09:27,483 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:27,484 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:09:27,484 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:09:27,484 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-06 22:09:27,484 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-06 22:09:27,484 INFO L87 Difference]: Start difference. First operand 12453 states and 17265 transitions. cyclomatic complexity: 4820 Second operand has 5 states, 5 states have (on average 19.6) internal successors, (98), 5 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:27,650 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:09:27,650 INFO L93 Difference]: Finished difference Result 24549 states and 33832 transitions. [2021-12-06 22:09:27,650 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-06 22:09:27,651 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24549 states and 33832 transitions. [2021-12-06 22:09:27,732 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 24284 [2021-12-06 22:09:27,763 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24549 states to 24549 states and 33832 transitions. [2021-12-06 22:09:27,764 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24549 [2021-12-06 22:09:27,771 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24549 [2021-12-06 22:09:27,771 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24549 states and 33832 transitions. [2021-12-06 22:09:27,777 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:09:27,777 INFO L681 BuchiCegarLoop]: Abstraction has 24549 states and 33832 transitions. [2021-12-06 22:09:27,783 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24549 states and 33832 transitions. [2021-12-06 22:09:27,860 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24549 to 12717. [2021-12-06 22:09:27,868 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12717 states, 12717 states have (on average 1.3720217032318942) internal successors, (17448), 12716 states have internal predecessors, (17448), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:27,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12717 states to 12717 states and 17448 transitions. [2021-12-06 22:09:27,887 INFO L704 BuchiCegarLoop]: Abstraction has 12717 states and 17448 transitions. [2021-12-06 22:09:27,887 INFO L587 BuchiCegarLoop]: Abstraction has 12717 states and 17448 transitions. [2021-12-06 22:09:27,887 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-06 22:09:27,887 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12717 states and 17448 transitions. [2021-12-06 22:09:27,913 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 12516 [2021-12-06 22:09:27,913 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:09:27,913 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:09:27,914 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:27,914 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:27,915 INFO L791 eck$LassoCheckResult]: Stem: 247101#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 247033#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 246951#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 246312#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 246308#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 246309#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 246869#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 247068#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 246400#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 246401#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 246557#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 246418#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 246419#L670 assume !(0 == ~M_E~0); 246823#L670-2 assume !(0 == ~T1_E~0); 246757#L675-1 assume !(0 == ~T2_E~0); 246758#L680-1 assume !(0 == ~T3_E~0); 246867#L685-1 assume !(0 == ~T4_E~0); 246828#L690-1 assume !(0 == ~T5_E~0); 246829#L695-1 assume !(0 == ~T6_E~0); 246919#L700-1 assume !(0 == ~E_1~0); 246905#L705-1 assume !(0 == ~E_2~0); 246906#L710-1 assume !(0 == ~E_3~0); 246756#L715-1 assume !(0 == ~E_4~0); 246668#L720-1 assume !(0 == ~E_5~0); 246669#L725-1 assume !(0 == ~E_6~0); 246731#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 246788#L320 assume !(1 == ~m_pc~0); 246941#L320-2 is_master_triggered_~__retres1~0#1 := 0; 246602#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 246603#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 246558#L825 assume !(0 != activate_threads_~tmp~1#1); 246559#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 246567#L339 assume !(1 == ~t1_pc~0); 246568#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 246955#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 246923#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 246420#L833 assume !(0 != activate_threads_~tmp___0~0#1); 246421#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 247127#L358 assume !(1 == ~t2_pc~0); 246897#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 246898#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 247031#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 247125#L841 assume !(0 != activate_threads_~tmp___1~0#1); 247124#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 247123#L377 assume !(1 == ~t3_pc~0); 246847#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 246848#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 246845#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 246846#L849 assume !(0 != activate_threads_~tmp___2~0#1); 247122#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 246506#L396 assume !(1 == ~t4_pc~0); 246507#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 246335#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 246336#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 247119#L857 assume !(0 != activate_threads_~tmp___3~0#1); 247118#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 247117#L415 assume !(1 == ~t5_pc~0); 246591#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 246592#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 247079#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 246958#L865 assume !(0 != activate_threads_~tmp___4~0#1); 246376#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 246377#L434 assume !(1 == ~t6_pc~0); 246707#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 246708#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 246883#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 247110#L873 assume !(0 != activate_threads_~tmp___5~0#1); 246577#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 246578#L743 assume !(1 == ~M_E~0); 246465#L743-2 assume !(1 == ~T1_E~0); 246466#L748-1 assume !(1 == ~T2_E~0); 247013#L753-1 assume !(1 == ~T3_E~0); 247108#L758-1 assume !(1 == ~T4_E~0); 247107#L763-1 assume !(1 == ~T5_E~0); 247106#L768-1 assume !(1 == ~T6_E~0); 247105#L773-1 assume !(1 == ~E_1~0); 246576#L778-1 assume !(1 == ~E_2~0); 246550#L783-1 assume !(1 == ~E_3~0); 246551#L788-1 assume !(1 == ~E_4~0); 246864#L793-1 assume !(1 == ~E_5~0); 246812#L798-1 assume !(1 == ~E_6~0); 246439#L803-1 assume { :end_inline_reset_delta_events } true; 246440#L1024-2 [2021-12-06 22:09:27,915 INFO L793 eck$LassoCheckResult]: Loop: 246440#L1024-2 assume !false; 252072#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 252064#L645 assume !false; 252060#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 252041#L504 assume !(0 == ~m_st~0); 252036#L508 assume !(0 == ~t1_st~0); 252037#L512 assume !(0 == ~t2_st~0); 252039#L516 assume !(0 == ~t3_st~0); 252034#L520 assume !(0 == ~t4_st~0); 252035#L524 assume !(0 == ~t5_st~0); 252038#L528 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 252040#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 251767#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 251768#L556 assume !(0 != eval_~tmp~0#1); 252474#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 252475#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 252466#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 252467#L670-5 assume !(0 == ~T1_E~0); 252458#L675-3 assume !(0 == ~T2_E~0); 252459#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 252450#L685-3 assume !(0 == ~T4_E~0); 252451#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 252442#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 252443#L700-3 assume !(0 == ~E_1~0); 252434#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 252435#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 252426#L715-3 assume !(0 == ~E_4~0); 252427#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 252418#L725-3 assume !(0 == ~E_6~0); 252419#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 252410#L320-21 assume !(1 == ~m_pc~0); 252411#L320-23 is_master_triggered_~__retres1~0#1 := 0; 252402#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 252403#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 252394#L825-21 assume !(0 != activate_threads_~tmp~1#1); 252395#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 252386#L339-21 assume !(1 == ~t1_pc~0); 252387#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 252377#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 252378#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 252369#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 252370#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 252363#L358-21 assume !(1 == ~t2_pc~0); 252361#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 252359#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 252357#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 252353#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 252349#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 252345#L377-21 assume !(1 == ~t3_pc~0); 252339#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 252335#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 252331#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 252327#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 252321#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 252317#L396-21 assume !(1 == ~t4_pc~0); 252313#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 252309#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 252305#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 252301#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 252297#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 252293#L415-21 assume !(1 == ~t5_pc~0); 252289#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 252285#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 252281#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 252277#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 252272#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 252266#L434-21 assume !(1 == ~t6_pc~0); 252260#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 252255#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 252250#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 252243#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 252238#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 252232#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 252228#L743-5 assume !(1 == ~T1_E~0); 252223#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 252218#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 252213#L758-3 assume !(1 == ~T4_E~0); 252207#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 252202#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 252196#L773-3 assume !(1 == ~E_1~0); 252189#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 252184#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 252178#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 252174#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 252170#L798-3 assume !(1 == ~E_6~0); 252167#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 252148#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 252141#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 252137#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 252132#L1043 assume !(0 == start_simulation_~tmp~3#1); 252130#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 252123#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 252115#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 252111#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 252107#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 252103#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 252098#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 252094#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 246440#L1024-2 [2021-12-06 22:09:27,915 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:27,915 INFO L85 PathProgramCache]: Analyzing trace with hash -2100463851, now seen corresponding path program 4 times [2021-12-06 22:09:27,915 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:27,915 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [776772791] [2021-12-06 22:09:27,915 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:27,916 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:27,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:27,923 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:09:27,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:27,938 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:09:27,938 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:27,938 INFO L85 PathProgramCache]: Analyzing trace with hash 1303888551, now seen corresponding path program 1 times [2021-12-06 22:09:27,938 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:27,939 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [410526402] [2021-12-06 22:09:27,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:27,939 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:27,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:27,958 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:27,958 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:27,958 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [410526402] [2021-12-06 22:09:27,958 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [410526402] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:27,958 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:27,958 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:09:27,958 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [619883395] [2021-12-06 22:09:27,958 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:27,959 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:09:27,959 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:09:27,959 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:09:27,959 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:09:27,959 INFO L87 Difference]: Start difference. First operand 12717 states and 17448 transitions. cyclomatic complexity: 4739 Second operand has 3 states, 3 states have (on average 32.666666666666664) internal successors, (98), 3 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:28,020 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:09:28,020 INFO L93 Difference]: Finished difference Result 22067 states and 29886 transitions. [2021-12-06 22:09:28,020 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:09:28,021 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22067 states and 29886 transitions. [2021-12-06 22:09:28,080 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21800 [2021-12-06 22:09:28,119 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22067 states to 22067 states and 29886 transitions. [2021-12-06 22:09:28,119 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22067 [2021-12-06 22:09:28,128 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22067 [2021-12-06 22:09:28,128 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22067 states and 29886 transitions. [2021-12-06 22:09:28,137 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:09:28,137 INFO L681 BuchiCegarLoop]: Abstraction has 22067 states and 29886 transitions. [2021-12-06 22:09:28,146 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22067 states and 29886 transitions. [2021-12-06 22:09:28,285 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22067 to 21711. [2021-12-06 22:09:28,297 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21711 states, 21711 states have (on average 1.3557182994795265) internal successors, (29434), 21710 states have internal predecessors, (29434), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:28,334 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21711 states to 21711 states and 29434 transitions. [2021-12-06 22:09:28,334 INFO L704 BuchiCegarLoop]: Abstraction has 21711 states and 29434 transitions. [2021-12-06 22:09:28,334 INFO L587 BuchiCegarLoop]: Abstraction has 21711 states and 29434 transitions. [2021-12-06 22:09:28,334 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-06 22:09:28,335 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21711 states and 29434 transitions. [2021-12-06 22:09:28,389 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21444 [2021-12-06 22:09:28,389 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:09:28,389 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:09:28,390 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:28,390 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:28,390 INFO L791 eck$LassoCheckResult]: Stem: 281876#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 281795#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 281709#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 281102#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 281098#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 281099#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 281636#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 281836#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 281189#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 281190#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 281344#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 281207#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 281208#L670 assume !(0 == ~M_E~0); 281591#L670-2 assume !(0 == ~T1_E~0); 281534#L675-1 assume !(0 == ~T2_E~0); 281535#L680-1 assume !(0 == ~T3_E~0); 281634#L685-1 assume !(0 == ~T4_E~0); 281596#L690-1 assume !(0 == ~T5_E~0); 281597#L695-1 assume !(0 == ~T6_E~0); 281681#L700-1 assume !(0 == ~E_1~0); 281670#L705-1 assume !(0 == ~E_2~0); 281671#L710-1 assume !(0 == ~E_3~0); 281533#L715-1 assume !(0 == ~E_4~0); 281455#L720-1 assume !(0 == ~E_5~0); 281456#L725-1 assume !(0 == ~E_6~0); 281510#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 281560#L320 assume !(1 == ~m_pc~0); 281704#L320-2 is_master_triggered_~__retres1~0#1 := 0; 281388#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 281389#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 281345#L825 assume !(0 != activate_threads_~tmp~1#1); 281346#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 281354#L339 assume !(1 == ~t1_pc~0); 281355#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 281714#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 281684#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 281209#L833 assume !(0 != activate_threads_~tmp___0~0#1); 281210#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 281901#L358 assume !(1 == ~t2_pc~0); 281663#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 281664#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 281792#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 281899#L841 assume !(0 != activate_threads_~tmp___1~0#1); 281898#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 281897#L377 assume !(1 == ~t3_pc~0); 281614#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 281615#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 281612#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 281613#L849 assume !(0 != activate_threads_~tmp___2~0#1); 281896#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 281297#L396 assume !(1 == ~t4_pc~0); 281298#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 281125#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 281126#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 281893#L857 assume !(0 != activate_threads_~tmp___3~0#1); 281892#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 281891#L415 assume !(1 == ~t5_pc~0); 281377#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 281378#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 281855#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 281719#L865 assume !(0 != activate_threads_~tmp___4~0#1); 281165#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 281166#L434 assume !(1 == ~t6_pc~0); 281487#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 281488#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 281649#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 281884#L873 assume !(0 != activate_threads_~tmp___5~0#1); 281363#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 281364#L743 assume !(1 == ~M_E~0); 281255#L743-2 assume !(1 == ~T1_E~0); 281256#L748-1 assume !(1 == ~T2_E~0); 281781#L753-1 assume !(1 == ~T3_E~0); 281882#L758-1 assume !(1 == ~T4_E~0); 281881#L763-1 assume !(1 == ~T5_E~0); 281880#L768-1 assume !(1 == ~T6_E~0); 281879#L773-1 assume !(1 == ~E_1~0); 281362#L778-1 assume !(1 == ~E_2~0); 281337#L783-1 assume !(1 == ~E_3~0); 281338#L788-1 assume !(1 == ~E_4~0); 281631#L793-1 assume !(1 == ~E_5~0); 281585#L798-1 assume !(1 == ~E_6~0); 281228#L803-1 assume { :end_inline_reset_delta_events } true; 281229#L1024-2 assume !false; 293974#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 293968#L645 [2021-12-06 22:09:28,390 INFO L793 eck$LassoCheckResult]: Loop: 293968#L645 assume !false; 293966#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 293963#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 293961#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 293959#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 293957#L556 assume 0 != eval_~tmp~0#1; 293953#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 293930#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 293929#L561 assume !(0 == ~t1_st~0); 293921#L575 assume !(0 == ~t2_st~0); 293918#L589 assume !(0 == ~t3_st~0); 293983#L603 assume !(0 == ~t4_st~0); 293979#L617 assume !(0 == ~t5_st~0); 293973#L631 assume !(0 == ~t6_st~0); 293968#L645 [2021-12-06 22:09:28,390 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:28,391 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 1 times [2021-12-06 22:09:28,391 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:28,391 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1542159780] [2021-12-06 22:09:28,391 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:28,391 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:28,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:28,399 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:09:28,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:28,415 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:09:28,415 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:28,415 INFO L85 PathProgramCache]: Analyzing trace with hash -1489034978, now seen corresponding path program 1 times [2021-12-06 22:09:28,415 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:28,416 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [701382554] [2021-12-06 22:09:28,416 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:28,416 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:28,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:28,418 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:09:28,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:28,421 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:09:28,422 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:28,422 INFO L85 PathProgramCache]: Analyzing trace with hash 1336774676, now seen corresponding path program 1 times [2021-12-06 22:09:28,422 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:28,422 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [297964793] [2021-12-06 22:09:28,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:28,422 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:28,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:28,445 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:28,445 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:28,445 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [297964793] [2021-12-06 22:09:28,446 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [297964793] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:28,446 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:28,446 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:09:28,446 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [347936857] [2021-12-06 22:09:28,446 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:28,511 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:09:28,512 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:09:28,512 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:09:28,512 INFO L87 Difference]: Start difference. First operand 21711 states and 29434 transitions. cyclomatic complexity: 7739 Second operand has 3 states, 3 states have (on average 32.666666666666664) internal successors, (98), 3 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:28,639 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:09:28,639 INFO L93 Difference]: Finished difference Result 40712 states and 54773 transitions. [2021-12-06 22:09:28,639 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:09:28,640 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40712 states and 54773 transitions. [2021-12-06 22:09:28,786 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 40184 [2021-12-06 22:09:28,880 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40712 states to 40712 states and 54773 transitions. [2021-12-06 22:09:28,881 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40712 [2021-12-06 22:09:28,900 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40712 [2021-12-06 22:09:28,900 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40712 states and 54773 transitions. [2021-12-06 22:09:28,920 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:09:28,920 INFO L681 BuchiCegarLoop]: Abstraction has 40712 states and 54773 transitions. [2021-12-06 22:09:28,938 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40712 states and 54773 transitions. [2021-12-06 22:09:29,187 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40712 to 38312. [2021-12-06 22:09:29,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38312 states, 38312 states have (on average 1.3503079974942578) internal successors, (51733), 38311 states have internal predecessors, (51733), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:29,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38312 states to 38312 states and 51733 transitions. [2021-12-06 22:09:29,283 INFO L704 BuchiCegarLoop]: Abstraction has 38312 states and 51733 transitions. [2021-12-06 22:09:29,283 INFO L587 BuchiCegarLoop]: Abstraction has 38312 states and 51733 transitions. [2021-12-06 22:09:29,283 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-12-06 22:09:29,283 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38312 states and 51733 transitions. [2021-12-06 22:09:29,385 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 37784 [2021-12-06 22:09:29,385 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:09:29,386 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:09:29,386 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:29,386 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:29,387 INFO L791 eck$LassoCheckResult]: Stem: 344368#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 344275#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 344178#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 343533#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 343529#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 343530#L461-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 344095#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 344321#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 343621#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 343622#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 343777#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 343778#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 344288#L670 assume !(0 == ~M_E~0); 344289#L670-2 assume !(0 == ~T1_E~0); 343981#L675-1 assume !(0 == ~T2_E~0); 343982#L680-1 assume !(0 == ~T3_E~0); 344196#L685-1 assume !(0 == ~T4_E~0); 344197#L690-1 assume !(0 == ~T5_E~0); 344352#L695-1 assume !(0 == ~T6_E~0); 344353#L700-1 assume !(0 == ~E_1~0); 344133#L705-1 assume !(0 == ~E_2~0); 344134#L710-1 assume !(0 == ~E_3~0); 343979#L715-1 assume !(0 == ~E_4~0); 343980#L720-1 assume !(0 == ~E_5~0); 343955#L725-1 assume !(0 == ~E_6~0); 343956#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 344172#L320 assume !(1 == ~m_pc~0); 344173#L320-2 is_master_triggered_~__retres1~0#1 := 0; 343820#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 343821#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 343779#L825 assume !(0 != activate_threads_~tmp~1#1); 343780#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 343785#L339 assume !(1 == ~t1_pc~0); 343786#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 344183#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 344147#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 343641#L833 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 343642#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 353958#L358 assume !(1 == ~t2_pc~0); 353957#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 353956#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 353955#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 353954#L841 assume !(0 != activate_threads_~tmp___1~0#1); 353953#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 353952#L377 assume !(1 == ~t3_pc~0); 353950#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 353949#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 353948#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 353947#L849 assume !(0 != activate_threads_~tmp___2~0#1); 353946#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 353945#L396 assume !(1 == ~t4_pc~0); 353944#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 353943#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 353942#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 353941#L857 assume !(0 != activate_threads_~tmp___3~0#1); 353940#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 344388#L415 assume !(1 == ~t5_pc~0); 343808#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 343809#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 344340#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 344341#L865 assume !(0 != activate_threads_~tmp___4~0#1); 343598#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 343599#L434 assume !(1 == ~t6_pc~0); 343928#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 343929#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 344108#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 344381#L873 assume !(0 != activate_threads_~tmp___5~0#1); 343794#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 343795#L743 assume !(1 == ~M_E~0); 343689#L743-2 assume !(1 == ~T1_E~0); 343690#L748-1 assume !(1 == ~T2_E~0); 344253#L753-1 assume !(1 == ~T3_E~0); 344378#L758-1 assume !(1 == ~T4_E~0); 344377#L763-1 assume !(1 == ~T5_E~0); 344376#L768-1 assume !(1 == ~T6_E~0); 344375#L773-1 assume !(1 == ~E_1~0); 343793#L778-1 assume !(1 == ~E_2~0); 343770#L783-1 assume !(1 == ~E_3~0); 343771#L788-1 assume !(1 == ~E_4~0); 344089#L793-1 assume !(1 == ~E_5~0); 344090#L798-1 assume !(1 == ~E_6~0); 343661#L803-1 assume { :end_inline_reset_delta_events } true; 343662#L1024-2 assume !false; 354576#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 354570#L645 [2021-12-06 22:09:29,387 INFO L793 eck$LassoCheckResult]: Loop: 354570#L645 assume !false; 354568#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 354565#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 354563#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 354561#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 354559#L556 assume 0 != eval_~tmp~0#1; 354556#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 352982#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 352983#L561 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 353710#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 354826#L575 assume !(0 == ~t2_st~0); 355267#L589 assume !(0 == ~t3_st~0); 355262#L603 assume !(0 == ~t4_st~0); 355257#L617 assume !(0 == ~t5_st~0); 354575#L631 assume !(0 == ~t6_st~0); 354570#L645 [2021-12-06 22:09:29,387 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:29,387 INFO L85 PathProgramCache]: Analyzing trace with hash -1610041797, now seen corresponding path program 1 times [2021-12-06 22:09:29,387 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:29,387 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1969424306] [2021-12-06 22:09:29,388 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:29,388 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:29,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:29,404 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:29,404 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:29,405 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1969424306] [2021-12-06 22:09:29,405 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1969424306] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:29,405 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:29,405 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:09:29,405 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1077350630] [2021-12-06 22:09:29,405 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:29,405 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:09:29,406 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:29,406 INFO L85 PathProgramCache]: Analyzing trace with hash 2146507872, now seen corresponding path program 1 times [2021-12-06 22:09:29,406 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:29,406 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [293790008] [2021-12-06 22:09:29,406 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:29,406 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:29,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:29,409 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:09:29,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:29,412 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:09:29,494 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:09:29,495 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:09:29,495 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:09:29,495 INFO L87 Difference]: Start difference. First operand 38312 states and 51733 transitions. cyclomatic complexity: 13437 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:29,637 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:09:29,637 INFO L93 Difference]: Finished difference Result 38187 states and 51565 transitions. [2021-12-06 22:09:29,637 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:09:29,638 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38187 states and 51565 transitions. [2021-12-06 22:09:29,793 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 37784 [2021-12-06 22:09:29,885 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38187 states to 38187 states and 51565 transitions. [2021-12-06 22:09:29,885 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 38187 [2021-12-06 22:09:29,905 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 38187 [2021-12-06 22:09:29,905 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38187 states and 51565 transitions. [2021-12-06 22:09:29,924 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:09:29,925 INFO L681 BuchiCegarLoop]: Abstraction has 38187 states and 51565 transitions. [2021-12-06 22:09:29,942 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38187 states and 51565 transitions. [2021-12-06 22:09:30,144 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38187 to 38187. [2021-12-06 22:09:30,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38187 states, 38187 states have (on average 1.3503286458742505) internal successors, (51565), 38186 states have internal predecessors, (51565), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:30,322 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38187 states to 38187 states and 51565 transitions. [2021-12-06 22:09:30,323 INFO L704 BuchiCegarLoop]: Abstraction has 38187 states and 51565 transitions. [2021-12-06 22:09:30,323 INFO L587 BuchiCegarLoop]: Abstraction has 38187 states and 51565 transitions. [2021-12-06 22:09:30,323 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-12-06 22:09:30,323 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38187 states and 51565 transitions. [2021-12-06 22:09:30,398 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 37784 [2021-12-06 22:09:30,399 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:09:30,399 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:09:30,399 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:30,399 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:30,400 INFO L791 eck$LassoCheckResult]: Stem: 420788#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 420724#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 420645#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 420038#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 420034#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 420035#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 420578#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 420756#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 420127#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 420128#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 420276#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 420145#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 420146#L670 assume !(0 == ~M_E~0); 420532#L670-2 assume !(0 == ~T1_E~0); 420469#L675-1 assume !(0 == ~T2_E~0); 420470#L680-1 assume !(0 == ~T3_E~0); 420576#L685-1 assume !(0 == ~T4_E~0); 420537#L690-1 assume !(0 == ~T5_E~0); 420538#L695-1 assume !(0 == ~T6_E~0); 420619#L700-1 assume !(0 == ~E_1~0); 420608#L705-1 assume !(0 == ~E_2~0); 420609#L710-1 assume !(0 == ~E_3~0); 420468#L715-1 assume !(0 == ~E_4~0); 420384#L720-1 assume !(0 == ~E_5~0); 420385#L725-1 assume !(0 == ~E_6~0); 420444#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 420499#L320 assume !(1 == ~m_pc~0); 420641#L320-2 is_master_triggered_~__retres1~0#1 := 0; 420318#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 420319#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 420277#L825 assume !(0 != activate_threads_~tmp~1#1); 420278#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 420283#L339 assume !(1 == ~t1_pc~0); 420284#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 420652#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 420622#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 420147#L833 assume !(0 != activate_threads_~tmp___0~0#1); 420148#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 420814#L358 assume !(1 == ~t2_pc~0); 420600#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 420601#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 420722#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 420812#L841 assume !(0 != activate_threads_~tmp___1~0#1); 420811#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 420810#L377 assume !(1 == ~t3_pc~0); 420556#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 420557#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 420554#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 420555#L849 assume !(0 != activate_threads_~tmp___2~0#1); 420809#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 420231#L396 assume !(1 == ~t4_pc~0); 420232#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 420061#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 420062#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 420806#L857 assume !(0 != activate_threads_~tmp___3~0#1); 420805#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 420804#L415 assume !(1 == ~t5_pc~0); 420306#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 420307#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 420771#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 420654#L865 assume !(0 != activate_threads_~tmp___4~0#1); 420104#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 420105#L434 assume !(1 == ~t6_pc~0); 420419#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 420420#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 420590#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 420797#L873 assume !(0 != activate_threads_~tmp___5~0#1); 420292#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 420293#L743 assume !(1 == ~M_E~0); 420192#L743-2 assume !(1 == ~T1_E~0); 420193#L748-1 assume !(1 == ~T2_E~0); 420708#L753-1 assume !(1 == ~T3_E~0); 420795#L758-1 assume !(1 == ~T4_E~0); 420794#L763-1 assume !(1 == ~T5_E~0); 420793#L768-1 assume !(1 == ~T6_E~0); 420792#L773-1 assume !(1 == ~E_1~0); 420291#L778-1 assume !(1 == ~E_2~0); 420269#L783-1 assume !(1 == ~E_3~0); 420270#L788-1 assume !(1 == ~E_4~0); 420573#L793-1 assume !(1 == ~E_5~0); 420523#L798-1 assume !(1 == ~E_6~0); 420166#L803-1 assume { :end_inline_reset_delta_events } true; 420167#L1024-2 assume !false; 431828#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 431821#L645 [2021-12-06 22:09:30,400 INFO L793 eck$LassoCheckResult]: Loop: 431821#L645 assume !false; 431819#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 431816#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 431814#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 431812#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 431810#L556 assume 0 != eval_~tmp~0#1; 431806#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 431804#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 431802#L561 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 431490#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 431798#L575 assume !(0 == ~t2_st~0); 431796#L589 assume !(0 == ~t3_st~0); 431836#L603 assume !(0 == ~t4_st~0); 431833#L617 assume !(0 == ~t5_st~0); 431827#L631 assume !(0 == ~t6_st~0); 431821#L645 [2021-12-06 22:09:30,400 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:30,400 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 2 times [2021-12-06 22:09:30,400 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:30,401 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [814681102] [2021-12-06 22:09:30,401 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:30,401 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:30,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:30,408 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:09:30,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:30,422 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:09:30,422 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:30,422 INFO L85 PathProgramCache]: Analyzing trace with hash 2146507872, now seen corresponding path program 2 times [2021-12-06 22:09:30,422 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:30,422 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1911950791] [2021-12-06 22:09:30,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:30,423 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:30,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:30,425 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:09:30,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:30,427 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:09:30,428 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:30,428 INFO L85 PathProgramCache]: Analyzing trace with hash -447706070, now seen corresponding path program 1 times [2021-12-06 22:09:30,428 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:30,428 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [382747796] [2021-12-06 22:09:30,428 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:30,428 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:30,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:30,447 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:30,447 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:30,447 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [382747796] [2021-12-06 22:09:30,448 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [382747796] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:30,448 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:30,448 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:09:30,448 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1698241797] [2021-12-06 22:09:30,448 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:30,516 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:09:30,517 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:09:30,517 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:09:30,517 INFO L87 Difference]: Start difference. First operand 38187 states and 51565 transitions. cyclomatic complexity: 13394 Second operand has 3 states, 3 states have (on average 33.0) internal successors, (99), 3 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:30,694 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:09:30,694 INFO L93 Difference]: Finished difference Result 72339 states and 97157 transitions. [2021-12-06 22:09:30,694 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:09:30,694 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 72339 states and 97157 transitions. [2021-12-06 22:09:30,928 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 71664 [2021-12-06 22:09:31,075 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 72339 states to 72339 states and 97157 transitions. [2021-12-06 22:09:31,076 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 72339 [2021-12-06 22:09:31,109 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 72339 [2021-12-06 22:09:31,109 INFO L73 IsDeterministic]: Start isDeterministic. Operand 72339 states and 97157 transitions. [2021-12-06 22:09:31,137 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:09:31,138 INFO L681 BuchiCegarLoop]: Abstraction has 72339 states and 97157 transitions. [2021-12-06 22:09:31,166 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72339 states and 97157 transitions. [2021-12-06 22:09:31,636 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72339 to 70355. [2021-12-06 22:09:31,677 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 70355 states, 70355 states have (on average 1.345476511974984) internal successors, (94661), 70354 states have internal predecessors, (94661), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:31,791 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70355 states to 70355 states and 94661 transitions. [2021-12-06 22:09:31,791 INFO L704 BuchiCegarLoop]: Abstraction has 70355 states and 94661 transitions. [2021-12-06 22:09:31,791 INFO L587 BuchiCegarLoop]: Abstraction has 70355 states and 94661 transitions. [2021-12-06 22:09:31,791 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-12-06 22:09:31,791 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 70355 states and 94661 transitions. [2021-12-06 22:09:31,960 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 69680 [2021-12-06 22:09:31,960 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:09:31,960 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:09:31,961 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:31,961 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:31,961 INFO L791 eck$LassoCheckResult]: Stem: 531356#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 531279#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 531192#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 530572#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 530568#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 530569#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 531108#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 531310#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 530658#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 530659#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 530815#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 530677#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 530678#L670 assume !(0 == ~M_E~0); 531063#L670-2 assume !(0 == ~T1_E~0); 531004#L675-1 assume !(0 == ~T2_E~0); 531005#L680-1 assume !(0 == ~T3_E~0); 531107#L685-1 assume !(0 == ~T4_E~0); 531066#L690-1 assume !(0 == ~T5_E~0); 531067#L695-1 assume !(0 == ~T6_E~0); 531159#L700-1 assume !(0 == ~E_1~0); 531148#L705-1 assume !(0 == ~E_2~0); 531149#L710-1 assume !(0 == ~E_3~0); 531002#L715-1 assume !(0 == ~E_4~0); 530922#L720-1 assume !(0 == ~E_5~0); 530923#L725-1 assume !(0 == ~E_6~0); 530980#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 531034#L320 assume !(1 == ~m_pc~0); 531185#L320-2 is_master_triggered_~__retres1~0#1 := 0; 530855#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 530856#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 530816#L825 assume !(0 != activate_threads_~tmp~1#1); 530817#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 530821#L339 assume !(1 == ~t1_pc~0); 530822#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 531196#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 531162#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 530680#L833 assume !(0 != activate_threads_~tmp___0~0#1); 530681#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 531388#L358 assume !(1 == ~t2_pc~0); 531141#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 531142#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 531277#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 531386#L841 assume !(0 != activate_threads_~tmp___1~0#1); 531385#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 531384#L377 assume !(1 == ~t3_pc~0); 531086#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 531087#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 531096#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 530819#L849 assume !(0 != activate_threads_~tmp___2~0#1); 530820#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 530766#L396 assume !(1 == ~t4_pc~0); 530767#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 530595#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 530596#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 531378#L857 assume !(0 != activate_threads_~tmp___3~0#1); 531377#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 531376#L415 assume !(1 == ~t5_pc~0); 530845#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 530846#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 531329#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 531198#L865 assume !(0 != activate_threads_~tmp___4~0#1); 530637#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 530638#L434 assume !(1 == ~t6_pc~0); 530957#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 530958#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 531122#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 531369#L873 assume !(0 != activate_threads_~tmp___5~0#1); 530831#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 530832#L743 assume !(1 == ~M_E~0); 530728#L743-2 assume !(1 == ~T1_E~0); 530729#L748-1 assume !(1 == ~T2_E~0); 531258#L753-1 assume !(1 == ~T3_E~0); 531367#L758-1 assume !(1 == ~T4_E~0); 531366#L763-1 assume !(1 == ~T5_E~0); 531365#L768-1 assume !(1 == ~T6_E~0); 531364#L773-1 assume !(1 == ~E_1~0); 530826#L778-1 assume !(1 == ~E_2~0); 530808#L783-1 assume !(1 == ~E_3~0); 530809#L788-1 assume !(1 == ~E_4~0); 531105#L793-1 assume !(1 == ~E_5~0); 531056#L798-1 assume !(1 == ~E_6~0); 530697#L803-1 assume { :end_inline_reset_delta_events } true; 530698#L1024-2 assume !false; 552799#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 552793#L645 [2021-12-06 22:09:31,962 INFO L793 eck$LassoCheckResult]: Loop: 552793#L645 assume !false; 552791#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 552788#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 552784#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 552781#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 552778#L556 assume 0 != eval_~tmp~0#1; 552776#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 552773#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 552771#L561 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 544580#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 546007#L575 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 546005#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 546006#L589 assume !(0 == ~t3_st~0); 570571#L603 assume !(0 == ~t4_st~0); 570568#L617 assume !(0 == ~t5_st~0); 552798#L631 assume !(0 == ~t6_st~0); 552793#L645 [2021-12-06 22:09:31,962 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:31,962 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 3 times [2021-12-06 22:09:31,962 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:31,963 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1241312202] [2021-12-06 22:09:31,963 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:31,963 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:31,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:31,972 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:09:31,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:31,993 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:09:31,993 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:31,993 INFO L85 PathProgramCache]: Analyzing trace with hash 488929788, now seen corresponding path program 1 times [2021-12-06 22:09:31,993 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:31,993 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1875251703] [2021-12-06 22:09:31,993 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:31,993 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:31,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:31,996 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:09:31,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:31,998 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:09:31,999 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:31,999 INFO L85 PathProgramCache]: Analyzing trace with hash 1672676210, now seen corresponding path program 1 times [2021-12-06 22:09:31,999 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:31,999 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1873175301] [2021-12-06 22:09:31,999 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:31,999 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:32,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:32,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:32,017 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:32,017 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1873175301] [2021-12-06 22:09:32,017 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1873175301] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:32,017 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:32,017 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:09:32,017 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1379461718] [2021-12-06 22:09:32,018 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:32,100 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:09:32,101 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:09:32,101 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:09:32,101 INFO L87 Difference]: Start difference. First operand 70355 states and 94661 transitions. cyclomatic complexity: 24322 Second operand has 3 states, 3 states have (on average 33.333333333333336) internal successors, (100), 3 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:32,538 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:09:32,538 INFO L93 Difference]: Finished difference Result 128931 states and 172661 transitions. [2021-12-06 22:09:32,538 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:09:32,539 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 128931 states and 172661 transitions. [2021-12-06 22:09:33,083 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 127712 [2021-12-06 22:09:33,332 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 128931 states to 128931 states and 172661 transitions. [2021-12-06 22:09:33,332 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 128931 [2021-12-06 22:09:33,378 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 128931 [2021-12-06 22:09:33,379 INFO L73 IsDeterministic]: Start isDeterministic. Operand 128931 states and 172661 transitions. [2021-12-06 22:09:33,425 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:09:33,425 INFO L681 BuchiCegarLoop]: Abstraction has 128931 states and 172661 transitions. [2021-12-06 22:09:33,466 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128931 states and 172661 transitions. [2021-12-06 22:09:34,362 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128931 to 122787. [2021-12-06 22:09:34,420 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 122787 states, 122787 states have (on average 1.3457206381783087) internal successors, (165237), 122786 states have internal predecessors, (165237), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:34,625 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122787 states to 122787 states and 165237 transitions. [2021-12-06 22:09:34,625 INFO L704 BuchiCegarLoop]: Abstraction has 122787 states and 165237 transitions. [2021-12-06 22:09:34,625 INFO L587 BuchiCegarLoop]: Abstraction has 122787 states and 165237 transitions. [2021-12-06 22:09:34,625 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-12-06 22:09:34,625 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 122787 states and 165237 transitions. [2021-12-06 22:09:34,929 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 121568 [2021-12-06 22:09:34,930 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:09:34,930 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:09:34,930 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:34,931 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:34,931 INFO L791 eck$LassoCheckResult]: Stem: 730679#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 730595#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 730504#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 729866#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 729862#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 729863#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 730429#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 730632#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 729954#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 729955#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 730114#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 729973#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 729974#L670 assume !(0 == ~M_E~0); 730380#L670-2 assume !(0 == ~T1_E~0); 730310#L675-1 assume !(0 == ~T2_E~0); 730311#L680-1 assume !(0 == ~T3_E~0); 730428#L685-1 assume !(0 == ~T4_E~0); 730384#L690-1 assume !(0 == ~T5_E~0); 730385#L695-1 assume !(0 == ~T6_E~0); 730474#L700-1 assume !(0 == ~E_1~0); 730461#L705-1 assume !(0 == ~E_2~0); 730462#L710-1 assume !(0 == ~E_3~0); 730307#L715-1 assume !(0 == ~E_4~0); 730226#L720-1 assume !(0 == ~E_5~0); 730227#L725-1 assume !(0 == ~E_6~0); 730285#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 730341#L320 assume !(1 == ~m_pc~0); 730498#L320-2 is_master_triggered_~__retres1~0#1 := 0; 730158#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 730159#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 730115#L825 assume !(0 != activate_threads_~tmp~1#1); 730116#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 730121#L339 assume !(1 == ~t1_pc~0); 730122#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 730510#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 730478#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 729977#L833 assume !(0 != activate_threads_~tmp___0~0#1); 729978#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 730709#L358 assume !(1 == ~t2_pc~0); 730453#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 730454#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 730593#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 730707#L841 assume !(0 != activate_threads_~tmp___1~0#1); 730706#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 730705#L377 assume !(1 == ~t3_pc~0); 730405#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 730406#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 730415#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 730119#L849 assume !(0 != activate_threads_~tmp___2~0#1); 730120#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 730065#L396 assume !(1 == ~t4_pc~0); 730066#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 729889#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 729890#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 730699#L857 assume !(0 != activate_threads_~tmp___3~0#1); 730698#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 730697#L415 assume !(1 == ~t5_pc~0); 730145#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 730146#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 730653#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 730514#L865 assume !(0 != activate_threads_~tmp___4~0#1); 729933#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 729934#L434 assume !(1 == ~t6_pc~0); 730261#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 730262#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 730443#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 730690#L873 assume !(0 != activate_threads_~tmp___5~0#1); 730133#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 730134#L743 assume !(1 == ~M_E~0); 730026#L743-2 assume !(1 == ~T1_E~0); 730027#L748-1 assume !(1 == ~T2_E~0); 730570#L753-1 assume !(1 == ~T3_E~0); 730688#L758-1 assume !(1 == ~T4_E~0); 730687#L763-1 assume !(1 == ~T5_E~0); 730686#L768-1 assume !(1 == ~T6_E~0); 730685#L773-1 assume !(1 == ~E_1~0); 730128#L778-1 assume !(1 == ~E_2~0); 730107#L783-1 assume !(1 == ~E_3~0); 730108#L788-1 assume !(1 == ~E_4~0); 730426#L793-1 assume !(1 == ~E_5~0); 730370#L798-1 assume !(1 == ~E_6~0); 729995#L803-1 assume { :end_inline_reset_delta_events } true; 729996#L1024-2 assume !false; 813557#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 813553#L645 [2021-12-06 22:09:34,931 INFO L793 eck$LassoCheckResult]: Loop: 813553#L645 assume !false; 813552#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 813549#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 813547#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 813545#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 811703#L556 assume 0 != eval_~tmp~0#1; 804165#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 766752#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 766753#L561 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 789667#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 789547#L575 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 789545#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 789543#L589 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 789165#L606 assume !(0 != eval_~tmp_ndt_4~0#1); 789542#L603 assume !(0 == ~t4_st~0); 793807#L617 assume !(0 == ~t5_st~0); 793078#L631 assume !(0 == ~t6_st~0); 813553#L645 [2021-12-06 22:09:34,931 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:34,931 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 4 times [2021-12-06 22:09:34,932 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:34,932 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [157019048] [2021-12-06 22:09:34,932 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:34,932 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:34,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:34,938 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:09:34,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:34,953 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:09:34,953 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:34,954 INFO L85 PathProgramCache]: Analyzing trace with hash 2080854914, now seen corresponding path program 1 times [2021-12-06 22:09:34,954 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:34,954 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2094102210] [2021-12-06 22:09:34,954 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:34,954 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:34,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:34,956 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:09:34,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:34,959 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:09:34,960 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:34,960 INFO L85 PathProgramCache]: Analyzing trace with hash 122288332, now seen corresponding path program 1 times [2021-12-06 22:09:34,960 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:34,960 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1874518011] [2021-12-06 22:09:34,961 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:34,961 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:34,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:34,979 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:34,979 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:34,979 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1874518011] [2021-12-06 22:09:34,979 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1874518011] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:34,979 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:34,980 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:09:34,980 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1433770958] [2021-12-06 22:09:34,980 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:35,062 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:09:35,063 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:09:35,063 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:09:35,063 INFO L87 Difference]: Start difference. First operand 122787 states and 165237 transitions. cyclomatic complexity: 42466 Second operand has 3 states, 3 states have (on average 33.666666666666664) internal successors, (101), 3 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:35,598 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:09:35,599 INFO L93 Difference]: Finished difference Result 158675 states and 212545 transitions. [2021-12-06 22:09:35,599 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:09:35,600 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 158675 states and 212545 transitions. [2021-12-06 22:09:36,089 INFO L131 ngComponentsAnalysis]: Automaton has 18 accepting balls. 157168 [2021-12-06 22:09:36,371 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 158675 states to 158675 states and 212545 transitions. [2021-12-06 22:09:36,372 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 158675 [2021-12-06 22:09:36,427 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 158675 [2021-12-06 22:09:36,427 INFO L73 IsDeterministic]: Start isDeterministic. Operand 158675 states and 212545 transitions. [2021-12-06 22:09:36,626 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:09:36,626 INFO L681 BuchiCegarLoop]: Abstraction has 158675 states and 212545 transitions. [2021-12-06 22:09:36,662 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158675 states and 212545 transitions. [2021-12-06 22:09:37,542 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158675 to 154195. [2021-12-06 22:09:37,618 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 154195 states, 154195 states have (on average 1.3443821135575083) internal successors, (207297), 154194 states have internal predecessors, (207297), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:37,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154195 states to 154195 states and 207297 transitions. [2021-12-06 22:09:37,918 INFO L704 BuchiCegarLoop]: Abstraction has 154195 states and 207297 transitions. [2021-12-06 22:09:37,918 INFO L587 BuchiCegarLoop]: Abstraction has 154195 states and 207297 transitions. [2021-12-06 22:09:37,918 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-12-06 22:09:37,918 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 154195 states and 207297 transitions. [2021-12-06 22:09:38,371 INFO L131 ngComponentsAnalysis]: Automaton has 18 accepting balls. 152688 [2021-12-06 22:09:38,371 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:09:38,371 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:09:38,372 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:38,372 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:38,372 INFO L791 eck$LassoCheckResult]: Stem: 1012172#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 1012084#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1011986#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1011336#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1011332#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 1011333#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1011896#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1012117#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1011425#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1011426#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1011584#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1011445#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1011446#L670 assume !(0 == ~M_E~0); 1011850#L670-2 assume !(0 == ~T1_E~0); 1011783#L675-1 assume !(0 == ~T2_E~0); 1011784#L680-1 assume !(0 == ~T3_E~0); 1011895#L685-1 assume !(0 == ~T4_E~0); 1011855#L690-1 assume !(0 == ~T5_E~0); 1011856#L695-1 assume !(0 == ~T6_E~0); 1011950#L700-1 assume !(0 == ~E_1~0); 1011937#L705-1 assume !(0 == ~E_2~0); 1011938#L710-1 assume !(0 == ~E_3~0); 1011781#L715-1 assume !(0 == ~E_4~0); 1011699#L720-1 assume !(0 == ~E_5~0); 1011700#L725-1 assume !(0 == ~E_6~0); 1011760#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1011814#L320 assume !(1 == ~m_pc~0); 1011978#L320-2 is_master_triggered_~__retres1~0#1 := 0; 1011628#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1011629#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1011585#L825 assume !(0 != activate_threads_~tmp~1#1); 1011586#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1011591#L339 assume !(1 == ~t1_pc~0); 1011592#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1011991#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1011954#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1011448#L833 assume !(0 != activate_threads_~tmp___0~0#1); 1011449#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1012203#L358 assume !(1 == ~t2_pc~0); 1011928#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1011929#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1012082#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1012201#L841 assume !(0 != activate_threads_~tmp___1~0#1); 1012200#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1012199#L377 assume !(1 == ~t3_pc~0); 1011877#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1011878#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1011887#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1011589#L849 assume !(0 != activate_threads_~tmp___2~0#1); 1011590#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1011534#L396 assume !(1 == ~t4_pc~0); 1011535#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1011359#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1011360#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1012193#L857 assume !(0 != activate_threads_~tmp___3~0#1); 1012192#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1012191#L415 assume !(1 == ~t5_pc~0); 1011615#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1011616#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1012142#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1011995#L865 assume !(0 != activate_threads_~tmp___4~0#1); 1011403#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1011404#L434 assume !(1 == ~t6_pc~0); 1011735#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1011736#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1011913#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1012184#L873 assume !(0 != activate_threads_~tmp___5~0#1); 1011603#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1011604#L743 assume !(1 == ~M_E~0); 1011495#L743-2 assume !(1 == ~T1_E~0); 1011496#L748-1 assume !(1 == ~T2_E~0); 1012058#L753-1 assume !(1 == ~T3_E~0); 1012182#L758-1 assume !(1 == ~T4_E~0); 1012181#L763-1 assume !(1 == ~T5_E~0); 1012180#L768-1 assume !(1 == ~T6_E~0); 1012179#L773-1 assume !(1 == ~E_1~0); 1011598#L778-1 assume !(1 == ~E_2~0); 1011577#L783-1 assume !(1 == ~E_3~0); 1011578#L788-1 assume !(1 == ~E_4~0); 1011893#L793-1 assume !(1 == ~E_5~0); 1011842#L798-1 assume !(1 == ~E_6~0); 1011466#L803-1 assume { :end_inline_reset_delta_events } true; 1011467#L1024-2 assume !false; 1101110#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1101105#L645 [2021-12-06 22:09:38,373 INFO L793 eck$LassoCheckResult]: Loop: 1101105#L645 assume !false; 1101102#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1101099#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1101097#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1101095#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1101092#L556 assume 0 != eval_~tmp~0#1; 1101089#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1101078#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 1101067#L561 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1100688#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 1083132#L575 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1083130#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 1078974#L589 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1078971#L606 assume !(0 != eval_~tmp_ndt_4~0#1); 1078969#L603 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1078966#L620 assume !(0 != eval_~tmp_ndt_5~0#1); 1078967#L617 assume !(0 == ~t5_st~0); 1095992#L631 assume !(0 == ~t6_st~0); 1101105#L645 [2021-12-06 22:09:38,373 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:38,373 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 5 times [2021-12-06 22:09:38,373 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:38,373 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1524119605] [2021-12-06 22:09:38,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:38,374 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:38,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:38,381 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:09:38,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:38,397 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:09:38,398 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:38,398 INFO L85 PathProgramCache]: Analyzing trace with hash 75836122, now seen corresponding path program 1 times [2021-12-06 22:09:38,398 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:38,398 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [35729072] [2021-12-06 22:09:38,398 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:38,398 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:38,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:38,401 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:09:38,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:38,405 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:09:38,405 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:38,405 INFO L85 PathProgramCache]: Analyzing trace with hash -510185776, now seen corresponding path program 1 times [2021-12-06 22:09:38,405 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:38,405 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1897085246] [2021-12-06 22:09:38,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:38,406 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:38,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:38,425 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:38,425 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:38,425 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1897085246] [2021-12-06 22:09:38,425 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1897085246] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:38,426 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:38,426 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:09:38,426 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1528189697] [2021-12-06 22:09:38,426 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:38,704 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:09:38,704 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:09:38,704 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:09:38,705 INFO L87 Difference]: Start difference. First operand 154195 states and 207297 transitions. cyclomatic complexity: 53120 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:39,238 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:09:39,238 INFO L93 Difference]: Finished difference Result 203787 states and 272575 transitions. [2021-12-06 22:09:39,239 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:09:39,239 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 203787 states and 272575 transitions. [2021-12-06 22:09:40,198 INFO L131 ngComponentsAnalysis]: Automaton has 19 accepting balls. 201976 [2021-12-06 22:09:40,586 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 203787 states to 203787 states and 272575 transitions. [2021-12-06 22:09:40,586 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 203787 [2021-12-06 22:09:40,661 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 203787 [2021-12-06 22:09:40,661 INFO L73 IsDeterministic]: Start isDeterministic. Operand 203787 states and 272575 transitions. [2021-12-06 22:09:40,721 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:09:40,721 INFO L681 BuchiCegarLoop]: Abstraction has 203787 states and 272575 transitions. [2021-12-06 22:09:40,780 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 203787 states and 272575 transitions. [2021-12-06 22:09:42,092 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 203787 to 198411. [2021-12-06 22:09:42,167 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 198411 states, 198411 states have (on average 1.3408883580043445) internal successors, (266047), 198410 states have internal predecessors, (266047), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:42,600 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 198411 states to 198411 states and 266047 transitions. [2021-12-06 22:09:42,601 INFO L704 BuchiCegarLoop]: Abstraction has 198411 states and 266047 transitions. [2021-12-06 22:09:42,601 INFO L587 BuchiCegarLoop]: Abstraction has 198411 states and 266047 transitions. [2021-12-06 22:09:42,601 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-12-06 22:09:42,601 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 198411 states and 266047 transitions. [2021-12-06 22:09:43,244 INFO L131 ngComponentsAnalysis]: Automaton has 19 accepting balls. 196600 [2021-12-06 22:09:43,244 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:09:43,244 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:09:43,245 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:43,245 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:43,245 INFO L791 eck$LassoCheckResult]: Stem: 1370165#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 1370073#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1369975#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1369326#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1369322#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 1369323#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1369885#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1370116#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1369414#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1369415#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1369567#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1369433#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1369434#L670 assume !(0 == ~M_E~0); 1369837#L670-2 assume !(0 == ~T1_E~0); 1369772#L675-1 assume !(0 == ~T2_E~0); 1369773#L680-1 assume !(0 == ~T3_E~0); 1369883#L685-1 assume !(0 == ~T4_E~0); 1369840#L690-1 assume !(0 == ~T5_E~0); 1369841#L695-1 assume !(0 == ~T6_E~0); 1369946#L700-1 assume !(0 == ~E_1~0); 1369931#L705-1 assume !(0 == ~E_2~0); 1369932#L710-1 assume !(0 == ~E_3~0); 1369770#L715-1 assume !(0 == ~E_4~0); 1369685#L720-1 assume !(0 == ~E_5~0); 1369686#L725-1 assume !(0 == ~E_6~0); 1369748#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1369801#L320 assume !(1 == ~m_pc~0); 1369970#L320-2 is_master_triggered_~__retres1~0#1 := 0; 1369614#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1369615#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1369568#L825 assume !(0 != activate_threads_~tmp~1#1); 1369569#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1369574#L339 assume !(1 == ~t1_pc~0); 1369575#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1369979#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1369950#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1369436#L833 assume !(0 != activate_threads_~tmp___0~0#1); 1369437#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1370195#L358 assume !(1 == ~t2_pc~0); 1369921#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1369922#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1370071#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1370193#L841 assume !(0 != activate_threads_~tmp___1~0#1); 1370192#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1370191#L377 assume !(1 == ~t3_pc~0); 1369862#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1369863#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1369872#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1369572#L849 assume !(0 != activate_threads_~tmp___2~0#1); 1369573#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1369521#L396 assume !(1 == ~t4_pc~0); 1369522#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1369349#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1369350#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1370185#L857 assume !(0 != activate_threads_~tmp___3~0#1); 1370184#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1370183#L415 assume !(1 == ~t5_pc~0); 1369598#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1369599#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1370140#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1369983#L865 assume !(0 != activate_threads_~tmp___4~0#1); 1369392#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1369393#L434 assume !(1 == ~t6_pc~0); 1369724#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1369725#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1369901#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1370176#L873 assume !(0 != activate_threads_~tmp___5~0#1); 1369586#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1369587#L743 assume !(1 == ~M_E~0); 1369481#L743-2 assume !(1 == ~T1_E~0); 1369482#L748-1 assume !(1 == ~T2_E~0); 1370048#L753-1 assume !(1 == ~T3_E~0); 1370174#L758-1 assume !(1 == ~T4_E~0); 1370173#L763-1 assume !(1 == ~T5_E~0); 1370172#L768-1 assume !(1 == ~T6_E~0); 1370171#L773-1 assume !(1 == ~E_1~0); 1369581#L778-1 assume !(1 == ~E_2~0); 1369559#L783-1 assume !(1 == ~E_3~0); 1369560#L788-1 assume !(1 == ~E_4~0); 1369881#L793-1 assume !(1 == ~E_5~0); 1369827#L798-1 assume !(1 == ~E_6~0); 1369453#L803-1 assume { :end_inline_reset_delta_events } true; 1369454#L1024-2 assume !false; 1442964#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1442956#L645 [2021-12-06 22:09:43,245 INFO L793 eck$LassoCheckResult]: Loop: 1442956#L645 assume !false; 1442957#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1442949#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1442950#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1442943#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1442944#L556 assume 0 != eval_~tmp~0#1; 1442935#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1442936#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 1442929#L561 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1442924#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 1442922#L575 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1441117#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 1442918#L589 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1438924#L606 assume !(0 != eval_~tmp_ndt_4~0#1); 1442915#L603 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1442911#L620 assume !(0 != eval_~tmp_ndt_5~0#1); 1442912#L617 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 1439455#L634 assume !(0 != eval_~tmp_ndt_6~0#1); 1439456#L631 assume !(0 == ~t6_st~0); 1442956#L645 [2021-12-06 22:09:43,245 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:43,245 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 6 times [2021-12-06 22:09:43,246 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:43,246 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1290442581] [2021-12-06 22:09:43,246 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:43,246 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:43,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:43,252 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:09:43,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:43,265 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:09:43,266 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:43,266 INFO L85 PathProgramCache]: Analyzing trace with hash -1944239452, now seen corresponding path program 1 times [2021-12-06 22:09:43,266 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:43,266 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [239869414] [2021-12-06 22:09:43,266 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:43,266 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:43,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:43,269 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:09:43,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:43,272 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:09:43,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:43,272 INFO L85 PathProgramCache]: Analyzing trace with hash 1363918190, now seen corresponding path program 1 times [2021-12-06 22:09:43,272 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:43,272 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1873709253] [2021-12-06 22:09:43,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:43,272 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:43,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:09:43,288 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:09:43,288 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:09:43,288 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1873709253] [2021-12-06 22:09:43,288 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1873709253] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:09:43,288 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:09:43,289 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 22:09:43,289 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1929076628] [2021-12-06 22:09:43,289 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:09:43,414 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:09:43,414 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:09:43,415 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:09:43,415 INFO L87 Difference]: Start difference. First operand 198411 states and 266047 transitions. cyclomatic complexity: 67655 Second operand has 3 states, 2 states have (on average 51.5) internal successors, (103), 3 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:44,460 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:09:44,460 INFO L93 Difference]: Finished difference Result 367107 states and 489757 transitions. [2021-12-06 22:09:44,461 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:09:44,461 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 367107 states and 489757 transitions. [2021-12-06 22:09:45,869 INFO L131 ngComponentsAnalysis]: Automaton has 19 accepting balls. 363616 [2021-12-06 22:09:46,744 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 367107 states to 367107 states and 489757 transitions. [2021-12-06 22:09:46,744 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 367107 [2021-12-06 22:09:46,889 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 367107 [2021-12-06 22:09:46,889 INFO L73 IsDeterministic]: Start isDeterministic. Operand 367107 states and 489757 transitions. [2021-12-06 22:09:47,020 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:09:47,020 INFO L681 BuchiCegarLoop]: Abstraction has 367107 states and 489757 transitions. [2021-12-06 22:09:47,159 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 367107 states and 489757 transitions. [2021-12-06 22:09:49,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 367107 to 367107. [2021-12-06 22:09:49,655 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 367107 states, 367107 states have (on average 1.3340987777405497) internal successors, (489757), 367106 states have internal predecessors, (489757), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:09:50,534 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 367107 states to 367107 states and 489757 transitions. [2021-12-06 22:09:50,534 INFO L704 BuchiCegarLoop]: Abstraction has 367107 states and 489757 transitions. [2021-12-06 22:09:50,534 INFO L587 BuchiCegarLoop]: Abstraction has 367107 states and 489757 transitions. [2021-12-06 22:09:50,534 INFO L425 BuchiCegarLoop]: ======== Iteration 29============ [2021-12-06 22:09:50,534 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 367107 states and 489757 transitions. [2021-12-06 22:09:51,442 INFO L131 ngComponentsAnalysis]: Automaton has 19 accepting balls. 363616 [2021-12-06 22:09:51,442 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:09:51,442 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:09:51,443 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:51,443 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:09:51,444 INFO L791 eck$LassoCheckResult]: Stem: 1935661#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 1935581#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1935494#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1934852#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1934848#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 1934849#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1935412#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1935620#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1934942#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1934943#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1935101#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1934961#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1934962#L670 assume !(0 == ~M_E~0); 1935367#L670-2 assume !(0 == ~T1_E~0); 1935302#L675-1 assume !(0 == ~T2_E~0); 1935303#L680-1 assume !(0 == ~T3_E~0); 1935410#L685-1 assume !(0 == ~T4_E~0); 1935372#L690-1 assume !(0 == ~T5_E~0); 1935373#L695-1 assume !(0 == ~T6_E~0); 1935466#L700-1 assume !(0 == ~E_1~0); 1935453#L705-1 assume !(0 == ~E_2~0); 1935454#L710-1 assume !(0 == ~E_3~0); 1935301#L715-1 assume !(0 == ~E_4~0); 1935217#L720-1 assume !(0 == ~E_5~0); 1935218#L725-1 assume !(0 == ~E_6~0); 1935278#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1935331#L320 assume !(1 == ~m_pc~0); 1935487#L320-2 is_master_triggered_~__retres1~0#1 := 0; 1935147#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1935148#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1935102#L825 assume !(0 != activate_threads_~tmp~1#1); 1935103#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1935111#L339 assume !(1 == ~t1_pc~0); 1935112#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1935500#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1935469#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1934963#L833 assume !(0 != activate_threads_~tmp___0~0#1); 1934964#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1935686#L358 assume !(1 == ~t2_pc~0); 1935442#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1935443#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1935578#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1935684#L841 assume !(0 != activate_threads_~tmp___1~0#1); 1935683#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1935682#L377 assume !(1 == ~t3_pc~0); 1935388#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1935389#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1935386#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1935387#L849 assume !(0 != activate_threads_~tmp___2~0#1); 1935681#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1935048#L396 assume !(1 == ~t4_pc~0); 1935049#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1934875#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1934876#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1935678#L857 assume !(0 != activate_threads_~tmp___3~0#1); 1935677#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1935676#L415 assume !(1 == ~t5_pc~0); 1935134#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1935135#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1935638#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1935501#L865 assume !(0 != activate_threads_~tmp___4~0#1); 1934917#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1934918#L434 assume !(1 == ~t6_pc~0); 1935255#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1935256#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1935424#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1935669#L873 assume !(0 != activate_threads_~tmp___5~0#1); 1935120#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1935121#L743 assume !(1 == ~M_E~0); 1935008#L743-2 assume !(1 == ~T1_E~0); 1935009#L748-1 assume !(1 == ~T2_E~0); 1935563#L753-1 assume !(1 == ~T3_E~0); 1935667#L758-1 assume !(1 == ~T4_E~0); 1935666#L763-1 assume !(1 == ~T5_E~0); 1935665#L768-1 assume !(1 == ~T6_E~0); 1935664#L773-1 assume !(1 == ~E_1~0); 1935119#L778-1 assume !(1 == ~E_2~0); 1935093#L783-1 assume !(1 == ~E_3~0); 1935094#L788-1 assume !(1 == ~E_4~0); 1935408#L793-1 assume !(1 == ~E_5~0); 1935357#L798-1 assume !(1 == ~E_6~0); 1934982#L803-1 assume { :end_inline_reset_delta_events } true; 1934983#L1024-2 assume !false; 2078165#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2078116#L645 [2021-12-06 22:09:51,444 INFO L793 eck$LassoCheckResult]: Loop: 2078116#L645 assume !false; 2078160#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2078157#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2078155#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2078153#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2078149#L556 assume 0 != eval_~tmp~0#1; 2078147#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 2078145#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 2078143#L561 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 2078140#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 2078138#L575 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 2061692#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 2078134#L589 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 2078129#L606 assume !(0 != eval_~tmp_ndt_4~0#1); 2078127#L603 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 2078124#L620 assume !(0 != eval_~tmp_ndt_5~0#1); 2078122#L617 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 2078120#L634 assume !(0 != eval_~tmp_ndt_6~0#1); 2078118#L631 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0#1;eval_~tmp_ndt_7~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 2078083#L648 assume !(0 != eval_~tmp_ndt_7~0#1); 2078116#L645 [2021-12-06 22:09:51,444 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:51,444 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 7 times [2021-12-06 22:09:51,444 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:51,444 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [544818562] [2021-12-06 22:09:51,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:51,445 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:51,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:51,451 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:09:51,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:51,465 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:09:51,465 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:51,465 INFO L85 PathProgramCache]: Analyzing trace with hash -141880392, now seen corresponding path program 1 times [2021-12-06 22:09:51,465 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:51,465 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1992596401] [2021-12-06 22:09:51,465 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:51,466 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:51,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:51,468 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:09:51,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:51,471 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:09:51,471 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:09:51,472 INFO L85 PathProgramCache]: Analyzing trace with hash -668208594, now seen corresponding path program 1 times [2021-12-06 22:09:51,472 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:09:51,472 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [579859548] [2021-12-06 22:09:51,472 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:09:51,472 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:09:51,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:51,478 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:09:51,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:09:51,495 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:09:52,694 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 06.12 10:09:52 BoogieIcfgContainer [2021-12-06 22:09:52,695 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-12-06 22:09:52,695 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-12-06 22:09:52,695 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-12-06 22:09:52,695 INFO L275 PluginConnector]: Witness Printer initialized [2021-12-06 22:09:52,695 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 10:09:21" (3/4) ... [2021-12-06 22:09:52,697 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-12-06 22:09:52,738 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ab77971-ef11-4f75-af24-bd2dcc5fc51c/bin/uautomizer-DrprNOufMa/witness.graphml [2021-12-06 22:09:52,738 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-12-06 22:09:52,739 INFO L158 Benchmark]: Toolchain (without parser) took 31972.05ms. Allocated memory was 113.2MB in the beginning and 10.0GB in the end (delta: 9.9GB). Free memory was 74.8MB in the beginning and 5.4GB in the end (delta: -5.3GB). Peak memory consumption was 4.6GB. Max. memory is 16.1GB. [2021-12-06 22:09:52,739 INFO L158 Benchmark]: CDTParser took 0.14ms. Allocated memory is still 113.2MB. Free memory is still 91.5MB. There was no memory consumed. Max. memory is 16.1GB. [2021-12-06 22:09:52,739 INFO L158 Benchmark]: CACSL2BoogieTranslator took 264.30ms. Allocated memory is still 113.2MB. Free memory was 74.6MB in the beginning and 83.3MB in the end (delta: -8.7MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2021-12-06 22:09:52,739 INFO L158 Benchmark]: Boogie Procedure Inliner took 60.72ms. Allocated memory is still 113.2MB. Free memory was 83.3MB in the beginning and 78.2MB in the end (delta: 5.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-06 22:09:52,740 INFO L158 Benchmark]: Boogie Preprocessor took 73.69ms. Allocated memory is still 113.2MB. Free memory was 78.2MB in the beginning and 72.8MB in the end (delta: 5.4MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2021-12-06 22:09:52,740 INFO L158 Benchmark]: RCFGBuilder took 770.35ms. Allocated memory is still 113.2MB. Free memory was 72.8MB in the beginning and 63.9MB in the end (delta: 8.9MB). Peak memory consumption was 36.1MB. Max. memory is 16.1GB. [2021-12-06 22:09:52,740 INFO L158 Benchmark]: BuchiAutomizer took 30754.99ms. Allocated memory was 113.2MB in the beginning and 10.0GB in the end (delta: 9.9GB). Free memory was 63.9MB in the beginning and 5.4GB in the end (delta: -5.3GB). Peak memory consumption was 4.6GB. Max. memory is 16.1GB. [2021-12-06 22:09:52,740 INFO L158 Benchmark]: Witness Printer took 43.20ms. Allocated memory is still 10.0GB. Free memory was 5.4GB in the beginning and 5.4GB in the end (delta: 5.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-06 22:09:52,742 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14ms. Allocated memory is still 113.2MB. Free memory is still 91.5MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 264.30ms. Allocated memory is still 113.2MB. Free memory was 74.6MB in the beginning and 83.3MB in the end (delta: -8.7MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 60.72ms. Allocated memory is still 113.2MB. Free memory was 83.3MB in the beginning and 78.2MB in the end (delta: 5.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 73.69ms. Allocated memory is still 113.2MB. Free memory was 78.2MB in the beginning and 72.8MB in the end (delta: 5.4MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * RCFGBuilder took 770.35ms. Allocated memory is still 113.2MB. Free memory was 72.8MB in the beginning and 63.9MB in the end (delta: 8.9MB). Peak memory consumption was 36.1MB. Max. memory is 16.1GB. * BuchiAutomizer took 30754.99ms. Allocated memory was 113.2MB in the beginning and 10.0GB in the end (delta: 9.9GB). Free memory was 63.9MB in the beginning and 5.4GB in the end (delta: -5.3GB). Peak memory consumption was 4.6GB. Max. memory is 16.1GB. * Witness Printer took 43.20ms. Allocated memory is still 10.0GB. Free memory was 5.4GB in the beginning and 5.4GB in the end (delta: 5.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 28 terminating modules (28 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.28 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 367107 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 30.7s and 29 iterations. TraceHistogramMax:1. Analysis of lassos took 3.7s. Construction of modules took 0.5s. Büchi inclusion checks took 4.0s. Highest rank in rank-based complementation 0. Minimization of det autom 28. Minimization of nondet autom 0. Automata minimization 11.0s AutomataMinimizationTime, 28 MinimizatonAttempts, 71126 StatesRemovedByMinimization, 19 NontrivialMinimizations. Non-live state removal took 7.0s Buchi closure took 0.5s. Biggest automaton had 367107 states and ocurred in iteration 28. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 33336 SdHoareTripleChecker+Valid, 0.7s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 33336 mSDsluCounter, 52310 SdHoareTripleChecker+Invalid, 0.6s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 23591 mSDsCounter, 350 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 836 IncrementalHoareTripleChecker+Invalid, 1186 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 350 mSolverCounterUnsat, 28719 mSDtfsCounter, 836 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc6 concLT0 SILN1 SILU0 SILI17 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 551]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {tmp_ndt_3=0, NULL=0, t3_st=0, NULL=1, tmp=0, \result=0, t5_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@667c8a0d=0, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6aff4a48=0, tmp___5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@20cc1b08=0, tmp_ndt_2=0, \result=0, t4_i=1, \result=0, E_3=2, t4_pc=0, E_5=2, T6_E=2, E_1=2, tmp_ndt_1=0, tmp___4=0, __retres1=1, tmp=1, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@67f70a5e=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7b9c2cd5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@cccb788=0, m_st=0, t6_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@31c4c61f=0, NULL=0, t3_pc=0, tmp___3=0, __retres1=0, tmp___0=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@44f0e917=0, t6_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3e85cb7=0, tmp___2=0, m_pc=0, \result=0, \result=1, __retres1=0, t6_st=0, __retres1=0, tmp_ndt_7=0, E_6=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@133cbc2e=0, \result=0, \result=0, __retres1=0, tmp___1=0, T2_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2520c4f2=0, tmp_ndt_6=0, tmp=0, t1_pc=0, t5_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@30f1ba54=0, E_2=2, tmp___0=0, E_4=2, T1_E=2, __retres1=0, M_E=2, T5_E=2, t2_i=1, T4_E=2, \result=0, t3_i=1, t4_st=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5089ca79=0, t1_st=0, t5_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@712b172d=0, __retres1=0, t2_pc=0, tmp_ndt_5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@295482c6=0, __retres1=0, tmp_ndt_4=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1c68225=0, kernel_st=1, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@51bf0a36=0, t1_i=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 551]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int t6_pc = 0; [L32] int m_st ; [L33] int t1_st ; [L34] int t2_st ; [L35] int t3_st ; [L36] int t4_st ; [L37] int t5_st ; [L38] int t6_st ; [L39] int m_i ; [L40] int t1_i ; [L41] int t2_i ; [L42] int t3_i ; [L43] int t4_i ; [L44] int t5_i ; [L45] int t6_i ; [L46] int M_E = 2; [L47] int T1_E = 2; [L48] int T2_E = 2; [L49] int T3_E = 2; [L50] int T4_E = 2; [L51] int T5_E = 2; [L52] int T6_E = 2; [L53] int E_1 = 2; [L54] int E_2 = 2; [L55] int E_3 = 2; [L56] int E_4 = 2; [L57] int E_5 = 2; [L58] int E_6 = 2; [L1069] int __retres1 ; [L1073] CALL init_model() [L979] m_i = 1 [L980] t1_i = 1 [L981] t2_i = 1 [L982] t3_i = 1 [L983] t4_i = 1 [L984] t5_i = 1 [L985] t6_i = 1 [L1073] RET init_model() [L1074] CALL start_simulation() [L1010] int kernel_st ; [L1011] int tmp ; [L1012] int tmp___0 ; [L1016] kernel_st = 0 [L1017] FCALL update_channels() [L1018] CALL init_threads() [L461] COND TRUE m_i == 1 [L462] m_st = 0 [L466] COND TRUE t1_i == 1 [L467] t1_st = 0 [L471] COND TRUE t2_i == 1 [L472] t2_st = 0 [L476] COND TRUE t3_i == 1 [L477] t3_st = 0 [L481] COND TRUE t4_i == 1 [L482] t4_st = 0 [L486] COND TRUE t5_i == 1 [L487] t5_st = 0 [L491] COND TRUE t6_i == 1 [L492] t6_st = 0 [L1018] RET init_threads() [L1019] CALL fire_delta_events() [L670] COND FALSE !(M_E == 0) [L675] COND FALSE !(T1_E == 0) [L680] COND FALSE !(T2_E == 0) [L685] COND FALSE !(T3_E == 0) [L690] COND FALSE !(T4_E == 0) [L695] COND FALSE !(T5_E == 0) [L700] COND FALSE !(T6_E == 0) [L705] COND FALSE !(E_1 == 0) [L710] COND FALSE !(E_2 == 0) [L715] COND FALSE !(E_3 == 0) [L720] COND FALSE !(E_4 == 0) [L725] COND FALSE !(E_5 == 0) [L730] COND FALSE !(E_6 == 0) [L1019] RET fire_delta_events() [L1020] CALL activate_threads() [L813] int tmp ; [L814] int tmp___0 ; [L815] int tmp___1 ; [L816] int tmp___2 ; [L817] int tmp___3 ; [L818] int tmp___4 ; [L819] int tmp___5 ; [L823] CALL, EXPR is_master_triggered() [L317] int __retres1 ; [L320] COND FALSE !(m_pc == 1) [L330] __retres1 = 0 [L332] return (__retres1); [L823] RET, EXPR is_master_triggered() [L823] tmp = is_master_triggered() [L825] COND FALSE !(\read(tmp)) [L831] CALL, EXPR is_transmit1_triggered() [L336] int __retres1 ; [L339] COND FALSE !(t1_pc == 1) [L349] __retres1 = 0 [L351] return (__retres1); [L831] RET, EXPR is_transmit1_triggered() [L831] tmp___0 = is_transmit1_triggered() [L833] COND FALSE !(\read(tmp___0)) [L839] CALL, EXPR is_transmit2_triggered() [L355] int __retres1 ; [L358] COND FALSE !(t2_pc == 1) [L368] __retres1 = 0 [L370] return (__retres1); [L839] RET, EXPR is_transmit2_triggered() [L839] tmp___1 = is_transmit2_triggered() [L841] COND FALSE !(\read(tmp___1)) [L847] CALL, EXPR is_transmit3_triggered() [L374] int __retres1 ; [L377] COND FALSE !(t3_pc == 1) [L387] __retres1 = 0 [L389] return (__retres1); [L847] RET, EXPR is_transmit3_triggered() [L847] tmp___2 = is_transmit3_triggered() [L849] COND FALSE !(\read(tmp___2)) [L855] CALL, EXPR is_transmit4_triggered() [L393] int __retres1 ; [L396] COND FALSE !(t4_pc == 1) [L406] __retres1 = 0 [L408] return (__retres1); [L855] RET, EXPR is_transmit4_triggered() [L855] tmp___3 = is_transmit4_triggered() [L857] COND FALSE !(\read(tmp___3)) [L863] CALL, EXPR is_transmit5_triggered() [L412] int __retres1 ; [L415] COND FALSE !(t5_pc == 1) [L425] __retres1 = 0 [L427] return (__retres1); [L863] RET, EXPR is_transmit5_triggered() [L863] tmp___4 = is_transmit5_triggered() [L865] COND FALSE !(\read(tmp___4)) [L871] CALL, EXPR is_transmit6_triggered() [L431] int __retres1 ; [L434] COND FALSE !(t6_pc == 1) [L444] __retres1 = 0 [L446] return (__retres1); [L871] RET, EXPR is_transmit6_triggered() [L871] tmp___5 = is_transmit6_triggered() [L873] COND FALSE !(\read(tmp___5)) [L1020] RET activate_threads() [L1021] CALL reset_delta_events() [L743] COND FALSE !(M_E == 1) [L748] COND FALSE !(T1_E == 1) [L753] COND FALSE !(T2_E == 1) [L758] COND FALSE !(T3_E == 1) [L763] COND FALSE !(T4_E == 1) [L768] COND FALSE !(T5_E == 1) [L773] COND FALSE !(T6_E == 1) [L778] COND FALSE !(E_1 == 1) [L783] COND FALSE !(E_2 == 1) [L788] COND FALSE !(E_3 == 1) [L793] COND FALSE !(E_4 == 1) [L798] COND FALSE !(E_5 == 1) [L803] COND FALSE !(E_6 == 1) [L1021] RET reset_delta_events() [L1024] COND TRUE 1 [L1027] kernel_st = 1 [L1028] CALL eval() [L547] int tmp ; Loop: [L551] COND TRUE 1 [L554] CALL, EXPR exists_runnable_thread() [L501] int __retres1 ; [L504] COND TRUE m_st == 0 [L505] __retres1 = 1 [L542] return (__retres1); [L554] RET, EXPR exists_runnable_thread() [L554] tmp = exists_runnable_thread() [L556] COND TRUE \read(tmp) [L561] COND TRUE m_st == 0 [L562] int tmp_ndt_1; [L563] tmp_ndt_1 = __VERIFIER_nondet_int() [L564] COND FALSE !(\read(tmp_ndt_1)) [L575] COND TRUE t1_st == 0 [L576] int tmp_ndt_2; [L577] tmp_ndt_2 = __VERIFIER_nondet_int() [L578] COND FALSE !(\read(tmp_ndt_2)) [L589] COND TRUE t2_st == 0 [L590] int tmp_ndt_3; [L591] tmp_ndt_3 = __VERIFIER_nondet_int() [L592] COND FALSE !(\read(tmp_ndt_3)) [L603] COND TRUE t3_st == 0 [L604] int tmp_ndt_4; [L605] tmp_ndt_4 = __VERIFIER_nondet_int() [L606] COND FALSE !(\read(tmp_ndt_4)) [L617] COND TRUE t4_st == 0 [L618] int tmp_ndt_5; [L619] tmp_ndt_5 = __VERIFIER_nondet_int() [L620] COND FALSE !(\read(tmp_ndt_5)) [L631] COND TRUE t5_st == 0 [L632] int tmp_ndt_6; [L633] tmp_ndt_6 = __VERIFIER_nondet_int() [L634] COND FALSE !(\read(tmp_ndt_6)) [L645] COND TRUE t6_st == 0 [L646] int tmp_ndt_7; [L647] tmp_ndt_7 = __VERIFIER_nondet_int() [L648] COND FALSE !(\read(tmp_ndt_7)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-12-06 22:09:52,783 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8ab77971-ef11-4f75-af24-bd2dcc5fc51c/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)