./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.07.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 839c364b Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6ae3e5e5-cf62-4174-8737-dd2fe952f97a/bin/uautomizer-DrprNOufMa/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6ae3e5e5-cf62-4174-8737-dd2fe952f97a/bin/uautomizer-DrprNOufMa/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6ae3e5e5-cf62-4174-8737-dd2fe952f97a/bin/uautomizer-DrprNOufMa/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6ae3e5e5-cf62-4174-8737-dd2fe952f97a/bin/uautomizer-DrprNOufMa/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.07.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6ae3e5e5-cf62-4174-8737-dd2fe952f97a/bin/uautomizer-DrprNOufMa/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6ae3e5e5-cf62-4174-8737-dd2fe952f97a/bin/uautomizer-DrprNOufMa --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 022987cd4c8c671e376c5c3e5a08e2f1b98444b4d5d48bc73787bff74aa0de0f --- Real Ultimate output --- This is Ultimate 0.2.2-hotfix-svcomp22-839c364 [2021-12-06 22:17:29,459 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-06 22:17:29,461 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-06 22:17:29,492 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-06 22:17:29,493 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-06 22:17:29,494 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-06 22:17:29,496 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-06 22:17:29,498 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-06 22:17:29,500 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-06 22:17:29,501 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-06 22:17:29,502 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-06 22:17:29,503 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-06 22:17:29,504 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-06 22:17:29,505 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-06 22:17:29,506 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-06 22:17:29,508 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-06 22:17:29,509 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-06 22:17:29,510 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-06 22:17:29,511 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-06 22:17:29,513 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-06 22:17:29,514 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-06 22:17:29,516 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-06 22:17:29,517 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-06 22:17:29,518 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-06 22:17:29,521 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-06 22:17:29,522 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-06 22:17:29,522 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-06 22:17:29,523 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-06 22:17:29,524 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-06 22:17:29,525 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-06 22:17:29,525 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-06 22:17:29,526 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-06 22:17:29,527 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-06 22:17:29,527 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-06 22:17:29,529 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-06 22:17:29,529 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-06 22:17:29,530 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-06 22:17:29,530 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-06 22:17:29,530 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-06 22:17:29,531 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-06 22:17:29,532 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-06 22:17:29,533 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6ae3e5e5-cf62-4174-8737-dd2fe952f97a/bin/uautomizer-DrprNOufMa/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-06 22:17:29,557 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-06 22:17:29,557 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-06 22:17:29,557 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-06 22:17:29,558 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-06 22:17:29,559 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-06 22:17:29,559 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-06 22:17:29,559 INFO L138 SettingsManager]: * Use SBE=true [2021-12-06 22:17:29,559 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-06 22:17:29,559 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-06 22:17:29,560 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-06 22:17:29,560 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-06 22:17:29,560 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-06 22:17:29,560 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-06 22:17:29,560 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-06 22:17:29,560 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-06 22:17:29,561 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-06 22:17:29,561 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-06 22:17:29,561 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-06 22:17:29,561 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-06 22:17:29,561 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-06 22:17:29,561 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-06 22:17:29,562 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-06 22:17:29,562 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-06 22:17:29,562 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-06 22:17:29,562 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-06 22:17:29,562 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-06 22:17:29,562 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-06 22:17:29,563 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-06 22:17:29,563 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-06 22:17:29,563 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-06 22:17:29,563 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-06 22:17:29,563 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-06 22:17:29,564 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-06 22:17:29,565 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6ae3e5e5-cf62-4174-8737-dd2fe952f97a/bin/uautomizer-DrprNOufMa/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6ae3e5e5-cf62-4174-8737-dd2fe952f97a/bin/uautomizer-DrprNOufMa Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 022987cd4c8c671e376c5c3e5a08e2f1b98444b4d5d48bc73787bff74aa0de0f [2021-12-06 22:17:29,768 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-06 22:17:29,783 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-06 22:17:29,785 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-06 22:17:29,786 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-06 22:17:29,786 INFO L275 PluginConnector]: CDTParser initialized [2021-12-06 22:17:29,787 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6ae3e5e5-cf62-4174-8737-dd2fe952f97a/bin/uautomizer-DrprNOufMa/../../sv-benchmarks/c/systemc/transmitter.07.cil.c [2021-12-06 22:17:29,829 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6ae3e5e5-cf62-4174-8737-dd2fe952f97a/bin/uautomizer-DrprNOufMa/data/aad19d4a7/03328913478c4c26982338cc818ed993/FLAGc31395e1d [2021-12-06 22:17:30,218 INFO L306 CDTParser]: Found 1 translation units. [2021-12-06 22:17:30,218 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6ae3e5e5-cf62-4174-8737-dd2fe952f97a/sv-benchmarks/c/systemc/transmitter.07.cil.c [2021-12-06 22:17:30,230 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6ae3e5e5-cf62-4174-8737-dd2fe952f97a/bin/uautomizer-DrprNOufMa/data/aad19d4a7/03328913478c4c26982338cc818ed993/FLAGc31395e1d [2021-12-06 22:17:30,243 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6ae3e5e5-cf62-4174-8737-dd2fe952f97a/bin/uautomizer-DrprNOufMa/data/aad19d4a7/03328913478c4c26982338cc818ed993 [2021-12-06 22:17:30,245 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-06 22:17:30,246 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-06 22:17:30,248 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-06 22:17:30,248 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-06 22:17:30,251 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-06 22:17:30,251 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 10:17:30" (1/1) ... [2021-12-06 22:17:30,252 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5159d985 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 10:17:30, skipping insertion in model container [2021-12-06 22:17:30,252 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 10:17:30" (1/1) ... [2021-12-06 22:17:30,258 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-06 22:17:30,287 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-06 22:17:30,399 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6ae3e5e5-cf62-4174-8737-dd2fe952f97a/sv-benchmarks/c/systemc/transmitter.07.cil.c[706,719] [2021-12-06 22:17:30,480 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-06 22:17:30,490 INFO L203 MainTranslator]: Completed pre-run [2021-12-06 22:17:30,501 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6ae3e5e5-cf62-4174-8737-dd2fe952f97a/sv-benchmarks/c/systemc/transmitter.07.cil.c[706,719] [2021-12-06 22:17:30,543 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-06 22:17:30,560 INFO L208 MainTranslator]: Completed translation [2021-12-06 22:17:30,561 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 10:17:30 WrapperNode [2021-12-06 22:17:30,561 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-06 22:17:30,562 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-06 22:17:30,562 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-06 22:17:30,562 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-06 22:17:30,569 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 10:17:30" (1/1) ... [2021-12-06 22:17:30,580 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 10:17:30" (1/1) ... [2021-12-06 22:17:30,640 INFO L137 Inliner]: procedures = 42, calls = 51, calls flagged for inlining = 46, calls inlined = 124, statements flattened = 1845 [2021-12-06 22:17:30,641 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-06 22:17:30,641 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-06 22:17:30,642 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-06 22:17:30,642 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-06 22:17:30,650 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 10:17:30" (1/1) ... [2021-12-06 22:17:30,650 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 10:17:30" (1/1) ... [2021-12-06 22:17:30,656 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 10:17:30" (1/1) ... [2021-12-06 22:17:30,657 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 10:17:30" (1/1) ... [2021-12-06 22:17:30,682 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 10:17:30" (1/1) ... [2021-12-06 22:17:30,705 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 10:17:30" (1/1) ... [2021-12-06 22:17:30,709 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 10:17:30" (1/1) ... [2021-12-06 22:17:30,719 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-06 22:17:30,720 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-06 22:17:30,720 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-06 22:17:30,720 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-06 22:17:30,721 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 10:17:30" (1/1) ... [2021-12-06 22:17:30,728 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 22:17:30,740 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6ae3e5e5-cf62-4174-8737-dd2fe952f97a/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 22:17:30,750 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6ae3e5e5-cf62-4174-8737-dd2fe952f97a/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 22:17:30,752 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6ae3e5e5-cf62-4174-8737-dd2fe952f97a/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-06 22:17:30,786 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-06 22:17:30,787 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-06 22:17:30,787 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-06 22:17:30,787 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-06 22:17:30,860 INFO L236 CfgBuilder]: Building ICFG [2021-12-06 22:17:30,862 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-06 22:17:31,543 INFO L277 CfgBuilder]: Performing block encoding [2021-12-06 22:17:31,558 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-06 22:17:31,558 INFO L301 CfgBuilder]: Removed 11 assume(true) statements. [2021-12-06 22:17:31,562 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 10:17:31 BoogieIcfgContainer [2021-12-06 22:17:31,562 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-06 22:17:31,563 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-06 22:17:31,563 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-06 22:17:31,566 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-06 22:17:31,567 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 22:17:31,567 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.12 10:17:30" (1/3) ... [2021-12-06 22:17:31,568 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@77e0a2cd and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.12 10:17:31, skipping insertion in model container [2021-12-06 22:17:31,568 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 22:17:31,568 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 10:17:30" (2/3) ... [2021-12-06 22:17:31,569 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@77e0a2cd and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.12 10:17:31, skipping insertion in model container [2021-12-06 22:17:31,569 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 22:17:31,569 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 10:17:31" (3/3) ... [2021-12-06 22:17:31,570 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.07.cil.c [2021-12-06 22:17:31,607 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-06 22:17:31,608 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-06 22:17:31,608 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-06 22:17:31,608 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-06 22:17:31,608 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-06 22:17:31,608 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-06 22:17:31,608 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-06 22:17:31,608 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-06 22:17:31,644 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 775 states, 774 states have (on average 1.5232558139534884) internal successors, (1179), 774 states have internal predecessors, (1179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:31,688 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 670 [2021-12-06 22:17:31,689 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:17:31,689 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:17:31,700 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:31,700 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:31,700 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-06 22:17:31,702 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 775 states, 774 states have (on average 1.5232558139534884) internal successors, (1179), 774 states have internal predecessors, (1179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:31,715 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 670 [2021-12-06 22:17:31,715 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:17:31,715 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:17:31,720 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:31,720 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:31,729 INFO L791 eck$LassoCheckResult]: Stem: 386#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 711#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 717#L1111true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 453#L514true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 641#L521true assume !(1 == ~m_i~0);~m_st~0 := 2; 606#L521-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 635#L526-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 192#L531-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 552#L536-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 238#L541-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 142#L546-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 599#L551-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 125#L556-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 683#L754true assume !(0 == ~M_E~0); 728#L754-2true assume !(0 == ~T1_E~0); 512#L759-1true assume !(0 == ~T2_E~0); 380#L764-1true assume !(0 == ~T3_E~0); 342#L769-1true assume !(0 == ~T4_E~0); 381#L774-1true assume !(0 == ~T5_E~0); 625#L779-1true assume 0 == ~T6_E~0;~T6_E~0 := 1; 524#L784-1true assume !(0 == ~T7_E~0); 340#L789-1true assume !(0 == ~E_1~0); 424#L794-1true assume !(0 == ~E_2~0); 755#L799-1true assume !(0 == ~E_3~0); 349#L804-1true assume !(0 == ~E_4~0); 377#L809-1true assume !(0 == ~E_5~0); 553#L814-1true assume !(0 == ~E_6~0); 11#L819-1true assume 0 == ~E_7~0;~E_7~0 := 1; 170#L824-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 141#L361true assume 1 == ~m_pc~0; 666#L362true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 708#L372true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77#L373true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 624#L930true assume !(0 != activate_threads_~tmp~1#1); 269#L930-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 137#L380true assume !(1 == ~t1_pc~0); 756#L380-2true is_transmit1_triggered_~__retres1~1#1 := 0; 636#L391true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 325#L392true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 760#L938true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 462#L938-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 440#L399true assume 1 == ~t2_pc~0; 628#L400true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 645#L410true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 344#L411true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 174#L946true assume !(0 != activate_threads_~tmp___1~0#1); 416#L946-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15#L418true assume !(1 == ~t3_pc~0); 692#L418-2true is_transmit3_triggered_~__retres1~3#1 := 0; 555#L429true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 696#L430true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 768#L954true assume !(0 != activate_threads_~tmp___2~0#1); 364#L954-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 685#L437true assume 1 == ~t4_pc~0; 747#L438true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 495#L448true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 441#L449true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 204#L962true assume !(0 != activate_threads_~tmp___3~0#1); 591#L962-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 478#L456true assume !(1 == ~t5_pc~0); 333#L456-2true is_transmit5_triggered_~__retres1~5#1 := 0; 673#L467true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 274#L468true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 412#L970true assume !(0 != activate_threads_~tmp___4~0#1); 726#L970-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 44#L475true assume 1 == ~t6_pc~0; 221#L476true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 63#L486true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 694#L487true activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 403#L978true assume !(0 != activate_threads_~tmp___5~0#1); 355#L978-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 551#L494true assume 1 == ~t7_pc~0; 301#L495true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 315#L505true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 265#L506true activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 383#L986true assume !(0 != activate_threads_~tmp___6~0#1); 752#L986-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 659#L837true assume !(1 == ~M_E~0); 571#L837-2true assume !(1 == ~T1_E~0); 435#L842-1true assume !(1 == ~T2_E~0); 212#L847-1true assume !(1 == ~T3_E~0); 262#L852-1true assume !(1 == ~T4_E~0); 772#L857-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 179#L862-1true assume !(1 == ~T6_E~0); 188#L867-1true assume !(1 == ~T7_E~0); 237#L872-1true assume !(1 == ~E_1~0); 394#L877-1true assume !(1 == ~E_2~0); 581#L882-1true assume !(1 == ~E_3~0); 703#L887-1true assume !(1 == ~E_4~0); 456#L892-1true assume !(1 == ~E_5~0); 651#L897-1true assume 1 == ~E_6~0;~E_6~0 := 2; 197#L902-1true assume !(1 == ~E_7~0); 477#L907-1true assume { :end_inline_reset_delta_events } true; 229#L1148-2true [2021-12-06 22:17:31,732 INFO L793 eck$LassoCheckResult]: Loop: 229#L1148-2true assume !false; 12#L1149true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 112#L729true assume !true; 214#L744true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 215#L514-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 151#L754-3true assume 0 == ~M_E~0;~M_E~0 := 1; 18#L754-5true assume !(0 == ~T1_E~0); 534#L759-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 224#L764-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 609#L769-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 365#L774-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 93#L779-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 16#L784-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 765#L789-3true assume 0 == ~E_1~0;~E_1~0 := 1; 13#L794-3true assume !(0 == ~E_2~0); 35#L799-3true assume 0 == ~E_3~0;~E_3~0 := 1; 154#L804-3true assume 0 == ~E_4~0;~E_4~0 := 1; 291#L809-3true assume 0 == ~E_5~0;~E_5~0 := 1; 34#L814-3true assume 0 == ~E_6~0;~E_6~0 := 1; 529#L819-3true assume 0 == ~E_7~0;~E_7~0 := 1; 487#L824-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 234#L361-24true assume 1 == ~m_pc~0; 85#L362-8true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 300#L372-8true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 406#L373-8true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 556#L930-24true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 584#L930-26true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 347#L380-24true assume 1 == ~t1_pc~0; 585#L381-8true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 618#L391-8true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 253#L392-8true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 149#L938-24true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 442#L938-26true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 508#L399-24true assume 1 == ~t2_pc~0; 741#L400-8true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 114#L410-8true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49#L411-8true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 261#L946-24true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 146#L946-26true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 616#L418-24true assume !(1 == ~t3_pc~0); 33#L418-26true is_transmit3_triggered_~__retres1~3#1 := 0; 183#L429-8true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 147#L430-8true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 95#L954-24true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 414#L954-26true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 560#L437-24true assume !(1 == ~t4_pc~0); 775#L437-26true is_transmit4_triggered_~__retres1~4#1 := 0; 733#L448-8true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 457#L449-8true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 86#L962-24true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 354#L962-26true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 637#L456-24true assume 1 == ~t5_pc~0; 329#L457-8true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 304#L467-8true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 110#L468-8true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 576#L970-24true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 271#L970-26true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 759#L475-24true assume !(1 == ~t6_pc~0); 586#L475-26true is_transmit6_triggered_~__retres1~6#1 := 0; 313#L486-8true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 670#L487-8true activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 350#L978-24true assume !(0 != activate_threads_~tmp___5~0#1); 7#L978-26true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 308#L494-24true assume 1 == ~t7_pc~0; 246#L495-8true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 173#L505-8true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 532#L506-8true activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 144#L986-24true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 490#L986-26true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 519#L837-3true assume !(1 == ~M_E~0); 661#L837-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 267#L842-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 603#L847-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 409#L852-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 312#L857-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 739#L862-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 699#L867-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 245#L872-3true assume !(1 == ~E_1~0); 303#L877-3true assume 1 == ~E_2~0;~E_2~0 := 2; 721#L882-3true assume 1 == ~E_3~0;~E_3~0 := 2; 358#L887-3true assume 1 == ~E_4~0;~E_4~0 := 2; 106#L892-3true assume 1 == ~E_5~0;~E_5~0 := 2; 518#L897-3true assume 1 == ~E_6~0;~E_6~0 := 2; 763#L902-3true assume 1 == ~E_7~0;~E_7~0 := 2; 194#L907-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 583#L569-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 370#L611-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 382#L612-1true start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 679#L1167true assume !(0 == start_simulation_~tmp~3#1); 232#L1167-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 738#L569-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 255#L611-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 674#L612-2true stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 306#L1122true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 222#L1129true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8#L1130true start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 124#L1180true assume !(0 != start_simulation_~tmp___0~1#1); 229#L1148-2true [2021-12-06 22:17:31,738 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:31,739 INFO L85 PathProgramCache]: Analyzing trace with hash -171938705, now seen corresponding path program 1 times [2021-12-06 22:17:31,748 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:31,749 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2088561711] [2021-12-06 22:17:31,749 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:31,750 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:31,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:31,921 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:31,921 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:31,922 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2088561711] [2021-12-06 22:17:31,923 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2088561711] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:31,923 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:31,923 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:31,925 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [841923083] [2021-12-06 22:17:31,926 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:31,930 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:17:31,931 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:31,932 INFO L85 PathProgramCache]: Analyzing trace with hash -1169217165, now seen corresponding path program 1 times [2021-12-06 22:17:31,932 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:31,932 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [81882357] [2021-12-06 22:17:31,932 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:31,933 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:31,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:31,976 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:31,976 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:31,977 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [81882357] [2021-12-06 22:17:31,977 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [81882357] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:31,977 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:31,977 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 22:17:31,978 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [906012770] [2021-12-06 22:17:31,978 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:31,979 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:17:31,980 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:17:32,008 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:17:32,009 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:17:32,012 INFO L87 Difference]: Start difference. First operand has 775 states, 774 states have (on average 1.5232558139534884) internal successors, (1179), 774 states have internal predecessors, (1179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:32,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:17:32,087 INFO L93 Difference]: Finished difference Result 774 states and 1154 transitions. [2021-12-06 22:17:32,088 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:17:32,092 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 774 states and 1154 transitions. [2021-12-06 22:17:32,100 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2021-12-06 22:17:32,111 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 774 states to 768 states and 1148 transitions. [2021-12-06 22:17:32,112 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2021-12-06 22:17:32,114 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2021-12-06 22:17:32,114 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1148 transitions. [2021-12-06 22:17:32,118 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:17:32,119 INFO L681 BuchiCegarLoop]: Abstraction has 768 states and 1148 transitions. [2021-12-06 22:17:32,132 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1148 transitions. [2021-12-06 22:17:32,159 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2021-12-06 22:17:32,161 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.4947916666666667) internal successors, (1148), 767 states have internal predecessors, (1148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:32,164 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1148 transitions. [2021-12-06 22:17:32,164 INFO L704 BuchiCegarLoop]: Abstraction has 768 states and 1148 transitions. [2021-12-06 22:17:32,165 INFO L587 BuchiCegarLoop]: Abstraction has 768 states and 1148 transitions. [2021-12-06 22:17:32,165 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-06 22:17:32,165 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1148 transitions. [2021-12-06 22:17:32,168 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2021-12-06 22:17:32,169 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:17:32,169 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:17:32,171 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:32,171 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:32,171 INFO L791 eck$LassoCheckResult]: Stem: 2325#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 2304#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2305#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1765#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1766#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 2182#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2183#L526-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2151#L531-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2074#L536-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2075#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2064#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2065#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2024#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2025#L754 assume !(0 == ~M_E~0); 2283#L754-2 assume !(0 == ~T1_E~0); 1967#L759-1 assume !(0 == ~T2_E~0); 1968#L764-1 assume !(0 == ~T3_E~0); 2312#L769-1 assume !(0 == ~T4_E~0); 2313#L774-1 assume !(0 == ~T5_E~0); 2213#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1998#L784-1 assume !(0 == ~T7_E~0); 1999#L789-1 assume !(0 == ~E_1~0); 1678#L794-1 assume !(0 == ~E_2~0); 1679#L799-1 assume !(0 == ~E_3~0); 2314#L804-1 assume !(0 == ~E_4~0); 2315#L809-1 assume !(0 == ~E_5~0); 2078#L814-1 assume !(0 == ~E_6~0); 1594#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 1595#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2060#L361 assume 1 == ~m_pc~0; 2061#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2102#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1883#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1884#L930 assume !(0 != activate_threads_~tmp~1#1); 2208#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2054#L380 assume !(1 == ~t1_pc~0); 1728#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1727#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2233#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2308#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1804#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1729#L399 assume 1 == ~t2_pc~0; 1730#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1936#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2243#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2122#L946 assume !(0 != activate_threads_~tmp___1~0#1); 1634#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1602#L418 assume !(1 == ~t3_pc~0); 1563#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1564#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2082#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2290#L954 assume !(0 != activate_threads_~tmp___2~0#1); 2320#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2285#L437 assume 1 == ~t4_pc~0; 2286#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1904#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1732#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1733#L962 assume !(0 != activate_threads_~tmp___3~0#1); 2161#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1860#L456 assume !(1 == ~t5_pc~0); 1861#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1964#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2264#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1624#L970 assume !(0 != activate_threads_~tmp___4~0#1); 1625#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1748#L475 assume 1 == ~t6_pc~0; 1749#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1824#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1825#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1584#L978 assume !(0 != activate_threads_~tmp___5~0#1); 1585#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2067#L494 assume 1 == ~t7_pc~0; 2068#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2108#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2260#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2261#L986 assume !(0 != activate_threads_~tmp___6~0#1); 2323#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2262#L837 assume !(1 == ~M_E~0); 2125#L837-2 assume !(1 == ~T1_E~0); 1711#L842-1 assume !(1 == ~T2_E~0); 1712#L847-1 assume !(1 == ~T3_E~0); 2178#L852-1 assume !(1 == ~T4_E~0); 2255#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2134#L862-1 assume !(1 == ~T6_E~0); 2135#L867-1 assume !(1 == ~T7_E~0); 2144#L872-1 assume !(1 == ~E_1~0); 2210#L877-1 assume !(1 == ~E_2~0); 2140#L882-1 assume !(1 == ~E_3~0); 2141#L887-1 assume !(1 == ~E_4~0); 1771#L892-1 assume !(1 == ~E_5~0); 1772#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 2158#L902-1 assume !(1 == ~E_7~0); 1852#L907-1 assume { :end_inline_reset_delta_events } true; 1853#L1148-2 [2021-12-06 22:17:32,172 INFO L793 eck$LassoCheckResult]: Loop: 1853#L1148-2 assume !false; 1596#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1597#L729 assume !false; 1995#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1991#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1942#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2011#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2049#L626 assume !(0 != eval_~tmp~0#1); 2050#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2180#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2084#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1637#L754-5 assume !(0 == ~T1_E~0); 1638#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2020#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2188#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2189#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1952#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1613#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1614#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1598#L794-3 assume !(0 == ~E_2~0); 1599#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1693#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2090#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1686#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1687#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1886#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1887#L361-24 assume 1 == ~m_pc~0; 1923#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1924#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1606#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1607#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2083#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2147#L380-24 assume 1 == ~t1_pc~0; 2148#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1774#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2206#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2079#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1734#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1735#L399-24 assume 1 == ~t2_pc~0; 1947#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1997#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1775#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1776#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2071#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2072#L418-24 assume !(1 == ~t3_pc~0); 1682#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1683#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2073#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1951#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1626#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1627#L437-24 assume 1 == ~t4_pc~0; 1898#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1899#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1777#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1778#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1926#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2235#L456-24 assume 1 == ~t5_pc~0; 2236#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2296#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1989#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1990#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2129#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2263#L475-24 assume 1 == ~t6_pc~0; 1628#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1629#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2272#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2273#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 1571#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1572#L494-24 assume 1 == ~t7_pc~0; 2229#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2119#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2016#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2017#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1896#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1897#L837-3 assume !(1 == ~M_E~0); 1979#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2259#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2175#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1615#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1616#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2300#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2292#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2226#L872-3 assume !(1 == ~E_1~0); 2227#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2295#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2310#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1982#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1975#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1976#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2152#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2145#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1601#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2321#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 2281#L1167 assume !(0 == start_simulation_~tmp~3#1); 2176#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2203#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2008#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2242#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 2275#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2190#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1577#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1578#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 1853#L1148-2 [2021-12-06 22:17:32,172 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:32,172 INFO L85 PathProgramCache]: Analyzing trace with hash 598794861, now seen corresponding path program 1 times [2021-12-06 22:17:32,173 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:32,173 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1926262818] [2021-12-06 22:17:32,173 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:32,173 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:32,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:32,221 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:32,222 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:32,222 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1926262818] [2021-12-06 22:17:32,222 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1926262818] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:32,222 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:32,222 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:32,222 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [380690436] [2021-12-06 22:17:32,223 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:32,223 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:17:32,223 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:32,224 INFO L85 PathProgramCache]: Analyzing trace with hash 1141273896, now seen corresponding path program 1 times [2021-12-06 22:17:32,224 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:32,224 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [618360701] [2021-12-06 22:17:32,224 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:32,224 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:32,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:32,305 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:32,305 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:32,306 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [618360701] [2021-12-06 22:17:32,306 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [618360701] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:32,306 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:32,306 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:32,306 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1290813389] [2021-12-06 22:17:32,306 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:32,307 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:17:32,307 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:17:32,308 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:17:32,308 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:17:32,308 INFO L87 Difference]: Start difference. First operand 768 states and 1148 transitions. cyclomatic complexity: 381 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:32,345 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:17:32,345 INFO L93 Difference]: Finished difference Result 768 states and 1147 transitions. [2021-12-06 22:17:32,345 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:17:32,346 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 768 states and 1147 transitions. [2021-12-06 22:17:32,352 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2021-12-06 22:17:32,359 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 768 states to 768 states and 1147 transitions. [2021-12-06 22:17:32,360 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2021-12-06 22:17:32,361 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2021-12-06 22:17:32,361 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1147 transitions. [2021-12-06 22:17:32,363 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:17:32,363 INFO L681 BuchiCegarLoop]: Abstraction has 768 states and 1147 transitions. [2021-12-06 22:17:32,364 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1147 transitions. [2021-12-06 22:17:32,376 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2021-12-06 22:17:32,378 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.4934895833333333) internal successors, (1147), 767 states have internal predecessors, (1147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:32,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1147 transitions. [2021-12-06 22:17:32,381 INFO L704 BuchiCegarLoop]: Abstraction has 768 states and 1147 transitions. [2021-12-06 22:17:32,381 INFO L587 BuchiCegarLoop]: Abstraction has 768 states and 1147 transitions. [2021-12-06 22:17:32,382 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-06 22:17:32,382 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1147 transitions. [2021-12-06 22:17:32,386 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2021-12-06 22:17:32,386 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:17:32,386 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:17:32,388 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:32,389 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:32,389 INFO L791 eck$LassoCheckResult]: Stem: 3868#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 3846#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 3847#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3308#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3309#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 3725#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3726#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3694#L531-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3614#L536-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3615#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3607#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3608#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3567#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3568#L754 assume !(0 == ~M_E~0); 3826#L754-2 assume !(0 == ~T1_E~0); 3510#L759-1 assume !(0 == ~T2_E~0); 3511#L764-1 assume !(0 == ~T3_E~0); 3855#L769-1 assume !(0 == ~T4_E~0); 3856#L774-1 assume !(0 == ~T5_E~0); 3754#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3541#L784-1 assume !(0 == ~T7_E~0); 3542#L789-1 assume !(0 == ~E_1~0); 3217#L794-1 assume !(0 == ~E_2~0); 3218#L799-1 assume !(0 == ~E_3~0); 3857#L804-1 assume !(0 == ~E_4~0); 3858#L809-1 assume !(0 == ~E_5~0); 3619#L814-1 assume !(0 == ~E_6~0); 3137#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 3138#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3603#L361 assume 1 == ~m_pc~0; 3604#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3645#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3426#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3427#L930 assume !(0 != activate_threads_~tmp~1#1); 3751#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3597#L380 assume !(1 == ~t1_pc~0); 3271#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3270#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3774#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3851#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3347#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3272#L399 assume 1 == ~t2_pc~0; 3273#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3479#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3786#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3665#L946 assume !(0 != activate_threads_~tmp___1~0#1); 3177#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3145#L418 assume !(1 == ~t3_pc~0); 3106#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3107#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3625#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3833#L954 assume !(0 != activate_threads_~tmp___2~0#1); 3863#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3827#L437 assume 1 == ~t4_pc~0; 3828#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3447#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3275#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3276#L962 assume !(0 != activate_threads_~tmp___3~0#1); 3704#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3398#L456 assume !(1 == ~t5_pc~0); 3399#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3507#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3807#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3164#L970 assume !(0 != activate_threads_~tmp___4~0#1); 3165#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3288#L475 assume 1 == ~t6_pc~0; 3289#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3367#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3368#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3127#L978 assume !(0 != activate_threads_~tmp___5~0#1); 3128#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3610#L494 assume 1 == ~t7_pc~0; 3611#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3651#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3801#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3802#L986 assume !(0 != activate_threads_~tmp___6~0#1); 3866#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3803#L837 assume !(1 == ~M_E~0); 3668#L837-2 assume !(1 == ~T1_E~0); 3254#L842-1 assume !(1 == ~T2_E~0); 3255#L847-1 assume !(1 == ~T3_E~0); 3721#L852-1 assume !(1 == ~T4_E~0); 3796#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3676#L862-1 assume !(1 == ~T6_E~0); 3677#L867-1 assume !(1 == ~T7_E~0); 3685#L872-1 assume !(1 == ~E_1~0); 3753#L877-1 assume !(1 == ~E_2~0); 3683#L882-1 assume !(1 == ~E_3~0); 3684#L887-1 assume !(1 == ~E_4~0); 3314#L892-1 assume !(1 == ~E_5~0); 3315#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 3699#L902-1 assume !(1 == ~E_7~0); 3395#L907-1 assume { :end_inline_reset_delta_events } true; 3396#L1148-2 [2021-12-06 22:17:32,390 INFO L793 eck$LassoCheckResult]: Loop: 3396#L1148-2 assume !false; 3139#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3140#L729 assume !false; 3538#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3534#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3485#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3554#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3591#L626 assume !(0 != eval_~tmp~0#1); 3592#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3722#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3627#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3178#L754-5 assume !(0 == ~T1_E~0); 3179#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3563#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3731#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3732#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3490#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3154#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3155#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3141#L794-3 assume !(0 == ~E_2~0); 3142#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3236#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3633#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3231#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3232#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3429#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3430#L361-24 assume 1 == ~m_pc~0; 3466#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3467#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3149#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3150#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3626#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3690#L380-24 assume !(1 == ~t1_pc~0); 3316#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 3317#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3749#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3622#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3277#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3278#L399-24 assume 1 == ~t2_pc~0; 3491#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3540#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3318#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3319#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3616#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3617#L418-24 assume 1 == ~t3_pc~0; 3620#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3226#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3618#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3495#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3169#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3170#L437-24 assume 1 == ~t4_pc~0; 3441#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3442#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3320#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3321#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3469#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3778#L456-24 assume 1 == ~t5_pc~0; 3779#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3839#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3532#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3533#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3674#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3806#L475-24 assume 1 == ~t6_pc~0; 3171#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3172#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3815#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3816#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 3114#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3115#L494-24 assume !(1 == ~t7_pc~0); 3682#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 3663#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3559#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3560#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3439#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3440#L837-3 assume !(1 == ~M_E~0); 3522#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3805#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3719#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3158#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3159#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3843#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3835#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3770#L872-3 assume !(1 == ~E_1~0); 3771#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3838#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3853#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3527#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3520#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3521#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3695#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3688#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3144#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3864#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 3824#L1167 assume !(0 == start_simulation_~tmp~3#1); 3718#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3746#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3552#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3785#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 3818#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3733#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3120#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 3121#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 3396#L1148-2 [2021-12-06 22:17:32,390 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:32,390 INFO L85 PathProgramCache]: Analyzing trace with hash 1185071083, now seen corresponding path program 1 times [2021-12-06 22:17:32,391 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:32,391 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [973363384] [2021-12-06 22:17:32,391 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:32,391 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:32,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:32,431 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:32,431 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:32,432 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [973363384] [2021-12-06 22:17:32,432 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [973363384] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:32,432 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:32,432 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:32,432 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1538092064] [2021-12-06 22:17:32,432 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:32,433 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:17:32,433 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:32,434 INFO L85 PathProgramCache]: Analyzing trace with hash 1561027463, now seen corresponding path program 1 times [2021-12-06 22:17:32,434 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:32,434 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1795595073] [2021-12-06 22:17:32,434 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:32,434 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:32,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:32,491 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:32,492 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:32,492 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1795595073] [2021-12-06 22:17:32,492 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1795595073] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:32,492 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:32,492 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:32,492 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [101828697] [2021-12-06 22:17:32,493 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:32,493 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:17:32,493 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:17:32,494 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:17:32,494 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:17:32,494 INFO L87 Difference]: Start difference. First operand 768 states and 1147 transitions. cyclomatic complexity: 380 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:32,509 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:17:32,509 INFO L93 Difference]: Finished difference Result 768 states and 1146 transitions. [2021-12-06 22:17:32,509 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:17:32,510 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 768 states and 1146 transitions. [2021-12-06 22:17:32,514 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2021-12-06 22:17:32,518 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 768 states to 768 states and 1146 transitions. [2021-12-06 22:17:32,518 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2021-12-06 22:17:32,519 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2021-12-06 22:17:32,519 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1146 transitions. [2021-12-06 22:17:32,520 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:17:32,520 INFO L681 BuchiCegarLoop]: Abstraction has 768 states and 1146 transitions. [2021-12-06 22:17:32,521 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1146 transitions. [2021-12-06 22:17:32,528 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2021-12-06 22:17:32,529 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.4921875) internal successors, (1146), 767 states have internal predecessors, (1146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:32,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1146 transitions. [2021-12-06 22:17:32,532 INFO L704 BuchiCegarLoop]: Abstraction has 768 states and 1146 transitions. [2021-12-06 22:17:32,532 INFO L587 BuchiCegarLoop]: Abstraction has 768 states and 1146 transitions. [2021-12-06 22:17:32,532 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-06 22:17:32,532 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1146 transitions. [2021-12-06 22:17:32,535 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2021-12-06 22:17:32,535 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:17:32,535 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:17:32,536 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:32,536 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:32,537 INFO L791 eck$LassoCheckResult]: Stem: 5411#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 5390#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 5391#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4851#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4852#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 5268#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5269#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5237#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5160#L536-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5161#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5150#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5151#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5110#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5111#L754 assume !(0 == ~M_E~0); 5369#L754-2 assume !(0 == ~T1_E~0); 5053#L759-1 assume !(0 == ~T2_E~0); 5054#L764-1 assume !(0 == ~T3_E~0); 5398#L769-1 assume !(0 == ~T4_E~0); 5399#L774-1 assume !(0 == ~T5_E~0); 5299#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5084#L784-1 assume !(0 == ~T7_E~0); 5085#L789-1 assume !(0 == ~E_1~0); 4764#L794-1 assume !(0 == ~E_2~0); 4765#L799-1 assume !(0 == ~E_3~0); 5400#L804-1 assume !(0 == ~E_4~0); 5401#L809-1 assume !(0 == ~E_5~0); 5164#L814-1 assume !(0 == ~E_6~0); 4680#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 4681#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5146#L361 assume 1 == ~m_pc~0; 5147#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5188#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4969#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4970#L930 assume !(0 != activate_threads_~tmp~1#1); 5294#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5140#L380 assume !(1 == ~t1_pc~0); 4814#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4813#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5319#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5394#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4890#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4815#L399 assume 1 == ~t2_pc~0; 4816#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5022#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5329#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5208#L946 assume !(0 != activate_threads_~tmp___1~0#1); 4720#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4688#L418 assume !(1 == ~t3_pc~0); 4649#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4650#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5168#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5376#L954 assume !(0 != activate_threads_~tmp___2~0#1); 5406#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5371#L437 assume 1 == ~t4_pc~0; 5372#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4991#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4818#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4819#L962 assume !(0 != activate_threads_~tmp___3~0#1); 5247#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4946#L456 assume !(1 == ~t5_pc~0); 4947#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5050#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5350#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4710#L970 assume !(0 != activate_threads_~tmp___4~0#1); 4711#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4834#L475 assume 1 == ~t6_pc~0; 4835#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4910#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4911#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4670#L978 assume !(0 != activate_threads_~tmp___5~0#1); 4671#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5153#L494 assume 1 == ~t7_pc~0; 5154#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5194#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5346#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5347#L986 assume !(0 != activate_threads_~tmp___6~0#1); 5409#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5348#L837 assume !(1 == ~M_E~0); 5211#L837-2 assume !(1 == ~T1_E~0); 4797#L842-1 assume !(1 == ~T2_E~0); 4798#L847-1 assume !(1 == ~T3_E~0); 5264#L852-1 assume !(1 == ~T4_E~0); 5341#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5220#L862-1 assume !(1 == ~T6_E~0); 5221#L867-1 assume !(1 == ~T7_E~0); 5230#L872-1 assume !(1 == ~E_1~0); 5296#L877-1 assume !(1 == ~E_2~0); 5226#L882-1 assume !(1 == ~E_3~0); 5227#L887-1 assume !(1 == ~E_4~0); 4857#L892-1 assume !(1 == ~E_5~0); 4858#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 5244#L902-1 assume !(1 == ~E_7~0); 4938#L907-1 assume { :end_inline_reset_delta_events } true; 4939#L1148-2 [2021-12-06 22:17:32,537 INFO L793 eck$LassoCheckResult]: Loop: 4939#L1148-2 assume !false; 4682#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4683#L729 assume !false; 5081#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5077#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5028#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5097#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5135#L626 assume !(0 != eval_~tmp~0#1); 5136#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5266#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5170#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4723#L754-5 assume !(0 == ~T1_E~0); 4724#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5106#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5274#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5275#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5038#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4699#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4700#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4684#L794-3 assume !(0 == ~E_2~0); 4685#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4776#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5176#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4772#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4773#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4972#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4973#L361-24 assume 1 == ~m_pc~0; 5009#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5010#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4692#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4693#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5169#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5233#L380-24 assume 1 == ~t1_pc~0; 5234#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4860#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5292#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5165#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4820#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4821#L399-24 assume 1 == ~t2_pc~0; 5033#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5083#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4861#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4862#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5157#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5158#L418-24 assume !(1 == ~t3_pc~0); 4768#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 4769#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5159#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5037#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4712#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4713#L437-24 assume 1 == ~t4_pc~0; 4984#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4985#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4863#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4864#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5012#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5321#L456-24 assume 1 == ~t5_pc~0; 5322#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5382#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5075#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5076#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5215#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5349#L475-24 assume 1 == ~t6_pc~0; 4714#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4715#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5358#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5359#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 4657#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4658#L494-24 assume 1 == ~t7_pc~0; 5315#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5205#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5102#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5103#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4982#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4983#L837-3 assume !(1 == ~M_E~0); 5065#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5345#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5261#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4701#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4702#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5386#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5378#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5312#L872-3 assume !(1 == ~E_1~0); 5313#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5381#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5396#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5068#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5061#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5062#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5238#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5231#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 4687#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5407#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 5367#L1167 assume !(0 == start_simulation_~tmp~3#1); 5262#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5289#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5094#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5328#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 5361#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5276#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4663#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 4664#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 4939#L1148-2 [2021-12-06 22:17:32,538 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:32,538 INFO L85 PathProgramCache]: Analyzing trace with hash -1151321427, now seen corresponding path program 1 times [2021-12-06 22:17:32,538 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:32,538 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2039496561] [2021-12-06 22:17:32,538 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:32,538 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:32,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:32,560 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:32,560 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:32,560 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2039496561] [2021-12-06 22:17:32,560 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2039496561] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:32,560 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:32,560 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:32,561 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [464350932] [2021-12-06 22:17:32,561 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:32,561 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:17:32,561 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:32,561 INFO L85 PathProgramCache]: Analyzing trace with hash 1141273896, now seen corresponding path program 2 times [2021-12-06 22:17:32,561 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:32,562 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [749641119] [2021-12-06 22:17:32,562 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:32,562 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:32,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:32,591 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:32,591 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:32,591 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [749641119] [2021-12-06 22:17:32,592 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [749641119] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:32,592 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:32,592 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:32,592 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1957493034] [2021-12-06 22:17:32,592 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:32,592 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:17:32,592 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:17:32,593 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:17:32,593 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:17:32,593 INFO L87 Difference]: Start difference. First operand 768 states and 1146 transitions. cyclomatic complexity: 379 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:32,615 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:17:32,615 INFO L93 Difference]: Finished difference Result 768 states and 1145 transitions. [2021-12-06 22:17:32,615 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:17:32,616 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 768 states and 1145 transitions. [2021-12-06 22:17:32,619 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2021-12-06 22:17:32,623 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 768 states to 768 states and 1145 transitions. [2021-12-06 22:17:32,624 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2021-12-06 22:17:32,624 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2021-12-06 22:17:32,624 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1145 transitions. [2021-12-06 22:17:32,625 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:17:32,625 INFO L681 BuchiCegarLoop]: Abstraction has 768 states and 1145 transitions. [2021-12-06 22:17:32,626 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1145 transitions. [2021-12-06 22:17:32,633 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2021-12-06 22:17:32,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.4908854166666667) internal successors, (1145), 767 states have internal predecessors, (1145), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:32,636 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1145 transitions. [2021-12-06 22:17:32,636 INFO L704 BuchiCegarLoop]: Abstraction has 768 states and 1145 transitions. [2021-12-06 22:17:32,636 INFO L587 BuchiCegarLoop]: Abstraction has 768 states and 1145 transitions. [2021-12-06 22:17:32,636 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-06 22:17:32,636 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1145 transitions. [2021-12-06 22:17:32,639 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2021-12-06 22:17:32,639 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:17:32,639 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:17:32,640 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:32,640 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:32,641 INFO L791 eck$LassoCheckResult]: Stem: 6954#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 6932#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 6933#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6394#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6395#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 6811#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6812#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6780#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6700#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6701#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6693#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6694#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6653#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6654#L754 assume !(0 == ~M_E~0); 6912#L754-2 assume !(0 == ~T1_E~0); 6596#L759-1 assume !(0 == ~T2_E~0); 6597#L764-1 assume !(0 == ~T3_E~0); 6941#L769-1 assume !(0 == ~T4_E~0); 6942#L774-1 assume !(0 == ~T5_E~0); 6840#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6627#L784-1 assume !(0 == ~T7_E~0); 6628#L789-1 assume !(0 == ~E_1~0); 6303#L794-1 assume !(0 == ~E_2~0); 6304#L799-1 assume !(0 == ~E_3~0); 6943#L804-1 assume !(0 == ~E_4~0); 6944#L809-1 assume !(0 == ~E_5~0); 6705#L814-1 assume !(0 == ~E_6~0); 6223#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 6224#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6689#L361 assume 1 == ~m_pc~0; 6690#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6731#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6512#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6513#L930 assume !(0 != activate_threads_~tmp~1#1); 6837#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6683#L380 assume !(1 == ~t1_pc~0); 6357#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6356#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6860#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6937#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6433#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6358#L399 assume 1 == ~t2_pc~0; 6359#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6565#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6872#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6751#L946 assume !(0 != activate_threads_~tmp___1~0#1); 6263#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6231#L418 assume !(1 == ~t3_pc~0); 6192#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6193#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6711#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6919#L954 assume !(0 != activate_threads_~tmp___2~0#1); 6949#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6913#L437 assume 1 == ~t4_pc~0; 6914#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6533#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6361#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6362#L962 assume !(0 != activate_threads_~tmp___3~0#1); 6790#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6484#L456 assume !(1 == ~t5_pc~0); 6485#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 6593#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6893#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6250#L970 assume !(0 != activate_threads_~tmp___4~0#1); 6251#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6374#L475 assume 1 == ~t6_pc~0; 6375#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6453#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6454#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6213#L978 assume !(0 != activate_threads_~tmp___5~0#1); 6214#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6696#L494 assume 1 == ~t7_pc~0; 6697#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6737#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6887#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6888#L986 assume !(0 != activate_threads_~tmp___6~0#1); 6952#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6889#L837 assume !(1 == ~M_E~0); 6754#L837-2 assume !(1 == ~T1_E~0); 6340#L842-1 assume !(1 == ~T2_E~0); 6341#L847-1 assume !(1 == ~T3_E~0); 6807#L852-1 assume !(1 == ~T4_E~0); 6882#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6762#L862-1 assume !(1 == ~T6_E~0); 6763#L867-1 assume !(1 == ~T7_E~0); 6771#L872-1 assume !(1 == ~E_1~0); 6839#L877-1 assume !(1 == ~E_2~0); 6769#L882-1 assume !(1 == ~E_3~0); 6770#L887-1 assume !(1 == ~E_4~0); 6400#L892-1 assume !(1 == ~E_5~0); 6401#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 6785#L902-1 assume !(1 == ~E_7~0); 6481#L907-1 assume { :end_inline_reset_delta_events } true; 6482#L1148-2 [2021-12-06 22:17:32,641 INFO L793 eck$LassoCheckResult]: Loop: 6482#L1148-2 assume !false; 6225#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6226#L729 assume !false; 6624#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6620#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6571#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6640#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6677#L626 assume !(0 != eval_~tmp~0#1); 6678#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6808#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6713#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6264#L754-5 assume !(0 == ~T1_E~0); 6265#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6649#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6817#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6818#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6576#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6242#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6243#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6227#L794-3 assume !(0 == ~E_2~0); 6228#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6322#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6719#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6317#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6318#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6515#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6516#L361-24 assume 1 == ~m_pc~0; 6552#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6553#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6235#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6236#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6712#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6776#L380-24 assume !(1 == ~t1_pc~0); 6402#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 6403#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6835#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6708#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6363#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6364#L399-24 assume 1 == ~t2_pc~0; 6577#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6626#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6404#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6405#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6702#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6703#L418-24 assume 1 == ~t3_pc~0; 6706#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6312#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6704#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6581#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6255#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6256#L437-24 assume !(1 == ~t4_pc~0); 6529#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 6528#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6406#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6407#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6555#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6864#L456-24 assume 1 == ~t5_pc~0; 6865#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6925#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6618#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6619#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6760#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6892#L475-24 assume 1 == ~t6_pc~0; 6257#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6258#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6901#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6902#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 6200#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6201#L494-24 assume !(1 == ~t7_pc~0); 6768#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 6749#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6645#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6646#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6525#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6526#L837-3 assume !(1 == ~M_E~0); 6608#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6891#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6805#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6244#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6245#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6929#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6921#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6856#L872-3 assume !(1 == ~E_1~0); 6857#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6924#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6939#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6613#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6606#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6607#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6781#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6774#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6230#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6950#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 6910#L1167 assume !(0 == start_simulation_~tmp~3#1); 6804#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6832#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6638#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6871#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 6904#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6819#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6206#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 6207#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 6482#L1148-2 [2021-12-06 22:17:32,641 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:32,641 INFO L85 PathProgramCache]: Analyzing trace with hash 1267163051, now seen corresponding path program 1 times [2021-12-06 22:17:32,641 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:32,641 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1377378128] [2021-12-06 22:17:32,641 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:32,642 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:32,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:32,660 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:32,660 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:32,660 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1377378128] [2021-12-06 22:17:32,660 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1377378128] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:32,660 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:32,661 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:32,661 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [810276615] [2021-12-06 22:17:32,661 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:32,661 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:17:32,661 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:32,661 INFO L85 PathProgramCache]: Analyzing trace with hash 859459238, now seen corresponding path program 1 times [2021-12-06 22:17:32,661 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:32,662 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2041692368] [2021-12-06 22:17:32,662 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:32,662 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:32,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:32,688 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:32,688 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:32,688 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2041692368] [2021-12-06 22:17:32,688 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2041692368] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:32,688 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:32,688 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:32,689 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [294808435] [2021-12-06 22:17:32,689 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:32,689 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:17:32,689 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:17:32,689 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:17:32,689 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:17:32,690 INFO L87 Difference]: Start difference. First operand 768 states and 1145 transitions. cyclomatic complexity: 378 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:32,702 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:17:32,702 INFO L93 Difference]: Finished difference Result 768 states and 1144 transitions. [2021-12-06 22:17:32,702 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:17:32,703 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 768 states and 1144 transitions. [2021-12-06 22:17:32,706 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2021-12-06 22:17:32,710 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 768 states to 768 states and 1144 transitions. [2021-12-06 22:17:32,711 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2021-12-06 22:17:32,711 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2021-12-06 22:17:32,711 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1144 transitions. [2021-12-06 22:17:32,712 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:17:32,712 INFO L681 BuchiCegarLoop]: Abstraction has 768 states and 1144 transitions. [2021-12-06 22:17:32,713 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1144 transitions. [2021-12-06 22:17:32,720 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2021-12-06 22:17:32,722 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.4895833333333333) internal successors, (1144), 767 states have internal predecessors, (1144), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:32,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1144 transitions. [2021-12-06 22:17:32,724 INFO L704 BuchiCegarLoop]: Abstraction has 768 states and 1144 transitions. [2021-12-06 22:17:32,724 INFO L587 BuchiCegarLoop]: Abstraction has 768 states and 1144 transitions. [2021-12-06 22:17:32,724 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-06 22:17:32,724 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1144 transitions. [2021-12-06 22:17:32,726 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2021-12-06 22:17:32,726 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:17:32,727 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:17:32,728 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:32,728 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:32,728 INFO L791 eck$LassoCheckResult]: Stem: 8497#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 8476#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 8477#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7937#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7938#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 8354#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8355#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8323#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8246#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8247#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8236#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8237#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8196#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8197#L754 assume !(0 == ~M_E~0); 8455#L754-2 assume !(0 == ~T1_E~0); 8139#L759-1 assume !(0 == ~T2_E~0); 8140#L764-1 assume !(0 == ~T3_E~0); 8484#L769-1 assume !(0 == ~T4_E~0); 8485#L774-1 assume !(0 == ~T5_E~0); 8385#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8170#L784-1 assume !(0 == ~T7_E~0); 8171#L789-1 assume !(0 == ~E_1~0); 7850#L794-1 assume !(0 == ~E_2~0); 7851#L799-1 assume !(0 == ~E_3~0); 8486#L804-1 assume !(0 == ~E_4~0); 8487#L809-1 assume !(0 == ~E_5~0); 8250#L814-1 assume !(0 == ~E_6~0); 7768#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 7769#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8232#L361 assume 1 == ~m_pc~0; 8233#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8274#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8055#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8056#L930 assume !(0 != activate_threads_~tmp~1#1); 8380#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8226#L380 assume !(1 == ~t1_pc~0); 7900#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7899#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8405#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8481#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7976#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7901#L399 assume 1 == ~t2_pc~0; 7902#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8108#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8415#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8294#L946 assume !(0 != activate_threads_~tmp___1~0#1); 7806#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7774#L418 assume !(1 == ~t3_pc~0); 7735#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7736#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8254#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8462#L954 assume !(0 != activate_threads_~tmp___2~0#1); 8492#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8457#L437 assume 1 == ~t4_pc~0; 8458#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8077#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7904#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7905#L962 assume !(0 != activate_threads_~tmp___3~0#1); 8333#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8032#L456 assume !(1 == ~t5_pc~0); 8033#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8136#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8436#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7796#L970 assume !(0 != activate_threads_~tmp___4~0#1); 7797#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7920#L475 assume 1 == ~t6_pc~0; 7921#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7996#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7997#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7756#L978 assume !(0 != activate_threads_~tmp___5~0#1); 7757#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8239#L494 assume 1 == ~t7_pc~0; 8240#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8280#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8432#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8433#L986 assume !(0 != activate_threads_~tmp___6~0#1); 8495#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8434#L837 assume !(1 == ~M_E~0); 8297#L837-2 assume !(1 == ~T1_E~0); 7883#L842-1 assume !(1 == ~T2_E~0); 7884#L847-1 assume !(1 == ~T3_E~0); 8350#L852-1 assume !(1 == ~T4_E~0); 8427#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8306#L862-1 assume !(1 == ~T6_E~0); 8307#L867-1 assume !(1 == ~T7_E~0); 8316#L872-1 assume !(1 == ~E_1~0); 8382#L877-1 assume !(1 == ~E_2~0); 8312#L882-1 assume !(1 == ~E_3~0); 8313#L887-1 assume !(1 == ~E_4~0); 7943#L892-1 assume !(1 == ~E_5~0); 7944#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 8330#L902-1 assume !(1 == ~E_7~0); 8024#L907-1 assume { :end_inline_reset_delta_events } true; 8025#L1148-2 [2021-12-06 22:17:32,728 INFO L793 eck$LassoCheckResult]: Loop: 8025#L1148-2 assume !false; 7770#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7771#L729 assume !false; 8167#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8163#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8114#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8183#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8221#L626 assume !(0 != eval_~tmp~0#1); 8222#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8352#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8256#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7809#L754-5 assume !(0 == ~T1_E~0); 7810#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8192#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8360#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8361#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8124#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7785#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7786#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7766#L794-3 assume !(0 == ~E_2~0); 7767#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7862#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8262#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7858#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7859#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8058#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8059#L361-24 assume !(1 == ~m_pc~0); 8097#L361-26 is_master_triggered_~__retres1~0#1 := 0; 8096#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7778#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7779#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8255#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8319#L380-24 assume 1 == ~t1_pc~0; 8320#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7946#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8378#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8251#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7906#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7907#L399-24 assume 1 == ~t2_pc~0; 8119#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8169#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7947#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7948#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8243#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8244#L418-24 assume 1 == ~t3_pc~0; 8248#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7855#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8245#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8123#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7798#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7799#L437-24 assume 1 == ~t4_pc~0; 8070#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8071#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7949#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7950#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8098#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8407#L456-24 assume 1 == ~t5_pc~0; 8408#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8468#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8161#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8162#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8301#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8435#L475-24 assume 1 == ~t6_pc~0; 7800#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7801#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8444#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8445#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 7743#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7744#L494-24 assume 1 == ~t7_pc~0; 8401#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8291#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8188#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8189#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8068#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8069#L837-3 assume !(1 == ~M_E~0); 8151#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8431#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8347#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7787#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7788#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8472#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8464#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8398#L872-3 assume !(1 == ~E_1~0); 8399#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8467#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8482#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8154#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8147#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8148#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8324#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8317#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 7773#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8493#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 8453#L1167 assume !(0 == start_simulation_~tmp~3#1); 8348#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8375#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8180#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8414#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 8447#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8362#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7749#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 7750#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 8025#L1148-2 [2021-12-06 22:17:32,728 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:32,728 INFO L85 PathProgramCache]: Analyzing trace with hash -1148673299, now seen corresponding path program 1 times [2021-12-06 22:17:32,729 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:32,729 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [854812981] [2021-12-06 22:17:32,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:32,729 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:32,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:32,745 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:32,745 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:32,746 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [854812981] [2021-12-06 22:17:32,746 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [854812981] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:32,746 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:32,746 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:32,746 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [339912146] [2021-12-06 22:17:32,746 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:32,746 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:17:32,747 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:32,747 INFO L85 PathProgramCache]: Analyzing trace with hash -1932928152, now seen corresponding path program 1 times [2021-12-06 22:17:32,747 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:32,747 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [289379335] [2021-12-06 22:17:32,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:32,748 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:32,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:32,771 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:32,772 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:32,772 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [289379335] [2021-12-06 22:17:32,772 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [289379335] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:32,772 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:32,772 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:32,772 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [692548927] [2021-12-06 22:17:32,772 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:32,772 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:17:32,773 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:17:32,773 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:17:32,773 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:17:32,773 INFO L87 Difference]: Start difference. First operand 768 states and 1144 transitions. cyclomatic complexity: 377 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:32,785 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:17:32,786 INFO L93 Difference]: Finished difference Result 768 states and 1143 transitions. [2021-12-06 22:17:32,786 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:17:32,786 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 768 states and 1143 transitions. [2021-12-06 22:17:32,790 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2021-12-06 22:17:32,794 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 768 states to 768 states and 1143 transitions. [2021-12-06 22:17:32,794 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2021-12-06 22:17:32,795 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2021-12-06 22:17:32,795 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1143 transitions. [2021-12-06 22:17:32,796 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:17:32,796 INFO L681 BuchiCegarLoop]: Abstraction has 768 states and 1143 transitions. [2021-12-06 22:17:32,797 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1143 transitions. [2021-12-06 22:17:32,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2021-12-06 22:17:32,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.48828125) internal successors, (1143), 767 states have internal predecessors, (1143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:32,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1143 transitions. [2021-12-06 22:17:32,807 INFO L704 BuchiCegarLoop]: Abstraction has 768 states and 1143 transitions. [2021-12-06 22:17:32,807 INFO L587 BuchiCegarLoop]: Abstraction has 768 states and 1143 transitions. [2021-12-06 22:17:32,807 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-06 22:17:32,807 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1143 transitions. [2021-12-06 22:17:32,809 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2021-12-06 22:17:32,810 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:17:32,810 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:17:32,811 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:32,811 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:32,811 INFO L791 eck$LassoCheckResult]: Stem: 10040#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 10018#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 10019#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9480#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9481#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 9897#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9898#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9866#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9786#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9787#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9779#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 9780#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9739#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9740#L754 assume !(0 == ~M_E~0); 9998#L754-2 assume !(0 == ~T1_E~0); 9682#L759-1 assume !(0 == ~T2_E~0); 9683#L764-1 assume !(0 == ~T3_E~0); 10027#L769-1 assume !(0 == ~T4_E~0); 10028#L774-1 assume !(0 == ~T5_E~0); 9926#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9713#L784-1 assume !(0 == ~T7_E~0); 9714#L789-1 assume !(0 == ~E_1~0); 9389#L794-1 assume !(0 == ~E_2~0); 9390#L799-1 assume !(0 == ~E_3~0); 10029#L804-1 assume !(0 == ~E_4~0); 10030#L809-1 assume !(0 == ~E_5~0); 9791#L814-1 assume !(0 == ~E_6~0); 9309#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 9310#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9775#L361 assume 1 == ~m_pc~0; 9776#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9817#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9598#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9599#L930 assume !(0 != activate_threads_~tmp~1#1); 9923#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9769#L380 assume !(1 == ~t1_pc~0); 9443#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9442#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9946#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10023#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9519#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9444#L399 assume 1 == ~t2_pc~0; 9445#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9651#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9958#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9837#L946 assume !(0 != activate_threads_~tmp___1~0#1); 9349#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9317#L418 assume !(1 == ~t3_pc~0); 9278#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9279#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9797#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10005#L954 assume !(0 != activate_threads_~tmp___2~0#1); 10035#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9999#L437 assume 1 == ~t4_pc~0; 10000#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9619#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9447#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9448#L962 assume !(0 != activate_threads_~tmp___3~0#1); 9876#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9570#L456 assume !(1 == ~t5_pc~0); 9571#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9679#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9979#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9336#L970 assume !(0 != activate_threads_~tmp___4~0#1); 9337#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9460#L475 assume 1 == ~t6_pc~0; 9461#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9539#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9540#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9299#L978 assume !(0 != activate_threads_~tmp___5~0#1); 9300#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9782#L494 assume 1 == ~t7_pc~0; 9783#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9823#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9973#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9974#L986 assume !(0 != activate_threads_~tmp___6~0#1); 10038#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9975#L837 assume !(1 == ~M_E~0); 9840#L837-2 assume !(1 == ~T1_E~0); 9426#L842-1 assume !(1 == ~T2_E~0); 9427#L847-1 assume !(1 == ~T3_E~0); 9893#L852-1 assume !(1 == ~T4_E~0); 9968#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9848#L862-1 assume !(1 == ~T6_E~0); 9849#L867-1 assume !(1 == ~T7_E~0); 9857#L872-1 assume !(1 == ~E_1~0); 9925#L877-1 assume !(1 == ~E_2~0); 9855#L882-1 assume !(1 == ~E_3~0); 9856#L887-1 assume !(1 == ~E_4~0); 9486#L892-1 assume !(1 == ~E_5~0); 9487#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 9871#L902-1 assume !(1 == ~E_7~0); 9567#L907-1 assume { :end_inline_reset_delta_events } true; 9568#L1148-2 [2021-12-06 22:17:32,811 INFO L793 eck$LassoCheckResult]: Loop: 9568#L1148-2 assume !false; 9311#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9312#L729 assume !false; 9710#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9706#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 9657#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 9726#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9763#L626 assume !(0 != eval_~tmp~0#1); 9764#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9894#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9799#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9350#L754-5 assume !(0 == ~T1_E~0); 9351#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9735#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9903#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9904#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9662#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9328#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9329#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9313#L794-3 assume !(0 == ~E_2~0); 9314#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9408#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9805#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9403#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9404#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9601#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9602#L361-24 assume 1 == ~m_pc~0; 9638#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9639#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9321#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9322#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9798#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9862#L380-24 assume !(1 == ~t1_pc~0); 9488#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 9489#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9921#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9794#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9449#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9450#L399-24 assume !(1 == ~t2_pc~0); 9664#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 9712#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9490#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9491#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9788#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9789#L418-24 assume 1 == ~t3_pc~0; 9792#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9398#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9790#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9667#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9341#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9342#L437-24 assume 1 == ~t4_pc~0; 9613#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9614#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9492#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9493#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9641#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9950#L456-24 assume !(1 == ~t5_pc~0); 9952#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 10011#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9704#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9705#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9846#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9978#L475-24 assume !(1 == ~t6_pc~0); 9345#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 9344#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9987#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9988#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 9286#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9287#L494-24 assume 1 == ~t7_pc~0; 9944#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9835#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9731#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9732#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9611#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9612#L837-3 assume !(1 == ~M_E~0); 9694#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9977#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9891#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9330#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9331#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10015#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10007#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9942#L872-3 assume !(1 == ~E_1~0); 9943#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10010#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10025#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9699#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9692#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9693#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9867#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9860#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 9316#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10036#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 9996#L1167 assume !(0 == start_simulation_~tmp~3#1); 9890#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9918#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 9724#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 9957#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 9990#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9905#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9292#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 9293#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 9568#L1148-2 [2021-12-06 22:17:32,811 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:32,816 INFO L85 PathProgramCache]: Analyzing trace with hash 1821437803, now seen corresponding path program 1 times [2021-12-06 22:17:32,816 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:32,816 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1714997144] [2021-12-06 22:17:32,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:32,816 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:32,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:32,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:32,836 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:32,836 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1714997144] [2021-12-06 22:17:32,836 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1714997144] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:32,837 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:32,837 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:32,837 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [280806282] [2021-12-06 22:17:32,837 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:32,837 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:17:32,838 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:32,838 INFO L85 PathProgramCache]: Analyzing trace with hash -1308384443, now seen corresponding path program 1 times [2021-12-06 22:17:32,838 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:32,838 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [824381773] [2021-12-06 22:17:32,838 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:32,838 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:32,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:32,863 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:32,863 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:32,863 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [824381773] [2021-12-06 22:17:32,864 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [824381773] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:32,864 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:32,864 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:32,864 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [653456623] [2021-12-06 22:17:32,864 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:32,864 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:17:32,864 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:17:32,865 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:17:32,865 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:17:32,865 INFO L87 Difference]: Start difference. First operand 768 states and 1143 transitions. cyclomatic complexity: 376 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:32,877 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:17:32,877 INFO L93 Difference]: Finished difference Result 768 states and 1142 transitions. [2021-12-06 22:17:32,877 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:17:32,878 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 768 states and 1142 transitions. [2021-12-06 22:17:32,881 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2021-12-06 22:17:32,885 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 768 states to 768 states and 1142 transitions. [2021-12-06 22:17:32,885 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2021-12-06 22:17:32,886 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2021-12-06 22:17:32,886 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1142 transitions. [2021-12-06 22:17:32,887 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:17:32,887 INFO L681 BuchiCegarLoop]: Abstraction has 768 states and 1142 transitions. [2021-12-06 22:17:32,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1142 transitions. [2021-12-06 22:17:32,894 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2021-12-06 22:17:32,896 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.4869791666666667) internal successors, (1142), 767 states have internal predecessors, (1142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:32,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1142 transitions. [2021-12-06 22:17:32,897 INFO L704 BuchiCegarLoop]: Abstraction has 768 states and 1142 transitions. [2021-12-06 22:17:32,898 INFO L587 BuchiCegarLoop]: Abstraction has 768 states and 1142 transitions. [2021-12-06 22:17:32,898 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-06 22:17:32,898 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1142 transitions. [2021-12-06 22:17:32,900 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2021-12-06 22:17:32,900 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:17:32,900 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:17:32,901 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:32,901 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:32,902 INFO L791 eck$LassoCheckResult]: Stem: 11583#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 11562#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 11563#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11023#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11024#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 11440#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11441#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11409#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11332#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11333#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11322#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11323#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 11282#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11283#L754 assume !(0 == ~M_E~0); 11541#L754-2 assume !(0 == ~T1_E~0); 11225#L759-1 assume !(0 == ~T2_E~0); 11226#L764-1 assume !(0 == ~T3_E~0); 11570#L769-1 assume !(0 == ~T4_E~0); 11571#L774-1 assume !(0 == ~T5_E~0); 11471#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11256#L784-1 assume !(0 == ~T7_E~0); 11257#L789-1 assume !(0 == ~E_1~0); 10936#L794-1 assume !(0 == ~E_2~0); 10937#L799-1 assume !(0 == ~E_3~0); 11572#L804-1 assume !(0 == ~E_4~0); 11573#L809-1 assume !(0 == ~E_5~0); 11336#L814-1 assume !(0 == ~E_6~0); 10854#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 10855#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11318#L361 assume 1 == ~m_pc~0; 11319#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11360#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11141#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11142#L930 assume !(0 != activate_threads_~tmp~1#1); 11466#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11312#L380 assume !(1 == ~t1_pc~0); 10986#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10985#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11491#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11567#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11062#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10987#L399 assume 1 == ~t2_pc~0; 10988#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11194#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11501#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11380#L946 assume !(0 != activate_threads_~tmp___1~0#1); 10892#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10860#L418 assume !(1 == ~t3_pc~0); 10821#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10822#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11340#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11548#L954 assume !(0 != activate_threads_~tmp___2~0#1); 11578#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11543#L437 assume 1 == ~t4_pc~0; 11544#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11163#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10990#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10991#L962 assume !(0 != activate_threads_~tmp___3~0#1); 11419#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11118#L456 assume !(1 == ~t5_pc~0); 11119#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11222#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11522#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10882#L970 assume !(0 != activate_threads_~tmp___4~0#1); 10883#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11006#L475 assume 1 == ~t6_pc~0; 11007#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11082#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11083#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10842#L978 assume !(0 != activate_threads_~tmp___5~0#1); 10843#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11325#L494 assume 1 == ~t7_pc~0; 11326#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11366#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11518#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11519#L986 assume !(0 != activate_threads_~tmp___6~0#1); 11581#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11520#L837 assume !(1 == ~M_E~0); 11383#L837-2 assume !(1 == ~T1_E~0); 10969#L842-1 assume !(1 == ~T2_E~0); 10970#L847-1 assume !(1 == ~T3_E~0); 11436#L852-1 assume !(1 == ~T4_E~0); 11513#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11392#L862-1 assume !(1 == ~T6_E~0); 11393#L867-1 assume !(1 == ~T7_E~0); 11402#L872-1 assume !(1 == ~E_1~0); 11468#L877-1 assume !(1 == ~E_2~0); 11398#L882-1 assume !(1 == ~E_3~0); 11399#L887-1 assume !(1 == ~E_4~0); 11029#L892-1 assume !(1 == ~E_5~0); 11030#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 11416#L902-1 assume !(1 == ~E_7~0); 11111#L907-1 assume { :end_inline_reset_delta_events } true; 11112#L1148-2 [2021-12-06 22:17:32,902 INFO L793 eck$LassoCheckResult]: Loop: 11112#L1148-2 assume !false; 10856#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10857#L729 assume !false; 11253#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11249#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11200#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11269#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11307#L626 assume !(0 != eval_~tmp~0#1); 11308#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11438#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11342#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10895#L754-5 assume !(0 == ~T1_E~0); 10896#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11278#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11446#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11447#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11210#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10871#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10872#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10852#L794-3 assume !(0 == ~E_2~0); 10853#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10948#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11348#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10946#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10947#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11144#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11145#L361-24 assume 1 == ~m_pc~0; 11181#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11182#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10864#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10865#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11341#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11405#L380-24 assume !(1 == ~t1_pc~0); 11031#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 11032#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11464#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11337#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10992#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10993#L399-24 assume 1 == ~t2_pc~0; 11205#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11255#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11033#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11034#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11329#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11330#L418-24 assume 1 == ~t3_pc~0; 11334#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10941#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11331#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11209#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10884#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10885#L437-24 assume 1 == ~t4_pc~0; 11156#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11157#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11035#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11036#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11184#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11493#L456-24 assume 1 == ~t5_pc~0; 11494#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11554#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11247#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11248#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11387#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11521#L475-24 assume 1 == ~t6_pc~0; 10886#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10887#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11530#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11531#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 10829#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10830#L494-24 assume !(1 == ~t7_pc~0); 11397#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 11377#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11274#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11275#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11154#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11155#L837-3 assume !(1 == ~M_E~0); 11237#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11517#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11433#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10873#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10874#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11558#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11550#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11484#L872-3 assume !(1 == ~E_1~0); 11485#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11553#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11568#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11240#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11233#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11234#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11410#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11403#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10859#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11579#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 11539#L1167 assume !(0 == start_simulation_~tmp~3#1); 11434#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11461#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11266#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11500#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 11533#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11448#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10835#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 10836#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 11112#L1148-2 [2021-12-06 22:17:32,902 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:32,902 INFO L85 PathProgramCache]: Analyzing trace with hash 254679853, now seen corresponding path program 1 times [2021-12-06 22:17:32,902 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:32,903 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1702929961] [2021-12-06 22:17:32,903 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:32,903 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:32,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:32,930 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:32,931 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:32,931 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1702929961] [2021-12-06 22:17:32,931 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1702929961] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:32,931 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:32,931 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:32,931 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2119156434] [2021-12-06 22:17:32,931 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:32,932 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:17:32,932 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:32,932 INFO L85 PathProgramCache]: Analyzing trace with hash 1561027463, now seen corresponding path program 2 times [2021-12-06 22:17:32,932 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:32,933 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1973771901] [2021-12-06 22:17:32,933 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:32,933 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:32,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:32,957 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:32,957 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:32,957 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1973771901] [2021-12-06 22:17:32,957 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1973771901] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:32,957 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:32,958 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:32,958 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [785923706] [2021-12-06 22:17:32,958 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:32,958 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:17:32,958 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:17:32,959 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 22:17:32,959 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 22:17:32,959 INFO L87 Difference]: Start difference. First operand 768 states and 1142 transitions. cyclomatic complexity: 375 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:33,022 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:17:33,022 INFO L93 Difference]: Finished difference Result 1449 states and 2150 transitions. [2021-12-06 22:17:33,022 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 22:17:33,023 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1449 states and 2150 transitions. [2021-12-06 22:17:33,030 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1334 [2021-12-06 22:17:33,037 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1449 states to 1449 states and 2150 transitions. [2021-12-06 22:17:33,038 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1449 [2021-12-06 22:17:33,039 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1449 [2021-12-06 22:17:33,039 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1449 states and 2150 transitions. [2021-12-06 22:17:33,040 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:17:33,040 INFO L681 BuchiCegarLoop]: Abstraction has 1449 states and 2150 transitions. [2021-12-06 22:17:33,042 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1449 states and 2150 transitions. [2021-12-06 22:17:33,059 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1449 to 1449. [2021-12-06 22:17:33,061 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1449 states, 1449 states have (on average 1.4837819185645273) internal successors, (2150), 1448 states have internal predecessors, (2150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:33,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1449 states to 1449 states and 2150 transitions. [2021-12-06 22:17:33,065 INFO L704 BuchiCegarLoop]: Abstraction has 1449 states and 2150 transitions. [2021-12-06 22:17:33,065 INFO L587 BuchiCegarLoop]: Abstraction has 1449 states and 2150 transitions. [2021-12-06 22:17:33,065 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-06 22:17:33,065 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1449 states and 2150 transitions. [2021-12-06 22:17:33,078 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1334 [2021-12-06 22:17:33,078 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:17:33,078 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:17:33,080 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:33,080 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:33,081 INFO L791 eck$LassoCheckResult]: Stem: 13850#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 13822#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 13823#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13250#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13251#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 13686#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13687#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13653#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13571#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13572#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13561#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13562#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 13517#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13518#L754 assume !(0 == ~M_E~0); 13799#L754-2 assume !(0 == ~T1_E~0); 13456#L759-1 assume !(0 == ~T2_E~0); 13457#L764-1 assume !(0 == ~T3_E~0); 13831#L769-1 assume !(0 == ~T4_E~0); 13832#L774-1 assume !(0 == ~T5_E~0); 13719#L779-1 assume !(0 == ~T6_E~0); 13487#L784-1 assume !(0 == ~T7_E~0); 13488#L789-1 assume !(0 == ~E_1~0); 13163#L794-1 assume !(0 == ~E_2~0); 13164#L799-1 assume !(0 == ~E_3~0); 13835#L804-1 assume !(0 == ~E_4~0); 13836#L809-1 assume !(0 == ~E_5~0); 13575#L814-1 assume !(0 == ~E_6~0); 13079#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 13080#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13557#L361 assume 1 == ~m_pc~0; 13558#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13601#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13370#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13371#L930 assume !(0 != activate_threads_~tmp~1#1); 13714#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13550#L380 assume !(1 == ~t1_pc~0); 13213#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13212#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13739#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13827#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13290#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13214#L399 assume 1 == ~t2_pc~0; 13215#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13424#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13749#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13622#L946 assume !(0 != activate_threads_~tmp___1~0#1); 13119#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13087#L418 assume !(1 == ~t3_pc~0); 13048#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13049#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13579#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13807#L954 assume !(0 != activate_threads_~tmp___2~0#1); 13841#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13800#L437 assume 1 == ~t4_pc~0; 13801#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13391#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13217#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13218#L962 assume !(0 != activate_threads_~tmp___3~0#1); 13664#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13347#L456 assume !(1 == ~t5_pc~0); 13348#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13453#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13775#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13109#L970 assume !(0 != activate_threads_~tmp___4~0#1); 13110#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13233#L475 assume 1 == ~t6_pc~0; 13234#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13310#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13311#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13069#L978 assume !(0 != activate_threads_~tmp___5~0#1); 13070#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13564#L494 assume 1 == ~t7_pc~0; 13565#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13607#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13771#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13772#L986 assume !(0 != activate_threads_~tmp___6~0#1); 13846#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13773#L837 assume !(1 == ~M_E~0); 13625#L837-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13196#L842-1 assume !(1 == ~T2_E~0); 13197#L847-1 assume !(1 == ~T3_E~0); 13681#L852-1 assume !(1 == ~T4_E~0); 13766#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13636#L862-1 assume !(1 == ~T6_E~0); 13637#L867-1 assume !(1 == ~T7_E~0); 13646#L872-1 assume !(1 == ~E_1~0); 13716#L877-1 assume !(1 == ~E_2~0); 13642#L882-1 assume !(1 == ~E_3~0); 13643#L887-1 assume !(1 == ~E_4~0); 13256#L892-1 assume !(1 == ~E_5~0); 13257#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 13659#L902-1 assume !(1 == ~E_7~0); 13339#L907-1 assume { :end_inline_reset_delta_events } true; 13340#L1148-2 [2021-12-06 22:17:33,081 INFO L793 eck$LassoCheckResult]: Loop: 13340#L1148-2 assume !false; 13707#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13865#L729 assume !false; 13864#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 13860#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 13500#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 13501#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13543#L626 assume !(0 != eval_~tmp~0#1); 13544#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13683#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13684#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13851#L754-5 assume !(0 == ~T1_E~0); 13511#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13512#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13692#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13693#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13441#L779-3 assume !(0 == ~T6_E~0); 13098#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13099#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13083#L794-3 assume !(0 == ~E_2~0); 13084#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13178#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13587#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13173#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13174#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13376#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13377#L361-24 assume 1 == ~m_pc~0; 13410#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13411#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13091#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13092#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13580#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13649#L380-24 assume 1 == ~t1_pc~0; 13652#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13259#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13712#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13576#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13221#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13222#L399-24 assume 1 == ~t2_pc~0; 13436#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13486#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13260#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13261#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13568#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13569#L418-24 assume 1 == ~t3_pc~0; 13573#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13168#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13570#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13440#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13111#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13112#L437-24 assume 1 == ~t4_pc~0; 13385#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13386#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13262#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13263#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13413#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13741#L456-24 assume 1 == ~t5_pc~0; 13742#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13814#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13478#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13479#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13630#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13774#L475-24 assume 1 == ~t6_pc~0; 13113#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13114#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13785#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13786#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 13054#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13055#L494-24 assume 1 == ~t7_pc~0; 13735#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13618#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13507#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13508#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13383#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13384#L837-3 assume !(1 == ~M_E~0); 13468#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13770#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13678#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13100#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13101#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13818#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13808#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13732#L872-3 assume !(1 == ~E_1~0); 13733#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13813#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13829#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13471#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13464#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13465#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13654#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 13647#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 13086#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 13842#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 13796#L1167 assume !(0 == start_simulation_~tmp~3#1); 13679#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 13709#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 13496#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 13748#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 13788#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13694#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13062#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 13063#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 13340#L1148-2 [2021-12-06 22:17:33,081 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:33,082 INFO L85 PathProgramCache]: Analyzing trace with hash -1873200919, now seen corresponding path program 1 times [2021-12-06 22:17:33,082 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:33,082 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1993389054] [2021-12-06 22:17:33,082 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:33,082 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:33,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:33,115 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:33,115 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:33,115 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1993389054] [2021-12-06 22:17:33,115 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1993389054] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:33,115 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:33,116 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 22:17:33,116 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1412840497] [2021-12-06 22:17:33,116 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:33,116 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:17:33,117 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:33,117 INFO L85 PathProgramCache]: Analyzing trace with hash 324346503, now seen corresponding path program 1 times [2021-12-06 22:17:33,117 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:33,117 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [525366259] [2021-12-06 22:17:33,117 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:33,117 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:33,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:33,151 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:33,151 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:33,151 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [525366259] [2021-12-06 22:17:33,151 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [525366259] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:33,152 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:33,152 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:33,152 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1283561204] [2021-12-06 22:17:33,152 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:33,152 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:17:33,152 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:17:33,153 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:17:33,153 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:17:33,153 INFO L87 Difference]: Start difference. First operand 1449 states and 2150 transitions. cyclomatic complexity: 703 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:33,191 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:17:33,191 INFO L93 Difference]: Finished difference Result 1449 states and 2124 transitions. [2021-12-06 22:17:33,191 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:17:33,192 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1449 states and 2124 transitions. [2021-12-06 22:17:33,199 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1334 [2021-12-06 22:17:33,207 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1449 states to 1449 states and 2124 transitions. [2021-12-06 22:17:33,208 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1449 [2021-12-06 22:17:33,209 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1449 [2021-12-06 22:17:33,209 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1449 states and 2124 transitions. [2021-12-06 22:17:33,210 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:17:33,211 INFO L681 BuchiCegarLoop]: Abstraction has 1449 states and 2124 transitions. [2021-12-06 22:17:33,212 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1449 states and 2124 transitions. [2021-12-06 22:17:33,230 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1449 to 1449. [2021-12-06 22:17:33,233 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1449 states, 1449 states have (on average 1.4658385093167703) internal successors, (2124), 1448 states have internal predecessors, (2124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:33,236 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1449 states to 1449 states and 2124 transitions. [2021-12-06 22:17:33,236 INFO L704 BuchiCegarLoop]: Abstraction has 1449 states and 2124 transitions. [2021-12-06 22:17:33,236 INFO L587 BuchiCegarLoop]: Abstraction has 1449 states and 2124 transitions. [2021-12-06 22:17:33,236 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-06 22:17:33,237 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1449 states and 2124 transitions. [2021-12-06 22:17:33,242 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1334 [2021-12-06 22:17:33,242 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:17:33,242 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:17:33,243 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:33,243 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:33,243 INFO L791 eck$LassoCheckResult]: Stem: 16760#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 16726#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 16727#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16155#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16156#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 16585#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16586#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16552#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16467#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16468#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16459#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16460#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16418#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16419#L754 assume !(0 == ~M_E~0); 16699#L754-2 assume !(0 == ~T1_E~0); 16357#L759-1 assume !(0 == ~T2_E~0); 16358#L764-1 assume !(0 == ~T3_E~0); 16736#L769-1 assume !(0 == ~T4_E~0); 16737#L774-1 assume !(0 == ~T5_E~0); 16618#L779-1 assume !(0 == ~T6_E~0); 16389#L784-1 assume !(0 == ~T7_E~0); 16390#L789-1 assume !(0 == ~E_1~0); 16064#L794-1 assume !(0 == ~E_2~0); 16065#L799-1 assume !(0 == ~E_3~0); 16740#L804-1 assume !(0 == ~E_4~0); 16741#L809-1 assume !(0 == ~E_5~0); 16472#L814-1 assume !(0 == ~E_6~0); 15984#L819-1 assume !(0 == ~E_7~0); 15985#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16455#L361 assume 1 == ~m_pc~0; 16456#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16500#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16273#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16274#L930 assume !(0 != activate_threads_~tmp~1#1); 16614#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16449#L380 assume !(1 == ~t1_pc~0); 16119#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16118#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16638#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16732#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16194#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16120#L399 assume 1 == ~t2_pc~0; 16121#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16326#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16651#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16521#L946 assume !(0 != activate_threads_~tmp___1~0#1); 16024#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15992#L418 assume !(1 == ~t3_pc~0); 15953#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15954#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16476#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16708#L954 assume !(0 != activate_threads_~tmp___2~0#1); 16749#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16700#L437 assume 1 == ~t4_pc~0; 16701#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16294#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16123#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16124#L962 assume !(0 != activate_threads_~tmp___3~0#1); 16563#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16245#L456 assume !(1 == ~t5_pc~0); 16246#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 16354#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16675#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16011#L970 assume !(0 != activate_threads_~tmp___4~0#1); 16012#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16136#L475 assume 1 == ~t6_pc~0; 16137#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16214#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16215#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15974#L978 assume !(0 != activate_threads_~tmp___5~0#1); 15975#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16462#L494 assume !(1 == ~t7_pc~0); 16464#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 16506#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16668#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16669#L986 assume !(0 != activate_threads_~tmp___6~0#1); 16757#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16670#L837 assume !(1 == ~M_E~0); 16524#L837-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16525#L842-1 assume !(1 == ~T2_E~0); 16803#L847-1 assume !(1 == ~T3_E~0); 16801#L852-1 assume !(1 == ~T4_E~0); 16800#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16799#L862-1 assume !(1 == ~T6_E~0); 16534#L867-1 assume !(1 == ~T7_E~0); 16616#L872-1 assume !(1 == ~E_1~0); 16617#L877-1 assume !(1 == ~E_2~0); 16541#L882-1 assume !(1 == ~E_3~0); 16542#L887-1 assume !(1 == ~E_4~0); 16161#L892-1 assume !(1 == ~E_5~0); 16162#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 16660#L902-1 assume !(1 == ~E_7~0); 16242#L907-1 assume { :end_inline_reset_delta_events } true; 16243#L1148-2 [2021-12-06 22:17:33,243 INFO L793 eck$LassoCheckResult]: Loop: 16243#L1148-2 assume !false; 16778#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16777#L729 assume !false; 16776#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 16772#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 16402#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 16403#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16443#L626 assume !(0 != eval_~tmp~0#1); 16444#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16582#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16583#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16762#L754-5 assume !(0 == ~T1_E~0); 16412#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16413#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17342#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17341#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16337#L779-3 assume !(0 == ~T6_E~0); 16001#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16002#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17090#L794-3 assume !(0 == ~E_2~0); 17089#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17088#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17087#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17086#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17085#L819-3 assume !(0 == ~E_7~0); 17084#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17083#L361-24 assume 1 == ~m_pc~0; 17081#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17080#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17079#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17078#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17077#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17076#L380-24 assume !(1 == ~t1_pc~0); 17074#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 17073#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17072#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17071#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17070#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17069#L399-24 assume 1 == ~t2_pc~0; 17067#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17066#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17065#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 17064#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17063#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17062#L418-24 assume !(1 == ~t3_pc~0); 17060#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 17059#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17058#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17057#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17056#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17055#L437-24 assume 1 == ~t4_pc~0; 17053#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17052#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17051#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17050#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17049#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17048#L456-24 assume !(1 == ~t5_pc~0); 17046#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 17045#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17044#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17043#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17042#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17041#L475-24 assume !(1 == ~t6_pc~0); 17040#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 17038#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17037#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17036#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 17035#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17034#L494-24 assume !(1 == ~t7_pc~0); 17032#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 17031#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17030#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17029#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17028#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17027#L837-3 assume !(1 == ~M_E~0); 17026#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16673#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17025#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17024#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17023#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17022#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16746#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17021#L872-3 assume !(1 == ~E_1~0); 17020#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17019#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17018#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17010#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17009#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 17005#L902-3 assume !(1 == ~E_7~0); 17004#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 16964#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 16956#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 16955#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 16951#L1167 assume !(0 == start_simulation_~tmp~3#1); 16948#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 16872#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 16649#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 16650#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 16687#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16718#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16788#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 16417#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 16243#L1148-2 [2021-12-06 22:17:33,244 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:33,244 INFO L85 PathProgramCache]: Analyzing trace with hash 1576412294, now seen corresponding path program 1 times [2021-12-06 22:17:33,244 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:33,244 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [18426760] [2021-12-06 22:17:33,244 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:33,244 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:33,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:33,261 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:33,261 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:33,261 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [18426760] [2021-12-06 22:17:33,261 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [18426760] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:33,261 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:33,261 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 22:17:33,261 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [333793661] [2021-12-06 22:17:33,262 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:33,262 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:17:33,262 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:33,262 INFO L85 PathProgramCache]: Analyzing trace with hash 1675675422, now seen corresponding path program 1 times [2021-12-06 22:17:33,262 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:33,262 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [21840419] [2021-12-06 22:17:33,262 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:33,262 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:33,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:33,283 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:33,283 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:33,283 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [21840419] [2021-12-06 22:17:33,283 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [21840419] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:33,283 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:33,283 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:33,284 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1328029721] [2021-12-06 22:17:33,284 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:33,284 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:17:33,284 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:17:33,284 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:17:33,284 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:17:33,284 INFO L87 Difference]: Start difference. First operand 1449 states and 2124 transitions. cyclomatic complexity: 677 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:33,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:17:33,338 INFO L93 Difference]: Finished difference Result 2760 states and 4006 transitions. [2021-12-06 22:17:33,338 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:17:33,338 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2760 states and 4006 transitions. [2021-12-06 22:17:33,350 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2644 [2021-12-06 22:17:33,365 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2760 states to 2760 states and 4006 transitions. [2021-12-06 22:17:33,365 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2760 [2021-12-06 22:17:33,367 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2760 [2021-12-06 22:17:33,367 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2760 states and 4006 transitions. [2021-12-06 22:17:33,370 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:17:33,370 INFO L681 BuchiCegarLoop]: Abstraction has 2760 states and 4006 transitions. [2021-12-06 22:17:33,373 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2760 states and 4006 transitions. [2021-12-06 22:17:33,416 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2760 to 2646. [2021-12-06 22:17:33,420 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2646 states, 2646 states have (on average 1.4550264550264551) internal successors, (3850), 2645 states have internal predecessors, (3850), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:33,426 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2646 states to 2646 states and 3850 transitions. [2021-12-06 22:17:33,427 INFO L704 BuchiCegarLoop]: Abstraction has 2646 states and 3850 transitions. [2021-12-06 22:17:33,427 INFO L587 BuchiCegarLoop]: Abstraction has 2646 states and 3850 transitions. [2021-12-06 22:17:33,427 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-06 22:17:33,427 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2646 states and 3850 transitions. [2021-12-06 22:17:33,433 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2530 [2021-12-06 22:17:33,434 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:17:33,434 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:17:33,435 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:33,435 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:33,435 INFO L791 eck$LassoCheckResult]: Stem: 21015#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 20971#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 20972#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20373#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20374#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 20819#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20820#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20783#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20693#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20694#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20685#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20686#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 20641#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20642#L754 assume !(0 == ~M_E~0); 20942#L754-2 assume !(0 == ~T1_E~0); 20578#L759-1 assume !(0 == ~T2_E~0); 20579#L764-1 assume !(0 == ~T3_E~0); 20986#L769-1 assume !(0 == ~T4_E~0); 20987#L774-1 assume !(0 == ~T5_E~0); 20854#L779-1 assume !(0 == ~T6_E~0); 20611#L784-1 assume !(0 == ~T7_E~0); 20612#L789-1 assume !(0 == ~E_1~0); 20281#L794-1 assume !(0 == ~E_2~0); 20282#L799-1 assume !(0 == ~E_3~0); 20989#L804-1 assume !(0 == ~E_4~0); 20990#L809-1 assume !(0 == ~E_5~0); 20698#L814-1 assume !(0 == ~E_6~0); 20200#L819-1 assume !(0 == ~E_7~0); 20201#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20682#L361 assume !(1 == ~m_pc~0); 20683#L361-2 is_master_triggered_~__retres1~0#1 := 0; 20726#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20494#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 20495#L930 assume !(0 != activate_threads_~tmp~1#1); 20851#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20675#L380 assume !(1 == ~t1_pc~0); 20337#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20336#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20875#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20980#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20413#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20338#L399 assume 1 == ~t2_pc~0; 20339#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20548#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20888#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20750#L946 assume !(0 != activate_threads_~tmp___1~0#1); 20240#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20208#L418 assume !(1 == ~t3_pc~0); 20169#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 20170#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20702#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20955#L954 assume !(0 != activate_threads_~tmp___2~0#1); 21002#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20944#L437 assume 1 == ~t4_pc~0; 20945#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20515#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20341#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20342#L962 assume !(0 != activate_threads_~tmp___3~0#1); 20794#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20466#L456 assume !(1 == ~t5_pc~0); 20467#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 20575#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20916#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20227#L970 assume !(0 != activate_threads_~tmp___4~0#1); 20228#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20354#L475 assume 1 == ~t6_pc~0; 20355#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20434#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20435#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20190#L978 assume !(0 != activate_threads_~tmp___5~0#1); 20191#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20689#L494 assume !(1 == ~t7_pc~0); 20691#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 20735#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20909#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20910#L986 assume !(0 != activate_threads_~tmp___6~0#1); 21011#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20911#L837 assume !(1 == ~M_E~0); 20753#L837-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20320#L842-1 assume !(1 == ~T2_E~0); 20321#L847-1 assume !(1 == ~T3_E~0); 20815#L852-1 assume !(1 == ~T4_E~0); 20904#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20763#L862-1 assume !(1 == ~T6_E~0); 20764#L867-1 assume !(1 == ~T7_E~0); 20774#L872-1 assume !(1 == ~E_1~0); 20853#L877-1 assume !(1 == ~E_2~0); 20772#L882-1 assume !(1 == ~E_3~0); 20773#L887-1 assume !(1 == ~E_4~0); 20380#L892-1 assume !(1 == ~E_5~0); 20381#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 20787#L902-1 assume !(1 == ~E_7~0); 20788#L907-1 assume { :end_inline_reset_delta_events } true; 21215#L1148-2 [2021-12-06 22:17:33,435 INFO L793 eck$LassoCheckResult]: Loop: 21215#L1148-2 assume !false; 21216#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21203#L729 assume !false; 21204#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 21116#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 21112#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 21095#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 21096#L626 assume !(0 != eval_~tmp~0#1); 22121#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22120#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22119#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22118#L754-5 assume !(0 == ~T1_E~0); 20635#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20636#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20826#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20827#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20559#L779-3 assume !(0 == ~T6_E~0); 20217#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20218#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20204#L794-3 assume !(0 == ~E_2~0); 20205#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21416#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 21413#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 21411#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21409#L819-3 assume !(0 == ~E_7~0); 21407#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21405#L361-24 assume !(1 == ~m_pc~0); 21403#L361-26 is_master_triggered_~__retres1~0#1 := 0; 21400#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21397#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21395#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21393#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21391#L380-24 assume !(1 == ~t1_pc~0); 21388#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 21384#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21382#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 21380#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21377#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21375#L399-24 assume 1 == ~t2_pc~0; 21372#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21369#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21367#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 21365#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21362#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21360#L418-24 assume !(1 == ~t3_pc~0); 21357#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 21354#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21352#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21350#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21348#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21346#L437-24 assume 1 == ~t4_pc~0; 21342#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21340#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21337#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21335#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21333#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21331#L456-24 assume !(1 == ~t5_pc~0); 21328#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 21326#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21323#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21321#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21319#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21317#L475-24 assume 1 == ~t6_pc~0; 21313#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21310#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21308#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21306#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 21304#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21302#L494-24 assume !(1 == ~t7_pc~0); 21299#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 21296#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21294#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21292#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21290#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21288#L837-3 assume !(1 == ~M_E~0); 21285#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21283#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21281#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21279#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21277#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21275#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21273#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21271#L872-3 assume !(1 == ~E_1~0); 21269#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21267#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21265#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21263#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21261#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21259#L902-3 assume !(1 == ~E_7~0); 21257#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 21251#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 21243#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 21241#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 21239#L1167 assume !(0 == start_simulation_~tmp~3#1); 21236#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 21237#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 22157#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 22156#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 22155#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21223#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21221#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 21222#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 21215#L1148-2 [2021-12-06 22:17:33,435 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:33,435 INFO L85 PathProgramCache]: Analyzing trace with hash -2013636315, now seen corresponding path program 1 times [2021-12-06 22:17:33,435 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:33,436 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1010746040] [2021-12-06 22:17:33,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:33,436 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:33,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:33,463 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:33,464 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:33,464 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1010746040] [2021-12-06 22:17:33,464 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1010746040] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:33,464 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:33,464 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 22:17:33,464 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1324229808] [2021-12-06 22:17:33,464 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:33,464 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:17:33,464 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:33,465 INFO L85 PathProgramCache]: Analyzing trace with hash 1354802078, now seen corresponding path program 1 times [2021-12-06 22:17:33,465 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:33,465 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [578017126] [2021-12-06 22:17:33,465 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:33,465 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:33,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:33,486 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:33,486 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:33,486 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [578017126] [2021-12-06 22:17:33,486 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [578017126] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:33,486 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:33,486 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:33,486 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1473548309] [2021-12-06 22:17:33,486 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:33,487 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:17:33,487 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:17:33,487 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-06 22:17:33,487 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-06 22:17:33,487 INFO L87 Difference]: Start difference. First operand 2646 states and 3850 transitions. cyclomatic complexity: 1208 Second operand has 5 states, 5 states have (on average 18.6) internal successors, (93), 5 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:33,653 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:17:33,653 INFO L93 Difference]: Finished difference Result 7329 states and 10633 transitions. [2021-12-06 22:17:33,654 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-06 22:17:33,654 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7329 states and 10633 transitions. [2021-12-06 22:17:33,682 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7060 [2021-12-06 22:17:33,721 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7329 states to 7329 states and 10633 transitions. [2021-12-06 22:17:33,721 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7329 [2021-12-06 22:17:33,726 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7329 [2021-12-06 22:17:33,726 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7329 states and 10633 transitions. [2021-12-06 22:17:33,750 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:17:33,751 INFO L681 BuchiCegarLoop]: Abstraction has 7329 states and 10633 transitions. [2021-12-06 22:17:33,757 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7329 states and 10633 transitions. [2021-12-06 22:17:33,809 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7329 to 2751. [2021-12-06 22:17:33,813 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2751 states, 2751 states have (on average 1.4376590330788803) internal successors, (3955), 2750 states have internal predecessors, (3955), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:33,818 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2751 states to 2751 states and 3955 transitions. [2021-12-06 22:17:33,818 INFO L704 BuchiCegarLoop]: Abstraction has 2751 states and 3955 transitions. [2021-12-06 22:17:33,818 INFO L587 BuchiCegarLoop]: Abstraction has 2751 states and 3955 transitions. [2021-12-06 22:17:33,818 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-06 22:17:33,818 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2751 states and 3955 transitions. [2021-12-06 22:17:33,825 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2632 [2021-12-06 22:17:33,825 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:17:33,825 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:17:33,826 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:33,826 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:33,826 INFO L791 eck$LassoCheckResult]: Stem: 31040#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 30992#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 30993#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30359#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30360#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 30824#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30825#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30789#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30687#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30688#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30678#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30679#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 30634#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30635#L754 assume !(0 == ~M_E~0); 30957#L754-2 assume !(0 == ~T1_E~0); 30566#L759-1 assume !(0 == ~T2_E~0); 30567#L764-1 assume !(0 == ~T3_E~0); 31008#L769-1 assume !(0 == ~T4_E~0); 31009#L774-1 assume !(0 == ~T5_E~0); 30859#L779-1 assume !(0 == ~T6_E~0); 30602#L784-1 assume !(0 == ~T7_E~0); 30603#L789-1 assume !(0 == ~E_1~0); 30268#L794-1 assume !(0 == ~E_2~0); 30269#L799-1 assume !(0 == ~E_3~0); 31014#L804-1 assume !(0 == ~E_4~0); 31015#L809-1 assume !(0 == ~E_5~0); 30693#L814-1 assume !(0 == ~E_6~0); 30188#L819-1 assume !(0 == ~E_7~0); 30189#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30674#L361 assume !(1 == ~m_pc~0); 30675#L361-2 is_master_triggered_~__retres1~0#1 := 0; 30725#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30481#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 30482#L930 assume !(0 != activate_threads_~tmp~1#1); 30855#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30667#L380 assume !(1 == ~t1_pc~0); 30323#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 30881#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30882#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 31039#L938 assume !(0 != activate_threads_~tmp___0~0#1); 30400#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30324#L399 assume 1 == ~t2_pc~0; 30325#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30535#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30899#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 30748#L946 assume !(0 != activate_threads_~tmp___1~0#1); 30228#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30196#L418 assume !(1 == ~t3_pc~0); 30157#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 30158#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30697#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30975#L954 assume !(0 != activate_threads_~tmp___2~0#1); 31028#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30958#L437 assume 1 == ~t4_pc~0; 30959#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30502#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30327#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30328#L962 assume !(0 != activate_threads_~tmp___3~0#1); 30798#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30453#L456 assume !(1 == ~t5_pc~0); 30454#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 30563#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30929#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30215#L970 assume !(0 != activate_threads_~tmp___4~0#1); 30216#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30340#L475 assume 1 == ~t6_pc~0; 30341#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30421#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30422#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30178#L978 assume !(0 != activate_threads_~tmp___5~0#1); 30179#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30683#L494 assume !(1 == ~t7_pc~0); 30685#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 30731#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30922#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30923#L986 assume !(0 != activate_threads_~tmp___6~0#1); 31034#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30924#L837 assume !(1 == ~M_E~0); 30751#L837-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30752#L842-1 assume !(1 == ~T2_E~0); 32397#L847-1 assume !(1 == ~T3_E~0); 32395#L852-1 assume !(1 == ~T4_E~0); 32393#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 32391#L862-1 assume !(1 == ~T6_E~0); 30763#L867-1 assume !(1 == ~T7_E~0); 32387#L872-1 assume !(1 == ~E_1~0); 32385#L877-1 assume !(1 == ~E_2~0); 32384#L882-1 assume !(1 == ~E_3~0); 32383#L887-1 assume !(1 == ~E_4~0); 32382#L892-1 assume !(1 == ~E_5~0); 32380#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 32378#L902-1 assume !(1 == ~E_7~0); 31602#L907-1 assume { :end_inline_reset_delta_events } true; 31601#L1148-2 [2021-12-06 22:17:33,826 INFO L793 eck$LassoCheckResult]: Loop: 31601#L1148-2 assume !false; 31594#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31593#L729 assume !false; 31125#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 31126#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 31108#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 31109#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 31099#L626 assume !(0 != eval_~tmp~0#1); 31100#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31541#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31538#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 31510#L754-5 assume !(0 == ~T1_E~0); 31505#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31499#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31497#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 31498#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 31493#L779-3 assume !(0 == ~T6_E~0); 31494#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 31490#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 31489#L794-3 assume !(0 == ~E_2~0); 31487#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31488#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 32158#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32156#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32154#L819-3 assume !(0 == ~E_7~0); 32152#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32151#L361-24 assume !(1 == ~m_pc~0); 32150#L361-26 is_master_triggered_~__retres1~0#1 := 0; 32149#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32148#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 32147#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 32146#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32145#L380-24 assume !(1 == ~t1_pc~0); 32144#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 32142#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32140#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 32138#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 32135#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32132#L399-24 assume 1 == ~t2_pc~0; 32123#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32116#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32110#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 32104#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 32093#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32091#L418-24 assume !(1 == ~t3_pc~0); 32088#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 32085#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32083#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 31757#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 31753#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31751#L437-24 assume 1 == ~t4_pc~0; 31748#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 31747#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31746#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31745#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 31744#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31743#L456-24 assume !(1 == ~t5_pc~0); 31741#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 31740#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31739#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31738#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 31737#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31736#L475-24 assume 1 == ~t6_pc~0; 31734#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 31733#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31732#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31731#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 31730#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31729#L494-24 assume !(1 == ~t7_pc~0); 31727#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 31726#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31725#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31724#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 31723#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31722#L837-3 assume !(1 == ~M_E~0); 31721#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31246#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 31720#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31719#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31718#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31717#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 31234#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 31716#L872-3 assume !(1 == ~E_1~0); 31715#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 31714#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 31713#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31712#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31711#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 31710#L902-3 assume !(1 == ~E_7~0); 31709#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 31707#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 31700#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 31699#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 31697#L1167 assume !(0 == start_simulation_~tmp~3#1); 31695#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 31613#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 31608#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 31607#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 31606#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31605#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31604#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 31603#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 31601#L1148-2 [2021-12-06 22:17:33,826 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:33,827 INFO L85 PathProgramCache]: Analyzing trace with hash -1137617309, now seen corresponding path program 1 times [2021-12-06 22:17:33,827 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:33,827 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1022054604] [2021-12-06 22:17:33,827 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:33,827 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:33,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:33,848 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:33,848 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:33,848 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1022054604] [2021-12-06 22:17:33,848 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1022054604] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:33,848 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:33,849 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:33,849 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [362427478] [2021-12-06 22:17:33,849 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:33,849 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:17:33,849 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:33,849 INFO L85 PathProgramCache]: Analyzing trace with hash 622834652, now seen corresponding path program 1 times [2021-12-06 22:17:33,849 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:33,849 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1881379661] [2021-12-06 22:17:33,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:33,850 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:33,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:33,871 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:33,871 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:33,871 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1881379661] [2021-12-06 22:17:33,871 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1881379661] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:33,871 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:33,871 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:33,871 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1908638983] [2021-12-06 22:17:33,871 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:33,872 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:17:33,872 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:17:33,872 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 22:17:33,872 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 22:17:33,872 INFO L87 Difference]: Start difference. First operand 2751 states and 3955 transitions. cyclomatic complexity: 1208 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:33,999 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:17:33,999 INFO L93 Difference]: Finished difference Result 6500 states and 9251 transitions. [2021-12-06 22:17:33,999 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 22:17:34,000 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6500 states and 9251 transitions. [2021-12-06 22:17:34,044 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 6246 [2021-12-06 22:17:34,068 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6500 states to 6500 states and 9251 transitions. [2021-12-06 22:17:34,069 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6500 [2021-12-06 22:17:34,073 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6500 [2021-12-06 22:17:34,073 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6500 states and 9251 transitions. [2021-12-06 22:17:34,078 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:17:34,079 INFO L681 BuchiCegarLoop]: Abstraction has 6500 states and 9251 transitions. [2021-12-06 22:17:34,083 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6500 states and 9251 transitions. [2021-12-06 22:17:34,138 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6500 to 5100. [2021-12-06 22:17:34,146 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5100 states, 5100 states have (on average 1.4301960784313725) internal successors, (7294), 5099 states have internal predecessors, (7294), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:34,155 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5100 states to 5100 states and 7294 transitions. [2021-12-06 22:17:34,155 INFO L704 BuchiCegarLoop]: Abstraction has 5100 states and 7294 transitions. [2021-12-06 22:17:34,155 INFO L587 BuchiCegarLoop]: Abstraction has 5100 states and 7294 transitions. [2021-12-06 22:17:34,155 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-06 22:17:34,156 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5100 states and 7294 transitions. [2021-12-06 22:17:34,167 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4980 [2021-12-06 22:17:34,167 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:17:34,167 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:17:34,168 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:34,168 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:34,168 INFO L791 eck$LassoCheckResult]: Stem: 40282#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 40239#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 40240#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39619#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39620#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 40074#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40075#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40035#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39942#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39943#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 39934#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 39935#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 39894#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 39895#L754 assume !(0 == ~M_E~0); 40195#L754-2 assume !(0 == ~T1_E~0); 39824#L759-1 assume !(0 == ~T2_E~0); 39825#L764-1 assume !(0 == ~T3_E~0); 40253#L769-1 assume !(0 == ~T4_E~0); 40254#L774-1 assume !(0 == ~T5_E~0); 40109#L779-1 assume !(0 == ~T6_E~0); 39861#L784-1 assume !(0 == ~T7_E~0); 39862#L789-1 assume !(0 == ~E_1~0); 39530#L794-1 assume !(0 == ~E_2~0); 39531#L799-1 assume !(0 == ~E_3~0); 40255#L804-1 assume !(0 == ~E_4~0); 40256#L809-1 assume !(0 == ~E_5~0); 39947#L814-1 assume !(0 == ~E_6~0); 39449#L819-1 assume !(0 == ~E_7~0); 39450#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39931#L361 assume !(1 == ~m_pc~0); 39932#L361-2 is_master_triggered_~__retres1~0#1 := 0; 39974#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39740#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 39741#L930 assume !(0 != activate_threads_~tmp~1#1); 40105#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39925#L380 assume !(1 == ~t1_pc~0); 39584#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 40131#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40132#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 40247#L938 assume !(0 != activate_threads_~tmp___0~0#1); 39660#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39585#L399 assume !(1 == ~t2_pc~0); 39586#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 39794#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40146#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 39998#L946 assume !(0 != activate_threads_~tmp___1~0#1); 39489#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39457#L418 assume !(1 == ~t3_pc~0); 39418#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 39419#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39951#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 40212#L954 assume !(0 != activate_threads_~tmp___2~0#1); 40273#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40197#L437 assume 1 == ~t4_pc~0; 40198#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39762#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39587#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 39588#L962 assume !(0 != activate_threads_~tmp___3~0#1); 40046#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39710#L456 assume !(1 == ~t5_pc~0); 39711#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 39821#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40175#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39476#L970 assume !(0 != activate_threads_~tmp___4~0#1); 39477#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39600#L475 assume 1 == ~t6_pc~0; 39601#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 39679#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39680#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39439#L978 assume !(0 != activate_threads_~tmp___5~0#1); 39440#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39938#L494 assume !(1 == ~t7_pc~0); 39940#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 39982#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40168#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40169#L986 assume !(0 != activate_threads_~tmp___6~0#1); 40278#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40170#L837 assume !(1 == ~M_E~0); 40001#L837-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40002#L842-1 assume !(1 == ~T2_E~0); 40070#L847-1 assume !(1 == ~T3_E~0); 40071#L852-1 assume !(1 == ~T4_E~0); 40292#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 40293#L862-1 assume !(1 == ~T6_E~0); 40013#L867-1 assume !(1 == ~T7_E~0); 40024#L872-1 assume !(1 == ~E_1~0); 40287#L877-1 assume !(1 == ~E_2~0); 40288#L882-1 assume !(1 == ~E_3~0); 40226#L887-1 assume !(1 == ~E_4~0); 40227#L892-1 assume !(1 == ~E_5~0); 40158#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 40159#L902-1 assume !(1 == ~E_7~0); 39707#L907-1 assume { :end_inline_reset_delta_events } true; 39708#L1148-2 [2021-12-06 22:17:34,169 INFO L793 eck$LassoCheckResult]: Loop: 39708#L1148-2 assume !false; 39451#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 39452#L729 assume !false; 39856#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 39850#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 39800#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 39876#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 39919#L626 assume !(0 != eval_~tmp~0#1); 39920#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40072#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 39955#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 39956#L754-5 assume !(0 == ~T1_E~0); 44390#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 44388#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44386#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44384#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44382#L779-3 assume !(0 == ~T6_E~0); 44379#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 44377#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 44375#L794-3 assume !(0 == ~E_2~0); 44373#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 44371#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 44369#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 44368#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 44365#L819-3 assume !(0 == ~E_7~0); 44363#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44361#L361-24 assume !(1 == ~m_pc~0); 44359#L361-26 is_master_triggered_~__retres1~0#1 := 0; 44357#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44355#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 44354#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 44351#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44349#L380-24 assume !(1 == ~t1_pc~0); 44346#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 44344#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44342#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 44340#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 44337#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44335#L399-24 assume !(1 == ~t2_pc~0); 41412#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 44332#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44330#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 44327#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 44325#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44323#L418-24 assume !(1 == ~t3_pc~0); 44320#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 44316#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44315#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 44314#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 44313#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44312#L437-24 assume 1 == ~t4_pc~0; 44310#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 44309#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44308#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 44307#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44306#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44305#L456-24 assume 1 == ~t5_pc~0; 44304#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44301#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44299#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 44298#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 44297#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 44294#L475-24 assume 1 == ~t6_pc~0; 44292#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 44290#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 44288#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 44287#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 39426#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39427#L494-24 assume !(1 == ~t7_pc~0); 44134#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 44132#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44130#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44128#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 44126#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44124#L837-3 assume !(1 == ~M_E~0); 44123#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40173#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44120#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44118#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 44116#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44115#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 40267#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 44112#L872-3 assume !(1 == ~E_1~0); 44110#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44108#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 44106#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 44104#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 44102#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 44098#L902-3 assume !(1 == ~E_7~0); 44094#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 44070#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 44059#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 44054#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 44046#L1167 assume !(0 == start_simulation_~tmp~3#1); 44043#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 44026#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 44020#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 44018#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 44016#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44013#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 39432#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 39433#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 39708#L1148-2 [2021-12-06 22:17:34,169 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:34,169 INFO L85 PathProgramCache]: Analyzing trace with hash -1839185534, now seen corresponding path program 1 times [2021-12-06 22:17:34,169 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:34,169 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [852667257] [2021-12-06 22:17:34,169 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:34,169 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:34,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:34,202 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:34,202 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:34,202 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [852667257] [2021-12-06 22:17:34,202 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [852667257] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:34,202 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:34,202 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 22:17:34,203 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [261427141] [2021-12-06 22:17:34,203 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:34,203 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:17:34,203 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:34,204 INFO L85 PathProgramCache]: Analyzing trace with hash -1659209188, now seen corresponding path program 1 times [2021-12-06 22:17:34,204 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:34,204 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1555642461] [2021-12-06 22:17:34,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:34,204 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:34,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:34,238 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:34,238 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:34,238 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1555642461] [2021-12-06 22:17:34,239 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1555642461] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:34,239 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:34,239 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:34,239 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [891248309] [2021-12-06 22:17:34,239 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:34,239 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:17:34,239 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:17:34,239 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:17:34,240 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:17:34,240 INFO L87 Difference]: Start difference. First operand 5100 states and 7294 transitions. cyclomatic complexity: 2198 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:34,307 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:17:34,307 INFO L93 Difference]: Finished difference Result 9539 states and 13579 transitions. [2021-12-06 22:17:34,308 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:17:34,308 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9539 states and 13579 transitions. [2021-12-06 22:17:34,343 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9400 [2021-12-06 22:17:34,371 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9539 states to 9539 states and 13579 transitions. [2021-12-06 22:17:34,371 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9539 [2021-12-06 22:17:34,378 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9539 [2021-12-06 22:17:34,378 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9539 states and 13579 transitions. [2021-12-06 22:17:34,387 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:17:34,387 INFO L681 BuchiCegarLoop]: Abstraction has 9539 states and 13579 transitions. [2021-12-06 22:17:34,394 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9539 states and 13579 transitions. [2021-12-06 22:17:34,504 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9539 to 9523. [2021-12-06 22:17:34,518 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9523 states, 9523 states have (on average 1.4242360600651056) internal successors, (13563), 9522 states have internal predecessors, (13563), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:34,535 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9523 states to 9523 states and 13563 transitions. [2021-12-06 22:17:34,536 INFO L704 BuchiCegarLoop]: Abstraction has 9523 states and 13563 transitions. [2021-12-06 22:17:34,536 INFO L587 BuchiCegarLoop]: Abstraction has 9523 states and 13563 transitions. [2021-12-06 22:17:34,536 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-06 22:17:34,536 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9523 states and 13563 transitions. [2021-12-06 22:17:34,559 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9384 [2021-12-06 22:17:34,559 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:17:34,559 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:17:34,560 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:34,560 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:34,561 INFO L791 eck$LassoCheckResult]: Stem: 54967#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 54910#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 54911#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 54264#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 54265#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 54734#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 54735#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 54698#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 54600#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 54601#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 54591#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 54592#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 54546#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 54547#L754 assume !(0 == ~M_E~0); 54875#L754-2 assume !(0 == ~T1_E~0); 54471#L759-1 assume !(0 == ~T2_E~0); 54472#L764-1 assume !(0 == ~T3_E~0); 54931#L769-1 assume !(0 == ~T4_E~0); 54932#L774-1 assume !(0 == ~T5_E~0); 54772#L779-1 assume !(0 == ~T6_E~0); 54511#L784-1 assume !(0 == ~T7_E~0); 54512#L789-1 assume !(0 == ~E_1~0); 54178#L794-1 assume !(0 == ~E_2~0); 54179#L799-1 assume !(0 == ~E_3~0); 54935#L804-1 assume !(0 == ~E_4~0); 54936#L809-1 assume !(0 == ~E_5~0); 54604#L814-1 assume !(0 == ~E_6~0); 54097#L819-1 assume !(0 == ~E_7~0); 54098#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54586#L361 assume !(1 == ~m_pc~0); 54587#L361-2 is_master_triggered_~__retres1~0#1 := 0; 54633#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54385#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 54386#L930 assume !(0 != activate_threads_~tmp~1#1); 54767#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54580#L380 assume !(1 == ~t1_pc~0); 54229#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 54796#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54797#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 54920#L938 assume !(0 != activate_threads_~tmp___0~0#1); 54305#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54230#L399 assume !(1 == ~t2_pc~0); 54231#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 54441#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54813#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 54656#L946 assume !(0 != activate_threads_~tmp___1~0#1); 54133#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54104#L418 assume !(1 == ~t3_pc~0); 54064#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 54065#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54609#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 54886#L954 assume !(0 != activate_threads_~tmp___2~0#1); 54944#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54878#L437 assume !(1 == ~t4_pc~0); 54737#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 54407#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54232#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 54233#L962 assume !(0 != activate_threads_~tmp___3~0#1); 54708#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54362#L456 assume !(1 == ~t5_pc~0); 54363#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 54468#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54846#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 54123#L970 assume !(0 != activate_threads_~tmp___4~0#1); 54124#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54248#L475 assume 1 == ~t6_pc~0; 54249#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 54326#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54327#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 54085#L978 assume !(0 != activate_threads_~tmp___5~0#1); 54086#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54593#L494 assume !(1 == ~t7_pc~0); 54595#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 54639#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54839#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 54840#L986 assume !(0 != activate_threads_~tmp___6~0#1); 54961#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54841#L837 assume !(1 == ~M_E~0); 54661#L837-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 54662#L842-1 assume !(1 == ~T2_E~0); 57751#L847-1 assume !(1 == ~T3_E~0); 57749#L852-1 assume !(1 == ~T4_E~0); 57747#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 57745#L862-1 assume !(1 == ~T6_E~0); 54675#L867-1 assume !(1 == ~T7_E~0); 57742#L872-1 assume !(1 == ~E_1~0); 57740#L877-1 assume !(1 == ~E_2~0); 57738#L882-1 assume !(1 == ~E_3~0); 57736#L887-1 assume !(1 == ~E_4~0); 57734#L892-1 assume !(1 == ~E_5~0); 57732#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 57730#L902-1 assume !(1 == ~E_7~0); 57422#L907-1 assume { :end_inline_reset_delta_events } true; 57419#L1148-2 [2021-12-06 22:17:34,561 INFO L793 eck$LassoCheckResult]: Loop: 57419#L1148-2 assume !false; 57315#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 57314#L729 assume !false; 57313#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 56864#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 56858#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 56856#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 56853#L626 assume !(0 != eval_~tmp~0#1); 56854#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 58690#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 58688#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 58686#L754-5 assume !(0 == ~T1_E~0); 58684#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 58682#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 58680#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 58678#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 58676#L779-3 assume !(0 == ~T6_E~0); 58674#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 58672#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 58670#L794-3 assume !(0 == ~E_2~0); 58667#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 58665#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 58663#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 58661#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 58659#L819-3 assume !(0 == ~E_7~0); 58657#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 58655#L361-24 assume !(1 == ~m_pc~0); 58647#L361-26 is_master_triggered_~__retres1~0#1 := 0; 58642#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58613#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 58610#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 58608#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 58606#L380-24 assume !(1 == ~t1_pc~0); 58602#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 58600#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 58598#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 58595#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 58592#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 58590#L399-24 assume !(1 == ~t2_pc~0); 55688#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 58587#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58585#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 58583#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 58581#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 58576#L418-24 assume !(1 == ~t3_pc~0); 58569#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 58562#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58556#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 58550#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 58531#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58530#L437-24 assume !(1 == ~t4_pc~0); 58528#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 58527#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58526#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 58525#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 58523#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 58521#L456-24 assume !(1 == ~t5_pc~0); 58518#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 58516#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58515#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 58493#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 58488#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58483#L475-24 assume 1 == ~t6_pc~0; 58475#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 58472#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58446#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 58440#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 58435#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 57539#L494-24 assume !(1 == ~t7_pc~0); 57536#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 57533#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 57531#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 57529#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 57527#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57525#L837-3 assume !(1 == ~M_E~0); 57522#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 57518#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 57516#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 57514#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 57512#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 57510#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 57506#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 57502#L872-3 assume !(1 == ~E_1~0); 57500#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 57498#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 57496#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 57494#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 57490#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 57488#L902-3 assume !(1 == ~E_7~0); 57486#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 57480#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 57472#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 57470#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 57468#L1167 assume !(0 == start_simulation_~tmp~3#1); 57466#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 57438#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 57433#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 57431#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 57429#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 57427#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 57425#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 57423#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 57419#L1148-2 [2021-12-06 22:17:34,561 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:34,561 INFO L85 PathProgramCache]: Analyzing trace with hash -1439194335, now seen corresponding path program 1 times [2021-12-06 22:17:34,561 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:34,561 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1741602113] [2021-12-06 22:17:34,562 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:34,562 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:34,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:34,586 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:34,586 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:34,586 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1741602113] [2021-12-06 22:17:34,586 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1741602113] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:34,586 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:34,586 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:34,586 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1764331036] [2021-12-06 22:17:34,586 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:34,587 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:17:34,587 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:34,587 INFO L85 PathProgramCache]: Analyzing trace with hash 626185114, now seen corresponding path program 1 times [2021-12-06 22:17:34,587 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:34,588 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [410474398] [2021-12-06 22:17:34,588 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:34,588 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:34,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:34,616 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:34,616 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:34,616 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [410474398] [2021-12-06 22:17:34,616 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [410474398] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:34,616 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:34,616 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:34,616 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [451673696] [2021-12-06 22:17:34,617 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:34,617 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:17:34,617 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:17:34,617 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 22:17:34,617 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 22:17:34,618 INFO L87 Difference]: Start difference. First operand 9523 states and 13563 transitions. cyclomatic complexity: 4048 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:34,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:17:34,783 INFO L93 Difference]: Finished difference Result 22430 states and 31672 transitions. [2021-12-06 22:17:34,783 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 22:17:34,783 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22430 states and 31672 transitions. [2021-12-06 22:17:34,867 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 21732 [2021-12-06 22:17:34,944 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22430 states to 22430 states and 31672 transitions. [2021-12-06 22:17:34,944 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22430 [2021-12-06 22:17:34,957 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22430 [2021-12-06 22:17:34,957 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22430 states and 31672 transitions. [2021-12-06 22:17:34,977 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:17:34,977 INFO L681 BuchiCegarLoop]: Abstraction has 22430 states and 31672 transitions. [2021-12-06 22:17:34,996 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22430 states and 31672 transitions. [2021-12-06 22:17:35,207 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22430 to 17826. [2021-12-06 22:17:35,227 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17826 states, 17826 states have (on average 1.4186020419611802) internal successors, (25288), 17825 states have internal predecessors, (25288), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:35,320 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17826 states to 17826 states and 25288 transitions. [2021-12-06 22:17:35,320 INFO L704 BuchiCegarLoop]: Abstraction has 17826 states and 25288 transitions. [2021-12-06 22:17:35,320 INFO L587 BuchiCegarLoop]: Abstraction has 17826 states and 25288 transitions. [2021-12-06 22:17:35,320 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-06 22:17:35,320 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17826 states and 25288 transitions. [2021-12-06 22:17:35,350 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 17664 [2021-12-06 22:17:35,350 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:17:35,350 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:17:35,351 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:35,351 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:35,351 INFO L791 eck$LassoCheckResult]: Stem: 86901#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 86852#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 86853#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 86226#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 86227#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 86690#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 86691#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 86650#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 86561#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 86562#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 86552#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 86553#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 86511#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 86512#L754 assume !(0 == ~M_E~0); 86822#L754-2 assume !(0 == ~T1_E~0); 86432#L759-1 assume !(0 == ~T2_E~0); 86433#L764-1 assume !(0 == ~T3_E~0); 86871#L769-1 assume !(0 == ~T4_E~0); 86872#L774-1 assume !(0 == ~T5_E~0); 86729#L779-1 assume !(0 == ~T6_E~0); 86476#L784-1 assume !(0 == ~T7_E~0); 86477#L789-1 assume !(0 == ~E_1~0); 86141#L794-1 assume !(0 == ~E_2~0); 86142#L799-1 assume !(0 == ~E_3~0); 86873#L804-1 assume !(0 == ~E_4~0); 86874#L809-1 assume !(0 == ~E_5~0); 86565#L814-1 assume !(0 == ~E_6~0); 86061#L819-1 assume !(0 == ~E_7~0); 86062#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 86547#L361 assume !(1 == ~m_pc~0); 86548#L361-2 is_master_triggered_~__retres1~0#1 := 0; 86590#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 86347#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 86348#L930 assume !(0 != activate_threads_~tmp~1#1); 86723#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 86541#L380 assume !(1 == ~t1_pc~0); 86192#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 86750#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86751#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 86860#L938 assume !(0 != activate_threads_~tmp___0~0#1); 86267#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 86193#L399 assume !(1 == ~t2_pc~0); 86194#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 86403#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 86765#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 86614#L946 assume !(0 != activate_threads_~tmp___1~0#1); 86097#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 86068#L418 assume !(1 == ~t3_pc~0); 86027#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 86028#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86569#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 86834#L954 assume !(0 != activate_threads_~tmp___2~0#1); 86889#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 86827#L437 assume !(1 == ~t4_pc~0); 86694#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 86370#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 86195#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 86196#L962 assume !(0 != activate_threads_~tmp___3~0#1); 86660#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 86322#L456 assume !(1 == ~t5_pc~0); 86323#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 86429#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 86796#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 86087#L970 assume !(0 != activate_threads_~tmp___4~0#1); 86088#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 86211#L475 assume !(1 == ~t6_pc~0); 86212#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 86286#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 86287#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 86048#L978 assume !(0 != activate_threads_~tmp___5~0#1); 86049#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 86554#L494 assume !(1 == ~t7_pc~0); 86556#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 86598#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 86791#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 86792#L986 assume !(0 != activate_threads_~tmp___6~0#1); 86897#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86793#L837 assume !(1 == ~M_E~0); 86617#L837-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 86175#L842-1 assume !(1 == ~T2_E~0); 86176#L847-1 assume !(1 == ~T3_E~0); 86783#L852-1 assume !(1 == ~T4_E~0); 86784#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 86627#L862-1 assume !(1 == ~T6_E~0); 86628#L867-1 assume !(1 == ~T7_E~0); 86725#L872-1 assume !(1 == ~E_1~0); 86726#L877-1 assume !(1 == ~E_2~0); 100488#L882-1 assume !(1 == ~E_3~0); 100486#L887-1 assume !(1 == ~E_4~0); 100484#L892-1 assume !(1 == ~E_5~0); 100482#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 100481#L902-1 assume !(1 == ~E_7~0); 86315#L907-1 assume { :end_inline_reset_delta_events } true; 86316#L1148-2 [2021-12-06 22:17:35,351 INFO L793 eck$LassoCheckResult]: Loop: 86316#L1148-2 assume !false; 102542#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 102502#L729 assume !false; 102486#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 101946#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 101932#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 101924#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 101917#L626 assume !(0 != eval_~tmp~0#1); 86687#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 86688#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 86571#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 86572#L754-5 assume !(0 == ~T1_E~0); 103607#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 103559#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 103558#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 103557#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 103556#L779-3 assume !(0 == ~T6_E~0); 86074#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 86075#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 86057#L794-3 assume !(0 == ~E_2~0); 86058#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 86156#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 86578#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 86151#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 86152#L819-3 assume !(0 == ~E_7~0); 103284#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 103283#L361-24 assume !(1 == ~m_pc~0); 103282#L361-26 is_master_triggered_~__retres1~0#1 := 0; 103281#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 103280#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 103279#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 103278#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 103277#L380-24 assume !(1 == ~t1_pc~0); 103275#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 103273#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 103271#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 103270#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 103268#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 103267#L399-24 assume !(1 == ~t2_pc~0); 101756#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 103265#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 103263#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 103213#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 103212#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 103211#L418-24 assume !(1 == ~t3_pc~0); 103209#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 103207#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 103206#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 103205#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 103204#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 103203#L437-24 assume !(1 == ~t4_pc~0); 103201#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 103199#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 103197#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 103195#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 103193#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 103191#L456-24 assume 1 == ~t5_pc~0; 103187#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 103184#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 103182#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 103180#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 103177#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 103175#L475-24 assume !(1 == ~t6_pc~0); 95380#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 102783#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 102774#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 102772#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 102770#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 102767#L494-24 assume !(1 == ~t7_pc~0); 102764#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 102763#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 102762#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 102761#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 102760#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 102759#L837-3 assume !(1 == ~M_E~0); 102750#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 102746#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 102744#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 102743#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 102741#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 102739#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 102735#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 102733#L872-3 assume !(1 == ~E_1~0); 102731#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 102729#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 102726#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 102724#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 102722#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 102720#L902-3 assume !(1 == ~E_7~0); 102718#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 102712#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 102704#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 102702#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 102699#L1167 assume !(0 == start_simulation_~tmp~3#1); 102695#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 102686#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 102680#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 102678#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 102676#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 102674#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 102671#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 102669#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 86316#L1148-2 [2021-12-06 22:17:35,352 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:35,352 INFO L85 PathProgramCache]: Analyzing trace with hash -1747633344, now seen corresponding path program 1 times [2021-12-06 22:17:35,352 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:35,352 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [577594348] [2021-12-06 22:17:35,352 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:35,352 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:35,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:35,372 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:35,372 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:35,372 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [577594348] [2021-12-06 22:17:35,373 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [577594348] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:35,373 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:35,373 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 22:17:35,373 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1730083495] [2021-12-06 22:17:35,373 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:35,373 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:17:35,373 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:35,373 INFO L85 PathProgramCache]: Analyzing trace with hash -1960786214, now seen corresponding path program 1 times [2021-12-06 22:17:35,373 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:35,373 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1139027258] [2021-12-06 22:17:35,373 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:35,374 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:35,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:35,393 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:35,393 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:35,393 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1139027258] [2021-12-06 22:17:35,393 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1139027258] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:35,393 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:35,393 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:35,393 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [308645473] [2021-12-06 22:17:35,393 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:35,394 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:17:35,394 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:17:35,394 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:17:35,394 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:17:35,394 INFO L87 Difference]: Start difference. First operand 17826 states and 25288 transitions. cyclomatic complexity: 7470 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:35,437 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:17:35,437 INFO L93 Difference]: Finished difference Result 17821 states and 25197 transitions. [2021-12-06 22:17:35,437 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:17:35,438 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17821 states and 25197 transitions. [2021-12-06 22:17:35,485 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 17664 [2021-12-06 22:17:35,542 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17821 states to 17821 states and 25197 transitions. [2021-12-06 22:17:35,542 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17821 [2021-12-06 22:17:35,549 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17821 [2021-12-06 22:17:35,549 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17821 states and 25197 transitions. [2021-12-06 22:17:35,556 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:17:35,556 INFO L681 BuchiCegarLoop]: Abstraction has 17821 states and 25197 transitions. [2021-12-06 22:17:35,563 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17821 states and 25197 transitions. [2021-12-06 22:17:35,630 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17821 to 8956. [2021-12-06 22:17:35,638 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8956 states, 8956 states have (on average 1.4136891469405986) internal successors, (12661), 8955 states have internal predecessors, (12661), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:35,649 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8956 states to 8956 states and 12661 transitions. [2021-12-06 22:17:35,650 INFO L704 BuchiCegarLoop]: Abstraction has 8956 states and 12661 transitions. [2021-12-06 22:17:35,650 INFO L587 BuchiCegarLoop]: Abstraction has 8956 states and 12661 transitions. [2021-12-06 22:17:35,650 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-06 22:17:35,650 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8956 states and 12661 transitions. [2021-12-06 22:17:35,668 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8832 [2021-12-06 22:17:35,668 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:17:35,668 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:17:35,669 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:35,669 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:35,670 INFO L791 eck$LassoCheckResult]: Stem: 122561#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 122506#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 122507#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 121881#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 121882#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 122343#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 122344#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 122303#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 122209#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 122210#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 122201#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 122202#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 122160#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 122161#L754 assume !(0 == ~M_E~0); 122473#L754-2 assume !(0 == ~T1_E~0); 122087#L759-1 assume !(0 == ~T2_E~0); 122088#L764-1 assume !(0 == ~T3_E~0); 122521#L769-1 assume !(0 == ~T4_E~0); 122522#L774-1 assume !(0 == ~T5_E~0); 122386#L779-1 assume !(0 == ~T6_E~0); 122127#L784-1 assume !(0 == ~T7_E~0); 122128#L789-1 assume !(0 == ~E_1~0); 121790#L794-1 assume !(0 == ~E_2~0); 121791#L799-1 assume !(0 == ~E_3~0); 122527#L804-1 assume !(0 == ~E_4~0); 122528#L809-1 assume !(0 == ~E_5~0); 122214#L814-1 assume !(0 == ~E_6~0); 121710#L819-1 assume !(0 == ~E_7~0); 121711#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 122198#L361 assume !(1 == ~m_pc~0); 122199#L361-2 is_master_triggered_~__retres1~0#1 := 0; 122242#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 122002#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 122003#L930 assume !(0 != activate_threads_~tmp~1#1); 122383#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 122192#L380 assume !(1 == ~t1_pc~0); 121846#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 122407#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 122408#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 122513#L938 assume !(0 != activate_threads_~tmp___0~0#1); 121920#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 121847#L399 assume !(1 == ~t2_pc~0); 121848#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 122057#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 122425#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 122266#L946 assume !(0 != activate_threads_~tmp___1~0#1); 121750#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 121718#L418 assume !(1 == ~t3_pc~0); 121681#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 121682#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 122219#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 122488#L954 assume !(0 != activate_threads_~tmp___2~0#1); 122539#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 122475#L437 assume !(1 == ~t4_pc~0); 122347#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 122024#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 121849#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 121850#L962 assume !(0 != activate_threads_~tmp___3~0#1); 122316#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 121972#L456 assume !(1 == ~t5_pc~0); 121973#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 122084#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 122450#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 121737#L970 assume !(0 != activate_threads_~tmp___4~0#1); 121738#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 121862#L475 assume !(1 == ~t6_pc~0); 121863#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 121939#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 121940#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 121702#L978 assume !(0 != activate_threads_~tmp___5~0#1); 121703#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 122205#L494 assume !(1 == ~t7_pc~0); 122207#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 122250#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 122444#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 122445#L986 assume !(0 != activate_threads_~tmp___6~0#1); 122555#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 122446#L837 assume !(1 == ~M_E~0); 122269#L837-2 assume !(1 == ~T1_E~0); 121828#L842-1 assume !(1 == ~T2_E~0); 121829#L847-1 assume !(1 == ~T3_E~0); 122339#L852-1 assume !(1 == ~T4_E~0); 122438#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 122279#L862-1 assume !(1 == ~T6_E~0); 122280#L867-1 assume !(1 == ~T7_E~0); 122293#L872-1 assume !(1 == ~E_1~0); 122385#L877-1 assume !(1 == ~E_2~0); 122290#L882-1 assume !(1 == ~E_3~0); 122291#L887-1 assume !(1 == ~E_4~0); 121887#L892-1 assume !(1 == ~E_5~0); 121888#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 122310#L902-1 assume !(1 == ~E_7~0); 121968#L907-1 assume { :end_inline_reset_delta_events } true; 121969#L1148-2 [2021-12-06 22:17:35,670 INFO L793 eck$LassoCheckResult]: Loop: 121969#L1148-2 assume !false; 128070#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 128065#L729 assume !false; 128059#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 128024#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 128014#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 128006#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 127998#L626 assume !(0 != eval_~tmp~0#1); 127999#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 129412#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 129410#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 129408#L754-5 assume !(0 == ~T1_E~0); 129406#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 129404#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 129402#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 129400#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 129398#L779-3 assume !(0 == ~T6_E~0); 129396#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 129394#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 129392#L794-3 assume !(0 == ~E_2~0); 129391#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 129390#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 129389#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 129388#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 129387#L819-3 assume !(0 == ~E_7~0); 129386#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 129384#L361-24 assume !(1 == ~m_pc~0); 129383#L361-26 is_master_triggered_~__retres1~0#1 := 0; 129382#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 129380#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 129378#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 129377#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 129376#L380-24 assume !(1 == ~t1_pc~0); 129372#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 129369#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 129367#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 129365#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 129362#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 122070#L399-24 assume !(1 == ~t2_pc~0); 122071#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 128378#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 128371#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 128366#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 128361#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 128357#L418-24 assume 1 == ~t3_pc~0; 128353#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 128348#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 128343#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 128338#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 128334#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 128331#L437-24 assume !(1 == ~t4_pc~0); 128327#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 128322#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 128316#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 128311#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 128306#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 128301#L456-24 assume !(1 == ~t5_pc~0); 128295#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 128288#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 128284#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 128279#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 128274#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 128269#L475-24 assume !(1 == ~t6_pc~0); 127130#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 128260#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 128255#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 128250#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 128246#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 128242#L494-24 assume !(1 == ~t7_pc~0); 128236#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 128232#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 128227#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 128222#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 128217#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 128212#L837-3 assume !(1 == ~M_E~0); 128207#L837-5 assume !(1 == ~T1_E~0); 128201#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 128195#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 128189#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 128182#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 128178#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 128174#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 128170#L872-3 assume !(1 == ~E_1~0); 128166#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 128162#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 128161#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 128160#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 128159#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 128158#L902-3 assume !(1 == ~E_7~0); 128157#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 128153#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 128144#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 128142#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 128139#L1167 assume !(0 == start_simulation_~tmp~3#1); 128136#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 128122#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 128116#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 128114#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 128111#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 128109#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 128107#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 128105#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 121969#L1148-2 [2021-12-06 22:17:35,670 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:35,670 INFO L85 PathProgramCache]: Analyzing trace with hash 1267470274, now seen corresponding path program 1 times [2021-12-06 22:17:35,670 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:35,670 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1596977281] [2021-12-06 22:17:35,671 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:35,671 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:35,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:35,693 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:35,694 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:35,694 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1596977281] [2021-12-06 22:17:35,694 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1596977281] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:35,694 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:35,694 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:35,694 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1349734068] [2021-12-06 22:17:35,694 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:35,694 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:17:35,695 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:35,695 INFO L85 PathProgramCache]: Analyzing trace with hash -203915556, now seen corresponding path program 1 times [2021-12-06 22:17:35,695 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:35,695 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1697698432] [2021-12-06 22:17:35,695 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:35,695 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:35,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:35,749 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:35,749 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:35,749 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1697698432] [2021-12-06 22:17:35,750 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1697698432] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:35,750 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:35,750 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:35,750 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [958260776] [2021-12-06 22:17:35,750 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:35,750 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:17:35,751 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:17:35,751 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 22:17:35,751 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 22:17:35,751 INFO L87 Difference]: Start difference. First operand 8956 states and 12661 transitions. cyclomatic complexity: 3709 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:35,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:17:35,852 INFO L93 Difference]: Finished difference Result 19061 states and 26896 transitions. [2021-12-06 22:17:35,852 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 22:17:35,853 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19061 states and 26896 transitions. [2021-12-06 22:17:35,915 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 18832 [2021-12-06 22:17:35,956 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19061 states to 19061 states and 26896 transitions. [2021-12-06 22:17:35,956 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19061 [2021-12-06 22:17:35,965 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19061 [2021-12-06 22:17:35,966 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19061 states and 26896 transitions. [2021-12-06 22:17:35,987 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:17:35,988 INFO L681 BuchiCegarLoop]: Abstraction has 19061 states and 26896 transitions. [2021-12-06 22:17:36,000 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19061 states and 26896 transitions. [2021-12-06 22:17:36,129 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19061 to 10195. [2021-12-06 22:17:36,141 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10195 states, 10195 states have (on average 1.411476213830309) internal successors, (14390), 10194 states have internal predecessors, (14390), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:36,164 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10195 states to 10195 states and 14390 transitions. [2021-12-06 22:17:36,165 INFO L704 BuchiCegarLoop]: Abstraction has 10195 states and 14390 transitions. [2021-12-06 22:17:36,165 INFO L587 BuchiCegarLoop]: Abstraction has 10195 states and 14390 transitions. [2021-12-06 22:17:36,165 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-06 22:17:36,165 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10195 states and 14390 transitions. [2021-12-06 22:17:36,199 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10000 [2021-12-06 22:17:36,200 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:17:36,200 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:17:36,202 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:36,202 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:36,202 INFO L791 eck$LassoCheckResult]: Stem: 150657#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 150581#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 150582#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 149909#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 149910#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 150392#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 150393#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 150354#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 150251#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 150252#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 150242#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 150243#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 150197#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 150198#L754 assume !(0 == ~M_E~0); 150532#L754-2 assume !(0 == ~T1_E~0); 150124#L759-1 assume !(0 == ~T2_E~0); 150125#L764-1 assume !(0 == ~T3_E~0); 150601#L769-1 assume !(0 == ~T4_E~0); 150602#L774-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 150441#L779-1 assume !(0 == ~T6_E~0); 150442#L784-1 assume !(0 == ~T7_E~0); 150597#L789-1 assume !(0 == ~E_1~0); 150598#L794-1 assume !(0 == ~E_2~0); 150648#L799-1 assume !(0 == ~E_3~0); 150649#L804-1 assume !(0 == ~E_4~0); 150643#L809-1 assume !(0 == ~E_5~0); 150644#L814-1 assume !(0 == ~E_6~0); 149741#L819-1 assume !(0 == ~E_7~0); 149742#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 150237#L361 assume !(1 == ~m_pc~0); 150238#L361-2 is_master_triggered_~__retres1~0#1 := 0; 150574#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 150575#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 150432#L930 assume !(0 != activate_threads_~tmp~1#1); 150433#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 150229#L380 assume !(1 == ~t1_pc~0); 150230#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 150683#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 150681#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 150656#L938 assume !(0 != activate_threads_~tmp___0~0#1); 149949#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 149950#L399 assume !(1 == ~t2_pc~0); 150677#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 150676#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 150603#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 150604#L946 assume !(0 != activate_threads_~tmp___1~0#1); 149779#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 149780#L418 assume !(1 == ~t3_pc~0); 149708#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 149709#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 150547#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 150548#L954 assume !(0 != activate_threads_~tmp___2~0#1); 150626#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 150627#L437 assume !(1 == ~t4_pc~0); 150675#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 150056#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 150057#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 150674#L962 assume !(0 != activate_threads_~tmp___3~0#1); 150673#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 150008#L456 assume !(1 == ~t5_pc~0); 150009#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 150521#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 150522#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 150672#L970 assume !(0 != activate_threads_~tmp___4~0#1); 150605#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 150606#L475 assume !(1 == ~t6_pc~0); 150566#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 150567#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 150546#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 149729#L978 assume !(0 != activate_threads_~tmp___5~0#1); 149730#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 150244#L494 assume !(1 == ~t7_pc~0); 150246#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 150576#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 150577#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 150654#L986 assume !(0 != activate_threads_~tmp___6~0#1); 150655#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 150499#L837 assume !(1 == ~M_E~0); 150500#L837-2 assume !(1 == ~T1_E~0); 149857#L842-1 assume !(1 == ~T2_E~0); 149858#L847-1 assume !(1 == ~T3_E~0); 150388#L852-1 assume !(1 == ~T4_E~0); 150668#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 150331#L862-1 assume !(1 == ~T6_E~0); 150332#L867-1 assume !(1 == ~T7_E~0); 150343#L872-1 assume !(1 == ~E_1~0); 150438#L877-1 assume !(1 == ~E_2~0); 150339#L882-1 assume !(1 == ~E_3~0); 150340#L887-1 assume !(1 == ~E_4~0); 149916#L892-1 assume !(1 == ~E_5~0); 149917#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 150362#L902-1 assume !(1 == ~E_7~0); 150001#L907-1 assume { :end_inline_reset_delta_events } true; 150002#L1148-2 [2021-12-06 22:17:36,203 INFO L793 eck$LassoCheckResult]: Loop: 150002#L1148-2 assume !false; 155937#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 155935#L729 assume !false; 155933#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 155924#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 155918#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 155915#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 155913#L626 assume !(0 != eval_~tmp~0#1); 150389#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 150390#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 150264#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 149781#L754-5 assume !(0 == ~T1_E~0); 149782#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 150189#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 150401#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 150402#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 157266#L779-3 assume !(0 == ~T6_E~0); 157267#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 157258#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 157259#L794-3 assume !(0 == ~E_2~0); 157251#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 157252#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 157245#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 157246#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 157239#L819-3 assume !(0 == ~E_7~0); 157240#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 157232#L361-24 assume !(1 == ~m_pc~0); 157233#L361-26 is_master_triggered_~__retres1~0#1 := 0; 157226#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 157227#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 157217#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 157218#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 157210#L380-24 assume !(1 == ~t1_pc~0); 157211#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 157205#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 157206#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 156967#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 156966#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 156196#L399-24 assume !(1 == ~t2_pc~0); 156197#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 156189#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 156190#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 156183#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 156184#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 156178#L418-24 assume !(1 == ~t3_pc~0); 156179#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 156170#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 156171#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 156159#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 156160#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 156153#L437-24 assume !(1 == ~t4_pc~0); 156154#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 156149#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 156150#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 156145#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 156146#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 156132#L456-24 assume !(1 == ~t5_pc~0); 156134#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 156125#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 156126#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 156118#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 156119#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 156113#L475-24 assume !(1 == ~t6_pc~0); 156112#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 156111#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 156110#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 156109#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 156108#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 156105#L494-24 assume !(1 == ~t7_pc~0); 156102#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 156100#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 156098#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 156096#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 156094#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 156092#L837-3 assume !(1 == ~M_E~0); 156090#L837-5 assume !(1 == ~T1_E~0); 156088#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 156086#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 156084#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 156082#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 156078#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 156076#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 156074#L872-3 assume !(1 == ~E_1~0); 156072#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 156069#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 156067#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 156064#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 156061#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 156059#L902-3 assume !(1 == ~E_7~0); 156057#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 156049#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 156041#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 156039#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 156036#L1167 assume !(0 == start_simulation_~tmp~3#1); 156033#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 156022#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 156015#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 156013#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 156011#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 156009#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 156007#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 156004#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 150002#L1148-2 [2021-12-06 22:17:36,203 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:36,203 INFO L85 PathProgramCache]: Analyzing trace with hash -466634176, now seen corresponding path program 1 times [2021-12-06 22:17:36,203 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:36,203 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [329631591] [2021-12-06 22:17:36,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:36,204 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:36,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:36,230 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:36,230 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:36,230 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [329631591] [2021-12-06 22:17:36,231 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [329631591] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:36,231 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:36,231 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:36,231 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1618526595] [2021-12-06 22:17:36,231 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:36,231 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:17:36,232 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:36,232 INFO L85 PathProgramCache]: Analyzing trace with hash -1345562949, now seen corresponding path program 1 times [2021-12-06 22:17:36,232 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:36,232 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [651966436] [2021-12-06 22:17:36,232 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:36,232 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:36,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:36,261 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:36,261 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:36,261 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [651966436] [2021-12-06 22:17:36,261 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [651966436] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:36,261 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:36,261 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:36,261 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [264597727] [2021-12-06 22:17:36,262 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:36,262 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:17:36,262 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:17:36,262 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 22:17:36,262 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 22:17:36,263 INFO L87 Difference]: Start difference. First operand 10195 states and 14390 transitions. cyclomatic complexity: 4199 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:36,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:17:36,315 INFO L93 Difference]: Finished difference Result 8956 states and 12611 transitions. [2021-12-06 22:17:36,316 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:17:36,316 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8956 states and 12611 transitions. [2021-12-06 22:17:36,351 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8832 [2021-12-06 22:17:36,401 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8956 states to 8956 states and 12611 transitions. [2021-12-06 22:17:36,402 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8956 [2021-12-06 22:17:36,405 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8956 [2021-12-06 22:17:36,405 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8956 states and 12611 transitions. [2021-12-06 22:17:36,408 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:17:36,408 INFO L681 BuchiCegarLoop]: Abstraction has 8956 states and 12611 transitions. [2021-12-06 22:17:36,411 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8956 states and 12611 transitions. [2021-12-06 22:17:36,454 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8956 to 8956. [2021-12-06 22:17:36,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8956 states, 8956 states have (on average 1.4081062974542207) internal successors, (12611), 8955 states have internal predecessors, (12611), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:36,473 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8956 states to 8956 states and 12611 transitions. [2021-12-06 22:17:36,473 INFO L704 BuchiCegarLoop]: Abstraction has 8956 states and 12611 transitions. [2021-12-06 22:17:36,473 INFO L587 BuchiCegarLoop]: Abstraction has 8956 states and 12611 transitions. [2021-12-06 22:17:36,473 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-06 22:17:36,473 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8956 states and 12611 transitions. [2021-12-06 22:17:36,493 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8832 [2021-12-06 22:17:36,493 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:17:36,493 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:17:36,494 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:36,494 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:36,495 INFO L791 eck$LassoCheckResult]: Stem: 169731#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 169681#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 169682#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 169068#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 169069#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 169518#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 169519#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 169477#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 169392#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 169393#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 169381#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 169382#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 169339#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 169340#L754 assume !(0 == ~M_E~0); 169651#L754-2 assume !(0 == ~T1_E~0); 169273#L759-1 assume !(0 == ~T2_E~0); 169274#L764-1 assume !(0 == ~T3_E~0); 169700#L769-1 assume !(0 == ~T4_E~0); 169701#L774-1 assume !(0 == ~T5_E~0); 169561#L779-1 assume !(0 == ~T6_E~0); 169309#L784-1 assume !(0 == ~T7_E~0); 169310#L789-1 assume !(0 == ~E_1~0); 168982#L794-1 assume !(0 == ~E_2~0); 168983#L799-1 assume !(0 == ~E_3~0); 169702#L804-1 assume !(0 == ~E_4~0); 169703#L809-1 assume !(0 == ~E_5~0); 169397#L814-1 assume !(0 == ~E_6~0); 168903#L819-1 assume !(0 == ~E_7~0); 168904#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 169376#L361 assume !(1 == ~m_pc~0); 169377#L361-2 is_master_triggered_~__retres1~0#1 := 0; 169422#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 169186#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 169187#L930 assume !(0 != activate_threads_~tmp~1#1); 169556#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 169370#L380 assume !(1 == ~t1_pc~0); 169033#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 169583#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 169584#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 169730#L938 assume !(0 != activate_threads_~tmp___0~0#1); 169108#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 169034#L399 assume !(1 == ~t2_pc~0); 169035#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 169243#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 169600#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 169445#L946 assume !(0 != activate_threads_~tmp___1~0#1); 168939#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 168910#L418 assume !(1 == ~t3_pc~0); 168869#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 168870#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 169402#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 169661#L954 assume !(0 != activate_threads_~tmp___2~0#1); 169716#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 169655#L437 assume !(1 == ~t4_pc~0); 169522#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 169209#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 169036#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 169037#L962 assume !(0 != activate_threads_~tmp___3~0#1); 169490#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 169163#L456 assume !(1 == ~t5_pc~0); 169164#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 169270#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 169627#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 168929#L970 assume !(0 != activate_threads_~tmp___4~0#1); 168930#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 169052#L475 assume !(1 == ~t6_pc~0); 169053#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 169127#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 169128#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 168890#L978 assume !(0 != activate_threads_~tmp___5~0#1); 168891#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 169384#L494 assume !(1 == ~t7_pc~0); 169386#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 169428#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 169623#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 169624#L986 assume !(0 != activate_threads_~tmp___6~0#1); 169724#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 169625#L837 assume !(1 == ~M_E~0); 169448#L837-2 assume !(1 == ~T1_E~0); 169016#L842-1 assume !(1 == ~T2_E~0); 169017#L847-1 assume !(1 == ~T3_E~0); 169514#L852-1 assume !(1 == ~T4_E~0); 169618#L857-1 assume !(1 == ~T5_E~0); 169458#L862-1 assume !(1 == ~T6_E~0); 169459#L867-1 assume !(1 == ~T7_E~0); 169469#L872-1 assume !(1 == ~E_1~0); 169558#L877-1 assume !(1 == ~E_2~0); 169465#L882-1 assume !(1 == ~E_3~0); 169466#L887-1 assume !(1 == ~E_4~0); 169075#L892-1 assume !(1 == ~E_5~0); 169076#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 169486#L902-1 assume !(1 == ~E_7~0); 169156#L907-1 assume { :end_inline_reset_delta_events } true; 169157#L1148-2 [2021-12-06 22:17:36,495 INFO L793 eck$LassoCheckResult]: Loop: 169157#L1148-2 assume !false; 174192#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 174191#L729 assume !false; 174190#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 174166#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 174082#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 174067#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 174059#L626 assume !(0 != eval_~tmp~0#1); 174060#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 176817#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 176815#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 176813#L754-5 assume !(0 == ~T1_E~0); 176811#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 176808#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 176807#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 176806#L774-3 assume !(0 == ~T5_E~0); 176804#L779-3 assume !(0 == ~T6_E~0); 176803#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 176802#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 176801#L794-3 assume !(0 == ~E_2~0); 176799#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 176797#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 176795#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 176793#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 176791#L819-3 assume !(0 == ~E_7~0); 176789#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 176787#L361-24 assume !(1 == ~m_pc~0); 176785#L361-26 is_master_triggered_~__retres1~0#1 := 0; 176783#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 176781#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 176779#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 176777#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 176775#L380-24 assume !(1 == ~t1_pc~0); 176771#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 176769#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 176767#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 176765#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 176762#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 175308#L399-24 assume !(1 == ~t2_pc~0); 175305#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 175303#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 175301#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 175300#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 175297#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 175295#L418-24 assume !(1 == ~t3_pc~0); 175290#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 175287#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 175284#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 175281#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 175277#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 175272#L437-24 assume !(1 == ~t4_pc~0); 175268#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 175263#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 175260#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 175255#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 175250#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 175245#L456-24 assume !(1 == ~t5_pc~0); 175238#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 175234#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 175227#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 175222#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 175216#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 175209#L475-24 assume !(1 == ~t6_pc~0); 172525#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 175196#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 175190#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 175184#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 175178#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 175173#L494-24 assume !(1 == ~t7_pc~0); 175166#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 175159#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 175154#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 175149#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 175144#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 175139#L837-3 assume !(1 == ~M_E~0); 175133#L837-5 assume !(1 == ~T1_E~0); 175129#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 175123#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 175117#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 175112#L857-3 assume !(1 == ~T5_E~0); 175107#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 175102#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 175096#L872-3 assume !(1 == ~E_1~0); 175090#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 175084#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 175078#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 175073#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 175068#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 175065#L902-3 assume !(1 == ~E_7~0); 175062#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 174580#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 174569#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 174561#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 174554#L1167 assume !(0 == start_simulation_~tmp~3#1); 174549#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 174348#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 174342#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 174340#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 174326#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 174317#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 174308#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 174303#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 169157#L1148-2 [2021-12-06 22:17:36,495 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:36,495 INFO L85 PathProgramCache]: Analyzing trace with hash 1968534852, now seen corresponding path program 1 times [2021-12-06 22:17:36,495 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:36,495 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2070812941] [2021-12-06 22:17:36,495 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:36,496 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:36,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:36,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:36,518 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:36,518 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2070812941] [2021-12-06 22:17:36,518 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2070812941] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:36,518 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:36,519 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:36,519 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1204780258] [2021-12-06 22:17:36,519 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:36,519 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:17:36,519 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:36,519 INFO L85 PathProgramCache]: Analyzing trace with hash 557689791, now seen corresponding path program 1 times [2021-12-06 22:17:36,520 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:36,520 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1004194377] [2021-12-06 22:17:36,520 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:36,520 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:36,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:36,544 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:36,544 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:36,544 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1004194377] [2021-12-06 22:17:36,544 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1004194377] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:36,544 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:36,544 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:36,544 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [49561239] [2021-12-06 22:17:36,544 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:36,545 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:17:36,545 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:17:36,545 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 22:17:36,545 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 22:17:36,545 INFO L87 Difference]: Start difference. First operand 8956 states and 12611 transitions. cyclomatic complexity: 3659 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:36,650 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:17:36,650 INFO L93 Difference]: Finished difference Result 18213 states and 25558 transitions. [2021-12-06 22:17:36,651 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 22:17:36,651 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18213 states and 25558 transitions. [2021-12-06 22:17:36,705 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 17976 [2021-12-06 22:17:36,736 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18213 states to 18213 states and 25558 transitions. [2021-12-06 22:17:36,736 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18213 [2021-12-06 22:17:36,745 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18213 [2021-12-06 22:17:36,745 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18213 states and 25558 transitions. [2021-12-06 22:17:36,755 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:17:36,755 INFO L681 BuchiCegarLoop]: Abstraction has 18213 states and 25558 transitions. [2021-12-06 22:17:36,763 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18213 states and 25558 transitions. [2021-12-06 22:17:36,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18213 to 10187. [2021-12-06 22:17:36,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10187 states, 10187 states have (on average 1.4017865907529203) internal successors, (14280), 10186 states have internal predecessors, (14280), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:36,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10187 states to 10187 states and 14280 transitions. [2021-12-06 22:17:36,861 INFO L704 BuchiCegarLoop]: Abstraction has 10187 states and 14280 transitions. [2021-12-06 22:17:36,861 INFO L587 BuchiCegarLoop]: Abstraction has 10187 states and 14280 transitions. [2021-12-06 22:17:36,862 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-06 22:17:36,862 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10187 states and 14280 transitions. [2021-12-06 22:17:36,885 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 9992 [2021-12-06 22:17:36,885 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:17:36,885 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:17:36,887 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:36,887 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:36,887 INFO L791 eck$LassoCheckResult]: Stem: 196967#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 196905#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 196906#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 196248#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 196249#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 196728#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 196729#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 196684#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 196583#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 196584#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 196575#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 196576#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 196532#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 196533#L754 assume !(0 == ~M_E~0); 196861#L754-2 assume !(0 == ~T1_E~0); 196461#L759-1 assume !(0 == ~T2_E~0); 196462#L764-1 assume !(0 == ~T3_E~0); 196925#L769-1 assume !(0 == ~T4_E~0); 196926#L774-1 assume !(0 == ~T5_E~0); 196770#L779-1 assume !(0 == ~T6_E~0); 196498#L784-1 assume !(0 == ~T7_E~0); 196499#L789-1 assume !(0 == ~E_1~0); 196158#L794-1 assume !(0 == ~E_2~0); 196159#L799-1 assume !(0 == ~E_3~0); 196934#L804-1 assume !(0 == ~E_4~0); 196935#L809-1 assume !(0 == ~E_5~0); 196588#L814-1 assume 0 == ~E_6~0;~E_6~0 := 1; 196078#L819-1 assume !(0 == ~E_7~0); 196079#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 196572#L361 assume !(1 == ~m_pc~0); 196573#L361-2 is_master_triggered_~__retres1~0#1 := 0; 196898#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 196899#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 196766#L930 assume !(0 != activate_threads_~tmp~1#1); 196767#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 196564#L380 assume !(1 == ~t1_pc~0); 196565#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 196994#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 196992#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 196965#L938 assume !(0 != activate_threads_~tmp___0~0#1); 196288#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 196289#L399 assume !(1 == ~t2_pc~0); 196427#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 196428#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 196806#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 196647#L946 assume !(0 != activate_threads_~tmp___1~0#1); 196648#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 196086#L418 assume !(1 == ~t3_pc~0); 196087#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 196593#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 196594#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 196970#L954 assume !(0 != activate_threads_~tmp___2~0#1); 196971#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 196865#L437 assume !(1 == ~t4_pc~0); 196732#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 196733#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 196217#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 196218#L962 assume !(0 != activate_threads_~tmp___3~0#1); 196711#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 196339#L456 assume !(1 == ~t5_pc~0); 196340#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 196848#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 196849#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 196985#L970 assume !(0 != activate_threads_~tmp___4~0#1); 196932#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 196933#L475 assume !(1 == ~t6_pc~0); 196890#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 196891#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 196877#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 196878#L978 assume !(0 != activate_threads_~tmp___5~0#1); 196940#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 196941#L494 assume !(1 == ~t7_pc~0); 196628#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 196629#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 196826#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 196827#L986 assume !(0 != activate_threads_~tmp___6~0#1); 196956#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 196957#L837 assume !(1 == ~M_E~0); 196651#L837-2 assume !(1 == ~T1_E~0); 196652#L842-1 assume !(1 == ~T2_E~0); 196983#L847-1 assume !(1 == ~T3_E~0); 196982#L852-1 assume !(1 == ~T4_E~0); 196977#L857-1 assume !(1 == ~T5_E~0); 196978#L862-1 assume !(1 == ~T6_E~0); 196673#L867-1 assume !(1 == ~T7_E~0); 196674#L872-1 assume !(1 == ~E_1~0); 196769#L877-1 assume !(1 == ~E_2~0); 196671#L882-1 assume !(1 == ~E_3~0); 196672#L887-1 assume !(1 == ~E_4~0); 196980#L892-1 assume !(1 == ~E_5~0); 196979#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 196690#L902-1 assume !(1 == ~E_7~0); 196336#L907-1 assume { :end_inline_reset_delta_events } true; 196337#L1148-2 [2021-12-06 22:17:36,888 INFO L793 eck$LassoCheckResult]: Loop: 196337#L1148-2 assume !false; 202274#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 202265#L729 assume !false; 202228#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 202177#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 202169#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 202167#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 202165#L626 assume !(0 != eval_~tmp~0#1); 202166#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 202932#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 202930#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 202928#L754-5 assume !(0 == ~T1_E~0); 202926#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 202924#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 202922#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 202919#L774-3 assume !(0 == ~T5_E~0); 202917#L779-3 assume !(0 == ~T6_E~0); 202915#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 202913#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 202911#L794-3 assume !(0 == ~E_2~0); 202909#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 202907#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 202905#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 202903#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 202650#L819-3 assume !(0 == ~E_7~0); 202651#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 202644#L361-24 assume !(1 == ~m_pc~0); 202645#L361-26 is_master_triggered_~__retres1~0#1 := 0; 202638#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 202639#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 202632#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 202633#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 202625#L380-24 assume 1 == ~t1_pc~0; 202627#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 202665#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 202666#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 202609#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 202610#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 202604#L399-24 assume !(1 == ~t2_pc~0); 200063#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 202599#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 202600#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 202593#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 202594#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 202586#L418-24 assume !(1 == ~t3_pc~0); 202587#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 202579#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 202580#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 202573#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 202574#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 202567#L437-24 assume !(1 == ~t4_pc~0); 202568#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 202561#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 202562#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 202555#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 202556#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 202549#L456-24 assume !(1 == ~t5_pc~0); 202551#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 202544#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 202545#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 202540#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 202541#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 202537#L475-24 assume !(1 == ~t6_pc~0); 202536#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 202535#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 202534#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 202533#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 202532#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 202531#L494-24 assume !(1 == ~t7_pc~0); 202529#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 202528#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 202527#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 202526#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 202525#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 202524#L837-3 assume !(1 == ~M_E~0); 202523#L837-5 assume !(1 == ~T1_E~0); 202522#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 202521#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 202520#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 202519#L857-3 assume !(1 == ~T5_E~0); 202518#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 202517#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 202516#L872-3 assume !(1 == ~E_1~0); 202515#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 202514#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 202513#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 202512#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 202510#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 202507#L902-3 assume !(1 == ~E_7~0); 202504#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 202451#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 202443#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 202441#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 202438#L1167 assume !(0 == start_simulation_~tmp~3#1); 202435#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 202411#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 202404#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 202402#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 202400#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 202398#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 202396#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 202394#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 196337#L1148-2 [2021-12-06 22:17:36,888 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:36,888 INFO L85 PathProgramCache]: Analyzing trace with hash -1110278718, now seen corresponding path program 1 times [2021-12-06 22:17:36,888 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:36,888 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [808428775] [2021-12-06 22:17:36,889 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:36,889 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:36,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:36,915 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:36,915 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:36,915 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [808428775] [2021-12-06 22:17:36,915 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [808428775] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:36,915 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:36,915 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:36,915 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1957912822] [2021-12-06 22:17:36,916 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:36,916 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:17:36,916 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:36,916 INFO L85 PathProgramCache]: Analyzing trace with hash 382900770, now seen corresponding path program 1 times [2021-12-06 22:17:36,916 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:36,917 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [91399791] [2021-12-06 22:17:36,917 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:36,917 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:36,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:36,937 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:36,938 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:36,938 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [91399791] [2021-12-06 22:17:36,938 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [91399791] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:36,938 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:36,938 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:36,938 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [478802534] [2021-12-06 22:17:36,938 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:36,938 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:17:36,939 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:17:36,939 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 22:17:36,939 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 22:17:36,939 INFO L87 Difference]: Start difference. First operand 10187 states and 14280 transitions. cyclomatic complexity: 4097 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:37,047 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:17:37,047 INFO L93 Difference]: Finished difference Result 16884 states and 23649 transitions. [2021-12-06 22:17:37,047 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 22:17:37,047 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16884 states and 23649 transitions. [2021-12-06 22:17:37,088 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 16720 [2021-12-06 22:17:37,113 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16884 states to 16884 states and 23649 transitions. [2021-12-06 22:17:37,113 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16884 [2021-12-06 22:17:37,119 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16884 [2021-12-06 22:17:37,119 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16884 states and 23649 transitions. [2021-12-06 22:17:37,128 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:17:37,128 INFO L681 BuchiCegarLoop]: Abstraction has 16884 states and 23649 transitions. [2021-12-06 22:17:37,135 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16884 states and 23649 transitions. [2021-12-06 22:17:37,195 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16884 to 8956. [2021-12-06 22:17:37,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8956 states, 8956 states have (on average 1.3967172845020097) internal successors, (12509), 8955 states have internal predecessors, (12509), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:37,220 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8956 states to 8956 states and 12509 transitions. [2021-12-06 22:17:37,220 INFO L704 BuchiCegarLoop]: Abstraction has 8956 states and 12509 transitions. [2021-12-06 22:17:37,220 INFO L587 BuchiCegarLoop]: Abstraction has 8956 states and 12509 transitions. [2021-12-06 22:17:37,220 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-06 22:17:37,221 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8956 states and 12509 transitions. [2021-12-06 22:17:37,239 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8832 [2021-12-06 22:17:37,239 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:17:37,239 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:17:37,240 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:37,240 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:37,241 INFO L791 eck$LassoCheckResult]: Stem: 223997#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 223949#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 223950#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 223324#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 223325#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 223781#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 223782#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 223741#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 223651#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 223652#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 223643#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 223644#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 223601#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 223602#L754 assume !(0 == ~M_E~0); 223911#L754-2 assume !(0 == ~T1_E~0); 223530#L759-1 assume !(0 == ~T2_E~0); 223531#L764-1 assume !(0 == ~T3_E~0); 223965#L769-1 assume !(0 == ~T4_E~0); 223966#L774-1 assume !(0 == ~T5_E~0); 223823#L779-1 assume !(0 == ~T6_E~0); 223571#L784-1 assume !(0 == ~T7_E~0); 223572#L789-1 assume !(0 == ~E_1~0); 223234#L794-1 assume !(0 == ~E_2~0); 223235#L799-1 assume !(0 == ~E_3~0); 223968#L804-1 assume !(0 == ~E_4~0); 223969#L809-1 assume !(0 == ~E_5~0); 223656#L814-1 assume !(0 == ~E_6~0); 223158#L819-1 assume !(0 == ~E_7~0); 223159#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 223639#L361 assume !(1 == ~m_pc~0); 223640#L361-2 is_master_triggered_~__retres1~0#1 := 0; 223685#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 223443#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 223444#L930 assume !(0 != activate_threads_~tmp~1#1); 223819#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 223633#L380 assume !(1 == ~t1_pc~0); 223290#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 223844#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 223845#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 223996#L938 assume !(0 != activate_threads_~tmp___0~0#1); 223364#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 223291#L399 assume !(1 == ~t2_pc~0); 223292#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 223501#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 223860#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 223709#L946 assume !(0 != activate_threads_~tmp___1~0#1); 223197#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 223166#L418 assume !(1 == ~t3_pc~0); 223129#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 223130#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 223661#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 223927#L954 assume !(0 != activate_threads_~tmp___2~0#1); 223981#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 223912#L437 assume !(1 == ~t4_pc~0); 223785#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 223466#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 223293#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 223294#L962 assume !(0 != activate_threads_~tmp___3~0#1); 223753#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 223415#L456 assume !(1 == ~t5_pc~0); 223416#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 223527#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 223889#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 223185#L970 assume !(0 != activate_threads_~tmp___4~0#1); 223186#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 223306#L475 assume !(1 == ~t6_pc~0); 223307#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 223383#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 223384#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 223150#L978 assume !(0 != activate_threads_~tmp___5~0#1); 223151#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 223647#L494 assume !(1 == ~t7_pc~0); 223649#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 223693#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 223880#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 223881#L986 assume !(0 != activate_threads_~tmp___6~0#1); 223992#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 223882#L837 assume !(1 == ~M_E~0); 223712#L837-2 assume !(1 == ~T1_E~0); 223272#L842-1 assume !(1 == ~T2_E~0); 223273#L847-1 assume !(1 == ~T3_E~0); 223777#L852-1 assume !(1 == ~T4_E~0); 223875#L857-1 assume !(1 == ~T5_E~0); 223720#L862-1 assume !(1 == ~T6_E~0); 223721#L867-1 assume !(1 == ~T7_E~0); 223731#L872-1 assume !(1 == ~E_1~0); 223822#L877-1 assume !(1 == ~E_2~0); 223728#L882-1 assume !(1 == ~E_3~0); 223729#L887-1 assume !(1 == ~E_4~0); 223331#L892-1 assume !(1 == ~E_5~0); 223332#L897-1 assume !(1 == ~E_6~0); 223747#L902-1 assume !(1 == ~E_7~0); 223411#L907-1 assume { :end_inline_reset_delta_events } true; 223412#L1148-2 [2021-12-06 22:17:37,241 INFO L793 eck$LassoCheckResult]: Loop: 223412#L1148-2 assume !false; 223160#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 223161#L729 assume !false; 223566#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 223560#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 223508#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 223586#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 223627#L626 assume !(0 != eval_~tmp~0#1); 223628#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 231890#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 231886#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 231884#L754-5 assume !(0 == ~T1_E~0); 231882#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 231880#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 231877#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 231874#L774-3 assume !(0 == ~T5_E~0); 231875#L779-3 assume !(0 == ~T6_E~0); 231956#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 231954#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 231952#L794-3 assume !(0 == ~E_2~0); 231950#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 231948#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 231947#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 231946#L814-3 assume !(0 == ~E_6~0); 223585#L819-3 assume !(0 == ~E_7~0); 223446#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 223447#L361-24 assume !(1 == ~m_pc~0); 223820#L361-26 is_master_triggered_~__retres1~0#1 := 0; 231857#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 231856#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 231855#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 231853#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 231851#L380-24 assume !(1 == ~t1_pc~0); 231847#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 231845#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 231843#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 231840#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 231837#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 231835#L399-24 assume !(1 == ~t2_pc~0); 231036#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 231625#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 231624#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 231621#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 231618#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 231616#L418-24 assume 1 == ~t3_pc~0; 231614#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 231611#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 231608#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 231604#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 231601#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 231598#L437-24 assume !(1 == ~t4_pc~0); 231595#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 231592#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 231589#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 231585#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 231581#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 231577#L456-24 assume 1 == ~t5_pc~0; 231573#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 231569#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 231566#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 231561#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 231558#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 231555#L475-24 assume !(1 == ~t6_pc~0); 230876#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 231550#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 231548#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 231544#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 231541#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 231538#L494-24 assume !(1 == ~t7_pc~0); 231534#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 231531#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 231528#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 231525#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 231521#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 231518#L837-3 assume !(1 == ~M_E~0); 231515#L837-5 assume !(1 == ~T1_E~0); 231512#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 231509#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 231505#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 231502#L857-3 assume !(1 == ~T5_E~0); 231499#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 231496#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 231493#L872-3 assume !(1 == ~E_1~0); 231491#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 231489#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 231486#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 231484#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 231482#L897-3 assume !(1 == ~E_6~0); 224001#L902-3 assume !(1 == ~E_7~0); 223743#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 223734#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 223165#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 223983#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 223908#L1167 assume !(0 == start_simulation_~tmp~3#1); 223810#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 223811#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 223581#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 223859#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 223902#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 223790#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 223143#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 223144#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 223412#L1148-2 [2021-12-06 22:17:37,241 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:37,241 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 1 times [2021-12-06 22:17:37,241 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:37,241 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [935869236] [2021-12-06 22:17:37,242 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:37,242 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:37,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:17:37,251 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:17:37,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:17:37,317 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:17:37,318 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:37,318 INFO L85 PathProgramCache]: Analyzing trace with hash 1967718021, now seen corresponding path program 1 times [2021-12-06 22:17:37,318 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:37,318 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2058627277] [2021-12-06 22:17:37,318 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:37,318 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:37,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:37,344 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:37,345 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:37,345 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2058627277] [2021-12-06 22:17:37,345 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2058627277] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:37,345 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:37,345 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:37,345 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [533251958] [2021-12-06 22:17:37,345 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:37,346 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:17:37,346 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:17:37,346 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:17:37,346 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:17:37,346 INFO L87 Difference]: Start difference. First operand 8956 states and 12509 transitions. cyclomatic complexity: 3557 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:37,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:17:37,423 INFO L93 Difference]: Finished difference Result 13391 states and 18516 transitions. [2021-12-06 22:17:37,423 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:17:37,424 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13391 states and 18516 transitions. [2021-12-06 22:17:37,465 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13188 [2021-12-06 22:17:37,489 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13391 states to 13391 states and 18516 transitions. [2021-12-06 22:17:37,489 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13391 [2021-12-06 22:17:37,495 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13391 [2021-12-06 22:17:37,495 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13391 states and 18516 transitions. [2021-12-06 22:17:37,500 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:17:37,500 INFO L681 BuchiCegarLoop]: Abstraction has 13391 states and 18516 transitions. [2021-12-06 22:17:37,505 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13391 states and 18516 transitions. [2021-12-06 22:17:37,571 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13391 to 13391. [2021-12-06 22:17:37,579 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13391 states, 13391 states have (on average 1.382719737136883) internal successors, (18516), 13390 states have internal predecessors, (18516), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:37,599 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13391 states to 13391 states and 18516 transitions. [2021-12-06 22:17:37,599 INFO L704 BuchiCegarLoop]: Abstraction has 13391 states and 18516 transitions. [2021-12-06 22:17:37,599 INFO L587 BuchiCegarLoop]: Abstraction has 13391 states and 18516 transitions. [2021-12-06 22:17:37,599 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-06 22:17:37,599 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13391 states and 18516 transitions. [2021-12-06 22:17:37,627 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13188 [2021-12-06 22:17:37,627 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:17:37,627 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:17:37,628 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:37,628 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:37,629 INFO L791 eck$LassoCheckResult]: Stem: 246417#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 246345#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 246346#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 245677#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 245678#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 246159#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 246160#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 246119#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 246015#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 246016#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 246007#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 246008#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 245963#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 245964#L754 assume 0 == ~M_E~0;~M_E~0 := 1; 246296#L754-2 assume !(0 == ~T1_E~0); 246372#L759-1 assume !(0 == ~T2_E~0); 246409#L764-1 assume !(0 == ~T3_E~0); 246410#L769-1 assume !(0 == ~T4_E~0); 246413#L774-1 assume !(0 == ~T5_E~0); 246204#L779-1 assume !(0 == ~T6_E~0); 245929#L784-1 assume !(0 == ~T7_E~0); 245930#L789-1 assume !(0 == ~E_1~0); 246450#L794-1 assume !(0 == ~E_2~0); 246411#L799-1 assume !(0 == ~E_3~0); 246412#L804-1 assume !(0 == ~E_4~0); 246403#L809-1 assume !(0 == ~E_5~0); 246404#L814-1 assume !(0 == ~E_6~0); 245511#L819-1 assume !(0 == ~E_7~0); 245512#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 246004#L361 assume !(1 == ~m_pc~0); 246005#L361-2 is_master_triggered_~__retres1~0#1 := 0; 246336#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 246337#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 246449#L930 assume !(0 != activate_threads_~tmp~1#1); 246264#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 246265#L380 assume !(1 == ~t1_pc~0); 245644#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 246414#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 246352#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 246353#L938 assume !(0 != activate_threads_~tmp___0~0#1); 245717#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 245718#L399 assume !(1 == ~t2_pc~0); 246440#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 246439#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 246364#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 246365#L946 assume !(0 != activate_threads_~tmp___1~0#1); 245551#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 245519#L418 assume !(1 == ~t3_pc~0); 245520#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 246026#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 246027#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 246437#L954 assume !(0 != activate_threads_~tmp___2~0#1); 246386#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 246387#L437 assume !(1 == ~t4_pc~0); 246436#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 245822#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 245823#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 246435#L962 assume !(0 != activate_threads_~tmp___3~0#1); 246434#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 245770#L456 assume !(1 == ~t5_pc~0); 245771#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 246282#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 246283#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 246433#L970 assume !(0 != activate_threads_~tmp___4~0#1); 246368#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 246369#L475 assume !(1 == ~t6_pc~0); 246330#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 245738#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 245739#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 246431#L978 assume !(0 != activate_threads_~tmp___5~0#1); 246376#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 246377#L494 assume !(1 == ~t7_pc~0); 246061#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 246062#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 246258#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 246259#L986 assume !(0 != activate_threads_~tmp___6~0#1); 246405#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 246260#L837 assume 1 == ~M_E~0;~M_E~0 := 2; 246088#L837-2 assume !(1 == ~T1_E~0); 245627#L842-1 assume !(1 == ~T2_E~0); 245628#L847-1 assume !(1 == ~T3_E~0); 246155#L852-1 assume !(1 == ~T4_E~0); 246252#L857-1 assume !(1 == ~T5_E~0); 246097#L862-1 assume !(1 == ~T6_E~0); 246098#L867-1 assume !(1 == ~T7_E~0); 246109#L872-1 assume !(1 == ~E_1~0); 246203#L877-1 assume !(1 == ~E_2~0); 246106#L882-1 assume !(1 == ~E_3~0); 246107#L887-1 assume !(1 == ~E_4~0); 245684#L892-1 assume !(1 == ~E_5~0); 245685#L897-1 assume !(1 == ~E_6~0); 246125#L902-1 assume !(1 == ~E_7~0); 245766#L907-1 assume { :end_inline_reset_delta_events } true; 245767#L1148-2 [2021-12-06 22:17:37,629 INFO L793 eck$LassoCheckResult]: Loop: 245767#L1148-2 assume !false; 255833#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 255829#L729 assume !false; 246393#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 245920#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 245862#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 245946#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 245990#L626 assume !(0 != eval_~tmp~0#1); 245991#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 256827#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 256824#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 256822#L754-5 assume !(0 == ~T1_E~0); 256819#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 256817#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 256815#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 256814#L774-3 assume !(0 == ~T5_E~0); 256813#L779-3 assume !(0 == ~T6_E~0); 256811#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 256810#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 256809#L794-3 assume !(0 == ~E_2~0); 256807#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 256806#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 256805#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 256804#L814-3 assume !(0 == ~E_6~0); 256803#L819-3 assume !(0 == ~E_7~0); 256801#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 256799#L361-24 assume !(1 == ~m_pc~0); 256797#L361-26 is_master_triggered_~__retres1~0#1 := 0; 256795#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 256793#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 256791#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 256786#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 256787#L380-24 assume 1 == ~t1_pc~0; 258390#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 258391#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 258413#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 258383#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 258381#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 258379#L399-24 assume !(1 == ~t2_pc~0); 256562#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 258374#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 258372#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 258370#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 258367#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 258365#L418-24 assume 1 == ~t3_pc~0; 258363#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 258361#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 258359#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 258357#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 258355#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 258353#L437-24 assume !(1 == ~t4_pc~0); 258351#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 258348#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 258346#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 258344#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 258342#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 258340#L456-24 assume 1 == ~t5_pc~0; 258338#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 258335#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 258333#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 258331#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 258329#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 256085#L475-24 assume !(1 == ~t6_pc~0); 256083#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 256081#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 256079#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 256077#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 256074#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 256071#L494-24 assume !(1 == ~t7_pc~0); 256066#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 256063#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 256060#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 256057#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 256054#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 256051#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 256047#L837-5 assume !(1 == ~T1_E~0); 256044#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 256041#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 256039#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 256037#L857-3 assume !(1 == ~T5_E~0); 256034#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 256031#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 256028#L872-3 assume !(1 == ~E_1~0); 256025#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 256022#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 256019#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 256016#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 256010#L897-3 assume !(1 == ~E_6~0); 256006#L902-3 assume !(1 == ~E_7~0); 256002#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 255939#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 255930#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 255928#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 255925#L1167 assume !(0 == start_simulation_~tmp~3#1); 255923#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 255883#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 255874#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 255869#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 255865#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 255861#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 255853#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 255847#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 245767#L1148-2 [2021-12-06 22:17:37,629 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:37,629 INFO L85 PathProgramCache]: Analyzing trace with hash -162859702, now seen corresponding path program 1 times [2021-12-06 22:17:37,630 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:37,630 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [384434021] [2021-12-06 22:17:37,630 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:37,630 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:37,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:37,650 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:37,650 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:37,650 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [384434021] [2021-12-06 22:17:37,650 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [384434021] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:37,651 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:37,651 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 22:17:37,651 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1100913325] [2021-12-06 22:17:37,651 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:37,651 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:17:37,652 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:37,652 INFO L85 PathProgramCache]: Analyzing trace with hash -1992565206, now seen corresponding path program 1 times [2021-12-06 22:17:37,652 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:37,652 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [10075791] [2021-12-06 22:17:37,652 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:37,652 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:37,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:37,676 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:37,677 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:37,677 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [10075791] [2021-12-06 22:17:37,677 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [10075791] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:37,677 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:37,677 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:37,677 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [134152623] [2021-12-06 22:17:37,677 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:37,678 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:17:37,678 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:17:37,678 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:17:37,678 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:17:37,678 INFO L87 Difference]: Start difference. First operand 13391 states and 18516 transitions. cyclomatic complexity: 5129 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:37,723 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:17:37,723 INFO L93 Difference]: Finished difference Result 8956 states and 12399 transitions. [2021-12-06 22:17:37,723 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:17:37,724 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8956 states and 12399 transitions. [2021-12-06 22:17:37,782 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8832 [2021-12-06 22:17:37,793 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8956 states to 8956 states and 12399 transitions. [2021-12-06 22:17:37,793 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8956 [2021-12-06 22:17:37,796 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8956 [2021-12-06 22:17:37,796 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8956 states and 12399 transitions. [2021-12-06 22:17:37,799 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:17:37,799 INFO L681 BuchiCegarLoop]: Abstraction has 8956 states and 12399 transitions. [2021-12-06 22:17:37,801 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8956 states and 12399 transitions. [2021-12-06 22:17:37,839 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8956 to 8956. [2021-12-06 22:17:37,843 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8956 states, 8956 states have (on average 1.3844350156319785) internal successors, (12399), 8955 states have internal predecessors, (12399), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:37,855 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8956 states to 8956 states and 12399 transitions. [2021-12-06 22:17:37,855 INFO L704 BuchiCegarLoop]: Abstraction has 8956 states and 12399 transitions. [2021-12-06 22:17:37,855 INFO L587 BuchiCegarLoop]: Abstraction has 8956 states and 12399 transitions. [2021-12-06 22:17:37,855 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-06 22:17:37,855 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8956 states and 12399 transitions. [2021-12-06 22:17:37,870 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8832 [2021-12-06 22:17:37,870 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:17:37,870 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:17:37,871 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:37,871 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:37,872 INFO L791 eck$LassoCheckResult]: Stem: 268685#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 268636#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 268637#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 268030#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 268031#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 268482#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 268483#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 268445#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 268358#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 268359#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 268349#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 268350#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 268307#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 268308#L754 assume !(0 == ~M_E~0); 268603#L754-2 assume !(0 == ~T1_E~0); 268235#L759-1 assume !(0 == ~T2_E~0); 268236#L764-1 assume !(0 == ~T3_E~0); 268651#L769-1 assume !(0 == ~T4_E~0); 268652#L774-1 assume !(0 == ~T5_E~0); 268521#L779-1 assume !(0 == ~T6_E~0); 268276#L784-1 assume !(0 == ~T7_E~0); 268277#L789-1 assume !(0 == ~E_1~0); 267945#L794-1 assume !(0 == ~E_2~0); 267946#L799-1 assume !(0 == ~E_3~0); 268654#L804-1 assume !(0 == ~E_4~0); 268655#L809-1 assume !(0 == ~E_5~0); 268362#L814-1 assume !(0 == ~E_6~0); 267869#L819-1 assume !(0 == ~E_7~0); 267870#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 268344#L361 assume !(1 == ~m_pc~0); 268345#L361-2 is_master_triggered_~__retres1~0#1 := 0; 268386#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 268152#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 268153#L930 assume !(0 != activate_threads_~tmp~1#1); 268516#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 268338#L380 assume !(1 == ~t1_pc~0); 267997#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 268541#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 268542#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 268684#L938 assume !(0 != activate_threads_~tmp___0~0#1); 268071#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 267998#L399 assume !(1 == ~t2_pc~0); 267999#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 268206#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 268556#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 268409#L946 assume !(0 != activate_threads_~tmp___1~0#1); 267903#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 267875#L418 assume !(1 == ~t3_pc~0); 267836#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 267837#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 268366#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 268615#L954 assume !(0 != activate_threads_~tmp___2~0#1); 268668#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 268608#L437 assume !(1 == ~t4_pc~0); 268486#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 268175#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 268000#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 268001#L962 assume !(0 != activate_threads_~tmp___3~0#1); 268456#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 268127#L456 assume !(1 == ~t5_pc~0); 268128#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 268232#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 268582#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 267894#L970 assume !(0 != activate_threads_~tmp___4~0#1); 267895#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 268015#L475 assume !(1 == ~t6_pc~0); 268016#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 268091#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 268092#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 267857#L978 assume !(0 != activate_threads_~tmp___5~0#1); 267858#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 268351#L494 assume !(1 == ~t7_pc~0); 268353#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 268393#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 268577#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 268578#L986 assume !(0 != activate_threads_~tmp___6~0#1); 268681#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 268576#L837 assume !(1 == ~M_E~0); 268412#L837-2 assume !(1 == ~T1_E~0); 267979#L842-1 assume !(1 == ~T2_E~0); 267980#L847-1 assume !(1 == ~T3_E~0); 268478#L852-1 assume !(1 == ~T4_E~0); 268571#L857-1 assume !(1 == ~T5_E~0); 268424#L862-1 assume !(1 == ~T6_E~0); 268425#L867-1 assume !(1 == ~T7_E~0); 268435#L872-1 assume !(1 == ~E_1~0); 268518#L877-1 assume !(1 == ~E_2~0); 268430#L882-1 assume !(1 == ~E_3~0); 268431#L887-1 assume !(1 == ~E_4~0); 268038#L892-1 assume !(1 == ~E_5~0); 268039#L897-1 assume !(1 == ~E_6~0); 268452#L902-1 assume !(1 == ~E_7~0); 268120#L907-1 assume { :end_inline_reset_delta_events } true; 268121#L1148-2 [2021-12-06 22:17:37,872 INFO L793 eck$LassoCheckResult]: Loop: 268121#L1148-2 assume !false; 267867#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 267868#L729 assume !false; 268271#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 268265#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 268212#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 268290#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 268332#L626 assume !(0 != eval_~tmp~0#1); 268333#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 276338#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 276337#L754-3 assume !(0 == ~M_E~0); 276336#L754-5 assume !(0 == ~T1_E~0); 276223#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 276222#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 276221#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 276219#L774-3 assume !(0 == ~T5_E~0); 276218#L779-3 assume !(0 == ~T6_E~0); 276217#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 276216#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 276215#L794-3 assume !(0 == ~E_2~0); 276214#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 276213#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 276212#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 276211#L814-3 assume !(0 == ~E_6~0); 276210#L819-3 assume !(0 == ~E_7~0); 276209#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 276208#L361-24 assume !(1 == ~m_pc~0); 276207#L361-26 is_master_triggered_~__retres1~0#1 := 0; 276206#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 276205#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 276204#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 276203#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 276202#L380-24 assume !(1 == ~t1_pc~0); 276200#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 276198#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 276196#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 276195#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 276193#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 268219#L399-24 assume !(1 == ~t2_pc~0); 268220#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 268275#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 268042#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 268043#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 268355#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 268356#L418-24 assume !(1 == ~t3_pc~0); 267949#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 267950#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 268357#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 268217#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 267896#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 267897#L437-24 assume !(1 == ~t4_pc~0); 268380#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 268661#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 268044#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 268045#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 268199#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 276192#L456-24 assume !(1 == ~t5_pc~0); 276190#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 276189#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 276188#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 276154#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 268580#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 268581#L475-24 assume !(1 == ~t6_pc~0); 268443#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 268444#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 268591#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 268592#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 267844#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 267845#L494-24 assume !(1 == ~t7_pc~0); 268429#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 268406#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 268296#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 268297#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 268165#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 268166#L837-3 assume !(1 == ~M_E~0); 268253#L837-5 assume !(1 == ~T1_E~0); 268574#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 268475#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 267885#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 267886#L857-3 assume !(1 == ~T5_E~0); 268632#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 268618#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 268534#L872-3 assume !(1 == ~E_1~0); 268535#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 268624#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 268648#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 268256#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 268251#L897-3 assume !(1 == ~E_6~0); 268252#L902-3 assume !(1 == ~E_7~0); 268446#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 268436#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 267872#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 268671#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 268599#L1167 assume !(0 == start_simulation_~tmp~3#1); 268476#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 268509#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 268283#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 268555#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 268594#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 268493#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 267850#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 267851#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 268121#L1148-2 [2021-12-06 22:17:37,872 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:37,872 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 2 times [2021-12-06 22:17:37,872 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:37,872 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1413024068] [2021-12-06 22:17:37,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:37,872 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:37,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:17:37,881 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:17:37,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:17:37,911 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:17:37,911 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:37,911 INFO L85 PathProgramCache]: Analyzing trace with hash -510434431, now seen corresponding path program 1 times [2021-12-06 22:17:37,911 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:37,911 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1814907065] [2021-12-06 22:17:37,912 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:37,912 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:37,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:37,931 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:37,931 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:37,931 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1814907065] [2021-12-06 22:17:37,932 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1814907065] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:37,932 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:37,932 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:37,932 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2122667353] [2021-12-06 22:17:37,932 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:37,932 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:17:37,932 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:17:37,932 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:17:37,932 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:17:37,933 INFO L87 Difference]: Start difference. First operand 8956 states and 12399 transitions. cyclomatic complexity: 3447 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:37,999 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:17:37,999 INFO L93 Difference]: Finished difference Result 16204 states and 22209 transitions. [2021-12-06 22:17:37,999 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:17:38,000 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16204 states and 22209 transitions. [2021-12-06 22:17:38,042 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 15988 [2021-12-06 22:17:38,068 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16204 states to 16204 states and 22209 transitions. [2021-12-06 22:17:38,068 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16204 [2021-12-06 22:17:38,074 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16204 [2021-12-06 22:17:38,074 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16204 states and 22209 transitions. [2021-12-06 22:17:38,080 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:17:38,080 INFO L681 BuchiCegarLoop]: Abstraction has 16204 states and 22209 transitions. [2021-12-06 22:17:38,085 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16204 states and 22209 transitions. [2021-12-06 22:17:38,158 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16204 to 16164. [2021-12-06 22:17:38,167 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16164 states, 16164 states have (on average 1.371504578074734) internal successors, (22169), 16163 states have internal predecessors, (22169), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:38,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16164 states to 16164 states and 22169 transitions. [2021-12-06 22:17:38,191 INFO L704 BuchiCegarLoop]: Abstraction has 16164 states and 22169 transitions. [2021-12-06 22:17:38,192 INFO L587 BuchiCegarLoop]: Abstraction has 16164 states and 22169 transitions. [2021-12-06 22:17:38,192 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-12-06 22:17:38,192 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16164 states and 22169 transitions. [2021-12-06 22:17:38,225 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 15956 [2021-12-06 22:17:38,225 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:17:38,225 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:17:38,226 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:38,226 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:38,226 INFO L791 eck$LassoCheckResult]: Stem: 293939#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 293871#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 293872#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 293199#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 293200#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 293688#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 293689#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 293643#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 293536#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 293537#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 293528#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 293529#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 293484#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 293485#L754 assume !(0 == ~M_E~0); 293823#L754-2 assume !(0 == ~T1_E~0); 293412#L759-1 assume !(0 == ~T2_E~0); 293413#L764-1 assume !(0 == ~T3_E~0); 293891#L769-1 assume !(0 == ~T4_E~0); 293892#L774-1 assume !(0 == ~T5_E~0); 293734#L779-1 assume !(0 == ~T6_E~0); 293451#L784-1 assume !(0 == ~T7_E~0); 293452#L789-1 assume 0 == ~E_1~0;~E_1~0 := 1; 293889#L794-1 assume !(0 == ~E_2~0); 293932#L799-1 assume !(0 == ~E_3~0); 293933#L804-1 assume !(0 == ~E_4~0); 293971#L809-1 assume !(0 == ~E_5~0); 293541#L814-1 assume !(0 == ~E_6~0); 293542#L819-1 assume !(0 == ~E_7~0); 293596#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 293597#L361 assume !(1 == ~m_pc~0); 293572#L361-2 is_master_triggered_~__retres1~0#1 := 0; 293573#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 293319#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 293320#L930 assume !(0 != activate_threads_~tmp~1#1); 293729#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 293793#L380 assume !(1 == ~t1_pc~0); 293934#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 293755#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 293756#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 293938#L938 assume !(0 != activate_threads_~tmp___0~0#1); 293237#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 293238#L399 assume !(1 == ~t2_pc~0); 293974#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 293973#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 293894#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 293895#L946 assume !(0 != activate_threads_~tmp___1~0#1); 293072#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 293040#L418 assume !(1 == ~t3_pc~0); 293041#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 293547#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 293548#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 293944#L954 assume !(0 != activate_threads_~tmp___2~0#1); 293945#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 293828#L437 assume !(1 == ~t4_pc~0); 293692#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 293693#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 293168#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 293169#L962 assume !(0 != activate_threads_~tmp___3~0#1); 293655#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 293656#L456 assume !(1 == ~t5_pc~0); 293409#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 293408#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 293797#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 293060#L970 assume !(0 != activate_threads_~tmp___4~0#1); 293061#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 293181#L475 assume !(1 == ~t6_pc~0); 293182#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 293962#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 293843#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 293023#L978 assume !(0 != activate_threads_~tmp___5~0#1); 293024#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 293532#L494 assume !(1 == ~t7_pc~0); 293534#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 293866#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 293788#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 293789#L986 assume !(0 != activate_threads_~tmp___6~0#1); 293926#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 293790#L837 assume !(1 == ~M_E~0); 293608#L837-2 assume !(1 == ~T1_E~0); 293148#L842-1 assume !(1 == ~T2_E~0); 293149#L847-1 assume !(1 == ~T3_E~0); 293683#L852-1 assume !(1 == ~T4_E~0); 293782#L857-1 assume !(1 == ~T5_E~0); 293618#L862-1 assume !(1 == ~T6_E~0); 293619#L867-1 assume !(1 == ~T7_E~0); 293631#L872-1 assume 1 == ~E_1~0;~E_1~0 := 2; 293733#L877-1 assume !(1 == ~E_2~0); 293627#L882-1 assume !(1 == ~E_3~0); 293628#L887-1 assume !(1 == ~E_4~0); 293205#L892-1 assume !(1 == ~E_5~0); 293206#L897-1 assume !(1 == ~E_6~0); 293650#L902-1 assume !(1 == ~E_7~0); 293285#L907-1 assume { :end_inline_reset_delta_events } true; 293286#L1148-2 [2021-12-06 22:17:38,227 INFO L793 eck$LassoCheckResult]: Loop: 293286#L1148-2 assume !false; 297264#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 297262#L729 assume !false; 297260#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 297201#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 297195#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 297193#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 297190#L626 assume !(0 != eval_~tmp~0#1); 297191#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 308220#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 308219#L754-3 assume !(0 == ~M_E~0); 308218#L754-5 assume !(0 == ~T1_E~0); 308217#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 308216#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 308215#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 308214#L774-3 assume !(0 == ~T5_E~0); 308213#L779-3 assume !(0 == ~T6_E~0); 308212#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 308190#L789-3 assume !(0 == ~E_1~0); 308189#L794-3 assume !(0 == ~E_2~0); 308187#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 308185#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 308183#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 308181#L814-3 assume !(0 == ~E_6~0); 308180#L819-3 assume !(0 == ~E_7~0); 308179#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 293730#L361-24 assume !(1 == ~m_pc~0); 293481#L361-26 is_master_triggered_~__retres1~0#1 := 0; 293482#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 293045#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 293046#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 293551#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 293635#L380-24 assume 1 == ~t1_pc~0; 293898#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 293640#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 293724#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 293768#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 308245#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 309041#L399-24 assume !(1 == ~t2_pc~0); 294717#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 309040#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 309039#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 309038#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 309037#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 309036#L418-24 assume !(1 == ~t3_pc~0); 309034#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 309033#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 309032#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 309031#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 309030#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 309029#L437-24 assume !(1 == ~t4_pc~0); 309028#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 309027#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 309026#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 293368#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 293369#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 293905#L456-24 assume 1 == ~t5_pc~0; 308896#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 308894#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 308893#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 308891#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 293794#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 293795#L475-24 assume !(1 == ~t6_pc~0); 302389#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 302388#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 302387#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 302385#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 302383#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 302381#L494-24 assume !(1 == ~t7_pc~0); 302378#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 302376#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 302374#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 302371#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 302369#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 302367#L837-3 assume !(1 == ~M_E~0); 302365#L837-5 assume !(1 == ~T1_E~0); 302362#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 302360#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 302358#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 302357#L857-3 assume !(1 == ~T5_E~0); 302355#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 302353#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 302351#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 302348#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 302346#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 302343#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 302341#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 302339#L897-3 assume !(1 == ~E_6~0); 302337#L902-3 assume !(1 == ~E_7~0); 302335#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 298707#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 298699#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 298697#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 298696#L1167 assume !(0 == start_simulation_~tmp~3#1); 298694#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 297393#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 297388#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 297382#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 297380#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 297378#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 297376#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 297374#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 293286#L1148-2 [2021-12-06 22:17:38,227 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:38,227 INFO L85 PathProgramCache]: Analyzing trace with hash -1593984694, now seen corresponding path program 1 times [2021-12-06 22:17:38,227 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:38,227 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [955723190] [2021-12-06 22:17:38,227 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:38,227 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:38,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:38,245 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:38,246 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:38,246 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [955723190] [2021-12-06 22:17:38,246 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [955723190] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:38,246 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:38,246 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:38,246 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [704771983] [2021-12-06 22:17:38,246 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:38,246 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:17:38,246 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:38,246 INFO L85 PathProgramCache]: Analyzing trace with hash -438701179, now seen corresponding path program 1 times [2021-12-06 22:17:38,247 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:38,247 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1376851705] [2021-12-06 22:17:38,247 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:38,247 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:38,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:38,267 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:38,268 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:38,268 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1376851705] [2021-12-06 22:17:38,268 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1376851705] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:38,268 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:38,268 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 22:17:38,268 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1126883421] [2021-12-06 22:17:38,268 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:38,269 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:17:38,269 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:17:38,269 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 22:17:38,269 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 22:17:38,269 INFO L87 Difference]: Start difference. First operand 16164 states and 22169 transitions. cyclomatic complexity: 6009 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:38,390 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:17:38,390 INFO L93 Difference]: Finished difference Result 23828 states and 32646 transitions. [2021-12-06 22:17:38,390 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 22:17:38,391 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23828 states and 32646 transitions. [2021-12-06 22:17:38,469 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 22496 [2021-12-06 22:17:38,520 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23828 states to 23828 states and 32646 transitions. [2021-12-06 22:17:38,520 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23828 [2021-12-06 22:17:38,530 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23828 [2021-12-06 22:17:38,530 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23828 states and 32646 transitions. [2021-12-06 22:17:38,541 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:17:38,541 INFO L681 BuchiCegarLoop]: Abstraction has 23828 states and 32646 transitions. [2021-12-06 22:17:38,552 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23828 states and 32646 transitions. [2021-12-06 22:17:38,697 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23828 to 16145. [2021-12-06 22:17:38,707 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16145 states, 16145 states have (on average 1.370517187983896) internal successors, (22127), 16144 states have internal predecessors, (22127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:38,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16145 states to 16145 states and 22127 transitions. [2021-12-06 22:17:38,737 INFO L704 BuchiCegarLoop]: Abstraction has 16145 states and 22127 transitions. [2021-12-06 22:17:38,737 INFO L587 BuchiCegarLoop]: Abstraction has 16145 states and 22127 transitions. [2021-12-06 22:17:38,737 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-12-06 22:17:38,737 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16145 states and 22127 transitions. [2021-12-06 22:17:38,777 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 15956 [2021-12-06 22:17:38,777 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:17:38,778 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:17:38,779 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:38,779 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:38,779 INFO L791 eck$LassoCheckResult]: Stem: 333911#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 333847#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 333848#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 333203#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 333204#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 333682#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 333683#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 333641#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 333539#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 333540#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 333531#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 333532#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 333486#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 333487#L754 assume !(0 == ~M_E~0); 333808#L754-2 assume !(0 == ~T1_E~0); 333412#L759-1 assume !(0 == ~T2_E~0); 333413#L764-1 assume !(0 == ~T3_E~0); 333866#L769-1 assume !(0 == ~T4_E~0); 333867#L774-1 assume !(0 == ~T5_E~0); 333721#L779-1 assume !(0 == ~T6_E~0); 333454#L784-1 assume !(0 == ~T7_E~0); 333455#L789-1 assume !(0 == ~E_1~0); 333117#L794-1 assume !(0 == ~E_2~0); 333118#L799-1 assume !(0 == ~E_3~0); 333873#L804-1 assume !(0 == ~E_4~0); 333874#L809-1 assume !(0 == ~E_5~0); 333545#L814-1 assume !(0 == ~E_6~0); 333040#L819-1 assume !(0 == ~E_7~0); 333041#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 333525#L361 assume !(1 == ~m_pc~0); 333526#L361-2 is_master_triggered_~__retres1~0#1 := 0; 333574#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 333322#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 333323#L930 assume !(0 != activate_threads_~tmp~1#1); 333716#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 333519#L380 assume !(1 == ~t1_pc~0); 333170#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 333740#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 333741#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 333910#L938 assume !(0 != activate_threads_~tmp___0~0#1); 333242#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 333243#L399 assume !(1 == ~t2_pc~0); 333930#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 333929#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 333868#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 333869#L946 assume !(0 != activate_threads_~tmp___1~0#1); 333076#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 333077#L418 assume !(1 == ~t3_pc~0); 333006#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 333007#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 333823#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 333824#L954 assume !(0 != activate_threads_~tmp___2~0#1); 333892#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 333893#L437 assume !(1 == ~t4_pc~0); 333928#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 333347#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 333348#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 333927#L962 assume !(0 != activate_threads_~tmp___3~0#1); 333926#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 333296#L456 assume !(1 == ~t5_pc~0); 333297#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 333797#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 333798#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 333925#L970 assume !(0 != activate_threads_~tmp___4~0#1); 333870#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 333871#L475 assume !(1 == ~t6_pc~0); 333836#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 333837#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 333821#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 333822#L978 assume !(0 != activate_threads_~tmp___5~0#1); 333880#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 333881#L494 assume !(1 == ~t7_pc~0); 333582#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 333583#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 333778#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 333779#L986 assume !(0 != activate_threads_~tmp___6~0#1); 333901#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 333902#L837 assume !(1 == ~M_E~0); 333606#L837-2 assume !(1 == ~T1_E~0); 333607#L842-1 assume !(1 == ~T2_E~0); 333923#L847-1 assume !(1 == ~T3_E~0); 333773#L852-1 assume !(1 == ~T4_E~0); 333774#L857-1 assume !(1 == ~T5_E~0); 333617#L862-1 assume !(1 == ~T6_E~0); 333618#L867-1 assume !(1 == ~T7_E~0); 333922#L872-1 assume !(1 == ~E_1~0); 333718#L877-1 assume !(1 == ~E_2~0); 333624#L882-1 assume !(1 == ~E_3~0); 333625#L887-1 assume !(1 == ~E_4~0); 333210#L892-1 assume !(1 == ~E_5~0); 333211#L897-1 assume !(1 == ~E_6~0); 333647#L902-1 assume !(1 == ~E_7~0); 333292#L907-1 assume { :end_inline_reset_delta_events } true; 333293#L1148-2 [2021-12-06 22:17:38,780 INFO L793 eck$LassoCheckResult]: Loop: 333293#L1148-2 assume !false; 333036#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 333037#L729 assume !false; 333451#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 333444#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 333387#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 333469#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 333511#L626 assume !(0 != eval_~tmp~0#1); 333512#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 348705#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 348704#L754-3 assume !(0 == ~M_E~0); 348703#L754-5 assume !(0 == ~T1_E~0); 348702#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 348694#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 348693#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 348690#L774-3 assume !(0 == ~T5_E~0); 348691#L779-3 assume !(0 == ~T6_E~0); 348692#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 348689#L789-3 assume !(0 == ~E_1~0); 348687#L794-3 assume !(0 == ~E_2~0); 348685#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 348683#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 348681#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 348679#L814-3 assume !(0 == ~E_6~0); 348677#L819-3 assume !(0 == ~E_7~0); 348675#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 348673#L361-24 assume !(1 == ~m_pc~0); 348671#L361-26 is_master_triggered_~__retres1~0#1 := 0; 348669#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 348667#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 348665#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 348663#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 348661#L380-24 assume !(1 == ~t1_pc~0); 348654#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 348653#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 348652#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 348650#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 333177#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 333178#L399-24 assume !(1 == ~t2_pc~0); 333394#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 348498#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 348496#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 348494#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 348492#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 348490#L418-24 assume !(1 == ~t3_pc~0); 348487#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 348485#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 348483#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 348481#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 348479#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 348477#L437-24 assume !(1 == ~t4_pc~0); 348475#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 348473#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 348471#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 348469#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 348466#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 348464#L456-24 assume !(1 == ~t5_pc~0); 348461#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 348459#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 348456#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 348455#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 348453#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 348454#L475-24 assume !(1 == ~t6_pc~0); 333639#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 333640#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 333793#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 333794#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 349009#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 349008#L494-24 assume !(1 == ~t7_pc~0); 348998#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 348997#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 348996#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 348995#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 348994#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 348993#L837-3 assume !(1 == ~M_E~0); 348992#L837-5 assume !(1 == ~T1_E~0); 348991#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 348990#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 348989#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 348988#L857-3 assume !(1 == ~T5_E~0); 348987#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 348986#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 348985#L872-3 assume !(1 == ~E_1~0); 333736#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 333831#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 333862#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 333435#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 333428#L897-3 assume !(1 == ~E_6~0); 333429#L902-3 assume !(1 == ~E_7~0); 333642#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 333631#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 333043#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 333895#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 333805#L1167 assume !(0 == start_simulation_~tmp~3#1); 333674#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 333709#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 333462#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 333756#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 333796#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 333692#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 333020#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 333021#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 333293#L1148-2 [2021-12-06 22:17:38,780 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:38,780 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 3 times [2021-12-06 22:17:38,780 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:38,780 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [68118850] [2021-12-06 22:17:38,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:38,781 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:38,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:17:38,788 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:17:38,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:17:38,806 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:17:38,806 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:38,807 INFO L85 PathProgramCache]: Analyzing trace with hash 1905401919, now seen corresponding path program 1 times [2021-12-06 22:17:38,807 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:38,807 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [233430344] [2021-12-06 22:17:38,807 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:38,807 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:38,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:38,829 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:38,829 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:38,829 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [233430344] [2021-12-06 22:17:38,830 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [233430344] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:38,830 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:38,830 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 22:17:38,830 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [36947344] [2021-12-06 22:17:38,830 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:38,830 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:17:38,831 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:17:38,831 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-06 22:17:38,831 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-06 22:17:38,831 INFO L87 Difference]: Start difference. First operand 16145 states and 22127 transitions. cyclomatic complexity: 5986 Second operand has 5 states, 5 states have (on average 20.4) internal successors, (102), 5 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:38,982 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:17:38,982 INFO L93 Difference]: Finished difference Result 29293 states and 39879 transitions. [2021-12-06 22:17:38,983 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-06 22:17:38,983 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29293 states and 39879 transitions. [2021-12-06 22:17:39,094 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 29064 [2021-12-06 22:17:39,162 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29293 states to 29293 states and 39879 transitions. [2021-12-06 22:17:39,163 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29293 [2021-12-06 22:17:39,178 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29293 [2021-12-06 22:17:39,178 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29293 states and 39879 transitions. [2021-12-06 22:17:39,192 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:17:39,192 INFO L681 BuchiCegarLoop]: Abstraction has 29293 states and 39879 transitions. [2021-12-06 22:17:39,206 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29293 states and 39879 transitions. [2021-12-06 22:17:39,339 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29293 to 16241. [2021-12-06 22:17:39,349 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16241 states, 16241 states have (on average 1.368327073456068) internal successors, (22223), 16240 states have internal predecessors, (22223), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:39,379 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16241 states to 16241 states and 22223 transitions. [2021-12-06 22:17:39,379 INFO L704 BuchiCegarLoop]: Abstraction has 16241 states and 22223 transitions. [2021-12-06 22:17:39,379 INFO L587 BuchiCegarLoop]: Abstraction has 16241 states and 22223 transitions. [2021-12-06 22:17:39,379 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-12-06 22:17:39,379 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16241 states and 22223 transitions. [2021-12-06 22:17:39,418 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 16052 [2021-12-06 22:17:39,419 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:17:39,419 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:17:39,420 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:39,420 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:39,421 INFO L791 eck$LassoCheckResult]: Stem: 379397#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 379331#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 379332#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 378658#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 378659#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 379149#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 379150#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 379108#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 379000#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 379001#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 378989#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 378990#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 378949#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 378950#L754 assume !(0 == ~M_E~0); 379280#L754-2 assume !(0 == ~T1_E~0); 378874#L759-1 assume !(0 == ~T2_E~0); 378875#L764-1 assume !(0 == ~T3_E~0); 379351#L769-1 assume !(0 == ~T4_E~0); 379352#L774-1 assume !(0 == ~T5_E~0); 379189#L779-1 assume !(0 == ~T6_E~0); 378915#L784-1 assume !(0 == ~T7_E~0); 378916#L789-1 assume !(0 == ~E_1~0); 378569#L794-1 assume !(0 == ~E_2~0); 378570#L799-1 assume !(0 == ~E_3~0); 379359#L804-1 assume !(0 == ~E_4~0); 379360#L809-1 assume !(0 == ~E_5~0); 379006#L814-1 assume !(0 == ~E_6~0); 378490#L819-1 assume !(0 == ~E_7~0); 378491#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 378986#L361 assume !(1 == ~m_pc~0); 378987#L361-2 is_master_triggered_~__retres1~0#1 := 0; 379039#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 378779#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 378780#L930 assume !(0 != activate_threads_~tmp~1#1); 379185#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 378980#L380 assume !(1 == ~t1_pc~0); 378625#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 379210#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 379211#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 379396#L938 assume !(0 != activate_threads_~tmp___0~0#1); 378697#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 378698#L399 assume !(1 == ~t2_pc~0); 378839#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 378840#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 379224#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 379065#L946 assume !(0 != activate_threads_~tmp___1~0#1); 379066#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 378498#L418 assume !(1 == ~t3_pc~0); 378499#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 379011#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 379012#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 379404#L954 assume !(0 != activate_threads_~tmp___2~0#1); 379405#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 379282#L437 assume !(1 == ~t4_pc~0); 379153#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 379154#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 378628#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 378629#L962 assume !(0 != activate_threads_~tmp___3~0#1); 379122#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 379123#L456 assume !(1 == ~t5_pc~0); 378871#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 378870#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 379254#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 378518#L970 assume !(0 != activate_threads_~tmp___4~0#1); 378519#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 378641#L475 assume !(1 == ~t6_pc~0); 378642#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 378718#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 378719#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 379417#L978 assume !(0 != activate_threads_~tmp___5~0#1); 379368#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 379369#L494 assume !(1 == ~t7_pc~0); 379045#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 379046#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 379245#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 379246#L986 assume !(0 != activate_threads_~tmp___6~0#1); 379394#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 379243#L837 assume !(1 == ~M_E~0); 379244#L837-2 assume !(1 == ~T1_E~0); 378608#L842-1 assume !(1 == ~T2_E~0); 378609#L847-1 assume !(1 == ~T3_E~0); 379143#L852-1 assume !(1 == ~T4_E~0); 379235#L857-1 assume !(1 == ~T5_E~0); 379409#L862-1 assume !(1 == ~T6_E~0); 379411#L867-1 assume !(1 == ~T7_E~0); 379410#L872-1 assume !(1 == ~E_1~0); 379188#L877-1 assume !(1 == ~E_2~0); 379093#L882-1 assume !(1 == ~E_3~0); 379094#L887-1 assume !(1 == ~E_4~0); 378665#L892-1 assume !(1 == ~E_5~0); 378666#L897-1 assume !(1 == ~E_6~0); 379117#L902-1 assume !(1 == ~E_7~0); 378746#L907-1 assume { :end_inline_reset_delta_events } true; 378747#L1148-2 [2021-12-06 22:17:39,421 INFO L793 eck$LassoCheckResult]: Loop: 378747#L1148-2 assume !false; 383001#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 382955#L729 assume !false; 382930#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 382922#L569 assume !(0 == ~m_st~0); 382923#L573 assume !(0 == ~t1_st~0); 382926#L577 assume !(0 == ~t2_st~0); 382920#L581 assume !(0 == ~t3_st~0); 382921#L585 assume !(0 == ~t4_st~0); 382925#L589 assume !(0 == ~t5_st~0); 382918#L593 assume !(0 == ~t6_st~0); 382919#L597 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 382924#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 381454#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 381455#L626 assume !(0 != eval_~tmp~0#1); 383202#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 383200#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 383198#L754-3 assume !(0 == ~M_E~0); 383196#L754-5 assume !(0 == ~T1_E~0); 383194#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 383192#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 383190#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 383188#L774-3 assume !(0 == ~T5_E~0); 383186#L779-3 assume !(0 == ~T6_E~0); 383184#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 383182#L789-3 assume !(0 == ~E_1~0); 383180#L794-3 assume !(0 == ~E_2~0); 383178#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 383176#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 383174#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 383172#L814-3 assume !(0 == ~E_6~0); 383170#L819-3 assume !(0 == ~E_7~0); 383168#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 383166#L361-24 assume !(1 == ~m_pc~0); 383164#L361-26 is_master_triggered_~__retres1~0#1 := 0; 383162#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 383160#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 383158#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 383156#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 383153#L380-24 assume !(1 == ~t1_pc~0); 383149#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 383146#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 383143#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 383140#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 383138#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 383136#L399-24 assume !(1 == ~t2_pc~0); 382116#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 383134#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 383132#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 383130#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 383128#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 383126#L418-24 assume 1 == ~t3_pc~0; 383123#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 383120#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 383118#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 383116#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 383114#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 383112#L437-24 assume !(1 == ~t4_pc~0); 383110#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 383108#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 383106#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 383104#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 383102#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 383100#L456-24 assume 1 == ~t5_pc~0; 383097#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 383094#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 383092#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 383090#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 383088#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 383086#L475-24 assume !(1 == ~t6_pc~0); 382487#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 383084#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 383082#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 383080#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 383078#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 383075#L494-24 assume !(1 == ~t7_pc~0); 383072#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 383070#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 383068#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 383066#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 383064#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 383062#L837-3 assume !(1 == ~M_E~0); 383060#L837-5 assume !(1 == ~T1_E~0); 383058#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 383056#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 383054#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 383052#L857-3 assume !(1 == ~T5_E~0); 383050#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 383048#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 383046#L872-3 assume !(1 == ~E_1~0); 383045#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 383044#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 383043#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 383042#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 383041#L897-3 assume !(1 == ~E_6~0); 383040#L902-3 assume !(1 == ~E_7~0); 383039#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 383037#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 383029#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 383027#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 383024#L1167 assume !(0 == start_simulation_~tmp~3#1); 383022#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 383018#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 383013#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 383012#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 383011#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 383010#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 383008#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 383006#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 378747#L1148-2 [2021-12-06 22:17:39,421 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:39,421 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 4 times [2021-12-06 22:17:39,421 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:39,422 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2056823014] [2021-12-06 22:17:39,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:39,422 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:39,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:17:39,429 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:17:39,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:17:39,446 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:17:39,446 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:39,446 INFO L85 PathProgramCache]: Analyzing trace with hash 747731205, now seen corresponding path program 1 times [2021-12-06 22:17:39,446 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:39,446 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1540143290] [2021-12-06 22:17:39,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:39,447 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:39,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:39,493 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:39,493 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:39,493 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1540143290] [2021-12-06 22:17:39,493 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1540143290] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:39,493 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:39,493 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 22:17:39,493 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1026366915] [2021-12-06 22:17:39,494 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:39,494 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:17:39,494 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:17:39,494 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-06 22:17:39,494 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-06 22:17:39,495 INFO L87 Difference]: Start difference. First operand 16241 states and 22223 transitions. cyclomatic complexity: 5986 Second operand has 5 states, 5 states have (on average 21.8) internal successors, (109), 5 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:39,645 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:17:39,645 INFO L93 Difference]: Finished difference Result 19929 states and 27326 transitions. [2021-12-06 22:17:39,645 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-06 22:17:39,646 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19929 states and 27326 transitions. [2021-12-06 22:17:39,730 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 19724 [2021-12-06 22:17:39,774 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19929 states to 19929 states and 27326 transitions. [2021-12-06 22:17:39,775 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19929 [2021-12-06 22:17:39,784 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19929 [2021-12-06 22:17:39,784 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19929 states and 27326 transitions. [2021-12-06 22:17:39,794 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:17:39,794 INFO L681 BuchiCegarLoop]: Abstraction has 19929 states and 27326 transitions. [2021-12-06 22:17:39,803 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19929 states and 27326 transitions. [2021-12-06 22:17:39,920 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19929 to 16265. [2021-12-06 22:17:39,930 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16265 states, 16265 states have (on average 1.3559176145096834) internal successors, (22054), 16264 states have internal predecessors, (22054), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:39,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16265 states to 16265 states and 22054 transitions. [2021-12-06 22:17:39,961 INFO L704 BuchiCegarLoop]: Abstraction has 16265 states and 22054 transitions. [2021-12-06 22:17:39,961 INFO L587 BuchiCegarLoop]: Abstraction has 16265 states and 22054 transitions. [2021-12-06 22:17:39,961 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-12-06 22:17:39,961 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16265 states and 22054 transitions. [2021-12-06 22:17:40,001 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 16076 [2021-12-06 22:17:40,002 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:17:40,002 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:17:40,003 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:40,003 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:40,004 INFO L791 eck$LassoCheckResult]: Stem: 415662#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 415564#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 415565#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 414839#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 414840#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 415360#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 415361#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 415305#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 415194#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 415195#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 415184#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 415185#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 415140#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 415141#L754 assume !(0 == ~M_E~0); 415512#L754-2 assume !(0 == ~T1_E~0); 415058#L759-1 assume !(0 == ~T2_E~0); 415059#L764-1 assume !(0 == ~T3_E~0); 415596#L769-1 assume !(0 == ~T4_E~0); 415597#L774-1 assume !(0 == ~T5_E~0); 415402#L779-1 assume !(0 == ~T6_E~0); 415102#L784-1 assume !(0 == ~T7_E~0); 415103#L789-1 assume !(0 == ~E_1~0); 414751#L794-1 assume !(0 == ~E_2~0); 414752#L799-1 assume !(0 == ~E_3~0); 415604#L804-1 assume !(0 == ~E_4~0); 415605#L809-1 assume !(0 == ~E_5~0); 415199#L814-1 assume !(0 == ~E_6~0); 414672#L819-1 assume !(0 == ~E_7~0); 414673#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 415181#L361 assume !(1 == ~m_pc~0); 415182#L361-2 is_master_triggered_~__retres1~0#1 := 0; 415230#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 414959#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 414960#L930 assume !(0 != activate_threads_~tmp~1#1); 415399#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 415172#L380 assume !(1 == ~t1_pc~0); 414806#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 415427#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 415428#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 415661#L938 assume !(0 != activate_threads_~tmp___0~0#1); 414879#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 414880#L399 assume !(1 == ~t2_pc~0); 415023#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 415024#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 415447#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 415258#L946 assume !(0 != activate_threads_~tmp___1~0#1); 415259#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 414680#L418 assume !(1 == ~t3_pc~0); 414681#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 415203#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 415204#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 415674#L954 assume !(0 != activate_threads_~tmp___2~0#1); 415675#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 415513#L437 assume !(1 == ~t4_pc~0); 415364#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 415365#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 414809#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 414810#L962 assume !(0 != activate_threads_~tmp___3~0#1); 415319#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 415320#L456 assume !(1 == ~t5_pc~0); 415055#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 415054#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 415480#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 414700#L970 assume !(0 != activate_threads_~tmp___4~0#1); 414701#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 414822#L475 assume !(1 == ~t6_pc~0); 414823#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 414901#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 414902#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 415692#L978 assume !(0 != activate_threads_~tmp___5~0#1); 415614#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 415615#L494 assume !(1 == ~t7_pc~0); 415237#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 415238#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 415464#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 415465#L986 assume !(0 != activate_threads_~tmp___6~0#1); 415659#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 415466#L837 assume !(1 == ~M_E~0); 415467#L837-2 assume !(1 == ~T1_E~0); 414789#L842-1 assume !(1 == ~T2_E~0); 414790#L847-1 assume !(1 == ~T3_E~0); 415354#L852-1 assume !(1 == ~T4_E~0); 415458#L857-1 assume !(1 == ~T5_E~0); 415679#L862-1 assume !(1 == ~T6_E~0); 415686#L867-1 assume !(1 == ~T7_E~0); 415685#L872-1 assume !(1 == ~E_1~0); 415401#L877-1 assume !(1 == ~E_2~0); 415286#L882-1 assume !(1 == ~E_3~0); 415287#L887-1 assume !(1 == ~E_4~0); 414846#L892-1 assume !(1 == ~E_5~0); 414847#L897-1 assume !(1 == ~E_6~0); 415313#L902-1 assume !(1 == ~E_7~0); 414928#L907-1 assume { :end_inline_reset_delta_events } true; 414929#L1148-2 [2021-12-06 22:17:40,004 INFO L793 eck$LassoCheckResult]: Loop: 414929#L1148-2 assume !false; 419077#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 419076#L729 assume !false; 419075#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 419070#L569 assume !(0 == ~m_st~0); 419071#L573 assume !(0 == ~t1_st~0); 419074#L577 assume !(0 == ~t2_st~0); 419068#L581 assume !(0 == ~t3_st~0); 419069#L585 assume !(0 == ~t4_st~0); 419073#L589 assume !(0 == ~t5_st~0); 419066#L593 assume !(0 == ~t6_st~0); 419067#L597 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 419072#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 418809#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 418810#L626 assume !(0 != eval_~tmp~0#1); 419413#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 419679#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 419678#L754-3 assume !(0 == ~M_E~0); 419677#L754-5 assume !(0 == ~T1_E~0); 419676#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 419675#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 419674#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 419673#L774-3 assume !(0 == ~T5_E~0); 419672#L779-3 assume !(0 == ~T6_E~0); 419671#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 419670#L789-3 assume !(0 == ~E_1~0); 419669#L794-3 assume !(0 == ~E_2~0); 419668#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 419667#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 419666#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 419665#L814-3 assume !(0 == ~E_6~0); 419664#L819-3 assume !(0 == ~E_7~0); 419663#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 419662#L361-24 assume !(1 == ~m_pc~0); 419661#L361-26 is_master_triggered_~__retres1~0#1 := 0; 419660#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 419659#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 419658#L930-24 assume !(0 != activate_threads_~tmp~1#1); 419657#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 419656#L380-24 assume 1 == ~t1_pc~0; 419654#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 419655#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 419723#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 419326#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 419323#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 419321#L399-24 assume !(1 == ~t2_pc~0); 419319#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 419317#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 419315#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 419313#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 419309#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 419305#L418-24 assume !(1 == ~t3_pc~0); 419300#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 419295#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 419291#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 419287#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 419283#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 419277#L437-24 assume !(1 == ~t4_pc~0); 419273#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 419269#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 419265#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 419261#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 419257#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 419253#L456-24 assume !(1 == ~t5_pc~0); 419248#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 419243#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 419239#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 419235#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 419231#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 419225#L475-24 assume !(1 == ~t6_pc~0); 416688#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 419219#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 419215#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 419211#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 419207#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 419205#L494-24 assume !(1 == ~t7_pc~0); 419199#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 419195#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 419191#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 419187#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 419181#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 419177#L837-3 assume !(1 == ~M_E~0); 419173#L837-5 assume !(1 == ~T1_E~0); 419169#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 419165#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 419161#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 419157#L857-3 assume !(1 == ~T5_E~0); 419153#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 419149#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 419145#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 419141#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 419138#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 419135#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 419123#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 419120#L897-3 assume !(1 == ~E_6~0); 419118#L902-3 assume !(1 == ~E_7~0); 419116#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 419113#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 419105#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 419103#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 419100#L1167 assume !(0 == start_simulation_~tmp~3#1); 419098#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 419094#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 419089#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 419088#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 419087#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 419086#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 419084#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 419082#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 414929#L1148-2 [2021-12-06 22:17:40,004 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:40,004 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 5 times [2021-12-06 22:17:40,004 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:40,004 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1059924350] [2021-12-06 22:17:40,005 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:40,005 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:40,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:17:40,014 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:17:40,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:17:40,032 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:17:40,032 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:40,032 INFO L85 PathProgramCache]: Analyzing trace with hash -982160730, now seen corresponding path program 1 times [2021-12-06 22:17:40,032 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:40,033 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [197094200] [2021-12-06 22:17:40,033 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:40,033 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:40,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:40,054 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:40,054 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:40,054 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [197094200] [2021-12-06 22:17:40,055 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [197094200] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:40,055 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:40,055 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:40,055 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [471323154] [2021-12-06 22:17:40,055 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:40,055 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 22:17:40,056 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:17:40,056 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:17:40,056 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:17:40,056 INFO L87 Difference]: Start difference. First operand 16265 states and 22054 transitions. cyclomatic complexity: 5793 Second operand has 3 states, 3 states have (on average 36.333333333333336) internal successors, (109), 3 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:40,162 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:17:40,163 INFO L93 Difference]: Finished difference Result 27243 states and 36568 transitions. [2021-12-06 22:17:40,163 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:17:40,163 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27243 states and 36568 transitions. [2021-12-06 22:17:40,260 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 27020 [2021-12-06 22:17:40,322 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27243 states to 27243 states and 36568 transitions. [2021-12-06 22:17:40,323 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27243 [2021-12-06 22:17:40,336 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27243 [2021-12-06 22:17:40,336 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27243 states and 36568 transitions. [2021-12-06 22:17:40,350 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:17:40,350 INFO L681 BuchiCegarLoop]: Abstraction has 27243 states and 36568 transitions. [2021-12-06 22:17:40,362 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27243 states and 36568 transitions. [2021-12-06 22:17:40,536 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27243 to 27243. [2021-12-06 22:17:40,553 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27243 states, 27243 states have (on average 1.3422897625078) internal successors, (36568), 27242 states have internal predecessors, (36568), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:40,605 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27243 states to 27243 states and 36568 transitions. [2021-12-06 22:17:40,605 INFO L704 BuchiCegarLoop]: Abstraction has 27243 states and 36568 transitions. [2021-12-06 22:17:40,605 INFO L587 BuchiCegarLoop]: Abstraction has 27243 states and 36568 transitions. [2021-12-06 22:17:40,605 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-12-06 22:17:40,605 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27243 states and 36568 transitions. [2021-12-06 22:17:40,679 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 27020 [2021-12-06 22:17:40,680 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:17:40,680 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:17:40,681 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:40,681 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:40,681 INFO L791 eck$LassoCheckResult]: Stem: 459105#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 459020#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 459021#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 458354#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 458355#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 458830#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 458831#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 458789#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 458691#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 458692#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 458683#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 458684#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 458643#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 458644#L754 assume !(0 == ~M_E~0); 458974#L754-2 assume !(0 == ~T1_E~0); 458567#L759-1 assume !(0 == ~T2_E~0); 458568#L764-1 assume !(0 == ~T3_E~0); 459046#L769-1 assume !(0 == ~T4_E~0); 459047#L774-1 assume !(0 == ~T5_E~0); 458875#L779-1 assume !(0 == ~T6_E~0); 458610#L784-1 assume !(0 == ~T7_E~0); 458611#L789-1 assume !(0 == ~E_1~0); 458265#L794-1 assume !(0 == ~E_2~0); 458266#L799-1 assume !(0 == ~E_3~0); 459054#L804-1 assume !(0 == ~E_4~0); 459055#L809-1 assume !(0 == ~E_5~0); 458696#L814-1 assume !(0 == ~E_6~0); 458186#L819-1 assume !(0 == ~E_7~0); 458187#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 458680#L361 assume !(1 == ~m_pc~0); 458681#L361-2 is_master_triggered_~__retres1~0#1 := 0; 458725#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 458474#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 458475#L930 assume !(0 != activate_threads_~tmp~1#1); 458872#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 458674#L380 assume !(1 == ~t1_pc~0); 458321#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 458896#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 458897#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 459104#L938 assume !(0 != activate_threads_~tmp___0~0#1); 458394#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 458395#L399 assume !(1 == ~t2_pc~0); 458532#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 458533#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 458913#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 458751#L946 assume !(0 != activate_threads_~tmp___1~0#1); 458752#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 458194#L418 assume !(1 == ~t3_pc~0); 458195#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 458700#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 458701#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 459111#L954 assume !(0 != activate_threads_~tmp___2~0#1); 459112#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 458978#L437 assume !(1 == ~t4_pc~0); 458834#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 458835#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 458324#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 458325#L962 assume !(0 != activate_threads_~tmp___3~0#1); 458799#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 458800#L456 assume !(1 == ~t5_pc~0); 458564#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 458563#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 458943#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 458214#L970 assume !(0 != activate_threads_~tmp___4~0#1); 458215#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 458337#L475 assume !(1 == ~t6_pc~0); 458338#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 458414#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 458415#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 459122#L978 assume !(0 != activate_threads_~tmp___5~0#1); 459062#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 459063#L494 assume !(1 == ~t7_pc~0); 458732#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 458733#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 458936#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 458937#L986 assume !(0 != activate_threads_~tmp___6~0#1); 459100#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 458938#L837 assume !(1 == ~M_E~0); 458939#L837-2 assume !(1 == ~T1_E~0); 458303#L842-1 assume !(1 == ~T2_E~0); 458304#L847-1 assume !(1 == ~T3_E~0); 458826#L852-1 assume !(1 == ~T4_E~0); 458927#L857-1 assume !(1 == ~T5_E~0); 459113#L862-1 assume !(1 == ~T6_E~0); 459116#L867-1 assume !(1 == ~T7_E~0); 459115#L872-1 assume !(1 == ~E_1~0); 458874#L877-1 assume !(1 == ~E_2~0); 458776#L882-1 assume !(1 == ~E_3~0); 458777#L887-1 assume !(1 == ~E_4~0); 458361#L892-1 assume !(1 == ~E_5~0); 458362#L897-1 assume !(1 == ~E_6~0); 458794#L902-1 assume !(1 == ~E_7~0); 458441#L907-1 assume { :end_inline_reset_delta_events } true; 458442#L1148-2 assume !false; 473162#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 473156#L729 [2021-12-06 22:17:40,681 INFO L793 eck$LassoCheckResult]: Loop: 473156#L729 assume !false; 473151#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 473146#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 473140#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 473132#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 473123#L626 assume 0 != eval_~tmp~0#1; 473116#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 473110#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 473101#L631 assume !(0 == ~t1_st~0); 473093#L645 assume !(0 == ~t2_st~0); 473083#L659 assume !(0 == ~t3_st~0); 473075#L673 assume !(0 == ~t4_st~0); 473065#L687 assume !(0 == ~t5_st~0); 473058#L701 assume !(0 == ~t6_st~0); 473054#L715 assume !(0 == ~t7_st~0); 473156#L729 [2021-12-06 22:17:40,681 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:40,682 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 1 times [2021-12-06 22:17:40,682 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:40,682 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [778485058] [2021-12-06 22:17:40,682 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:40,682 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:40,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:17:40,693 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:17:40,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:17:40,714 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:17:40,714 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:40,714 INFO L85 PathProgramCache]: Analyzing trace with hash -1503391009, now seen corresponding path program 1 times [2021-12-06 22:17:40,714 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:40,715 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1020810120] [2021-12-06 22:17:40,715 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:40,715 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:40,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:17:40,717 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:17:40,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:17:40,720 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:17:40,720 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:40,720 INFO L85 PathProgramCache]: Analyzing trace with hash -1562289544, now seen corresponding path program 1 times [2021-12-06 22:17:40,720 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:40,720 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [338511193] [2021-12-06 22:17:40,720 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:40,720 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:40,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:40,738 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:40,738 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:40,738 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [338511193] [2021-12-06 22:17:40,739 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [338511193] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:40,739 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:40,739 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:40,739 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [73826632] [2021-12-06 22:17:40,739 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:40,807 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:17:40,807 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:17:40,807 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:17:40,807 INFO L87 Difference]: Start difference. First operand 27243 states and 36568 transitions. cyclomatic complexity: 9333 Second operand has 3 states, 3 states have (on average 36.666666666666664) internal successors, (110), 3 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:40,925 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:17:40,925 INFO L93 Difference]: Finished difference Result 49528 states and 66201 transitions. [2021-12-06 22:17:40,926 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:17:40,926 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 49528 states and 66201 transitions. [2021-12-06 22:17:41,117 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 49088 [2021-12-06 22:17:41,197 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 49528 states to 49528 states and 66201 transitions. [2021-12-06 22:17:41,197 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 49528 [2021-12-06 22:17:41,214 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 49528 [2021-12-06 22:17:41,214 INFO L73 IsDeterministic]: Start isDeterministic. Operand 49528 states and 66201 transitions. [2021-12-06 22:17:41,230 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:17:41,230 INFO L681 BuchiCegarLoop]: Abstraction has 49528 states and 66201 transitions. [2021-12-06 22:17:41,245 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49528 states and 66201 transitions. [2021-12-06 22:17:41,470 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49528 to 48104. [2021-12-06 22:17:41,497 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 48104 states, 48104 states have (on average 1.3376226509230003) internal successors, (64345), 48103 states have internal predecessors, (64345), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:41,567 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48104 states to 48104 states and 64345 transitions. [2021-12-06 22:17:41,567 INFO L704 BuchiCegarLoop]: Abstraction has 48104 states and 64345 transitions. [2021-12-06 22:17:41,567 INFO L587 BuchiCegarLoop]: Abstraction has 48104 states and 64345 transitions. [2021-12-06 22:17:41,567 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-12-06 22:17:41,567 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 48104 states and 64345 transitions. [2021-12-06 22:17:41,674 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 47664 [2021-12-06 22:17:41,675 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:17:41,675 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:17:41,675 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:41,675 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:41,676 INFO L791 eck$LassoCheckResult]: Stem: 535884#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 535817#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 535818#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 535136#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 535137#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 535623#L521-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 535624#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 556865#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 556864#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 556863#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 556862#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 556861#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 556860#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 556859#L754 assume !(0 == ~M_E~0); 556858#L754-2 assume !(0 == ~T1_E~0); 556857#L759-1 assume !(0 == ~T2_E~0); 556856#L764-1 assume !(0 == ~T3_E~0); 556855#L769-1 assume !(0 == ~T4_E~0); 556854#L774-1 assume !(0 == ~T5_E~0); 556853#L779-1 assume !(0 == ~T6_E~0); 556852#L784-1 assume !(0 == ~T7_E~0); 556851#L789-1 assume !(0 == ~E_1~0); 556850#L794-1 assume !(0 == ~E_2~0); 556849#L799-1 assume !(0 == ~E_3~0); 556848#L804-1 assume !(0 == ~E_4~0); 556847#L809-1 assume !(0 == ~E_5~0); 556846#L814-1 assume !(0 == ~E_6~0); 556845#L819-1 assume !(0 == ~E_7~0); 556844#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 556843#L361 assume !(1 == ~m_pc~0); 556842#L361-2 is_master_triggered_~__retres1~0#1 := 0; 556841#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 556840#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 556839#L930 assume !(0 != activate_threads_~tmp~1#1); 556838#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 556837#L380 assume !(1 == ~t1_pc~0); 556836#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 556925#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 556924#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 556923#L938 assume !(0 != activate_threads_~tmp___0~0#1); 556922#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 556921#L399 assume !(1 == ~t2_pc~0); 535311#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 535312#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 535712#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 535541#L946 assume !(0 != activate_threads_~tmp___1~0#1); 535542#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 535930#L418 assume !(1 == ~t3_pc~0); 535928#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 535490#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 535491#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 535893#L954 assume !(0 != activate_threads_~tmp___2~0#1); 535894#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 535769#L437 assume !(1 == ~t4_pc~0); 535628#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 535629#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 535105#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 535106#L962 assume !(0 != activate_threads_~tmp___3~0#1); 535594#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 535595#L456 assume !(1 == ~t5_pc~0); 535343#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 535342#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 535738#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 534994#L970 assume !(0 != activate_threads_~tmp___4~0#1); 534995#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 535120#L475 assume !(1 == ~t6_pc~0); 535121#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 535194#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 535195#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 535919#L978 assume !(0 != activate_threads_~tmp___5~0#1); 535920#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 535918#L494 assume !(1 == ~t7_pc~0); 535522#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 535523#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 535732#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 535733#L986 assume !(0 != activate_threads_~tmp___6~0#1); 535876#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 535877#L837 assume !(1 == ~M_E~0); 535545#L837-2 assume !(1 == ~T1_E~0); 535546#L842-1 assume !(1 == ~T2_E~0); 535908#L847-1 assume !(1 == ~T3_E~0); 535909#L852-1 assume !(1 == ~T4_E~0); 535899#L857-1 assume !(1 == ~T5_E~0); 535900#L862-1 assume !(1 == ~T6_E~0); 535902#L867-1 assume !(1 == ~T7_E~0); 535903#L872-1 assume !(1 == ~E_1~0); 556772#L877-1 assume !(1 == ~E_2~0); 535568#L882-1 assume !(1 == ~E_3~0); 535569#L887-1 assume !(1 == ~E_4~0); 556763#L892-1 assume !(1 == ~E_5~0); 535724#L897-1 assume !(1 == ~E_6~0); 535591#L902-1 assume !(1 == ~E_7~0); 535223#L907-1 assume { :end_inline_reset_delta_events } true; 535224#L1148-2 assume !false; 564136#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 564134#L729 [2021-12-06 22:17:41,676 INFO L793 eck$LassoCheckResult]: Loop: 564134#L729 assume !false; 564132#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 564128#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 564126#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 564124#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 564120#L626 assume 0 != eval_~tmp~0#1; 564117#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 564115#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 564106#L631 assume !(0 == ~t1_st~0); 564100#L645 assume !(0 == ~t2_st~0); 564058#L659 assume !(0 == ~t3_st~0); 564153#L673 assume !(0 == ~t4_st~0); 564150#L687 assume !(0 == ~t5_st~0); 564144#L701 assume !(0 == ~t6_st~0); 564140#L715 assume !(0 == ~t7_st~0); 564134#L729 [2021-12-06 22:17:41,676 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:41,676 INFO L85 PathProgramCache]: Analyzing trace with hash -439660602, now seen corresponding path program 1 times [2021-12-06 22:17:41,676 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:41,676 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1129036188] [2021-12-06 22:17:41,676 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:41,676 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:41,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:41,691 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:41,691 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:41,691 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1129036188] [2021-12-06 22:17:41,691 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1129036188] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:41,691 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:41,691 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:41,691 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [245572846] [2021-12-06 22:17:41,692 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:41,692 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 22:17:41,692 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:41,692 INFO L85 PathProgramCache]: Analyzing trace with hash -1503391009, now seen corresponding path program 2 times [2021-12-06 22:17:41,692 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:41,692 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [435402733] [2021-12-06 22:17:41,692 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:41,692 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:41,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:17:41,695 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:17:41,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:17:41,697 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:17:41,763 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:17:41,763 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:17:41,763 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:17:41,764 INFO L87 Difference]: Start difference. First operand 48104 states and 64345 transitions. cyclomatic complexity: 16249 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:41,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:17:41,860 INFO L93 Difference]: Finished difference Result 47959 states and 64151 transitions. [2021-12-06 22:17:41,860 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:17:41,861 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 47959 states and 64151 transitions. [2021-12-06 22:17:42,003 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 47664 [2021-12-06 22:17:42,094 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 47959 states to 47959 states and 64151 transitions. [2021-12-06 22:17:42,094 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 47959 [2021-12-06 22:17:42,115 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 47959 [2021-12-06 22:17:42,115 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47959 states and 64151 transitions. [2021-12-06 22:17:42,134 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:17:42,135 INFO L681 BuchiCegarLoop]: Abstraction has 47959 states and 64151 transitions. [2021-12-06 22:17:42,155 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47959 states and 64151 transitions. [2021-12-06 22:17:42,383 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47959 to 47959. [2021-12-06 22:17:42,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47959 states, 47959 states have (on average 1.3376217185512624) internal successors, (64151), 47958 states have internal predecessors, (64151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:42,484 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47959 states to 47959 states and 64151 transitions. [2021-12-06 22:17:42,484 INFO L704 BuchiCegarLoop]: Abstraction has 47959 states and 64151 transitions. [2021-12-06 22:17:42,484 INFO L587 BuchiCegarLoop]: Abstraction has 47959 states and 64151 transitions. [2021-12-06 22:17:42,484 INFO L425 BuchiCegarLoop]: ======== Iteration 29============ [2021-12-06 22:17:42,484 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 47959 states and 64151 transitions. [2021-12-06 22:17:42,595 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 47664 [2021-12-06 22:17:42,595 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:17:42,595 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:17:42,596 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:42,596 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:42,596 INFO L791 eck$LassoCheckResult]: Stem: 631919#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 631855#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 631856#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 631201#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 631202#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 631680#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 631681#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 631637#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 631535#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 631536#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 631526#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 631527#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 631484#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 631485#L754 assume !(0 == ~M_E~0); 631812#L754-2 assume !(0 == ~T1_E~0); 631412#L759-1 assume !(0 == ~T2_E~0); 631413#L764-1 assume !(0 == ~T3_E~0); 631872#L769-1 assume !(0 == ~T4_E~0); 631873#L774-1 assume !(0 == ~T5_E~0); 631722#L779-1 assume !(0 == ~T6_E~0); 631450#L784-1 assume !(0 == ~T7_E~0); 631451#L789-1 assume !(0 == ~E_1~0); 631117#L794-1 assume !(0 == ~E_2~0); 631118#L799-1 assume !(0 == ~E_3~0); 631878#L804-1 assume !(0 == ~E_4~0); 631879#L809-1 assume !(0 == ~E_5~0); 631539#L814-1 assume !(0 == ~E_6~0); 631038#L819-1 assume !(0 == ~E_7~0); 631039#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 631521#L361 assume !(1 == ~m_pc~0); 631522#L361-2 is_master_triggered_~__retres1~0#1 := 0; 631568#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 631322#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 631323#L930 assume !(0 != activate_threads_~tmp~1#1); 631717#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 631515#L380 assume !(1 == ~t1_pc~0); 631170#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 631916#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 631862#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 631863#L938 assume !(0 != activate_threads_~tmp___0~0#1); 631947#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 631166#L399 assume !(1 == ~t2_pc~0); 631167#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 631946#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 631874#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 631875#L946 assume !(0 != activate_threads_~tmp___1~0#1); 631074#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 631075#L418 assume !(1 == ~t3_pc~0); 631005#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 631006#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 631828#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 631829#L954 assume !(0 != activate_threads_~tmp___2~0#1); 631897#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 631898#L437 assume !(1 == ~t4_pc~0); 631945#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 631345#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 631346#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 631944#L962 assume !(0 != activate_threads_~tmp___3~0#1); 631943#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 631297#L456 assume !(1 == ~t5_pc~0); 631298#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 631801#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 631802#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 631942#L970 assume !(0 != activate_threads_~tmp___4~0#1); 631876#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 631877#L475 assume !(1 == ~t6_pc~0); 631840#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 631841#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 631827#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 631026#L978 assume !(0 != activate_threads_~tmp___5~0#1); 631027#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 631528#L494 assume !(1 == ~t7_pc~0); 631530#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 631849#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 631850#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 631939#L986 assume !(0 != activate_threads_~tmp___6~0#1); 631912#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 631913#L837 assume !(1 == ~M_E~0); 631601#L837-2 assume !(1 == ~T1_E~0); 631602#L842-1 assume !(1 == ~T2_E~0); 631938#L847-1 assume !(1 == ~T3_E~0); 631772#L852-1 assume !(1 == ~T4_E~0); 631773#L857-1 assume !(1 == ~T5_E~0); 631933#L862-1 assume !(1 == ~T6_E~0); 631936#L867-1 assume !(1 == ~T7_E~0); 631935#L872-1 assume !(1 == ~E_1~0); 631719#L877-1 assume !(1 == ~E_2~0); 631620#L882-1 assume !(1 == ~E_3~0); 631621#L887-1 assume !(1 == ~E_4~0); 631208#L892-1 assume !(1 == ~E_5~0); 631209#L897-1 assume !(1 == ~E_6~0); 631644#L902-1 assume !(1 == ~E_7~0); 631290#L907-1 assume { :end_inline_reset_delta_events } true; 631291#L1148-2 assume !false; 659435#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 659433#L729 [2021-12-06 22:17:42,597 INFO L793 eck$LassoCheckResult]: Loop: 659433#L729 assume !false; 659431#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 659428#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 659426#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 659424#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 659422#L626 assume 0 != eval_~tmp~0#1; 659418#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 659416#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 659415#L631 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 659031#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 659413#L645 assume !(0 == ~t2_st~0); 659452#L659 assume !(0 == ~t3_st~0); 659448#L673 assume !(0 == ~t4_st~0); 659446#L687 assume !(0 == ~t5_st~0); 659440#L701 assume !(0 == ~t6_st~0); 659439#L715 assume !(0 == ~t7_st~0); 659433#L729 [2021-12-06 22:17:42,597 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:42,597 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 2 times [2021-12-06 22:17:42,597 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:42,597 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [849128019] [2021-12-06 22:17:42,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:42,597 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:42,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:17:42,604 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:17:42,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:17:42,621 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:17:42,621 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:42,621 INFO L85 PathProgramCache]: Analyzing trace with hash -1848014684, now seen corresponding path program 1 times [2021-12-06 22:17:42,621 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:42,621 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [687870242] [2021-12-06 22:17:42,621 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:42,621 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:42,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:17:42,623 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:17:42,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:17:42,626 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:17:42,626 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:42,626 INFO L85 PathProgramCache]: Analyzing trace with hash 621098027, now seen corresponding path program 1 times [2021-12-06 22:17:42,626 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:42,626 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1373238213] [2021-12-06 22:17:42,626 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:42,626 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:42,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:42,644 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:42,644 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:42,644 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1373238213] [2021-12-06 22:17:42,644 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1373238213] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:42,644 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:42,644 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:42,644 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1907826351] [2021-12-06 22:17:42,644 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:42,772 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:17:42,772 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:17:42,772 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:17:42,772 INFO L87 Difference]: Start difference. First operand 47959 states and 64151 transitions. cyclomatic complexity: 16200 Second operand has 3 states, 3 states have (on average 37.0) internal successors, (111), 3 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:42,981 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:17:42,981 INFO L93 Difference]: Finished difference Result 92159 states and 122847 transitions. [2021-12-06 22:17:42,982 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:17:42,982 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 92159 states and 122847 transitions. [2021-12-06 22:17:43,283 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 91720 [2021-12-06 22:17:43,466 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 92159 states to 92159 states and 122847 transitions. [2021-12-06 22:17:43,466 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 92159 [2021-12-06 22:17:43,509 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 92159 [2021-12-06 22:17:43,509 INFO L73 IsDeterministic]: Start isDeterministic. Operand 92159 states and 122847 transitions. [2021-12-06 22:17:43,547 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:17:43,547 INFO L681 BuchiCegarLoop]: Abstraction has 92159 states and 122847 transitions. [2021-12-06 22:17:43,587 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 92159 states and 122847 transitions. [2021-12-06 22:17:44,053 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 92159 to 89727. [2021-12-06 22:17:44,106 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 89727 states, 89727 states have (on average 1.3338125647798322) internal successors, (119679), 89726 states have internal predecessors, (119679), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:44,241 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89727 states to 89727 states and 119679 transitions. [2021-12-06 22:17:44,241 INFO L704 BuchiCegarLoop]: Abstraction has 89727 states and 119679 transitions. [2021-12-06 22:17:44,241 INFO L587 BuchiCegarLoop]: Abstraction has 89727 states and 119679 transitions. [2021-12-06 22:17:44,241 INFO L425 BuchiCegarLoop]: ======== Iteration 30============ [2021-12-06 22:17:44,241 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 89727 states and 119679 transitions. [2021-12-06 22:17:44,460 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 89288 [2021-12-06 22:17:44,460 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:17:44,460 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:17:44,461 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:44,461 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:44,461 INFO L791 eck$LassoCheckResult]: Stem: 772072#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 772005#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 772006#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 771328#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 771329#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 771817#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 771818#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 771776#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 771673#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 771674#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 771665#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 771666#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 771621#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 771622#L754 assume !(0 == ~M_E~0); 771963#L754-2 assume !(0 == ~T1_E~0); 771542#L759-1 assume !(0 == ~T2_E~0); 771543#L764-1 assume !(0 == ~T3_E~0); 772023#L769-1 assume !(0 == ~T4_E~0); 772024#L774-1 assume !(0 == ~T5_E~0); 771864#L779-1 assume !(0 == ~T6_E~0); 771584#L784-1 assume !(0 == ~T7_E~0); 771585#L789-1 assume !(0 == ~E_1~0); 771239#L794-1 assume !(0 == ~E_2~0); 771240#L799-1 assume !(0 == ~E_3~0); 772030#L804-1 assume !(0 == ~E_4~0); 772031#L809-1 assume !(0 == ~E_5~0); 771678#L814-1 assume !(0 == ~E_6~0); 771160#L819-1 assume !(0 == ~E_7~0); 771161#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 771661#L361 assume !(1 == ~m_pc~0); 771662#L361-2 is_master_triggered_~__retres1~0#1 := 0; 771708#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 771450#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 771451#L930 assume !(0 != activate_threads_~tmp~1#1); 771861#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 771654#L380 assume !(1 == ~t1_pc~0); 771294#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 771886#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 771887#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 772071#L938 assume !(0 != activate_threads_~tmp___0~0#1); 771367#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 771368#L399 assume !(1 == ~t2_pc~0); 771510#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 771511#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 771902#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 771736#L946 assume !(0 != activate_threads_~tmp___1~0#1); 771737#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 771168#L418 assume !(1 == ~t3_pc~0); 771169#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 771683#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 771684#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 772078#L954 assume !(0 != activate_threads_~tmp___2~0#1); 772079#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 771965#L437 assume !(1 == ~t4_pc~0); 771821#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 771822#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 771297#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 771298#L962 assume !(0 != activate_threads_~tmp___3~0#1); 771787#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 771788#L456 assume !(1 == ~t5_pc~0); 771539#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 771538#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 771934#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 771188#L970 assume !(0 != activate_threads_~tmp___4~0#1); 771189#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 771310#L475 assume !(1 == ~t6_pc~0); 771311#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 771387#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 771388#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 772093#L978 assume !(0 != activate_threads_~tmp___5~0#1); 772035#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 772036#L494 assume !(1 == ~t7_pc~0); 771715#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 771716#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 771924#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 771925#L986 assume !(0 != activate_threads_~tmp___6~0#1); 772068#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 771926#L837 assume !(1 == ~M_E~0); 771927#L837-2 assume !(1 == ~T1_E~0); 771277#L842-1 assume !(1 == ~T2_E~0); 771278#L847-1 assume !(1 == ~T3_E~0); 771810#L852-1 assume !(1 == ~T4_E~0); 771917#L857-1 assume !(1 == ~T5_E~0); 772085#L862-1 assume !(1 == ~T6_E~0); 772087#L867-1 assume !(1 == ~T7_E~0); 772086#L872-1 assume !(1 == ~E_1~0); 771863#L877-1 assume !(1 == ~E_2~0); 771759#L882-1 assume !(1 == ~E_3~0); 771760#L887-1 assume !(1 == ~E_4~0); 771335#L892-1 assume !(1 == ~E_5~0); 771336#L897-1 assume !(1 == ~E_6~0); 771782#L902-1 assume !(1 == ~E_7~0); 771416#L907-1 assume { :end_inline_reset_delta_events } true; 771417#L1148-2 assume !false; 830900#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 830898#L729 [2021-12-06 22:17:44,461 INFO L793 eck$LassoCheckResult]: Loop: 830898#L729 assume !false; 830896#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 830893#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 830892#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 830890#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 830888#L626 assume 0 != eval_~tmp~0#1; 830886#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 772053#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 772054#L631 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 834471#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 815281#L645 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 807548#L662 assume !(0 != eval_~tmp_ndt_3~0#1); 807549#L659 assume !(0 == ~t3_st~0); 827133#L673 assume !(0 == ~t4_st~0); 827119#L687 assume !(0 == ~t5_st~0); 830906#L701 assume !(0 == ~t6_st~0); 830904#L715 assume !(0 == ~t7_st~0); 830898#L729 [2021-12-06 22:17:44,462 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:44,462 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 3 times [2021-12-06 22:17:44,462 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:44,462 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1259581822] [2021-12-06 22:17:44,462 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:44,462 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:44,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:17:44,468 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:17:44,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:17:44,486 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:17:44,486 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:44,486 INFO L85 PathProgramCache]: Analyzing trace with hash -10094934, now seen corresponding path program 1 times [2021-12-06 22:17:44,486 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:44,486 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [813944314] [2021-12-06 22:17:44,486 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:44,486 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:44,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:17:44,488 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:17:44,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:17:44,491 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:17:44,491 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:44,492 INFO L85 PathProgramCache]: Analyzing trace with hash -777012221, now seen corresponding path program 1 times [2021-12-06 22:17:44,492 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:44,492 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [70491146] [2021-12-06 22:17:44,492 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:44,492 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:44,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:44,510 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:44,510 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:44,510 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [70491146] [2021-12-06 22:17:44,510 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [70491146] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:44,510 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:44,510 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:44,510 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [856414722] [2021-12-06 22:17:44,510 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:44,680 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:17:44,681 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:17:44,681 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:17:44,681 INFO L87 Difference]: Start difference. First operand 89727 states and 119679 transitions. cyclomatic complexity: 29960 Second operand has 3 states, 3 states have (on average 37.333333333333336) internal successors, (112), 3 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:45,102 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:17:45,103 INFO L93 Difference]: Finished difference Result 168623 states and 224463 transitions. [2021-12-06 22:17:45,103 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:17:45,103 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 168623 states and 224463 transitions. [2021-12-06 22:17:45,690 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 167896 [2021-12-06 22:17:46,055 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 168623 states to 168623 states and 224463 transitions. [2021-12-06 22:17:46,056 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 168623 [2021-12-06 22:17:46,139 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 168623 [2021-12-06 22:17:46,139 INFO L73 IsDeterministic]: Start isDeterministic. Operand 168623 states and 224463 transitions. [2021-12-06 22:17:46,210 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:17:46,210 INFO L681 BuchiCegarLoop]: Abstraction has 168623 states and 224463 transitions. [2021-12-06 22:17:46,288 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 168623 states and 224463 transitions. [2021-12-06 22:17:47,594 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 168623 to 160687. [2021-12-06 22:17:47,695 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 160687 states, 160687 states have (on average 1.3339660333443277) internal successors, (214351), 160686 states have internal predecessors, (214351), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:48,115 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160687 states to 160687 states and 214351 transitions. [2021-12-06 22:17:48,115 INFO L704 BuchiCegarLoop]: Abstraction has 160687 states and 214351 transitions. [2021-12-06 22:17:48,115 INFO L587 BuchiCegarLoop]: Abstraction has 160687 states and 214351 transitions. [2021-12-06 22:17:48,115 INFO L425 BuchiCegarLoop]: ======== Iteration 31============ [2021-12-06 22:17:48,115 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 160687 states and 214351 transitions. [2021-12-06 22:17:48,488 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 159960 [2021-12-06 22:17:48,489 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:17:48,489 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:17:48,489 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:48,489 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:48,490 INFO L791 eck$LassoCheckResult]: Stem: 1030471#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 1030387#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1030388#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1029686#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1029687#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 1030189#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1030190#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1030142#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1030030#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1030031#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1030022#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1030023#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1029978#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1029979#L754 assume !(0 == ~M_E~0); 1030342#L754-2 assume !(0 == ~T1_E~0); 1029905#L759-1 assume !(0 == ~T2_E~0); 1029906#L764-1 assume !(0 == ~T3_E~0); 1030410#L769-1 assume !(0 == ~T4_E~0); 1030411#L774-1 assume !(0 == ~T5_E~0); 1030235#L779-1 assume !(0 == ~T6_E~0); 1029943#L784-1 assume !(0 == ~T7_E~0); 1029944#L789-1 assume !(0 == ~E_1~0); 1029597#L794-1 assume !(0 == ~E_2~0); 1029598#L799-1 assume !(0 == ~E_3~0); 1030420#L804-1 assume !(0 == ~E_4~0); 1030421#L809-1 assume !(0 == ~E_5~0); 1030035#L814-1 assume !(0 == ~E_6~0); 1029518#L819-1 assume !(0 == ~E_7~0); 1029519#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1030019#L361 assume !(1 == ~m_pc~0); 1030020#L361-2 is_master_triggered_~__retres1~0#1 := 0; 1030068#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1029810#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1029811#L930 assume !(0 != activate_threads_~tmp~1#1); 1030230#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1030010#L380 assume !(1 == ~t1_pc~0); 1029654#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1030258#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1030259#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1030470#L938 assume !(0 != activate_threads_~tmp___0~0#1); 1029727#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1029728#L399 assume !(1 == ~t2_pc~0); 1029869#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1029870#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1030276#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1030095#L946 assume !(0 != activate_threads_~tmp___1~0#1); 1030096#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1029526#L418 assume !(1 == ~t3_pc~0); 1029527#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1030040#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1030041#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1030477#L954 assume !(0 != activate_threads_~tmp___2~0#1); 1030478#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1030343#L437 assume !(1 == ~t4_pc~0); 1030193#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1030194#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1029655#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1029656#L962 assume !(0 != activate_threads_~tmp___3~0#1); 1030154#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1030155#L456 assume !(1 == ~t5_pc~0); 1029902#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1029901#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1030310#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1029546#L970 assume !(0 != activate_threads_~tmp___4~0#1); 1029547#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1029668#L475 assume !(1 == ~t6_pc~0); 1029669#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1029747#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1029748#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1030490#L978 assume !(0 != activate_threads_~tmp___5~0#1); 1030429#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1030430#L494 assume !(1 == ~t7_pc~0); 1030074#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1030075#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1030304#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1030305#L986 assume !(0 != activate_threads_~tmp___6~0#1); 1030466#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1030302#L837 assume !(1 == ~M_E~0); 1030303#L837-2 assume !(1 == ~T1_E~0); 1029635#L842-1 assume !(1 == ~T2_E~0); 1029636#L847-1 assume !(1 == ~T3_E~0); 1030183#L852-1 assume !(1 == ~T4_E~0); 1030291#L857-1 assume !(1 == ~T5_E~0); 1030482#L862-1 assume !(1 == ~T6_E~0); 1030484#L867-1 assume !(1 == ~T7_E~0); 1030483#L872-1 assume !(1 == ~E_1~0); 1030234#L877-1 assume !(1 == ~E_2~0); 1030126#L882-1 assume !(1 == ~E_3~0); 1030127#L887-1 assume !(1 == ~E_4~0); 1029694#L892-1 assume !(1 == ~E_5~0); 1029695#L897-1 assume !(1 == ~E_6~0); 1030149#L902-1 assume !(1 == ~E_7~0); 1029776#L907-1 assume { :end_inline_reset_delta_events } true; 1029777#L1148-2 assume !false; 1077912#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1077909#L729 [2021-12-06 22:17:48,490 INFO L793 eck$LassoCheckResult]: Loop: 1077909#L729 assume !false; 1077910#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1077904#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1077905#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1077900#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1077901#L626 assume 0 != eval_~tmp~0#1; 1077895#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1077897#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 1081275#L631 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1081220#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 1072843#L645 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1072841#L662 assume !(0 != eval_~tmp_ndt_3~0#1); 1072839#L659 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1071564#L676 assume !(0 != eval_~tmp_ndt_4~0#1); 1072837#L673 assume !(0 == ~t4_st~0); 1077929#L687 assume !(0 == ~t5_st~0); 1077921#L701 assume !(0 == ~t6_st~0); 1077920#L715 assume !(0 == ~t7_st~0); 1077909#L729 [2021-12-06 22:17:48,490 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:48,490 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 4 times [2021-12-06 22:17:48,490 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:48,490 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [57184121] [2021-12-06 22:17:48,491 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:48,491 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:48,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:17:48,500 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:17:48,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:17:48,524 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:17:48,524 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:48,524 INFO L85 PathProgramCache]: Analyzing trace with hash 1673301209, now seen corresponding path program 1 times [2021-12-06 22:17:48,524 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:48,525 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [697229515] [2021-12-06 22:17:48,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:48,525 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:48,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:17:48,528 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:17:48,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:17:48,531 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:17:48,532 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:48,532 INFO L85 PathProgramCache]: Analyzing trace with hash -626298208, now seen corresponding path program 1 times [2021-12-06 22:17:48,532 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:48,532 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1418515427] [2021-12-06 22:17:48,532 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:48,532 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:48,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:48,557 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:48,557 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:48,557 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1418515427] [2021-12-06 22:17:48,557 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1418515427] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:48,557 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:48,557 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:48,557 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1410520623] [2021-12-06 22:17:48,557 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:48,658 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:17:48,658 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:17:48,658 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:17:48,658 INFO L87 Difference]: Start difference. First operand 160687 states and 214351 transitions. cyclomatic complexity: 53672 Second operand has 3 states, 3 states have (on average 37.666666666666664) internal successors, (113), 3 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:49,132 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:17:49,132 INFO L93 Difference]: Finished difference Result 205811 states and 274019 transitions. [2021-12-06 22:17:49,133 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:17:49,133 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 205811 states and 274019 transitions. [2021-12-06 22:17:49,990 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 203196 [2021-12-06 22:17:50,432 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 205811 states to 205811 states and 274019 transitions. [2021-12-06 22:17:50,432 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 205811 [2021-12-06 22:17:50,503 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 205811 [2021-12-06 22:17:50,503 INFO L73 IsDeterministic]: Start isDeterministic. Operand 205811 states and 274019 transitions. [2021-12-06 22:17:50,561 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:17:50,561 INFO L681 BuchiCegarLoop]: Abstraction has 205811 states and 274019 transitions. [2021-12-06 22:17:50,619 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 205811 states and 274019 transitions. [2021-12-06 22:17:51,894 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 205811 to 199539. [2021-12-06 22:17:51,980 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 199539 states, 199539 states have (on average 1.3334886914337547) internal successors, (266083), 199538 states have internal predecessors, (266083), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:52,440 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 199539 states to 199539 states and 266083 transitions. [2021-12-06 22:17:52,440 INFO L704 BuchiCegarLoop]: Abstraction has 199539 states and 266083 transitions. [2021-12-06 22:17:52,440 INFO L587 BuchiCegarLoop]: Abstraction has 199539 states and 266083 transitions. [2021-12-06 22:17:52,441 INFO L425 BuchiCegarLoop]: ======== Iteration 32============ [2021-12-06 22:17:52,441 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 199539 states and 266083 transitions. [2021-12-06 22:17:52,928 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 196924 [2021-12-06 22:17:52,928 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:17:52,928 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:17:52,929 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:52,929 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:17:52,929 INFO L791 eck$LassoCheckResult]: Stem: 1396967#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 1396891#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1396892#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1396194#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1396195#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 1396690#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1396691#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1396646#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1396542#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1396543#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1396534#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1396535#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1396490#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1396491#L754 assume !(0 == ~M_E~0); 1396840#L754-2 assume !(0 == ~T1_E~0); 1396412#L759-1 assume !(0 == ~T2_E~0); 1396413#L764-1 assume !(0 == ~T3_E~0); 1396916#L769-1 assume !(0 == ~T4_E~0); 1396917#L774-1 assume !(0 == ~T5_E~0); 1396735#L779-1 assume !(0 == ~T6_E~0); 1396451#L784-1 assume !(0 == ~T7_E~0); 1396452#L789-1 assume !(0 == ~E_1~0); 1396104#L794-1 assume !(0 == ~E_2~0); 1396105#L799-1 assume !(0 == ~E_3~0); 1396926#L804-1 assume !(0 == ~E_4~0); 1396927#L809-1 assume !(0 == ~E_5~0); 1396547#L814-1 assume !(0 == ~E_6~0); 1396025#L819-1 assume !(0 == ~E_7~0); 1396026#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1396531#L361 assume !(1 == ~m_pc~0); 1396532#L361-2 is_master_triggered_~__retres1~0#1 := 0; 1396575#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1396315#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1396316#L930 assume !(0 != activate_threads_~tmp~1#1); 1396731#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1396523#L380 assume !(1 == ~t1_pc~0); 1396162#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1396757#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1396758#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1396966#L938 assume !(0 != activate_threads_~tmp___0~0#1); 1396234#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1396235#L399 assume !(1 == ~t2_pc~0); 1396376#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1396377#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1396775#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1396602#L946 assume !(0 != activate_threads_~tmp___1~0#1); 1396603#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1396033#L418 assume !(1 == ~t3_pc~0); 1396034#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1396551#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1396552#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1396976#L954 assume !(0 != activate_threads_~tmp___2~0#1); 1396977#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1396842#L437 assume !(1 == ~t4_pc~0); 1396694#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1396695#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1396163#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1396164#L962 assume !(0 != activate_threads_~tmp___3~0#1); 1396658#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1396659#L456 assume !(1 == ~t5_pc~0); 1396409#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1396408#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1396809#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1396053#L970 assume !(0 != activate_threads_~tmp___4~0#1); 1396054#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1396176#L475 assume !(1 == ~t6_pc~0); 1396177#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1396255#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1396256#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1396987#L978 assume !(0 != activate_threads_~tmp___5~0#1); 1396933#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1396934#L494 assume !(1 == ~t7_pc~0); 1396582#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1396583#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1396797#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1396798#L986 assume !(0 != activate_threads_~tmp___6~0#1); 1396962#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1396799#L837 assume !(1 == ~M_E~0); 1396800#L837-2 assume !(1 == ~T1_E~0); 1396142#L842-1 assume !(1 == ~T2_E~0); 1396143#L847-1 assume !(1 == ~T3_E~0); 1396686#L852-1 assume !(1 == ~T4_E~0); 1396788#L857-1 assume !(1 == ~T5_E~0); 1396979#L862-1 assume !(1 == ~T6_E~0); 1396981#L867-1 assume !(1 == ~T7_E~0); 1396980#L872-1 assume !(1 == ~E_1~0); 1396734#L877-1 assume !(1 == ~E_2~0); 1396629#L882-1 assume !(1 == ~E_3~0); 1396630#L887-1 assume !(1 == ~E_4~0); 1396201#L892-1 assume !(1 == ~E_5~0); 1396202#L897-1 assume !(1 == ~E_6~0); 1396653#L902-1 assume !(1 == ~E_7~0); 1396284#L907-1 assume { :end_inline_reset_delta_events } true; 1396285#L1148-2 assume !false; 1411918#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1411915#L729 [2021-12-06 22:17:52,930 INFO L793 eck$LassoCheckResult]: Loop: 1411915#L729 assume !false; 1411913#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1411910#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1411908#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1411905#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1411901#L626 assume 0 != eval_~tmp~0#1; 1411902#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1412688#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 1412686#L631 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1412670#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 1412684#L645 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1409541#L662 assume !(0 != eval_~tmp_ndt_3~0#1); 1411992#L659 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1411989#L676 assume !(0 != eval_~tmp_ndt_4~0#1); 1411985#L673 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1411982#L690 assume !(0 != eval_~tmp_ndt_5~0#1); 1411980#L687 assume !(0 == ~t5_st~0); 1411974#L701 assume !(0 == ~t6_st~0); 1411922#L715 assume !(0 == ~t7_st~0); 1411915#L729 [2021-12-06 22:17:52,930 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:52,930 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 5 times [2021-12-06 22:17:52,930 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:52,930 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [926768665] [2021-12-06 22:17:52,930 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:52,930 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:52,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:17:52,938 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:17:52,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:17:52,955 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:17:52,955 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:52,955 INFO L85 PathProgramCache]: Analyzing trace with hash 119715445, now seen corresponding path program 1 times [2021-12-06 22:17:52,955 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:52,955 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1640185723] [2021-12-06 22:17:52,955 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:52,955 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:52,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:17:52,958 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:17:52,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:17:52,961 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:17:52,961 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:17:52,961 INFO L85 PathProgramCache]: Analyzing trace with hash 1846577550, now seen corresponding path program 1 times [2021-12-06 22:17:52,961 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:17:52,961 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1683003318] [2021-12-06 22:17:52,961 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:17:52,962 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:17:52,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:17:52,981 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:17:52,981 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:17:52,981 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1683003318] [2021-12-06 22:17:52,981 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1683003318] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:17:52,981 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:17:52,982 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:17:52,982 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1527135727] [2021-12-06 22:17:52,982 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:17:53,094 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:17:53,094 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:17:53,094 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:17:53,094 INFO L87 Difference]: Start difference. First operand 199539 states and 266083 transitions. cyclomatic complexity: 66554 Second operand has 3 states, 3 states have (on average 38.0) internal successors, (114), 3 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:54,025 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:17:54,025 INFO L93 Difference]: Finished difference Result 363283 states and 483083 transitions. [2021-12-06 22:17:54,026 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:17:54,026 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 363283 states and 483083 transitions. [2021-12-06 22:17:55,390 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 358204 [2021-12-06 22:17:55,941 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 363283 states to 363283 states and 483083 transitions. [2021-12-06 22:17:55,941 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 363283 [2021-12-06 22:17:56,158 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 363283 [2021-12-06 22:17:56,158 INFO L73 IsDeterministic]: Start isDeterministic. Operand 363283 states and 483083 transitions. [2021-12-06 22:17:56,254 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:17:56,254 INFO L681 BuchiCegarLoop]: Abstraction has 363283 states and 483083 transitions. [2021-12-06 22:17:56,362 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 363283 states and 483083 transitions. [2021-12-06 22:17:58,458 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 363283 to 350963. [2021-12-06 22:17:58,811 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 350963 states, 350963 states have (on average 1.333322885888256) internal successors, (467947), 350962 states have internal predecessors, (467947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:17:59,433 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 350963 states to 350963 states and 467947 transitions. [2021-12-06 22:17:59,433 INFO L704 BuchiCegarLoop]: Abstraction has 350963 states and 467947 transitions. [2021-12-06 22:17:59,433 INFO L587 BuchiCegarLoop]: Abstraction has 350963 states and 467947 transitions. [2021-12-06 22:17:59,434 INFO L425 BuchiCegarLoop]: ======== Iteration 33============ [2021-12-06 22:17:59,434 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 350963 states and 467947 transitions. [2021-12-06 22:18:00,433 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 345884 [2021-12-06 22:18:00,433 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:18:00,433 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:18:00,434 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:18:00,434 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:18:00,434 INFO L791 eck$LassoCheckResult]: Stem: 1959858#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 1959759#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1959760#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1959022#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1959023#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 1959539#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1959540#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1959487#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1959373#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1959374#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1959365#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1959366#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1959320#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1959321#L754 assume !(0 == ~M_E~0); 1959700#L754-2 assume !(0 == ~T1_E~0); 1959238#L759-1 assume !(0 == ~T2_E~0); 1959239#L764-1 assume !(0 == ~T3_E~0); 1959785#L769-1 assume !(0 == ~T4_E~0); 1959786#L774-1 assume !(0 == ~T5_E~0); 1959592#L779-1 assume !(0 == ~T6_E~0); 1959279#L784-1 assume !(0 == ~T7_E~0); 1959280#L789-1 assume !(0 == ~E_1~0); 1958933#L794-1 assume !(0 == ~E_2~0); 1958934#L799-1 assume !(0 == ~E_3~0); 1959802#L804-1 assume !(0 == ~E_4~0); 1959803#L809-1 assume !(0 == ~E_5~0); 1959378#L814-1 assume !(0 == ~E_6~0); 1958854#L819-1 assume !(0 == ~E_7~0); 1958855#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1959362#L361 assume !(1 == ~m_pc~0); 1959363#L361-2 is_master_triggered_~__retres1~0#1 := 0; 1959411#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1959146#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1959147#L930 assume !(0 != activate_threads_~tmp~1#1); 1959588#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1959354#L380 assume !(1 == ~t1_pc~0); 1958991#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1959616#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1959617#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1959857#L938 assume !(0 != activate_threads_~tmp___0~0#1); 1959061#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1959062#L399 assume !(1 == ~t2_pc~0); 1959206#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1959207#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1959637#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1959438#L946 assume !(0 != activate_threads_~tmp___1~0#1); 1959439#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1958862#L418 assume !(1 == ~t3_pc~0); 1958863#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1959383#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1959384#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1959864#L954 assume !(0 != activate_threads_~tmp___2~0#1); 1959865#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1959702#L437 assume !(1 == ~t4_pc~0); 1959543#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1959544#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1958992#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1958993#L962 assume !(0 != activate_threads_~tmp___3~0#1); 1959501#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1959502#L456 assume !(1 == ~t5_pc~0); 1959235#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1959234#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1959668#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1958882#L970 assume !(0 != activate_threads_~tmp___4~0#1); 1958883#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1959005#L475 assume !(1 == ~t6_pc~0); 1959006#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1959082#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1959083#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1959883#L978 assume !(0 != activate_threads_~tmp___5~0#1); 1959809#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1959810#L494 assume !(1 == ~t7_pc~0); 1959418#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1959419#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1959660#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1959661#L986 assume !(0 != activate_threads_~tmp___6~0#1); 1959853#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1959662#L837 assume !(1 == ~M_E~0); 1959663#L837-2 assume !(1 == ~T1_E~0); 1958971#L842-1 assume !(1 == ~T2_E~0); 1958972#L847-1 assume !(1 == ~T3_E~0); 1959534#L852-1 assume !(1 == ~T4_E~0); 1959652#L857-1 assume !(1 == ~T5_E~0); 1959871#L862-1 assume !(1 == ~T6_E~0); 1959877#L867-1 assume !(1 == ~T7_E~0); 1959876#L872-1 assume !(1 == ~E_1~0); 1959591#L877-1 assume !(1 == ~E_2~0); 1959468#L882-1 assume !(1 == ~E_3~0); 1959469#L887-1 assume !(1 == ~E_4~0); 1959029#L892-1 assume !(1 == ~E_5~0); 1959030#L897-1 assume !(1 == ~E_6~0); 1959495#L902-1 assume !(1 == ~E_7~0); 1959112#L907-1 assume { :end_inline_reset_delta_events } true; 1959113#L1148-2 assume !false; 2019351#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2019349#L729 [2021-12-06 22:18:00,434 INFO L793 eck$LassoCheckResult]: Loop: 2019349#L729 assume !false; 2019347#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2019344#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2019342#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2019341#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2019339#L626 assume 0 != eval_~tmp~0#1; 2019335#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 2019332#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 2019329#L631 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 2019317#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 2019189#L645 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 2019187#L662 assume !(0 != eval_~tmp_ndt_3~0#1); 2019186#L659 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 2019116#L676 assume !(0 != eval_~tmp_ndt_4~0#1); 2019184#L673 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 2065153#L690 assume !(0 != eval_~tmp_ndt_5~0#1); 2019367#L687 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 2019364#L704 assume !(0 != eval_~tmp_ndt_6~0#1); 2019357#L701 assume !(0 == ~t6_st~0); 2019355#L715 assume !(0 == ~t7_st~0); 2019349#L729 [2021-12-06 22:18:00,435 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:18:00,435 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 6 times [2021-12-06 22:18:00,435 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:18:00,435 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1554996455] [2021-12-06 22:18:00,435 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:18:00,435 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:18:00,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:18:00,441 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:18:00,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:18:00,457 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:18:00,457 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:18:00,457 INFO L85 PathProgramCache]: Analyzing trace with hash -590652146, now seen corresponding path program 1 times [2021-12-06 22:18:00,457 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:18:00,458 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1978956166] [2021-12-06 22:18:00,458 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:18:00,458 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:18:00,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:18:00,461 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:18:00,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:18:00,464 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:18:00,464 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:18:00,464 INFO L85 PathProgramCache]: Analyzing trace with hash 1402465557, now seen corresponding path program 1 times [2021-12-06 22:18:00,464 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:18:00,464 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1533460198] [2021-12-06 22:18:00,465 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:18:00,465 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:18:00,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:18:00,485 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:18:00,485 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:18:00,485 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1533460198] [2021-12-06 22:18:00,486 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1533460198] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:18:00,486 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:18:00,486 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 22:18:00,486 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [81209190] [2021-12-06 22:18:00,486 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:18:00,615 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:18:00,615 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:18:00,616 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:18:00,616 INFO L87 Difference]: Start difference. First operand 350963 states and 467947 transitions. cyclomatic complexity: 116994 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:18:02,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:18:02,186 INFO L93 Difference]: Finished difference Result 656627 states and 873243 transitions. [2021-12-06 22:18:02,187 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:18:02,187 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 656627 states and 873243 transitions. [2021-12-06 22:18:04,752 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 646620 [2021-12-06 22:18:06,161 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 656627 states to 656627 states and 873243 transitions. [2021-12-06 22:18:06,161 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 656627 [2021-12-06 22:18:06,337 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 656627 [2021-12-06 22:18:06,337 INFO L73 IsDeterministic]: Start isDeterministic. Operand 656627 states and 873243 transitions. [2021-12-06 22:18:06,506 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:18:06,506 INFO L681 BuchiCegarLoop]: Abstraction has 656627 states and 873243 transitions. [2021-12-06 22:18:06,706 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 656627 states and 873243 transitions. [2021-12-06 22:18:11,213 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 656627 to 648883. [2021-12-06 22:18:11,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 648883 states, 648883 states have (on average 1.3305742329510868) internal successors, (863387), 648882 states have internal predecessors, (863387), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:18:12,914 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 648883 states to 648883 states and 863387 transitions. [2021-12-06 22:18:12,914 INFO L704 BuchiCegarLoop]: Abstraction has 648883 states and 863387 transitions. [2021-12-06 22:18:12,914 INFO L587 BuchiCegarLoop]: Abstraction has 648883 states and 863387 transitions. [2021-12-06 22:18:12,914 INFO L425 BuchiCegarLoop]: ======== Iteration 34============ [2021-12-06 22:18:12,914 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 648883 states and 863387 transitions. [2021-12-06 22:18:14,783 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 638876 [2021-12-06 22:18:14,783 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:18:14,783 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:18:14,784 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:18:14,784 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:18:14,785 INFO L791 eck$LassoCheckResult]: Stem: 2967461#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 2967349#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2967350#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2966618#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2966619#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 2967131#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2967132#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2967083#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2966968#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2966969#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2966960#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2966961#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2966918#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2966919#L754 assume !(0 == ~M_E~0); 2967299#L754-2 assume !(0 == ~T1_E~0); 2966834#L759-1 assume !(0 == ~T2_E~0); 2966835#L764-1 assume !(0 == ~T3_E~0); 2967385#L769-1 assume !(0 == ~T4_E~0); 2967386#L774-1 assume !(0 == ~T5_E~0); 2967180#L779-1 assume !(0 == ~T6_E~0); 2966880#L784-1 assume !(0 == ~T7_E~0); 2966881#L789-1 assume !(0 == ~E_1~0); 2966531#L794-1 assume !(0 == ~E_2~0); 2966532#L799-1 assume !(0 == ~E_3~0); 2967401#L804-1 assume !(0 == ~E_4~0); 2967402#L809-1 assume !(0 == ~E_5~0); 2966973#L814-1 assume !(0 == ~E_6~0); 2966452#L819-1 assume !(0 == ~E_7~0); 2966453#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2966957#L361 assume !(1 == ~m_pc~0); 2966958#L361-2 is_master_triggered_~__retres1~0#1 := 0; 2967007#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2966741#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2966742#L930 assume !(0 != activate_threads_~tmp~1#1); 2967174#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2966950#L380 assume !(1 == ~t1_pc~0); 2966585#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2967204#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2967205#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2967460#L938 assume !(0 != activate_threads_~tmp___0~0#1); 2966659#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2966660#L399 assume !(1 == ~t2_pc~0); 2966801#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2966802#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2967226#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2967035#L946 assume !(0 != activate_threads_~tmp___1~0#1); 2967036#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2966460#L418 assume !(1 == ~t3_pc~0); 2966461#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2966979#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2966980#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2967469#L954 assume !(0 != activate_threads_~tmp___2~0#1); 2967470#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2967301#L437 assume !(1 == ~t4_pc~0); 2967135#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2967136#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2966588#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2966589#L962 assume !(0 != activate_threads_~tmp___3~0#1); 2967098#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2967099#L456 assume !(1 == ~t5_pc~0); 2966831#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2966830#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2967265#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2966480#L970 assume !(0 != activate_threads_~tmp___4~0#1); 2966481#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2966601#L475 assume !(1 == ~t6_pc~0); 2966602#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2966679#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2966680#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2967483#L978 assume !(0 != activate_threads_~tmp___5~0#1); 2967411#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2967412#L494 assume !(1 == ~t7_pc~0); 2967014#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2967015#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2967253#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2967254#L986 assume !(0 != activate_threads_~tmp___6~0#1); 2967458#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2967255#L837 assume !(1 == ~M_E~0); 2967256#L837-2 assume !(1 == ~T1_E~0); 2966568#L842-1 assume !(1 == ~T2_E~0); 2966569#L847-1 assume !(1 == ~T3_E~0); 2967127#L852-1 assume !(1 == ~T4_E~0); 2967242#L857-1 assume !(1 == ~T5_E~0); 2967474#L862-1 assume !(1 == ~T6_E~0); 2967477#L867-1 assume !(1 == ~T7_E~0); 2967476#L872-1 assume !(1 == ~E_1~0); 2967179#L877-1 assume !(1 == ~E_2~0); 2967065#L882-1 assume !(1 == ~E_3~0); 2967066#L887-1 assume !(1 == ~E_4~0); 2966626#L892-1 assume !(1 == ~E_5~0); 2966627#L897-1 assume !(1 == ~E_6~0); 2967092#L902-1 assume !(1 == ~E_7~0); 2966709#L907-1 assume { :end_inline_reset_delta_events } true; 2966710#L1148-2 assume !false; 3206662#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3206660#L729 [2021-12-06 22:18:14,785 INFO L793 eck$LassoCheckResult]: Loop: 3206660#L729 assume !false; 3206658#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3206656#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3206655#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3206654#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3206651#L626 assume 0 != eval_~tmp~0#1; 3206648#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 3206645#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 3206643#L631 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 3206625#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 3206641#L645 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 3172436#L662 assume !(0 != eval_~tmp_ndt_3~0#1); 3112134#L659 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 3112131#L676 assume !(0 != eval_~tmp_ndt_4~0#1); 3112129#L673 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 3112126#L690 assume !(0 != eval_~tmp_ndt_5~0#1); 3112125#L687 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 3112082#L704 assume !(0 != eval_~tmp_ndt_6~0#1); 3112124#L701 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0#1;eval_~tmp_ndt_7~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 3206668#L718 assume !(0 != eval_~tmp_ndt_7~0#1); 3206666#L715 assume !(0 == ~t7_st~0); 3206660#L729 [2021-12-06 22:18:14,785 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:18:14,785 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 7 times [2021-12-06 22:18:14,786 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:18:14,786 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1261572038] [2021-12-06 22:18:14,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:18:14,786 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:18:14,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:18:14,793 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:18:14,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:18:14,818 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:18:14,818 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:18:14,818 INFO L85 PathProgramCache]: Analyzing trace with hash -1130560960, now seen corresponding path program 1 times [2021-12-06 22:18:14,818 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:18:14,818 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1715458924] [2021-12-06 22:18:14,819 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:18:14,819 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:18:14,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:18:14,821 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:18:14,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:18:14,824 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:18:14,824 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:18:14,824 INFO L85 PathProgramCache]: Analyzing trace with hash 526545689, now seen corresponding path program 1 times [2021-12-06 22:18:14,825 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:18:14,825 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1100386626] [2021-12-06 22:18:14,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:18:14,825 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:18:14,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 22:18:14,844 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 22:18:14,844 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 22:18:14,844 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1100386626] [2021-12-06 22:18:14,844 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1100386626] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 22:18:14,844 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 22:18:14,844 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 22:18:14,844 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1494849410] [2021-12-06 22:18:14,844 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 22:18:14,986 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 22:18:14,986 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 22:18:14,986 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 22:18:14,986 INFO L87 Difference]: Start difference. First operand 648883 states and 863387 transitions. cyclomatic complexity: 214514 Second operand has 3 states, 2 states have (on average 58.0) internal successors, (116), 3 states have internal predecessors, (116), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:18:18,434 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 22:18:18,434 INFO L93 Difference]: Finished difference Result 1269731 states and 1686859 transitions. [2021-12-06 22:18:18,435 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 22:18:18,435 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1269731 states and 1686859 transitions. [2021-12-06 22:18:23,725 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 1249868 [2021-12-06 22:18:26,523 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1269731 states to 1269731 states and 1686859 transitions. [2021-12-06 22:18:26,523 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1269731 [2021-12-06 22:18:27,041 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1269731 [2021-12-06 22:18:27,041 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1269731 states and 1686859 transitions. [2021-12-06 22:18:27,676 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 22:18:27,677 INFO L681 BuchiCegarLoop]: Abstraction has 1269731 states and 1686859 transitions. [2021-12-06 22:18:28,149 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1269731 states and 1686859 transitions. [2021-12-06 22:18:36,676 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1269731 to 1269731. [2021-12-06 22:18:37,099 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1269731 states, 1269731 states have (on average 1.328516827580015) internal successors, (1686859), 1269730 states have internal predecessors, (1686859), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 22:18:40,061 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1269731 states to 1269731 states and 1686859 transitions. [2021-12-06 22:18:40,061 INFO L704 BuchiCegarLoop]: Abstraction has 1269731 states and 1686859 transitions. [2021-12-06 22:18:40,061 INFO L587 BuchiCegarLoop]: Abstraction has 1269731 states and 1686859 transitions. [2021-12-06 22:18:40,061 INFO L425 BuchiCegarLoop]: ======== Iteration 35============ [2021-12-06 22:18:40,061 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1269731 states and 1686859 transitions. [2021-12-06 22:18:43,554 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 1249868 [2021-12-06 22:18:43,555 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 22:18:43,555 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 22:18:43,556 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:18:43,556 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 22:18:43,556 INFO L791 eck$LassoCheckResult]: Stem: 4886053#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 4885955#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 4885956#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4885242#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4885243#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 4885754#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4885755#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4885709#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4885601#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4885602#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4885590#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4885591#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4885542#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4885543#L754 assume !(0 == ~M_E~0); 4885903#L754-2 assume !(0 == ~T1_E~0); 4885464#L759-1 assume !(0 == ~T2_E~0); 4885465#L764-1 assume !(0 == ~T3_E~0); 4885982#L769-1 assume !(0 == ~T4_E~0); 4885983#L774-1 assume !(0 == ~T5_E~0); 4885804#L779-1 assume !(0 == ~T6_E~0); 4885505#L784-1 assume !(0 == ~T7_E~0); 4885506#L789-1 assume !(0 == ~E_1~0); 4885158#L794-1 assume !(0 == ~E_2~0); 4885159#L799-1 assume !(0 == ~E_3~0); 4885997#L804-1 assume !(0 == ~E_4~0); 4885998#L809-1 assume !(0 == ~E_5~0); 4885606#L814-1 assume !(0 == ~E_6~0); 4885079#L819-1 assume !(0 == ~E_7~0); 4885080#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4885585#L361 assume !(1 == ~m_pc~0); 4885586#L361-2 is_master_triggered_~__retres1~0#1 := 0; 4885637#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4885365#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4885366#L930 assume !(0 != activate_threads_~tmp~1#1); 4885797#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4885576#L380 assume !(1 == ~t1_pc~0); 4885209#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4886044#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4885966#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4885967#L938 assume !(0 != activate_threads_~tmp___0~0#1); 4886079#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4885210#L399 assume !(1 == ~t2_pc~0); 4885211#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4886078#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4885988#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4885989#L946 assume !(0 != activate_threads_~tmp___1~0#1); 4885115#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4885116#L418 assume !(1 == ~t3_pc~0); 4885045#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4885046#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4885923#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4885924#L954 assume !(0 != activate_threads_~tmp___2~0#1); 4886022#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4886023#L437 assume !(1 == ~t4_pc~0); 4886077#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4885392#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4885393#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4886076#L962 assume !(0 != activate_threads_~tmp___3~0#1); 4886075#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4885342#L456 assume !(1 == ~t5_pc~0); 4885343#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4885888#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4885889#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4886074#L970 assume !(0 != activate_threads_~tmp___4~0#1); 4885990#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4885991#L475 assume !(1 == ~t6_pc~0); 4885940#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4885941#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4885922#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4885066#L978 assume !(0 != activate_threads_~tmp___5~0#1); 4885067#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4885594#L494 assume !(1 == ~t7_pc~0); 4885596#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4885949#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4885950#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4886071#L986 assume !(0 != activate_threads_~tmp___6~0#1); 4886038#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4886039#L837 assume !(1 == ~M_E~0); 4885668#L837-2 assume !(1 == ~T1_E~0); 4885669#L842-1 assume !(1 == ~T2_E~0); 4886070#L847-1 assume !(1 == ~T3_E~0); 4885855#L852-1 assume !(1 == ~T4_E~0); 4885856#L857-1 assume !(1 == ~T5_E~0); 4886065#L862-1 assume !(1 == ~T6_E~0); 4886068#L867-1 assume !(1 == ~T7_E~0); 4886067#L872-1 assume !(1 == ~E_1~0); 4885801#L877-1 assume !(1 == ~E_2~0); 4885691#L882-1 assume !(1 == ~E_3~0); 4885692#L887-1 assume !(1 == ~E_4~0); 4885248#L892-1 assume !(1 == ~E_5~0); 4885249#L897-1 assume !(1 == ~E_6~0); 4885717#L902-1 assume !(1 == ~E_7~0); 4885335#L907-1 assume { :end_inline_reset_delta_events } true; 4885336#L1148-2 assume !false; 5441001#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5436468#L729 [2021-12-06 22:18:43,557 INFO L793 eck$LassoCheckResult]: Loop: 5436468#L729 assume !false; 5440994#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5440988#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5440979#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5440969#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5440961#L626 assume 0 != eval_~tmp~0#1; 5440954#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 5440945#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 5440935#L631 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 5440852#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 5393035#L645 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 5393033#L662 assume !(0 != eval_~tmp_ndt_3~0#1); 5378625#L659 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 5378622#L676 assume !(0 != eval_~tmp_ndt_4~0#1); 5378619#L673 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 5378620#L690 assume !(0 != eval_~tmp_ndt_5~0#1); 5418503#L687 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 5418500#L704 assume !(0 != eval_~tmp_ndt_6~0#1); 5418498#L701 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0#1;eval_~tmp_ndt_7~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 5393723#L718 assume !(0 != eval_~tmp_ndt_7~0#1); 5418495#L715 assume 0 == ~t7_st~0;havoc eval_~tmp_ndt_8~0#1;eval_~tmp_ndt_8~0#1 := eval_#t~nondet12#1;havoc eval_#t~nondet12#1; 5434849#L732 assume !(0 != eval_~tmp_ndt_8~0#1); 5436468#L729 [2021-12-06 22:18:43,557 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:18:43,557 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 8 times [2021-12-06 22:18:43,557 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:18:43,557 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1973092049] [2021-12-06 22:18:43,557 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:18:43,557 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:18:43,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:18:43,563 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:18:43,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:18:43,576 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:18:43,577 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:18:43,577 INFO L85 PathProgramCache]: Analyzing trace with hash -687650493, now seen corresponding path program 1 times [2021-12-06 22:18:43,577 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:18:43,577 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1598243879] [2021-12-06 22:18:43,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:18:43,577 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:18:43,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:18:43,580 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:18:43,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:18:43,762 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:18:43,762 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 22:18:43,762 INFO L85 PathProgramCache]: Analyzing trace with hash -856951926, now seen corresponding path program 1 times [2021-12-06 22:18:43,763 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 22:18:43,763 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1271764565] [2021-12-06 22:18:43,763 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 22:18:43,763 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 22:18:43,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:18:43,770 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 22:18:43,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 22:18:43,788 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 22:18:45,038 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 06.12 10:18:45 BoogieIcfgContainer [2021-12-06 22:18:45,038 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-12-06 22:18:45,039 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-12-06 22:18:45,039 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-12-06 22:18:45,039 INFO L275 PluginConnector]: Witness Printer initialized [2021-12-06 22:18:45,039 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 10:17:31" (3/4) ... [2021-12-06 22:18:45,041 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-12-06 22:18:45,080 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6ae3e5e5-cf62-4174-8737-dd2fe952f97a/bin/uautomizer-DrprNOufMa/witness.graphml [2021-12-06 22:18:45,080 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-12-06 22:18:45,081 INFO L158 Benchmark]: Toolchain (without parser) took 74834.37ms. Allocated memory was 113.2MB in the beginning and 14.7GB in the end (delta: 14.6GB). Free memory was 72.9MB in the beginning and 2.3GB in the end (delta: -2.2GB). Peak memory consumption was 12.4GB. Max. memory is 16.1GB. [2021-12-06 22:18:45,081 INFO L158 Benchmark]: CDTParser took 0.17ms. Allocated memory is still 113.2MB. Free memory is still 89.8MB. There was no memory consumed. Max. memory is 16.1GB. [2021-12-06 22:18:45,081 INFO L158 Benchmark]: CACSL2BoogieTranslator took 313.12ms. Allocated memory is still 113.2MB. Free memory was 72.8MB in the beginning and 82.3MB in the end (delta: -9.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2021-12-06 22:18:45,081 INFO L158 Benchmark]: Boogie Procedure Inliner took 79.22ms. Allocated memory is still 113.2MB. Free memory was 82.3MB in the beginning and 76.0MB in the end (delta: 6.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2021-12-06 22:18:45,081 INFO L158 Benchmark]: Boogie Preprocessor took 77.53ms. Allocated memory is still 113.2MB. Free memory was 76.0MB in the beginning and 70.1MB in the end (delta: 5.9MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2021-12-06 22:18:45,082 INFO L158 Benchmark]: RCFGBuilder took 842.16ms. Allocated memory is still 113.2MB. Free memory was 70.1MB in the beginning and 51.1MB in the end (delta: 19.0MB). Peak memory consumption was 36.8MB. Max. memory is 16.1GB. [2021-12-06 22:18:45,082 INFO L158 Benchmark]: BuchiAutomizer took 73475.59ms. Allocated memory was 113.2MB in the beginning and 14.7GB in the end (delta: 14.6GB). Free memory was 50.6MB in the beginning and 2.3GB in the end (delta: -2.2GB). Peak memory consumption was 12.3GB. Max. memory is 16.1GB. [2021-12-06 22:18:45,082 INFO L158 Benchmark]: Witness Printer took 41.47ms. Allocated memory is still 14.7GB. Free memory was 2.3GB in the beginning and 2.3GB in the end (delta: 5.2MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2021-12-06 22:18:45,083 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17ms. Allocated memory is still 113.2MB. Free memory is still 89.8MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 313.12ms. Allocated memory is still 113.2MB. Free memory was 72.8MB in the beginning and 82.3MB in the end (delta: -9.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 79.22ms. Allocated memory is still 113.2MB. Free memory was 82.3MB in the beginning and 76.0MB in the end (delta: 6.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Boogie Preprocessor took 77.53ms. Allocated memory is still 113.2MB. Free memory was 76.0MB in the beginning and 70.1MB in the end (delta: 5.9MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * RCFGBuilder took 842.16ms. Allocated memory is still 113.2MB. Free memory was 70.1MB in the beginning and 51.1MB in the end (delta: 19.0MB). Peak memory consumption was 36.8MB. Max. memory is 16.1GB. * BuchiAutomizer took 73475.59ms. Allocated memory was 113.2MB in the beginning and 14.7GB in the end (delta: 14.6GB). Free memory was 50.6MB in the beginning and 2.3GB in the end (delta: -2.2GB). Peak memory consumption was 12.3GB. Max. memory is 16.1GB. * Witness Printer took 41.47ms. Allocated memory is still 14.7GB. Free memory was 2.3GB in the beginning and 2.3GB in the end (delta: 5.2MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 34 terminating modules (34 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.34 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 1269731 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 73.4s and 35 iterations. TraceHistogramMax:1. Analysis of lassos took 4.5s. Construction of modules took 0.7s. Büchi inclusion checks took 8.6s. Highest rank in rank-based complementation 0. Minimization of det autom 34. Minimization of nondet autom 0. Automata minimization 29.6s AutomataMinimizationTime, 34 MinimizatonAttempts, 106964 StatesRemovedByMinimization, 19 NontrivialMinimizations. Non-live state removal took 18.9s Buchi closure took 1.2s. Biggest automaton had 1269731 states and ocurred in iteration 34. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 50108 SdHoareTripleChecker+Valid, 0.9s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 50108 mSDsluCounter, 74841 SdHoareTripleChecker+Invalid, 0.7s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 31022 mSDsCounter, 487 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 993 IncrementalHoareTripleChecker+Invalid, 1480 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 487 mSolverCounterUnsat, 43819 mSDtfsCounter, 993 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI5 SFLT0 conc7 concLT0 SILN1 SILU0 SILI21 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 621]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {__retres1=0, tmp_ndt_3=0, NULL=0, E_7=2, t3_st=0, NULL=1, tmp=0, tmp___6=0, t5_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@efeab10=0, \result=0, E_3=2, T6_E=2, tmp_ndt_1=0, t7_i=1, tmp___4=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6ad6bdf5=0, m_st=0, t6_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@68e03107=0, t3_pc=0, tmp_ndt_8=0, __retres1=0, m_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@595f1358=0, tmp___2=0, \result=0, t6_st=0, tmp_ndt_7=0, E_6=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@38e1c73e=0, \result=0, T2_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6c60993d=0, tmp=0, t5_st=0, E_2=2, tmp___0=0, t7_pc=0, M_E=2, T4_E=2, \result=0, t4_st=0, t3_i=1, __retres1=1, t5_pc=0, t7_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@e522eac=0, tmp_ndt_5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3dd113d1=0, kernel_st=1, t1_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@28bee2cb=0, \result=0, T7_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@c51f489=0, t2_st=0, tmp___5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@319edd27=0, tmp_ndt_2=0, \result=0, t4_i=1, t4_pc=0, E_5=2, E_1=2, tmp=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@49ed784=0, NULL=0, tmp___3=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@540e11ad=0, tmp___0=0, __retres1=0, t6_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@159f3ef4=0, \result=0, \result=1, __retres1=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5df5dfd=0, __retres1=0, tmp___1=0, tmp_ndt_6=0, t1_pc=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@32e8924f=0, E_4=2, T1_E=2, __retres1=0, T5_E=2, t2_i=1, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@10ee65ae=0, t1_st=0, __retres1=0, t2_pc=0, tmp_ndt_4=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1c4ecf34=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@22028548=0, T3_E=2} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 621]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int t6_pc = 0; [L32] int t7_pc = 0; [L33] int m_st ; [L34] int t1_st ; [L35] int t2_st ; [L36] int t3_st ; [L37] int t4_st ; [L38] int t5_st ; [L39] int t6_st ; [L40] int t7_st ; [L41] int m_i ; [L42] int t1_i ; [L43] int t2_i ; [L44] int t3_i ; [L45] int t4_i ; [L46] int t5_i ; [L47] int t6_i ; [L48] int t7_i ; [L49] int M_E = 2; [L50] int T1_E = 2; [L51] int T2_E = 2; [L52] int T3_E = 2; [L53] int T4_E = 2; [L54] int T5_E = 2; [L55] int T6_E = 2; [L56] int T7_E = 2; [L57] int E_1 = 2; [L58] int E_2 = 2; [L59] int E_3 = 2; [L60] int E_4 = 2; [L61] int E_5 = 2; [L62] int E_6 = 2; [L63] int E_7 = 2; [L1193] int __retres1 ; [L1197] CALL init_model() [L1102] m_i = 1 [L1103] t1_i = 1 [L1104] t2_i = 1 [L1105] t3_i = 1 [L1106] t4_i = 1 [L1107] t5_i = 1 [L1108] t6_i = 1 [L1109] t7_i = 1 [L1197] RET init_model() [L1198] CALL start_simulation() [L1134] int kernel_st ; [L1135] int tmp ; [L1136] int tmp___0 ; [L1140] kernel_st = 0 [L1141] FCALL update_channels() [L1142] CALL init_threads() [L521] COND TRUE m_i == 1 [L522] m_st = 0 [L526] COND TRUE t1_i == 1 [L527] t1_st = 0 [L531] COND TRUE t2_i == 1 [L532] t2_st = 0 [L536] COND TRUE t3_i == 1 [L537] t3_st = 0 [L541] COND TRUE t4_i == 1 [L542] t4_st = 0 [L546] COND TRUE t5_i == 1 [L547] t5_st = 0 [L551] COND TRUE t6_i == 1 [L552] t6_st = 0 [L556] COND TRUE t7_i == 1 [L557] t7_st = 0 [L1142] RET init_threads() [L1143] CALL fire_delta_events() [L754] COND FALSE !(M_E == 0) [L759] COND FALSE !(T1_E == 0) [L764] COND FALSE !(T2_E == 0) [L769] COND FALSE !(T3_E == 0) [L774] COND FALSE !(T4_E == 0) [L779] COND FALSE !(T5_E == 0) [L784] COND FALSE !(T6_E == 0) [L789] COND FALSE !(T7_E == 0) [L794] COND FALSE !(E_1 == 0) [L799] COND FALSE !(E_2 == 0) [L804] COND FALSE !(E_3 == 0) [L809] COND FALSE !(E_4 == 0) [L814] COND FALSE !(E_5 == 0) [L819] COND FALSE !(E_6 == 0) [L824] COND FALSE !(E_7 == 0) [L1143] RET fire_delta_events() [L1144] CALL activate_threads() [L917] int tmp ; [L918] int tmp___0 ; [L919] int tmp___1 ; [L920] int tmp___2 ; [L921] int tmp___3 ; [L922] int tmp___4 ; [L923] int tmp___5 ; [L924] int tmp___6 ; [L928] CALL, EXPR is_master_triggered() [L358] int __retres1 ; [L361] COND FALSE !(m_pc == 1) [L371] __retres1 = 0 [L373] return (__retres1); [L928] RET, EXPR is_master_triggered() [L928] tmp = is_master_triggered() [L930] COND FALSE !(\read(tmp)) [L936] CALL, EXPR is_transmit1_triggered() [L377] int __retres1 ; [L380] COND FALSE !(t1_pc == 1) [L390] __retres1 = 0 [L392] return (__retres1); [L936] RET, EXPR is_transmit1_triggered() [L936] tmp___0 = is_transmit1_triggered() [L938] COND FALSE !(\read(tmp___0)) [L944] CALL, EXPR is_transmit2_triggered() [L396] int __retres1 ; [L399] COND FALSE !(t2_pc == 1) [L409] __retres1 = 0 [L411] return (__retres1); [L944] RET, EXPR is_transmit2_triggered() [L944] tmp___1 = is_transmit2_triggered() [L946] COND FALSE !(\read(tmp___1)) [L952] CALL, EXPR is_transmit3_triggered() [L415] int __retres1 ; [L418] COND FALSE !(t3_pc == 1) [L428] __retres1 = 0 [L430] return (__retres1); [L952] RET, EXPR is_transmit3_triggered() [L952] tmp___2 = is_transmit3_triggered() [L954] COND FALSE !(\read(tmp___2)) [L960] CALL, EXPR is_transmit4_triggered() [L434] int __retres1 ; [L437] COND FALSE !(t4_pc == 1) [L447] __retres1 = 0 [L449] return (__retres1); [L960] RET, EXPR is_transmit4_triggered() [L960] tmp___3 = is_transmit4_triggered() [L962] COND FALSE !(\read(tmp___3)) [L968] CALL, EXPR is_transmit5_triggered() [L453] int __retres1 ; [L456] COND FALSE !(t5_pc == 1) [L466] __retres1 = 0 [L468] return (__retres1); [L968] RET, EXPR is_transmit5_triggered() [L968] tmp___4 = is_transmit5_triggered() [L970] COND FALSE !(\read(tmp___4)) [L976] CALL, EXPR is_transmit6_triggered() [L472] int __retres1 ; [L475] COND FALSE !(t6_pc == 1) [L485] __retres1 = 0 [L487] return (__retres1); [L976] RET, EXPR is_transmit6_triggered() [L976] tmp___5 = is_transmit6_triggered() [L978] COND FALSE !(\read(tmp___5)) [L984] CALL, EXPR is_transmit7_triggered() [L491] int __retres1 ; [L494] COND FALSE !(t7_pc == 1) [L504] __retres1 = 0 [L506] return (__retres1); [L984] RET, EXPR is_transmit7_triggered() [L984] tmp___6 = is_transmit7_triggered() [L986] COND FALSE !(\read(tmp___6)) [L1144] RET activate_threads() [L1145] CALL reset_delta_events() [L837] COND FALSE !(M_E == 1) [L842] COND FALSE !(T1_E == 1) [L847] COND FALSE !(T2_E == 1) [L852] COND FALSE !(T3_E == 1) [L857] COND FALSE !(T4_E == 1) [L862] COND FALSE !(T5_E == 1) [L867] COND FALSE !(T6_E == 1) [L872] COND FALSE !(T7_E == 1) [L877] COND FALSE !(E_1 == 1) [L882] COND FALSE !(E_2 == 1) [L887] COND FALSE !(E_3 == 1) [L892] COND FALSE !(E_4 == 1) [L897] COND FALSE !(E_5 == 1) [L902] COND FALSE !(E_6 == 1) [L907] COND FALSE !(E_7 == 1) [L1145] RET reset_delta_events() [L1148] COND TRUE 1 [L1151] kernel_st = 1 [L1152] CALL eval() [L617] int tmp ; Loop: [L621] COND TRUE 1 [L624] CALL, EXPR exists_runnable_thread() [L566] int __retres1 ; [L569] COND TRUE m_st == 0 [L570] __retres1 = 1 [L612] return (__retres1); [L624] RET, EXPR exists_runnable_thread() [L624] tmp = exists_runnable_thread() [L626] COND TRUE \read(tmp) [L631] COND TRUE m_st == 0 [L632] int tmp_ndt_1; [L633] tmp_ndt_1 = __VERIFIER_nondet_int() [L634] COND FALSE !(\read(tmp_ndt_1)) [L645] COND TRUE t1_st == 0 [L646] int tmp_ndt_2; [L647] tmp_ndt_2 = __VERIFIER_nondet_int() [L648] COND FALSE !(\read(tmp_ndt_2)) [L659] COND TRUE t2_st == 0 [L660] int tmp_ndt_3; [L661] tmp_ndt_3 = __VERIFIER_nondet_int() [L662] COND FALSE !(\read(tmp_ndt_3)) [L673] COND TRUE t3_st == 0 [L674] int tmp_ndt_4; [L675] tmp_ndt_4 = __VERIFIER_nondet_int() [L676] COND FALSE !(\read(tmp_ndt_4)) [L687] COND TRUE t4_st == 0 [L688] int tmp_ndt_5; [L689] tmp_ndt_5 = __VERIFIER_nondet_int() [L690] COND FALSE !(\read(tmp_ndt_5)) [L701] COND TRUE t5_st == 0 [L702] int tmp_ndt_6; [L703] tmp_ndt_6 = __VERIFIER_nondet_int() [L704] COND FALSE !(\read(tmp_ndt_6)) [L715] COND TRUE t6_st == 0 [L716] int tmp_ndt_7; [L717] tmp_ndt_7 = __VERIFIER_nondet_int() [L718] COND FALSE !(\read(tmp_ndt_7)) [L729] COND TRUE t7_st == 0 [L730] int tmp_ndt_8; [L731] tmp_ndt_8 = __VERIFIER_nondet_int() [L732] COND FALSE !(\read(tmp_ndt_8)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-12-06 22:18:45,122 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6ae3e5e5-cf62-4174-8737-dd2fe952f97a/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)