./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.09.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 839c364b Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_711ccc98-c351-4520-bb63-2c8f9d053a0c/bin/uautomizer-DrprNOufMa/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_711ccc98-c351-4520-bb63-2c8f9d053a0c/bin/uautomizer-DrprNOufMa/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_711ccc98-c351-4520-bb63-2c8f9d053a0c/bin/uautomizer-DrprNOufMa/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_711ccc98-c351-4520-bb63-2c8f9d053a0c/bin/uautomizer-DrprNOufMa/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.09.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_711ccc98-c351-4520-bb63-2c8f9d053a0c/bin/uautomizer-DrprNOufMa/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_711ccc98-c351-4520-bb63-2c8f9d053a0c/bin/uautomizer-DrprNOufMa --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 3945fa4b58cef50cb4b44b435a699812e99a1f6375664d08551274c6b50bee45 --- Real Ultimate output --- This is Ultimate 0.2.2-hotfix-svcomp22-839c364 [2021-12-06 17:44:52,507 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-06 17:44:52,508 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-06 17:44:52,539 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-06 17:44:52,539 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-06 17:44:52,540 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-06 17:44:52,542 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-06 17:44:52,544 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-06 17:44:52,546 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-06 17:44:52,547 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-06 17:44:52,548 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-06 17:44:52,550 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-06 17:44:52,550 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-06 17:44:52,551 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-06 17:44:52,553 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-06 17:44:52,554 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-06 17:44:52,555 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-06 17:44:52,556 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-06 17:44:52,558 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-06 17:44:52,560 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-06 17:44:52,562 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-06 17:44:52,563 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-06 17:44:52,565 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-06 17:44:52,566 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-06 17:44:52,569 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-06 17:44:52,569 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-06 17:44:52,570 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-06 17:44:52,571 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-06 17:44:52,572 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-06 17:44:52,573 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-06 17:44:52,573 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-06 17:44:52,574 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-06 17:44:52,575 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-06 17:44:52,575 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-06 17:44:52,576 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-06 17:44:52,576 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-06 17:44:52,577 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-06 17:44:52,577 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-06 17:44:52,577 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-06 17:44:52,578 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-06 17:44:52,578 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-06 17:44:52,579 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_711ccc98-c351-4520-bb63-2c8f9d053a0c/bin/uautomizer-DrprNOufMa/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-06 17:44:52,602 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-06 17:44:52,602 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-06 17:44:52,602 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-06 17:44:52,602 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-06 17:44:52,604 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-06 17:44:52,604 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-06 17:44:52,604 INFO L138 SettingsManager]: * Use SBE=true [2021-12-06 17:44:52,604 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-06 17:44:52,604 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-06 17:44:52,604 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-06 17:44:52,605 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-06 17:44:52,605 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-06 17:44:52,605 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-06 17:44:52,605 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-06 17:44:52,605 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-06 17:44:52,606 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-06 17:44:52,606 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-06 17:44:52,606 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-06 17:44:52,606 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-06 17:44:52,606 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-06 17:44:52,606 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-06 17:44:52,607 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-06 17:44:52,607 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-06 17:44:52,607 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-06 17:44:52,607 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-06 17:44:52,607 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-06 17:44:52,607 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-06 17:44:52,608 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-06 17:44:52,608 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-06 17:44:52,608 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-06 17:44:52,608 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-06 17:44:52,608 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-06 17:44:52,609 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-06 17:44:52,610 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_711ccc98-c351-4520-bb63-2c8f9d053a0c/bin/uautomizer-DrprNOufMa/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_711ccc98-c351-4520-bb63-2c8f9d053a0c/bin/uautomizer-DrprNOufMa Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 3945fa4b58cef50cb4b44b435a699812e99a1f6375664d08551274c6b50bee45 [2021-12-06 17:44:52,806 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-06 17:44:52,821 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-06 17:44:52,823 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-06 17:44:52,823 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-06 17:44:52,824 INFO L275 PluginConnector]: CDTParser initialized [2021-12-06 17:44:52,825 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_711ccc98-c351-4520-bb63-2c8f9d053a0c/bin/uautomizer-DrprNOufMa/../../sv-benchmarks/c/systemc/transmitter.09.cil.c [2021-12-06 17:44:52,865 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_711ccc98-c351-4520-bb63-2c8f9d053a0c/bin/uautomizer-DrprNOufMa/data/2217c6ca9/cc4b03643e194a2a932b49e2d7f9eca1/FLAG28487746b [2021-12-06 17:44:53,293 INFO L306 CDTParser]: Found 1 translation units. [2021-12-06 17:44:53,294 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_711ccc98-c351-4520-bb63-2c8f9d053a0c/sv-benchmarks/c/systemc/transmitter.09.cil.c [2021-12-06 17:44:53,307 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_711ccc98-c351-4520-bb63-2c8f9d053a0c/bin/uautomizer-DrprNOufMa/data/2217c6ca9/cc4b03643e194a2a932b49e2d7f9eca1/FLAG28487746b [2021-12-06 17:44:53,316 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_711ccc98-c351-4520-bb63-2c8f9d053a0c/bin/uautomizer-DrprNOufMa/data/2217c6ca9/cc4b03643e194a2a932b49e2d7f9eca1 [2021-12-06 17:44:53,318 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-06 17:44:53,319 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-06 17:44:53,320 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-06 17:44:53,320 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-06 17:44:53,322 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-06 17:44:53,323 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 05:44:53" (1/1) ... [2021-12-06 17:44:53,324 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@653bc49a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:44:53, skipping insertion in model container [2021-12-06 17:44:53,324 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 05:44:53" (1/1) ... [2021-12-06 17:44:53,329 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-06 17:44:53,356 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-06 17:44:53,450 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_711ccc98-c351-4520-bb63-2c8f9d053a0c/sv-benchmarks/c/systemc/transmitter.09.cil.c[706,719] [2021-12-06 17:44:53,542 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-06 17:44:53,550 INFO L203 MainTranslator]: Completed pre-run [2021-12-06 17:44:53,558 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_711ccc98-c351-4520-bb63-2c8f9d053a0c/sv-benchmarks/c/systemc/transmitter.09.cil.c[706,719] [2021-12-06 17:44:53,595 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-06 17:44:53,608 INFO L208 MainTranslator]: Completed translation [2021-12-06 17:44:53,609 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:44:53 WrapperNode [2021-12-06 17:44:53,609 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-06 17:44:53,610 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-06 17:44:53,610 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-06 17:44:53,610 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-06 17:44:53,615 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:44:53" (1/1) ... [2021-12-06 17:44:53,624 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:44:53" (1/1) ... [2021-12-06 17:44:53,676 INFO L137 Inliner]: procedures = 46, calls = 57, calls flagged for inlining = 52, calls inlined = 170, statements flattened = 2581 [2021-12-06 17:44:53,676 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-06 17:44:53,676 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-06 17:44:53,677 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-06 17:44:53,677 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-06 17:44:53,683 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:44:53" (1/1) ... [2021-12-06 17:44:53,683 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:44:53" (1/1) ... [2021-12-06 17:44:53,689 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:44:53" (1/1) ... [2021-12-06 17:44:53,689 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:44:53" (1/1) ... [2021-12-06 17:44:53,713 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:44:53" (1/1) ... [2021-12-06 17:44:53,735 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:44:53" (1/1) ... [2021-12-06 17:44:53,739 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:44:53" (1/1) ... [2021-12-06 17:44:53,747 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-06 17:44:53,748 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-06 17:44:53,748 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-06 17:44:53,748 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-06 17:44:53,749 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:44:53" (1/1) ... [2021-12-06 17:44:53,755 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-06 17:44:53,762 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_711ccc98-c351-4520-bb63-2c8f9d053a0c/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 17:44:53,771 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_711ccc98-c351-4520-bb63-2c8f9d053a0c/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-06 17:44:53,773 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_711ccc98-c351-4520-bb63-2c8f9d053a0c/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-06 17:44:53,799 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-06 17:44:53,800 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-06 17:44:53,800 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-06 17:44:53,800 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-06 17:44:53,874 INFO L236 CfgBuilder]: Building ICFG [2021-12-06 17:44:53,875 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-06 17:44:54,709 INFO L277 CfgBuilder]: Performing block encoding [2021-12-06 17:44:54,728 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-06 17:44:54,729 INFO L301 CfgBuilder]: Removed 13 assume(true) statements. [2021-12-06 17:44:54,732 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 05:44:54 BoogieIcfgContainer [2021-12-06 17:44:54,732 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-06 17:44:54,733 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-06 17:44:54,733 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-06 17:44:54,735 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-06 17:44:54,736 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 17:44:54,736 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.12 05:44:53" (1/3) ... [2021-12-06 17:44:54,737 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@efa115 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.12 05:44:54, skipping insertion in model container [2021-12-06 17:44:54,737 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 17:44:54,737 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:44:53" (2/3) ... [2021-12-06 17:44:54,737 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@efa115 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.12 05:44:54, skipping insertion in model container [2021-12-06 17:44:54,737 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-06 17:44:54,737 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 05:44:54" (3/3) ... [2021-12-06 17:44:54,738 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.09.cil.c [2021-12-06 17:44:54,771 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-06 17:44:54,771 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-06 17:44:54,771 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-06 17:44:54,771 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-06 17:44:54,771 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-06 17:44:54,771 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-06 17:44:54,771 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-06 17:44:54,771 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-06 17:44:54,807 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1101 states, 1100 states have (on average 1.5136363636363637) internal successors, (1665), 1100 states have internal predecessors, (1665), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:44:54,862 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 972 [2021-12-06 17:44:54,862 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:44:54,862 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:44:54,874 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:44:54,874 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:44:54,874 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-06 17:44:54,876 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1101 states, 1100 states have (on average 1.5136363636363637) internal successors, (1665), 1100 states have internal predecessors, (1665), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:44:54,885 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 972 [2021-12-06 17:44:54,885 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:44:54,886 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:44:54,889 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:44:54,889 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:44:54,896 INFO L791 eck$LassoCheckResult]: Stem: 531#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 999#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 220#L1359true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1059#L634true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 721#L641true assume !(1 == ~m_i~0);~m_st~0 := 2; 769#L641-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 695#L646-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 483#L651-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 972#L656-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 327#L661-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 930#L666-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 849#L671-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 673#L676-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 374#L681-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 224#L686-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1090#L922true assume !(0 == ~M_E~0); 1027#L922-2true assume !(0 == ~T1_E~0); 1047#L927-1true assume !(0 == ~T2_E~0); 539#L932-1true assume !(0 == ~T3_E~0); 428#L937-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 482#L942-1true assume !(0 == ~T5_E~0); 725#L947-1true assume !(0 == ~T6_E~0); 543#L952-1true assume !(0 == ~T7_E~0); 620#L957-1true assume !(0 == ~T8_E~0); 969#L962-1true assume !(0 == ~T9_E~0); 409#L967-1true assume !(0 == ~E_1~0); 936#L972-1true assume !(0 == ~E_2~0); 704#L977-1true assume 0 == ~E_3~0;~E_3~0 := 1; 1038#L982-1true assume !(0 == ~E_4~0); 105#L987-1true assume !(0 == ~E_5~0); 109#L992-1true assume !(0 == ~E_6~0); 356#L997-1true assume !(0 == ~E_7~0); 880#L1002-1true assume !(0 == ~E_8~0); 346#L1007-1true assume !(0 == ~E_9~0); 8#L1012-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 872#L443true assume !(1 == ~m_pc~0); 557#L443-2true is_master_triggered_~__retres1~0#1 := 0; 548#L454true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 962#L455true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 190#L1140true assume !(0 != activate_threads_~tmp~1#1); 63#L1140-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 896#L462true assume 1 == ~t1_pc~0; 450#L463true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 942#L473true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48#L474true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 568#L1148true assume !(0 != activate_threads_~tmp___0~0#1); 315#L1148-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 980#L481true assume !(1 == ~t2_pc~0); 774#L481-2true is_transmit2_triggered_~__retres1~2#1 := 0; 529#L492true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 426#L493true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 237#L1156true assume !(0 != activate_threads_~tmp___1~0#1); 299#L1156-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1082#L500true assume 1 == ~t3_pc~0; 462#L501true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 738#L511true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 688#L512true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 765#L1164true assume !(0 != activate_threads_~tmp___2~0#1); 9#L1164-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 750#L519true assume 1 == ~t4_pc~0; 156#L520true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 298#L530true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 578#L531true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 210#L1172true assume !(0 != activate_threads_~tmp___3~0#1); 504#L1172-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 90#L538true assume !(1 == ~t5_pc~0); 827#L538-2true is_transmit5_triggered_~__retres1~5#1 := 0; 43#L549true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 954#L550true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 178#L1180true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 602#L1180-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1103#L557true assume 1 == ~t6_pc~0; 401#L558true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 809#L568true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 146#L569true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 211#L1188true assume !(0 != activate_threads_~tmp___5~0#1); 931#L1188-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1052#L576true assume !(1 == ~t7_pc~0); 303#L576-2true is_transmit7_triggered_~__retres1~7#1 := 0; 400#L587true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 349#L588true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1048#L1196true assume !(0 != activate_threads_~tmp___6~0#1); 657#L1196-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 258#L595true assume 1 == ~t8_pc~0; 1002#L596true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 689#L606true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 845#L607true activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 506#L1204true assume !(0 != activate_threads_~tmp___7~0#1); 934#L1204-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 153#L614true assume !(1 == ~t9_pc~0); 451#L614-2true is_transmit9_triggered_~__retres1~9#1 := 0; 101#L625true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 195#L626true activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 671#L1212true assume !(0 != activate_threads_~tmp___8~0#1); 238#L1212-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 415#L1025true assume !(1 == ~M_E~0); 461#L1025-2true assume !(1 == ~T1_E~0); 595#L1030-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 745#L1035-1true assume !(1 == ~T3_E~0); 234#L1040-1true assume !(1 == ~T4_E~0); 729#L1045-1true assume !(1 == ~T5_E~0); 184#L1050-1true assume !(1 == ~T6_E~0); 293#L1055-1true assume !(1 == ~T7_E~0); 94#L1060-1true assume !(1 == ~T8_E~0); 125#L1065-1true assume !(1 == ~T9_E~0); 949#L1070-1true assume 1 == ~E_1~0;~E_1~0 := 2; 544#L1075-1true assume !(1 == ~E_2~0); 1086#L1080-1true assume !(1 == ~E_3~0); 536#L1085-1true assume !(1 == ~E_4~0); 839#L1090-1true assume !(1 == ~E_5~0); 967#L1095-1true assume !(1 == ~E_6~0); 576#L1100-1true assume !(1 == ~E_7~0); 583#L1105-1true assume !(1 == ~E_8~0); 82#L1110-1true assume 1 == ~E_9~0;~E_9~0 := 2; 265#L1115-1true assume { :end_inline_reset_delta_events } true; 206#L1396-2true [2021-12-06 17:44:54,898 INFO L793 eck$LassoCheckResult]: Loop: 206#L1396-2true assume !false; 950#L1397true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 966#L897true assume false; 786#L912true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 51#L634-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 342#L922-3true assume 0 == ~M_E~0;~M_E~0 := 1; 971#L922-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 174#L927-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 278#L932-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 534#L937-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 77#L942-3true assume !(0 == ~T5_E~0); 624#L947-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 279#L952-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 811#L957-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 833#L962-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 633#L967-3true assume 0 == ~E_1~0;~E_1~0 := 1; 855#L972-3true assume 0 == ~E_2~0;~E_2~0 := 1; 538#L977-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1089#L982-3true assume !(0 == ~E_4~0); 1061#L987-3true assume 0 == ~E_5~0;~E_5~0 := 1; 244#L992-3true assume 0 == ~E_6~0;~E_6~0 := 1; 360#L997-3true assume 0 == ~E_7~0;~E_7~0 := 1; 242#L1002-3true assume 0 == ~E_8~0;~E_8~0 := 1; 494#L1007-3true assume 0 == ~E_9~0;~E_9~0 := 1; 95#L1012-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 272#L443-30true assume 1 == ~m_pc~0; 111#L444-10true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 262#L454-10true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 884#L455-10true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 946#L1140-30true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 711#L1140-32true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 332#L462-30true assume !(1 == ~t1_pc~0); 801#L462-32true is_transmit1_triggered_~__retres1~1#1 := 0; 701#L473-10true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 686#L474-10true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 741#L1148-30true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1067#L1148-32true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 323#L481-30true assume 1 == ~t2_pc~0; 157#L482-10true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 666#L492-10true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 185#L493-10true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 141#L1156-30true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 302#L1156-32true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 552#L500-30true assume !(1 == ~t3_pc~0); 1068#L500-32true is_transmit3_triggered_~__retres1~3#1 := 0; 362#L511-10true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 194#L512-10true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1026#L1164-30true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 291#L1164-32true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 638#L519-30true assume 1 == ~t4_pc~0; 586#L520-10true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 404#L530-10true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30#L531-10true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 411#L1172-30true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 519#L1172-32true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 926#L538-30true assume !(1 == ~t5_pc~0); 865#L538-32true is_transmit5_triggered_~__retres1~5#1 := 0; 281#L549-10true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 257#L550-10true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 661#L1180-30true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 138#L1180-32true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 144#L557-30true assume !(1 == ~t6_pc~0); 368#L557-32true is_transmit6_triggered_~__retres1~6#1 := 0; 389#L568-10true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 430#L569-10true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1045#L1188-30true assume !(0 != activate_threads_~tmp___5~0#1); 152#L1188-32true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 511#L576-30true assume !(1 == ~t7_pc~0); 42#L576-32true is_transmit7_triggered_~__retres1~7#1 := 0; 384#L587-10true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1074#L588-10true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 836#L1196-30true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 235#L1196-32true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 215#L595-30true assume !(1 == ~t8_pc~0); 756#L595-32true is_transmit8_triggered_~__retres1~8#1 := 0; 181#L606-10true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47#L607-10true activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 837#L1204-30true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1093#L1204-32true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 939#L614-30true assume 1 == ~t9_pc~0; 183#L615-10true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 640#L625-10true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 255#L626-10true activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 96#L1212-30true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 618#L1212-32true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 495#L1025-3true assume 1 == ~M_E~0;~M_E~0 := 2; 317#L1025-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 464#L1030-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 856#L1035-3true assume !(1 == ~T3_E~0); 1018#L1040-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1040#L1045-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 846#L1050-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 687#L1055-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 46#L1060-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 720#L1065-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 713#L1070-3true assume 1 == ~E_1~0;~E_1~0 := 2; 522#L1075-3true assume !(1 == ~E_2~0); 857#L1080-3true assume 1 == ~E_3~0;~E_3~0 := 2; 940#L1085-3true assume 1 == ~E_4~0;~E_4~0 := 2; 698#L1090-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1006#L1095-3true assume 1 == ~E_6~0;~E_6~0 := 2; 728#L1100-3true assume 1 == ~E_7~0;~E_7~0 := 2; 915#L1105-3true assume 1 == ~E_8~0;~E_8~0 := 2; 119#L1110-3true assume 1 == ~E_9~0;~E_9~0 := 2; 777#L1115-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 753#L699-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 122#L751-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 50#L752-1true start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 710#L1415true assume !(0 == start_simulation_~tmp~3#1); 408#L1415-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 970#L699-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 413#L751-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 598#L752-2true stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1077#L1370true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1062#L1377true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 458#L1378true start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 161#L1428true assume !(0 != start_simulation_~tmp___0~1#1); 206#L1396-2true [2021-12-06 17:44:54,904 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:44:54,905 INFO L85 PathProgramCache]: Analyzing trace with hash 1400170149, now seen corresponding path program 1 times [2021-12-06 17:44:54,911 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:44:54,912 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [134544050] [2021-12-06 17:44:54,912 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:44:54,913 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:44:55,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:44:55,086 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:44:55,087 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:44:55,087 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [134544050] [2021-12-06 17:44:55,087 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [134544050] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:44:55,088 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:44:55,088 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:44:55,089 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [618904703] [2021-12-06 17:44:55,089 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:44:55,093 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:44:55,093 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:44:55,094 INFO L85 PathProgramCache]: Analyzing trace with hash -2065415498, now seen corresponding path program 1 times [2021-12-06 17:44:55,094 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:44:55,094 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2095542288] [2021-12-06 17:44:55,094 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:44:55,094 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:44:55,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:44:55,133 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:44:55,133 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:44:55,133 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2095542288] [2021-12-06 17:44:55,133 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2095542288] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:44:55,134 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:44:55,134 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 17:44:55,134 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [681425740] [2021-12-06 17:44:55,134 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:44:55,136 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:44:55,137 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:44:55,162 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:44:55,162 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:44:55,165 INFO L87 Difference]: Start difference. First operand has 1101 states, 1100 states have (on average 1.5136363636363637) internal successors, (1665), 1100 states have internal predecessors, (1665), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:44:55,268 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:44:55,268 INFO L93 Difference]: Finished difference Result 1100 states and 1636 transitions. [2021-12-06 17:44:55,269 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:44:55,272 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1100 states and 1636 transitions. [2021-12-06 17:44:55,281 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2021-12-06 17:44:55,293 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1100 states to 1094 states and 1630 transitions. [2021-12-06 17:44:55,294 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1094 [2021-12-06 17:44:55,295 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1094 [2021-12-06 17:44:55,296 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1094 states and 1630 transitions. [2021-12-06 17:44:55,301 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:44:55,301 INFO L681 BuchiCegarLoop]: Abstraction has 1094 states and 1630 transitions. [2021-12-06 17:44:55,315 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1094 states and 1630 transitions. [2021-12-06 17:44:55,351 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1094 to 1094. [2021-12-06 17:44:55,354 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1094 states, 1094 states have (on average 1.489945155393053) internal successors, (1630), 1093 states have internal predecessors, (1630), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:44:55,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1094 states to 1094 states and 1630 transitions. [2021-12-06 17:44:55,359 INFO L704 BuchiCegarLoop]: Abstraction has 1094 states and 1630 transitions. [2021-12-06 17:44:55,359 INFO L587 BuchiCegarLoop]: Abstraction has 1094 states and 1630 transitions. [2021-12-06 17:44:55,359 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-06 17:44:55,359 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1094 states and 1630 transitions. [2021-12-06 17:44:55,364 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2021-12-06 17:44:55,364 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:44:55,364 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:44:55,366 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:44:55,367 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:44:55,367 INFO L791 eck$LassoCheckResult]: Stem: 3047#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 3048#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 2648#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2649#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3195#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 3196#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3178#L646-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2998#L651-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2999#L656-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2815#L661-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2816#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3255#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3162#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2870#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2654#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2655#L922 assume !(0 == ~M_E~0); 3300#L922-2 assume !(0 == ~T1_E~0); 3301#L927-1 assume !(0 == ~T2_E~0); 3055#L932-1 assume !(0 == ~T3_E~0); 2940#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2941#L942-1 assume !(0 == ~T5_E~0); 2997#L947-1 assume !(0 == ~T6_E~0); 3059#L952-1 assume !(0 == ~T7_E~0); 3060#L957-1 assume !(0 == ~T8_E~0); 3120#L962-1 assume !(0 == ~T9_E~0); 2916#L967-1 assume !(0 == ~E_1~0); 2917#L972-1 assume !(0 == ~E_2~0); 3183#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 3184#L982-1 assume !(0 == ~E_4~0); 2424#L987-1 assume !(0 == ~E_5~0); 2425#L992-1 assume !(0 == ~E_6~0); 2433#L997-1 assume !(0 == ~E_7~0); 2847#L1002-1 assume !(0 == ~E_8~0); 2834#L1007-1 assume !(0 == ~E_9~0); 2222#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2223#L443 assume !(1 == ~m_pc~0); 3075#L443-2 is_master_triggered_~__retres1~0#1 := 0; 3066#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3067#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2588#L1140 assume !(0 != activate_threads_~tmp~1#1); 2337#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2338#L462 assume 1 == ~t1_pc~0; 2966#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2933#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2308#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2309#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 2796#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2797#L481 assume !(1 == ~t2_pc~0); 2583#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2582#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2937#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2676#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 2677#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2769#L500 assume 1 == ~t3_pc~0; 2979#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2980#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3170#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3171#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 2224#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2225#L519 assume 1 == ~t4_pc~0; 2523#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2524#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2768#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2628#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 2629#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2391#L538 assume !(1 == ~t5_pc~0); 2392#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2298#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2299#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2567#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2568#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3105#L557 assume 1 == ~t6_pc~0; 2904#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2605#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2505#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2506#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 2630#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3283#L576 assume !(1 == ~t7_pc~0); 2592#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2593#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2837#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2838#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 3154#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2713#L595 assume 1 == ~t8_pc~0; 2714#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3172#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3173#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3022#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 3023#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2516#L614 assume !(1 == ~t9_pc~0); 2517#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2416#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2417#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2596#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 2678#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2679#L1025 assume !(1 == ~M_E~0); 2925#L1025-2 assume !(1 == ~T1_E~0); 2978#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3100#L1035-1 assume !(1 == ~T3_E~0); 2672#L1040-1 assume !(1 == ~T4_E~0); 2673#L1045-1 assume !(1 == ~T5_E~0); 2578#L1050-1 assume !(1 == ~T6_E~0); 2579#L1055-1 assume !(1 == ~T7_E~0); 2400#L1060-1 assume !(1 == ~T8_E~0); 2401#L1065-1 assume !(1 == ~T9_E~0); 2464#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3061#L1075-1 assume !(1 == ~E_2~0); 3062#L1080-1 assume !(1 == ~E_3~0); 3050#L1085-1 assume !(1 == ~E_4~0); 3051#L1090-1 assume !(1 == ~E_5~0); 3250#L1095-1 assume !(1 == ~E_6~0); 3084#L1100-1 assume !(1 == ~E_7~0); 3085#L1105-1 assume !(1 == ~E_8~0); 2373#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 2374#L1115-1 assume { :end_inline_reset_delta_events } true; 2535#L1396-2 [2021-12-06 17:44:55,374 INFO L793 eck$LassoCheckResult]: Loop: 2535#L1396-2 assume !false; 2618#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2647#L897 assume !false; 3290#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3197#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2245#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2246#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3245#L766 assume !(0 != eval_~tmp~0#1); 3231#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2315#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2316#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2830#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2559#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2560#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2738#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2365#L942-3 assume !(0 == ~T5_E~0); 2366#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2739#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2740#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3241#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3132#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3133#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3053#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3054#L982-3 assume !(0 == ~E_4~0); 3302#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2689#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2690#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2684#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2685#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2402#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2403#L443-30 assume 1 == ~m_pc~0; 2436#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2437#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2720#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3268#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3187#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2820#L462-30 assume 1 == ~t1_pc~0; 2664#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2666#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3168#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3169#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3209#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2807#L481-30 assume !(1 == ~t2_pc~0); 2528#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 2527#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2580#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2493#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2494#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2774#L500-30 assume 1 == ~t3_pc~0; 2531#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2532#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2594#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2595#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2757#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2758#L519-30 assume 1 == ~t4_pc~0; 3093#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2909#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2271#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2272#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2921#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3034#L538-30 assume 1 == ~t5_pc~0; 2412#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2413#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2711#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2712#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2489#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2490#L557-30 assume 1 == ~t6_pc~0; 2210#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2211#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2888#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2948#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 2514#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2515#L576-30 assume 1 == ~t7_pc~0; 3027#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2297#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2882#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3248#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2674#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2637#L595-30 assume !(1 == ~t8_pc~0); 2638#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2569#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2306#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2307#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3249#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3285#L614-30 assume !(1 == ~t9_pc~0); 2576#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 2575#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2710#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2404#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2405#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3013#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2798#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2799#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2983#L1035-3 assume !(1 == ~T3_E~0); 3258#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3298#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3254#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3167#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2304#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2305#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3189#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3035#L1075-3 assume !(1 == ~E_2~0); 3036#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3259#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3180#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3181#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3200#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3201#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2452#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2453#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3212#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2321#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2310#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2311#L1415 assume !(0 == start_simulation_~tmp~3#1); 2912#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2913#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2361#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2923#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 3102#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3303#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2971#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2534#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 2535#L1396-2 [2021-12-06 17:44:55,375 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:44:55,375 INFO L85 PathProgramCache]: Analyzing trace with hash -1247434205, now seen corresponding path program 1 times [2021-12-06 17:44:55,375 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:44:55,375 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1859047846] [2021-12-06 17:44:55,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:44:55,376 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:44:55,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:44:55,431 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:44:55,432 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:44:55,432 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1859047846] [2021-12-06 17:44:55,432 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1859047846] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:44:55,432 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:44:55,432 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:44:55,433 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1542585515] [2021-12-06 17:44:55,433 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:44:55,433 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:44:55,434 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:44:55,434 INFO L85 PathProgramCache]: Analyzing trace with hash -1392985774, now seen corresponding path program 1 times [2021-12-06 17:44:55,434 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:44:55,434 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1450117390] [2021-12-06 17:44:55,434 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:44:55,434 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:44:55,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:44:55,514 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:44:55,514 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:44:55,515 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1450117390] [2021-12-06 17:44:55,515 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1450117390] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:44:55,515 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:44:55,515 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:44:55,515 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [102749472] [2021-12-06 17:44:55,515 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:44:55,516 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:44:55,516 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:44:55,516 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:44:55,516 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:44:55,517 INFO L87 Difference]: Start difference. First operand 1094 states and 1630 transitions. cyclomatic complexity: 537 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:44:55,556 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:44:55,556 INFO L93 Difference]: Finished difference Result 1094 states and 1629 transitions. [2021-12-06 17:44:55,556 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:44:55,557 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1094 states and 1629 transitions. [2021-12-06 17:44:55,564 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2021-12-06 17:44:55,571 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1094 states to 1094 states and 1629 transitions. [2021-12-06 17:44:55,571 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1094 [2021-12-06 17:44:55,572 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1094 [2021-12-06 17:44:55,572 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1094 states and 1629 transitions. [2021-12-06 17:44:55,574 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:44:55,574 INFO L681 BuchiCegarLoop]: Abstraction has 1094 states and 1629 transitions. [2021-12-06 17:44:55,575 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1094 states and 1629 transitions. [2021-12-06 17:44:55,586 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1094 to 1094. [2021-12-06 17:44:55,588 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1094 states, 1094 states have (on average 1.4890310786106034) internal successors, (1629), 1093 states have internal predecessors, (1629), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:44:55,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1094 states to 1094 states and 1629 transitions. [2021-12-06 17:44:55,592 INFO L704 BuchiCegarLoop]: Abstraction has 1094 states and 1629 transitions. [2021-12-06 17:44:55,592 INFO L587 BuchiCegarLoop]: Abstraction has 1094 states and 1629 transitions. [2021-12-06 17:44:55,592 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-06 17:44:55,592 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1094 states and 1629 transitions. [2021-12-06 17:44:55,596 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2021-12-06 17:44:55,596 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:44:55,596 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:44:55,598 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:44:55,598 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:44:55,599 INFO L791 eck$LassoCheckResult]: Stem: 5242#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 5243#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 4843#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4844#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5390#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 5391#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5373#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5193#L651-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5194#L656-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5010#L661-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5011#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5450#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5357#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5065#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4849#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4850#L922 assume !(0 == ~M_E~0); 5495#L922-2 assume !(0 == ~T1_E~0); 5496#L927-1 assume !(0 == ~T2_E~0); 5250#L932-1 assume !(0 == ~T3_E~0); 5135#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5136#L942-1 assume !(0 == ~T5_E~0); 5192#L947-1 assume !(0 == ~T6_E~0); 5254#L952-1 assume !(0 == ~T7_E~0); 5255#L957-1 assume !(0 == ~T8_E~0); 5317#L962-1 assume !(0 == ~T9_E~0); 5111#L967-1 assume !(0 == ~E_1~0); 5112#L972-1 assume !(0 == ~E_2~0); 5378#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 5379#L982-1 assume !(0 == ~E_4~0); 4619#L987-1 assume !(0 == ~E_5~0); 4620#L992-1 assume !(0 == ~E_6~0); 4628#L997-1 assume !(0 == ~E_7~0); 5042#L1002-1 assume !(0 == ~E_8~0); 5029#L1007-1 assume !(0 == ~E_9~0); 4417#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4418#L443 assume !(1 == ~m_pc~0); 5270#L443-2 is_master_triggered_~__retres1~0#1 := 0; 5261#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5262#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4783#L1140 assume !(0 != activate_threads_~tmp~1#1); 4532#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4533#L462 assume 1 == ~t1_pc~0; 5161#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5128#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4503#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4504#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 4991#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4992#L481 assume !(1 == ~t2_pc~0); 4778#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4777#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5132#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4871#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 4872#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4964#L500 assume 1 == ~t3_pc~0; 5174#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5175#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5365#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5366#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 4419#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4420#L519 assume 1 == ~t4_pc~0; 4718#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4719#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4963#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4825#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 4826#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4586#L538 assume !(1 == ~t5_pc~0); 4587#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4493#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4494#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4762#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4763#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5302#L557 assume 1 == ~t6_pc~0; 5099#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4800#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4700#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4701#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 4827#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5478#L576 assume !(1 == ~t7_pc~0); 4787#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4788#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5032#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5033#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 5349#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4908#L595 assume 1 == ~t8_pc~0; 4909#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5367#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5368#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5217#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 5218#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4711#L614 assume !(1 == ~t9_pc~0); 4712#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4611#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4612#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4791#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 4873#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4874#L1025 assume !(1 == ~M_E~0); 5120#L1025-2 assume !(1 == ~T1_E~0); 5173#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5295#L1035-1 assume !(1 == ~T3_E~0); 4868#L1040-1 assume !(1 == ~T4_E~0); 4869#L1045-1 assume !(1 == ~T5_E~0); 4773#L1050-1 assume !(1 == ~T6_E~0); 4774#L1055-1 assume !(1 == ~T7_E~0); 4595#L1060-1 assume !(1 == ~T8_E~0); 4596#L1065-1 assume !(1 == ~T9_E~0); 4659#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 5256#L1075-1 assume !(1 == ~E_2~0); 5257#L1080-1 assume !(1 == ~E_3~0); 5245#L1085-1 assume !(1 == ~E_4~0); 5246#L1090-1 assume !(1 == ~E_5~0); 5445#L1095-1 assume !(1 == ~E_6~0); 5279#L1100-1 assume !(1 == ~E_7~0); 5280#L1105-1 assume !(1 == ~E_8~0); 4568#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 4569#L1115-1 assume { :end_inline_reset_delta_events } true; 4730#L1396-2 [2021-12-06 17:44:55,599 INFO L793 eck$LassoCheckResult]: Loop: 4730#L1396-2 assume !false; 4813#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4842#L897 assume !false; 5485#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5392#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4442#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4443#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5440#L766 assume !(0 != eval_~tmp~0#1); 5426#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4510#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4511#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5025#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4754#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4755#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4933#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4560#L942-3 assume !(0 == ~T5_E~0); 4561#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4934#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4935#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5436#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5327#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5328#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5248#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5249#L982-3 assume !(0 == ~E_4~0); 5497#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4884#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4885#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4882#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4883#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4597#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4598#L443-30 assume 1 == ~m_pc~0; 4631#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4632#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4915#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5463#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5382#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5015#L462-30 assume 1 == ~t1_pc~0; 4860#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4862#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5363#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5364#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5404#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5002#L481-30 assume 1 == ~t2_pc~0; 4721#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4722#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4775#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4688#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4689#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4969#L500-30 assume 1 == ~t3_pc~0; 4726#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4727#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4789#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4790#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4954#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4955#L519-30 assume 1 == ~t4_pc~0; 5289#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5104#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4466#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4467#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5116#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5229#L538-30 assume !(1 == ~t5_pc~0); 4609#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 4608#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4906#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4907#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4684#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4685#L557-30 assume 1 == ~t6_pc~0; 4405#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4406#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5083#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5137#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 4709#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4710#L576-30 assume 1 == ~t7_pc~0; 5222#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4487#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5076#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5443#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4867#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4832#L595-30 assume !(1 == ~t8_pc~0); 4833#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 4764#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4501#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4502#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5444#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5480#L614-30 assume 1 == ~t9_pc~0; 4769#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4770#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4905#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4599#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4600#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5208#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4993#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4994#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5178#L1035-3 assume !(1 == ~T3_E~0); 5453#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5493#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5449#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5362#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4499#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4500#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5384#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5230#L1075-3 assume !(1 == ~E_2~0); 5231#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5454#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5375#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5376#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5395#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5396#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4647#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4648#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5408#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4516#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4505#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 4506#L1415 assume !(0 == start_simulation_~tmp~3#1); 5108#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5109#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4556#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 5118#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 5297#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5498#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5168#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 4729#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 4730#L1396-2 [2021-12-06 17:44:55,600 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:44:55,600 INFO L85 PathProgramCache]: Analyzing trace with hash -208849631, now seen corresponding path program 1 times [2021-12-06 17:44:55,600 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:44:55,600 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [402750006] [2021-12-06 17:44:55,600 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:44:55,600 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:44:55,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:44:55,641 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:44:55,642 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:44:55,642 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [402750006] [2021-12-06 17:44:55,642 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [402750006] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:44:55,642 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:44:55,642 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:44:55,642 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [612348674] [2021-12-06 17:44:55,642 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:44:55,643 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:44:55,643 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:44:55,643 INFO L85 PathProgramCache]: Analyzing trace with hash -1113508429, now seen corresponding path program 1 times [2021-12-06 17:44:55,643 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:44:55,643 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [621767654] [2021-12-06 17:44:55,644 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:44:55,644 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:44:55,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:44:55,694 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:44:55,694 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:44:55,694 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [621767654] [2021-12-06 17:44:55,695 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [621767654] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:44:55,695 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:44:55,695 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:44:55,695 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [455620090] [2021-12-06 17:44:55,695 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:44:55,695 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:44:55,696 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:44:55,696 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:44:55,696 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:44:55,696 INFO L87 Difference]: Start difference. First operand 1094 states and 1629 transitions. cyclomatic complexity: 536 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:44:55,715 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:44:55,715 INFO L93 Difference]: Finished difference Result 1094 states and 1628 transitions. [2021-12-06 17:44:55,715 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:44:55,716 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1094 states and 1628 transitions. [2021-12-06 17:44:55,721 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2021-12-06 17:44:55,728 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1094 states to 1094 states and 1628 transitions. [2021-12-06 17:44:55,728 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1094 [2021-12-06 17:44:55,729 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1094 [2021-12-06 17:44:55,729 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1094 states and 1628 transitions. [2021-12-06 17:44:55,730 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:44:55,730 INFO L681 BuchiCegarLoop]: Abstraction has 1094 states and 1628 transitions. [2021-12-06 17:44:55,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1094 states and 1628 transitions. [2021-12-06 17:44:55,743 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1094 to 1094. [2021-12-06 17:44:55,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1094 states, 1094 states have (on average 1.4881170018281535) internal successors, (1628), 1093 states have internal predecessors, (1628), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:44:55,748 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1094 states to 1094 states and 1628 transitions. [2021-12-06 17:44:55,748 INFO L704 BuchiCegarLoop]: Abstraction has 1094 states and 1628 transitions. [2021-12-06 17:44:55,748 INFO L587 BuchiCegarLoop]: Abstraction has 1094 states and 1628 transitions. [2021-12-06 17:44:55,748 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-06 17:44:55,748 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1094 states and 1628 transitions. [2021-12-06 17:44:55,752 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2021-12-06 17:44:55,752 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:44:55,753 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:44:55,754 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:44:55,754 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:44:55,754 INFO L791 eck$LassoCheckResult]: Stem: 7437#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 7438#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 7038#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7039#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7585#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 7586#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7568#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7388#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7389#L656-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7205#L661-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7206#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7646#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7552#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7260#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7044#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7045#L922 assume !(0 == ~M_E~0); 7690#L922-2 assume !(0 == ~T1_E~0); 7691#L927-1 assume !(0 == ~T2_E~0); 7445#L932-1 assume !(0 == ~T3_E~0); 7330#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7331#L942-1 assume !(0 == ~T5_E~0); 7387#L947-1 assume !(0 == ~T6_E~0); 7449#L952-1 assume !(0 == ~T7_E~0); 7450#L957-1 assume !(0 == ~T8_E~0); 7512#L962-1 assume !(0 == ~T9_E~0); 7306#L967-1 assume !(0 == ~E_1~0); 7307#L972-1 assume !(0 == ~E_2~0); 7573#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 7574#L982-1 assume !(0 == ~E_4~0); 6814#L987-1 assume !(0 == ~E_5~0); 6815#L992-1 assume !(0 == ~E_6~0); 6823#L997-1 assume !(0 == ~E_7~0); 7239#L1002-1 assume !(0 == ~E_8~0); 7224#L1007-1 assume !(0 == ~E_9~0); 6612#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6613#L443 assume !(1 == ~m_pc~0); 7465#L443-2 is_master_triggered_~__retres1~0#1 := 0; 7456#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7457#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6978#L1140 assume !(0 != activate_threads_~tmp~1#1); 6727#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6728#L462 assume 1 == ~t1_pc~0; 7356#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7324#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6698#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6699#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 7186#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7187#L481 assume !(1 == ~t2_pc~0); 6973#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6972#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7327#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7066#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 7067#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7161#L500 assume 1 == ~t3_pc~0; 7369#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7370#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7560#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7561#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 6614#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6615#L519 assume 1 == ~t4_pc~0; 6913#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6914#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7158#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7020#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 7021#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6781#L538 assume !(1 == ~t5_pc~0); 6782#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 6688#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6689#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6957#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6958#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7497#L557 assume 1 == ~t6_pc~0; 7294#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6995#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6897#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6898#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 7022#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7673#L576 assume !(1 == ~t7_pc~0); 6982#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 6983#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7227#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7228#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 7544#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7103#L595 assume 1 == ~t8_pc~0; 7104#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7562#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7563#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7412#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 7413#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6906#L614 assume !(1 == ~t9_pc~0); 6907#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 6806#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6807#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6986#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 7068#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7069#L1025 assume !(1 == ~M_E~0); 7315#L1025-2 assume !(1 == ~T1_E~0); 7368#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7490#L1035-1 assume !(1 == ~T3_E~0); 7063#L1040-1 assume !(1 == ~T4_E~0); 7064#L1045-1 assume !(1 == ~T5_E~0); 6968#L1050-1 assume !(1 == ~T6_E~0); 6969#L1055-1 assume !(1 == ~T7_E~0); 6790#L1060-1 assume !(1 == ~T8_E~0); 6791#L1065-1 assume !(1 == ~T9_E~0); 6854#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7451#L1075-1 assume !(1 == ~E_2~0); 7452#L1080-1 assume !(1 == ~E_3~0); 7440#L1085-1 assume !(1 == ~E_4~0); 7441#L1090-1 assume !(1 == ~E_5~0); 7640#L1095-1 assume !(1 == ~E_6~0); 7474#L1100-1 assume !(1 == ~E_7~0); 7475#L1105-1 assume !(1 == ~E_8~0); 6763#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 6764#L1115-1 assume { :end_inline_reset_delta_events } true; 6925#L1396-2 [2021-12-06 17:44:55,755 INFO L793 eck$LassoCheckResult]: Loop: 6925#L1396-2 assume !false; 7008#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7037#L897 assume !false; 7680#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7587#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 6637#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 6638#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7635#L766 assume !(0 != eval_~tmp~0#1); 7621#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6705#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6706#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7222#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6949#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6950#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7128#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6755#L942-3 assume !(0 == ~T5_E~0); 6756#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7129#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7130#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7631#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7522#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7523#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7443#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7444#L982-3 assume !(0 == ~E_4~0); 7692#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7079#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7080#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7077#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7078#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6792#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6793#L443-30 assume 1 == ~m_pc~0; 6826#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6827#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7110#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7658#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7577#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7210#L462-30 assume !(1 == ~t1_pc~0); 7056#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 7057#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7558#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7559#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7599#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7197#L481-30 assume 1 == ~t2_pc~0; 6916#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6917#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6970#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6886#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6887#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7164#L500-30 assume 1 == ~t3_pc~0; 6921#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6922#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6984#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6985#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7147#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7148#L519-30 assume !(1 == ~t4_pc~0); 7322#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 7299#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6661#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6662#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7311#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7424#L538-30 assume 1 == ~t5_pc~0; 6802#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6803#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7101#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7102#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6879#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6880#L557-30 assume 1 == ~t6_pc~0; 6600#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6601#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7278#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7332#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 6904#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6905#L576-30 assume 1 == ~t7_pc~0; 7417#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6685#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7271#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7638#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7062#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7027#L595-30 assume !(1 == ~t8_pc~0); 7028#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 6961#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6696#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6697#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7639#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7675#L614-30 assume 1 == ~t9_pc~0; 6964#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6965#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7100#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6794#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6795#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7403#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7188#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7189#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7373#L1035-3 assume !(1 == ~T3_E~0); 7648#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7688#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7644#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7557#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6694#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6695#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7579#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7425#L1075-3 assume !(1 == ~E_2~0); 7426#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7649#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7570#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7571#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7590#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7591#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6842#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6843#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7603#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 6711#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 6700#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 6701#L1415 assume !(0 == start_simulation_~tmp~3#1); 7303#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7304#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 6751#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7313#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 7492#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7693#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7363#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 6924#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 6925#L1396-2 [2021-12-06 17:44:55,755 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:44:55,755 INFO L85 PathProgramCache]: Analyzing trace with hash 1764315747, now seen corresponding path program 1 times [2021-12-06 17:44:55,755 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:44:55,756 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1918713714] [2021-12-06 17:44:55,756 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:44:55,756 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:44:55,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:44:55,784 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:44:55,784 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:44:55,784 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1918713714] [2021-12-06 17:44:55,784 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1918713714] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:44:55,785 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:44:55,785 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:44:55,785 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1622124225] [2021-12-06 17:44:55,785 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:44:55,785 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:44:55,786 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:44:55,786 INFO L85 PathProgramCache]: Analyzing trace with hash -173500974, now seen corresponding path program 1 times [2021-12-06 17:44:55,786 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:44:55,786 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [995205640] [2021-12-06 17:44:55,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:44:55,786 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:44:55,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:44:55,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:44:55,836 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:44:55,836 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [995205640] [2021-12-06 17:44:55,837 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [995205640] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:44:55,837 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:44:55,837 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:44:55,837 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1333038455] [2021-12-06 17:44:55,837 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:44:55,837 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:44:55,838 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:44:55,838 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:44:55,838 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:44:55,838 INFO L87 Difference]: Start difference. First operand 1094 states and 1628 transitions. cyclomatic complexity: 535 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:44:55,858 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:44:55,858 INFO L93 Difference]: Finished difference Result 1094 states and 1627 transitions. [2021-12-06 17:44:55,858 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:44:55,859 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1094 states and 1627 transitions. [2021-12-06 17:44:55,865 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2021-12-06 17:44:55,871 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1094 states to 1094 states and 1627 transitions. [2021-12-06 17:44:55,871 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1094 [2021-12-06 17:44:55,872 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1094 [2021-12-06 17:44:55,872 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1094 states and 1627 transitions. [2021-12-06 17:44:55,874 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:44:55,874 INFO L681 BuchiCegarLoop]: Abstraction has 1094 states and 1627 transitions. [2021-12-06 17:44:55,875 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1094 states and 1627 transitions. [2021-12-06 17:44:55,887 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1094 to 1094. [2021-12-06 17:44:55,889 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1094 states, 1094 states have (on average 1.487202925045704) internal successors, (1627), 1093 states have internal predecessors, (1627), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:44:55,893 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1094 states to 1094 states and 1627 transitions. [2021-12-06 17:44:55,893 INFO L704 BuchiCegarLoop]: Abstraction has 1094 states and 1627 transitions. [2021-12-06 17:44:55,893 INFO L587 BuchiCegarLoop]: Abstraction has 1094 states and 1627 transitions. [2021-12-06 17:44:55,894 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-06 17:44:55,894 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1094 states and 1627 transitions. [2021-12-06 17:44:55,899 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2021-12-06 17:44:55,899 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:44:55,899 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:44:55,900 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:44:55,901 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:44:55,901 INFO L791 eck$LassoCheckResult]: Stem: 9632#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 9633#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 9233#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9234#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9780#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 9781#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9763#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9583#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9584#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9400#L661-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9401#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9841#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9747#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9455#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9239#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9240#L922 assume !(0 == ~M_E~0); 9885#L922-2 assume !(0 == ~T1_E~0); 9886#L927-1 assume !(0 == ~T2_E~0); 9640#L932-1 assume !(0 == ~T3_E~0); 9525#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9526#L942-1 assume !(0 == ~T5_E~0); 9582#L947-1 assume !(0 == ~T6_E~0); 9644#L952-1 assume !(0 == ~T7_E~0); 9645#L957-1 assume !(0 == ~T8_E~0); 9707#L962-1 assume !(0 == ~T9_E~0); 9501#L967-1 assume !(0 == ~E_1~0); 9502#L972-1 assume !(0 == ~E_2~0); 9768#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 9769#L982-1 assume !(0 == ~E_4~0); 9009#L987-1 assume !(0 == ~E_5~0); 9010#L992-1 assume !(0 == ~E_6~0); 9018#L997-1 assume !(0 == ~E_7~0); 9434#L1002-1 assume !(0 == ~E_8~0); 9420#L1007-1 assume !(0 == ~E_9~0); 8807#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8808#L443 assume !(1 == ~m_pc~0); 9660#L443-2 is_master_triggered_~__retres1~0#1 := 0; 9651#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9652#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9173#L1140 assume !(0 != activate_threads_~tmp~1#1); 8922#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8923#L462 assume 1 == ~t1_pc~0; 9551#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9519#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8893#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8894#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 9381#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9382#L481 assume !(1 == ~t2_pc~0); 9168#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9167#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9522#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9261#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 9262#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9356#L500 assume 1 == ~t3_pc~0; 9564#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9565#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9755#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9756#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 8812#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8813#L519 assume 1 == ~t4_pc~0; 9111#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9112#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9353#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9215#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 9216#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8976#L538 assume !(1 == ~t5_pc~0); 8977#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8883#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8884#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9152#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9153#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9692#L557 assume 1 == ~t6_pc~0; 9489#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9190#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9092#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9093#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 9217#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9868#L576 assume !(1 == ~t7_pc~0); 9177#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 9178#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9422#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9423#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 9739#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9298#L595 assume 1 == ~t8_pc~0; 9299#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9757#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9758#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9607#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 9608#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9101#L614 assume !(1 == ~t9_pc~0); 9102#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 9001#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9002#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9181#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 9263#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9264#L1025 assume !(1 == ~M_E~0); 9510#L1025-2 assume !(1 == ~T1_E~0); 9563#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9685#L1035-1 assume !(1 == ~T3_E~0); 9258#L1040-1 assume !(1 == ~T4_E~0); 9259#L1045-1 assume !(1 == ~T5_E~0); 9163#L1050-1 assume !(1 == ~T6_E~0); 9164#L1055-1 assume !(1 == ~T7_E~0); 8985#L1060-1 assume !(1 == ~T8_E~0); 8986#L1065-1 assume !(1 == ~T9_E~0); 9049#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 9646#L1075-1 assume !(1 == ~E_2~0); 9647#L1080-1 assume !(1 == ~E_3~0); 9635#L1085-1 assume !(1 == ~E_4~0); 9636#L1090-1 assume !(1 == ~E_5~0); 9835#L1095-1 assume !(1 == ~E_6~0); 9669#L1100-1 assume !(1 == ~E_7~0); 9670#L1105-1 assume !(1 == ~E_8~0); 8958#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 8959#L1115-1 assume { :end_inline_reset_delta_events } true; 9120#L1396-2 [2021-12-06 17:44:55,901 INFO L793 eck$LassoCheckResult]: Loop: 9120#L1396-2 assume !false; 9206#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9232#L897 assume !false; 9875#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 9782#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 8832#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 8833#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9830#L766 assume !(0 != eval_~tmp~0#1); 9816#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8900#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8901#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9417#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9144#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9145#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9323#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8950#L942-3 assume !(0 == ~T5_E~0); 8951#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9324#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9325#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9826#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9717#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9718#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9638#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9639#L982-3 assume !(0 == ~E_4~0); 9887#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9274#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9275#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9272#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9273#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8987#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8988#L443-30 assume 1 == ~m_pc~0; 9021#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9022#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9305#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9853#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9773#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9405#L462-30 assume 1 == ~t1_pc~0; 9250#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9252#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9752#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9753#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9794#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9392#L481-30 assume 1 == ~t2_pc~0; 9108#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9109#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9165#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9078#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9079#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9359#L500-30 assume 1 == ~t3_pc~0; 9116#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9117#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9179#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9180#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9342#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9343#L519-30 assume !(1 == ~t4_pc~0); 9517#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 9494#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8856#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8857#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9506#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9619#L538-30 assume 1 == ~t5_pc~0; 8997#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8998#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9296#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9297#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9074#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9075#L557-30 assume 1 == ~t6_pc~0; 8795#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8796#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9473#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9527#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 9099#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9100#L576-30 assume 1 == ~t7_pc~0; 9612#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8880#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9467#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9833#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9257#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9222#L595-30 assume !(1 == ~t8_pc~0); 9223#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 9158#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8891#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8892#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9834#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9870#L614-30 assume 1 == ~t9_pc~0; 9160#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9161#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9295#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8989#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8990#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9598#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9383#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9384#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9568#L1035-3 assume !(1 == ~T3_E~0); 9843#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9883#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9839#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9754#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8889#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8890#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9774#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9620#L1075-3 assume !(1 == ~E_2~0); 9621#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9844#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9765#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9766#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9785#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9786#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9037#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9038#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 9798#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 8906#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 8895#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 8896#L1415 assume !(0 == start_simulation_~tmp~3#1); 9499#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 9500#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 8946#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 9508#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 9687#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9888#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9558#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 9119#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 9120#L1396-2 [2021-12-06 17:44:55,902 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:44:55,902 INFO L85 PathProgramCache]: Analyzing trace with hash -388791071, now seen corresponding path program 1 times [2021-12-06 17:44:55,902 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:44:55,902 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [595874078] [2021-12-06 17:44:55,902 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:44:55,903 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:44:55,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:44:55,936 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:44:55,936 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:44:55,936 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [595874078] [2021-12-06 17:44:55,937 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [595874078] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:44:55,937 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:44:55,937 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:44:55,937 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [850286460] [2021-12-06 17:44:55,937 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:44:55,938 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:44:55,938 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:44:55,938 INFO L85 PathProgramCache]: Analyzing trace with hash -1095421325, now seen corresponding path program 1 times [2021-12-06 17:44:55,938 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:44:55,939 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [584577035] [2021-12-06 17:44:55,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:44:55,939 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:44:55,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:44:55,986 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:44:55,986 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:44:55,986 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [584577035] [2021-12-06 17:44:55,986 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [584577035] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:44:55,987 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:44:55,987 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:44:55,987 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2096796474] [2021-12-06 17:44:55,987 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:44:55,987 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:44:55,988 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:44:55,988 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:44:55,988 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:44:55,988 INFO L87 Difference]: Start difference. First operand 1094 states and 1627 transitions. cyclomatic complexity: 534 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:44:56,010 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:44:56,010 INFO L93 Difference]: Finished difference Result 1094 states and 1626 transitions. [2021-12-06 17:44:56,011 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:44:56,012 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1094 states and 1626 transitions. [2021-12-06 17:44:56,019 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2021-12-06 17:44:56,027 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1094 states to 1094 states and 1626 transitions. [2021-12-06 17:44:56,027 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1094 [2021-12-06 17:44:56,028 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1094 [2021-12-06 17:44:56,028 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1094 states and 1626 transitions. [2021-12-06 17:44:56,030 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:44:56,030 INFO L681 BuchiCegarLoop]: Abstraction has 1094 states and 1626 transitions. [2021-12-06 17:44:56,032 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1094 states and 1626 transitions. [2021-12-06 17:44:56,052 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1094 to 1094. [2021-12-06 17:44:56,053 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1094 states, 1094 states have (on average 1.4862888482632541) internal successors, (1626), 1093 states have internal predecessors, (1626), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:44:56,056 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1094 states to 1094 states and 1626 transitions. [2021-12-06 17:44:56,056 INFO L704 BuchiCegarLoop]: Abstraction has 1094 states and 1626 transitions. [2021-12-06 17:44:56,056 INFO L587 BuchiCegarLoop]: Abstraction has 1094 states and 1626 transitions. [2021-12-06 17:44:56,056 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-06 17:44:56,056 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1094 states and 1626 transitions. [2021-12-06 17:44:56,060 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2021-12-06 17:44:56,060 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:44:56,060 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:44:56,062 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:44:56,062 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:44:56,062 INFO L791 eck$LassoCheckResult]: Stem: 11827#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 11828#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 11428#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11429#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11975#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 11976#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11958#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11778#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11779#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11595#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11596#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12036#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11942#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11650#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11434#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11435#L922 assume !(0 == ~M_E~0); 12080#L922-2 assume !(0 == ~T1_E~0); 12081#L927-1 assume !(0 == ~T2_E~0); 11835#L932-1 assume !(0 == ~T3_E~0); 11720#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11721#L942-1 assume !(0 == ~T5_E~0); 11777#L947-1 assume !(0 == ~T6_E~0); 11839#L952-1 assume !(0 == ~T7_E~0); 11840#L957-1 assume !(0 == ~T8_E~0); 11902#L962-1 assume !(0 == ~T9_E~0); 11696#L967-1 assume !(0 == ~E_1~0); 11697#L972-1 assume !(0 == ~E_2~0); 11963#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 11964#L982-1 assume !(0 == ~E_4~0); 11204#L987-1 assume !(0 == ~E_5~0); 11205#L992-1 assume !(0 == ~E_6~0); 11213#L997-1 assume !(0 == ~E_7~0); 11629#L1002-1 assume !(0 == ~E_8~0); 11615#L1007-1 assume !(0 == ~E_9~0); 11002#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11003#L443 assume !(1 == ~m_pc~0); 11855#L443-2 is_master_triggered_~__retres1~0#1 := 0; 11846#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11847#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11368#L1140 assume !(0 != activate_threads_~tmp~1#1); 11117#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11118#L462 assume 1 == ~t1_pc~0; 11746#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11716#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11088#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11089#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 11576#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11577#L481 assume !(1 == ~t2_pc~0); 11363#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11362#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11717#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11456#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 11457#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11551#L500 assume 1 == ~t3_pc~0; 11759#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11760#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11950#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11951#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 11007#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11008#L519 assume 1 == ~t4_pc~0; 11306#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11307#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11548#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11410#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 11411#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11171#L538 assume !(1 == ~t5_pc~0); 11172#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11078#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11079#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11347#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11348#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11887#L557 assume 1 == ~t6_pc~0; 11684#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11385#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11287#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11288#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 11412#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12063#L576 assume !(1 == ~t7_pc~0); 11372#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 11373#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11617#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11618#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 11934#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11495#L595 assume 1 == ~t8_pc~0; 11496#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11952#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11953#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11802#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 11803#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11296#L614 assume !(1 == ~t9_pc~0); 11297#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 11196#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11197#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11376#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 11458#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11459#L1025 assume !(1 == ~M_E~0); 11705#L1025-2 assume !(1 == ~T1_E~0); 11758#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11881#L1035-1 assume !(1 == ~T3_E~0); 11453#L1040-1 assume !(1 == ~T4_E~0); 11454#L1045-1 assume !(1 == ~T5_E~0); 11358#L1050-1 assume !(1 == ~T6_E~0); 11359#L1055-1 assume !(1 == ~T7_E~0); 11180#L1060-1 assume !(1 == ~T8_E~0); 11181#L1065-1 assume !(1 == ~T9_E~0); 11244#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 11841#L1075-1 assume !(1 == ~E_2~0); 11842#L1080-1 assume !(1 == ~E_3~0); 11830#L1085-1 assume !(1 == ~E_4~0); 11831#L1090-1 assume !(1 == ~E_5~0); 12030#L1095-1 assume !(1 == ~E_6~0); 11864#L1100-1 assume !(1 == ~E_7~0); 11865#L1105-1 assume !(1 == ~E_8~0); 11153#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 11154#L1115-1 assume { :end_inline_reset_delta_events } true; 11315#L1396-2 [2021-12-06 17:44:56,062 INFO L793 eck$LassoCheckResult]: Loop: 11315#L1396-2 assume !false; 11401#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11427#L897 assume !false; 12070#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 11977#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11027#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11028#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12025#L766 assume !(0 != eval_~tmp~0#1); 12011#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11095#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11096#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11612#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11339#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11340#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11518#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11145#L942-3 assume !(0 == ~T5_E~0); 11146#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11519#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11520#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12021#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11912#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11913#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11833#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11834#L982-3 assume !(0 == ~E_4~0); 12082#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11469#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11470#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11464#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 11465#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11182#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11183#L443-30 assume 1 == ~m_pc~0; 11216#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11217#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11500#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12048#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11967#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11600#L462-30 assume 1 == ~t1_pc~0; 11444#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11446#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11947#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11948#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11989#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11587#L481-30 assume 1 == ~t2_pc~0; 11303#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11304#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11360#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11273#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11274#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11554#L500-30 assume !(1 == ~t3_pc~0); 11313#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 11312#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11374#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11375#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11537#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11538#L519-30 assume 1 == ~t4_pc~0; 11873#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11689#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11051#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11052#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11701#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11814#L538-30 assume 1 == ~t5_pc~0; 11192#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11193#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11491#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11492#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11269#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11270#L557-30 assume !(1 == ~t6_pc~0); 10992#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 10991#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11668#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11722#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 11294#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11295#L576-30 assume !(1 == ~t7_pc~0); 11076#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 11077#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11662#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12028#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11452#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11417#L595-30 assume !(1 == ~t8_pc~0); 11418#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 11353#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11086#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11087#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12029#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12065#L614-30 assume 1 == ~t9_pc~0; 11355#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11356#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11490#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11184#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11185#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11793#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11578#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11579#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11763#L1035-3 assume !(1 == ~T3_E~0); 12038#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12078#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12034#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11949#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11084#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11085#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11969#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11815#L1075-3 assume !(1 == ~E_2~0); 11816#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12039#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11960#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11961#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11980#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11981#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11232#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 11233#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 11993#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11101#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11090#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 11091#L1415 assume !(0 == start_simulation_~tmp~3#1); 11694#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 11695#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11141#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11703#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 11882#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12083#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11753#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 11314#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 11315#L1396-2 [2021-12-06 17:44:56,063 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:44:56,063 INFO L85 PathProgramCache]: Analyzing trace with hash 234490531, now seen corresponding path program 1 times [2021-12-06 17:44:56,063 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:44:56,063 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2140354970] [2021-12-06 17:44:56,063 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:44:56,063 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:44:56,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:44:56,083 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:44:56,083 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:44:56,084 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2140354970] [2021-12-06 17:44:56,084 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2140354970] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:44:56,084 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:44:56,084 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:44:56,084 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2120076962] [2021-12-06 17:44:56,084 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:44:56,084 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:44:56,085 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:44:56,085 INFO L85 PathProgramCache]: Analyzing trace with hash 1306266033, now seen corresponding path program 1 times [2021-12-06 17:44:56,085 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:44:56,085 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [147042052] [2021-12-06 17:44:56,085 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:44:56,085 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:44:56,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:44:56,112 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:44:56,113 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:44:56,113 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [147042052] [2021-12-06 17:44:56,113 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [147042052] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:44:56,113 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:44:56,113 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:44:56,113 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1376160830] [2021-12-06 17:44:56,113 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:44:56,114 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:44:56,114 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:44:56,114 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:44:56,114 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:44:56,114 INFO L87 Difference]: Start difference. First operand 1094 states and 1626 transitions. cyclomatic complexity: 533 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:44:56,136 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:44:56,136 INFO L93 Difference]: Finished difference Result 1094 states and 1625 transitions. [2021-12-06 17:44:56,136 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:44:56,137 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1094 states and 1625 transitions. [2021-12-06 17:44:56,144 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2021-12-06 17:44:56,152 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1094 states to 1094 states and 1625 transitions. [2021-12-06 17:44:56,152 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1094 [2021-12-06 17:44:56,154 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1094 [2021-12-06 17:44:56,154 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1094 states and 1625 transitions. [2021-12-06 17:44:56,156 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:44:56,156 INFO L681 BuchiCegarLoop]: Abstraction has 1094 states and 1625 transitions. [2021-12-06 17:44:56,158 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1094 states and 1625 transitions. [2021-12-06 17:44:56,172 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1094 to 1094. [2021-12-06 17:44:56,174 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1094 states, 1094 states have (on average 1.4853747714808043) internal successors, (1625), 1093 states have internal predecessors, (1625), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:44:56,177 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1094 states to 1094 states and 1625 transitions. [2021-12-06 17:44:56,177 INFO L704 BuchiCegarLoop]: Abstraction has 1094 states and 1625 transitions. [2021-12-06 17:44:56,177 INFO L587 BuchiCegarLoop]: Abstraction has 1094 states and 1625 transitions. [2021-12-06 17:44:56,177 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-06 17:44:56,177 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1094 states and 1625 transitions. [2021-12-06 17:44:56,181 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2021-12-06 17:44:56,181 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:44:56,181 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:44:56,182 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:44:56,182 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:44:56,183 INFO L791 eck$LassoCheckResult]: Stem: 14022#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 14023#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 13623#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13624#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14170#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 14171#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14153#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13973#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13974#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13790#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13791#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14231#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14137#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13845#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 13629#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13630#L922 assume !(0 == ~M_E~0); 14275#L922-2 assume !(0 == ~T1_E~0); 14276#L927-1 assume !(0 == ~T2_E~0); 14030#L932-1 assume !(0 == ~T3_E~0); 13915#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13916#L942-1 assume !(0 == ~T5_E~0); 13972#L947-1 assume !(0 == ~T6_E~0); 14034#L952-1 assume !(0 == ~T7_E~0); 14035#L957-1 assume !(0 == ~T8_E~0); 14098#L962-1 assume !(0 == ~T9_E~0); 13891#L967-1 assume !(0 == ~E_1~0); 13892#L972-1 assume !(0 == ~E_2~0); 14158#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 14159#L982-1 assume !(0 == ~E_4~0); 13401#L987-1 assume !(0 == ~E_5~0); 13402#L992-1 assume !(0 == ~E_6~0); 13408#L997-1 assume !(0 == ~E_7~0); 13824#L1002-1 assume !(0 == ~E_8~0); 13810#L1007-1 assume !(0 == ~E_9~0); 13197#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13198#L443 assume !(1 == ~m_pc~0); 14050#L443-2 is_master_triggered_~__retres1~0#1 := 0; 14041#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14042#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13563#L1140 assume !(0 != activate_threads_~tmp~1#1); 13312#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13313#L462 assume 1 == ~t1_pc~0; 13941#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13911#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13283#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13284#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 13771#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13772#L481 assume !(1 == ~t2_pc~0); 13558#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13557#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13912#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13651#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 13652#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13746#L500 assume 1 == ~t3_pc~0; 13954#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13955#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14145#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14146#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 13202#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13203#L519 assume 1 == ~t4_pc~0; 13501#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13502#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13743#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13605#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 13606#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13366#L538 assume !(1 == ~t5_pc~0); 13367#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13273#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13274#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13542#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13543#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14082#L557 assume 1 == ~t6_pc~0; 13879#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13580#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13484#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13485#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 13607#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14258#L576 assume !(1 == ~t7_pc~0); 13567#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 13568#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13812#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13813#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 14129#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13690#L595 assume 1 == ~t8_pc~0; 13691#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14147#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14148#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13997#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 13998#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13491#L614 assume !(1 == ~t9_pc~0); 13492#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 13391#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13392#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13571#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 13653#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13654#L1025 assume !(1 == ~M_E~0); 13900#L1025-2 assume !(1 == ~T1_E~0); 13953#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14076#L1035-1 assume !(1 == ~T3_E~0); 13648#L1040-1 assume !(1 == ~T4_E~0); 13649#L1045-1 assume !(1 == ~T5_E~0); 13553#L1050-1 assume !(1 == ~T6_E~0); 13554#L1055-1 assume !(1 == ~T7_E~0); 13375#L1060-1 assume !(1 == ~T8_E~0); 13376#L1065-1 assume !(1 == ~T9_E~0); 13439#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 14036#L1075-1 assume !(1 == ~E_2~0); 14037#L1080-1 assume !(1 == ~E_3~0); 14025#L1085-1 assume !(1 == ~E_4~0); 14026#L1090-1 assume !(1 == ~E_5~0); 14225#L1095-1 assume !(1 == ~E_6~0); 14059#L1100-1 assume !(1 == ~E_7~0); 14060#L1105-1 assume !(1 == ~E_8~0); 13348#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 13349#L1115-1 assume { :end_inline_reset_delta_events } true; 13510#L1396-2 [2021-12-06 17:44:56,183 INFO L793 eck$LassoCheckResult]: Loop: 13510#L1396-2 assume !false; 13596#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13620#L897 assume !false; 14265#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14172#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 13222#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 13223#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 14220#L766 assume !(0 != eval_~tmp~0#1); 14206#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13290#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13291#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13807#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13534#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13535#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13713#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13340#L942-3 assume !(0 == ~T5_E~0); 13341#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13714#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13715#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14216#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14107#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14108#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14028#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14029#L982-3 assume !(0 == ~E_4~0); 14277#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13664#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13665#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13659#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13660#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 13377#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13378#L443-30 assume 1 == ~m_pc~0; 13411#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13412#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13695#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14243#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14162#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13795#L462-30 assume 1 == ~t1_pc~0; 13639#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13641#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14142#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14143#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14184#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13782#L481-30 assume 1 == ~t2_pc~0; 13498#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13499#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13555#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13468#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13469#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13749#L500-30 assume 1 == ~t3_pc~0; 13506#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13507#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13569#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13570#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13732#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13733#L519-30 assume 1 == ~t4_pc~0; 14068#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13884#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13246#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13247#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13896#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14009#L538-30 assume 1 == ~t5_pc~0; 13387#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13388#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13686#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13687#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13464#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13465#L557-30 assume 1 == ~t6_pc~0; 13185#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13186#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13863#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13920#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 13489#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13490#L576-30 assume 1 == ~t7_pc~0; 14002#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13272#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13857#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14223#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13647#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13612#L595-30 assume !(1 == ~t8_pc~0); 13613#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 13548#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13281#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13282#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14224#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14260#L614-30 assume !(1 == ~t9_pc~0); 13552#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 13551#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13685#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13379#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13380#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13988#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13773#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13774#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13958#L1035-3 assume !(1 == ~T3_E~0); 14233#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14273#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14229#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14144#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13279#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13280#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14164#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14010#L1075-3 assume !(1 == ~E_2~0); 14011#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14234#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14155#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14156#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14175#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14176#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13427#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13428#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14189#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 13296#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 13285#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 13286#L1415 assume !(0 == start_simulation_~tmp~3#1); 13889#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 13890#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 13336#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 13898#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 14077#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14278#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13948#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 13509#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 13510#L1396-2 [2021-12-06 17:44:56,183 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:44:56,183 INFO L85 PathProgramCache]: Analyzing trace with hash 116049057, now seen corresponding path program 1 times [2021-12-06 17:44:56,183 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:44:56,183 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [434148337] [2021-12-06 17:44:56,184 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:44:56,184 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:44:56,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:44:56,202 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:44:56,203 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:44:56,203 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [434148337] [2021-12-06 17:44:56,203 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [434148337] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:44:56,203 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:44:56,203 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:44:56,203 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [474996169] [2021-12-06 17:44:56,203 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:44:56,204 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:44:56,204 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:44:56,204 INFO L85 PathProgramCache]: Analyzing trace with hash 1885053619, now seen corresponding path program 1 times [2021-12-06 17:44:56,204 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:44:56,204 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [11942334] [2021-12-06 17:44:56,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:44:56,204 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:44:56,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:44:56,230 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:44:56,230 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:44:56,230 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [11942334] [2021-12-06 17:44:56,230 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [11942334] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:44:56,230 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:44:56,230 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:44:56,230 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [596095777] [2021-12-06 17:44:56,230 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:44:56,231 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:44:56,231 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:44:56,231 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:44:56,231 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:44:56,231 INFO L87 Difference]: Start difference. First operand 1094 states and 1625 transitions. cyclomatic complexity: 532 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:44:56,246 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:44:56,246 INFO L93 Difference]: Finished difference Result 1094 states and 1624 transitions. [2021-12-06 17:44:56,246 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:44:56,247 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1094 states and 1624 transitions. [2021-12-06 17:44:56,252 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2021-12-06 17:44:56,258 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1094 states to 1094 states and 1624 transitions. [2021-12-06 17:44:56,258 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1094 [2021-12-06 17:44:56,259 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1094 [2021-12-06 17:44:56,259 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1094 states and 1624 transitions. [2021-12-06 17:44:56,269 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:44:56,269 INFO L681 BuchiCegarLoop]: Abstraction has 1094 states and 1624 transitions. [2021-12-06 17:44:56,271 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1094 states and 1624 transitions. [2021-12-06 17:44:56,285 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1094 to 1094. [2021-12-06 17:44:56,288 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1094 states, 1094 states have (on average 1.4844606946983547) internal successors, (1624), 1093 states have internal predecessors, (1624), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:44:56,291 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1094 states to 1094 states and 1624 transitions. [2021-12-06 17:44:56,292 INFO L704 BuchiCegarLoop]: Abstraction has 1094 states and 1624 transitions. [2021-12-06 17:44:56,292 INFO L587 BuchiCegarLoop]: Abstraction has 1094 states and 1624 transitions. [2021-12-06 17:44:56,292 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-06 17:44:56,292 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1094 states and 1624 transitions. [2021-12-06 17:44:56,297 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2021-12-06 17:44:56,297 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:44:56,297 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:44:56,299 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:44:56,299 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:44:56,300 INFO L791 eck$LassoCheckResult]: Stem: 16217#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 16218#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 15818#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15819#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16365#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 16366#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16349#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16168#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16169#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15985#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15986#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16426#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16332#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16040#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15824#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15825#L922 assume !(0 == ~M_E~0); 16470#L922-2 assume !(0 == ~T1_E~0); 16471#L927-1 assume !(0 == ~T2_E~0); 16225#L932-1 assume !(0 == ~T3_E~0); 16110#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16111#L942-1 assume !(0 == ~T5_E~0); 16167#L947-1 assume !(0 == ~T6_E~0); 16229#L952-1 assume !(0 == ~T7_E~0); 16230#L957-1 assume !(0 == ~T8_E~0); 16293#L962-1 assume !(0 == ~T9_E~0); 16089#L967-1 assume !(0 == ~E_1~0); 16090#L972-1 assume !(0 == ~E_2~0); 16353#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 16354#L982-1 assume !(0 == ~E_4~0); 15596#L987-1 assume !(0 == ~E_5~0); 15597#L992-1 assume !(0 == ~E_6~0); 15603#L997-1 assume !(0 == ~E_7~0); 16019#L1002-1 assume !(0 == ~E_8~0); 16005#L1007-1 assume !(0 == ~E_9~0); 15392#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15393#L443 assume !(1 == ~m_pc~0); 16245#L443-2 is_master_triggered_~__retres1~0#1 := 0; 16236#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16237#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15758#L1140 assume !(0 != activate_threads_~tmp~1#1); 15507#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15508#L462 assume 1 == ~t1_pc~0; 16136#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16106#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15478#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15479#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 15966#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15967#L481 assume !(1 == ~t2_pc~0); 15753#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15752#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16107#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15846#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 15847#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15939#L500 assume 1 == ~t3_pc~0; 16149#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16150#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16340#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16341#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 15394#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15395#L519 assume 1 == ~t4_pc~0; 15693#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15694#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15938#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15798#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 15799#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15561#L538 assume !(1 == ~t5_pc~0); 15562#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 15468#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15469#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15737#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15738#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16275#L557 assume 1 == ~t6_pc~0; 16074#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15775#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15672#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15673#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 15800#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16453#L576 assume !(1 == ~t7_pc~0); 15762#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 15763#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16007#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16008#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 16324#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15883#L595 assume 1 == ~t8_pc~0; 15884#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16342#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16343#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16192#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 16193#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15686#L614 assume !(1 == ~t9_pc~0); 15687#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 15585#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15586#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15766#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 15848#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15849#L1025 assume !(1 == ~M_E~0); 16095#L1025-2 assume !(1 == ~T1_E~0); 16148#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16270#L1035-1 assume !(1 == ~T3_E~0); 15842#L1040-1 assume !(1 == ~T4_E~0); 15843#L1045-1 assume !(1 == ~T5_E~0); 15748#L1050-1 assume !(1 == ~T6_E~0); 15749#L1055-1 assume !(1 == ~T7_E~0); 15570#L1060-1 assume !(1 == ~T8_E~0); 15571#L1065-1 assume !(1 == ~T9_E~0); 15634#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 16231#L1075-1 assume !(1 == ~E_2~0); 16232#L1080-1 assume !(1 == ~E_3~0); 16220#L1085-1 assume !(1 == ~E_4~0); 16221#L1090-1 assume !(1 == ~E_5~0); 16420#L1095-1 assume !(1 == ~E_6~0); 16254#L1100-1 assume !(1 == ~E_7~0); 16255#L1105-1 assume !(1 == ~E_8~0); 15543#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 15544#L1115-1 assume { :end_inline_reset_delta_events } true; 15707#L1396-2 [2021-12-06 17:44:56,300 INFO L793 eck$LassoCheckResult]: Loop: 15707#L1396-2 assume !false; 15788#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15817#L897 assume !false; 16460#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 16367#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 15415#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 15416#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16415#L766 assume !(0 != eval_~tmp~0#1); 16401#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15485#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15486#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15999#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15729#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15730#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15908#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15535#L942-3 assume !(0 == ~T5_E~0); 15536#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15909#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15910#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16411#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16302#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16303#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16223#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16224#L982-3 assume !(0 == ~E_4~0); 16472#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15859#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15860#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15854#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15855#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15572#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15573#L443-30 assume 1 == ~m_pc~0; 15606#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 15607#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15890#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16438#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16357#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15990#L462-30 assume 1 == ~t1_pc~0; 15834#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15836#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16337#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16338#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16379#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15977#L481-30 assume 1 == ~t2_pc~0; 15696#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15697#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15750#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15663#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15664#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15944#L500-30 assume 1 == ~t3_pc~0; 15701#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15702#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15764#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15765#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15927#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15928#L519-30 assume 1 == ~t4_pc~0; 16263#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16079#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15441#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15442#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16091#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16204#L538-30 assume !(1 == ~t5_pc~0); 15584#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 15583#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15881#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15882#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15659#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15660#L557-30 assume 1 == ~t6_pc~0; 15380#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15381#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16058#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16115#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 15684#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15685#L576-30 assume 1 == ~t7_pc~0; 16197#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15467#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16052#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16418#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15844#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15807#L595-30 assume !(1 == ~t8_pc~0); 15808#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 15743#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15476#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15477#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16419#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16455#L614-30 assume 1 == ~t9_pc~0; 15745#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15746#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15880#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15574#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15575#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16183#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15968#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15969#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16153#L1035-3 assume !(1 == ~T3_E~0); 16428#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16468#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16424#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16339#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15474#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 15475#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16359#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16205#L1075-3 assume !(1 == ~E_2~0); 16206#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16429#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16350#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16351#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16370#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16371#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 15622#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15623#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 16384#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 15491#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 15483#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 15484#L1415 assume !(0 == start_simulation_~tmp~3#1); 16084#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 16085#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 15531#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 16093#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 16272#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16473#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16143#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 15706#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 15707#L1396-2 [2021-12-06 17:44:56,300 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:44:56,301 INFO L85 PathProgramCache]: Analyzing trace with hash -1273244957, now seen corresponding path program 1 times [2021-12-06 17:44:56,301 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:44:56,301 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [339992548] [2021-12-06 17:44:56,301 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:44:56,301 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:44:56,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:44:56,322 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:44:56,322 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:44:56,322 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [339992548] [2021-12-06 17:44:56,322 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [339992548] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:44:56,322 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:44:56,323 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:44:56,323 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2050890712] [2021-12-06 17:44:56,323 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:44:56,323 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:44:56,323 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:44:56,323 INFO L85 PathProgramCache]: Analyzing trace with hash -1113508429, now seen corresponding path program 2 times [2021-12-06 17:44:56,323 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:44:56,324 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1776713889] [2021-12-06 17:44:56,324 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:44:56,324 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:44:56,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:44:56,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:44:56,348 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:44:56,349 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1776713889] [2021-12-06 17:44:56,349 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1776713889] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:44:56,349 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:44:56,349 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:44:56,349 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [541940034] [2021-12-06 17:44:56,349 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:44:56,349 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:44:56,349 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:44:56,350 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:44:56,350 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:44:56,350 INFO L87 Difference]: Start difference. First operand 1094 states and 1624 transitions. cyclomatic complexity: 531 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:44:56,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:44:56,364 INFO L93 Difference]: Finished difference Result 1094 states and 1623 transitions. [2021-12-06 17:44:56,365 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:44:56,365 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1094 states and 1623 transitions. [2021-12-06 17:44:56,370 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2021-12-06 17:44:56,376 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1094 states to 1094 states and 1623 transitions. [2021-12-06 17:44:56,376 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1094 [2021-12-06 17:44:56,377 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1094 [2021-12-06 17:44:56,377 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1094 states and 1623 transitions. [2021-12-06 17:44:56,378 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:44:56,378 INFO L681 BuchiCegarLoop]: Abstraction has 1094 states and 1623 transitions. [2021-12-06 17:44:56,380 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1094 states and 1623 transitions. [2021-12-06 17:44:56,390 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1094 to 1094. [2021-12-06 17:44:56,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1094 states, 1094 states have (on average 1.483546617915905) internal successors, (1623), 1093 states have internal predecessors, (1623), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:44:56,394 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1094 states to 1094 states and 1623 transitions. [2021-12-06 17:44:56,395 INFO L704 BuchiCegarLoop]: Abstraction has 1094 states and 1623 transitions. [2021-12-06 17:44:56,395 INFO L587 BuchiCegarLoop]: Abstraction has 1094 states and 1623 transitions. [2021-12-06 17:44:56,395 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-06 17:44:56,395 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1094 states and 1623 transitions. [2021-12-06 17:44:56,397 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2021-12-06 17:44:56,398 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:44:56,398 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:44:56,399 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:44:56,399 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:44:56,399 INFO L791 eck$LassoCheckResult]: Stem: 18411#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 18412#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 18013#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18014#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18560#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 18561#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18543#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18363#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18364#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18179#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18180#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 18620#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 18526#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 18235#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18019#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18020#L922 assume !(0 == ~M_E~0); 18665#L922-2 assume !(0 == ~T1_E~0); 18666#L927-1 assume !(0 == ~T2_E~0); 18420#L932-1 assume !(0 == ~T3_E~0); 18305#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18306#L942-1 assume !(0 == ~T5_E~0); 18362#L947-1 assume !(0 == ~T6_E~0); 18424#L952-1 assume !(0 == ~T7_E~0); 18425#L957-1 assume !(0 == ~T8_E~0); 18485#L962-1 assume !(0 == ~T9_E~0); 18281#L967-1 assume !(0 == ~E_1~0); 18282#L972-1 assume !(0 == ~E_2~0); 18548#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 18549#L982-1 assume !(0 == ~E_4~0); 17789#L987-1 assume !(0 == ~E_5~0); 17790#L992-1 assume !(0 == ~E_6~0); 17798#L997-1 assume !(0 == ~E_7~0); 18212#L1002-1 assume !(0 == ~E_8~0); 18199#L1007-1 assume !(0 == ~E_9~0); 17587#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17588#L443 assume !(1 == ~m_pc~0); 18440#L443-2 is_master_triggered_~__retres1~0#1 := 0; 18431#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18432#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 17953#L1140 assume !(0 != activate_threads_~tmp~1#1); 17702#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17703#L462 assume 1 == ~t1_pc~0; 18331#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18298#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17673#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17674#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 18160#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18161#L481 assume !(1 == ~t2_pc~0); 17948#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 17947#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18302#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18041#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 18042#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18134#L500 assume 1 == ~t3_pc~0; 18344#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18345#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18535#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18536#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 17589#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17590#L519 assume 1 == ~t4_pc~0; 17888#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17889#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18133#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17993#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 17994#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17756#L538 assume !(1 == ~t5_pc~0); 17757#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 17663#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17664#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17932#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17933#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18470#L557 assume 1 == ~t6_pc~0; 18269#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17970#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17867#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17868#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 17995#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18648#L576 assume !(1 == ~t7_pc~0); 17957#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 17958#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18202#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18203#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 18519#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18078#L595 assume 1 == ~t8_pc~0; 18079#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18537#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18538#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18387#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 18388#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17881#L614 assume !(1 == ~t9_pc~0); 17882#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 17780#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17781#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17961#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 18043#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18044#L1025 assume !(1 == ~M_E~0); 18290#L1025-2 assume !(1 == ~T1_E~0); 18343#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18465#L1035-1 assume !(1 == ~T3_E~0); 18037#L1040-1 assume !(1 == ~T4_E~0); 18038#L1045-1 assume !(1 == ~T5_E~0); 17943#L1050-1 assume !(1 == ~T6_E~0); 17944#L1055-1 assume !(1 == ~T7_E~0); 17765#L1060-1 assume !(1 == ~T8_E~0); 17766#L1065-1 assume !(1 == ~T9_E~0); 17829#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 18426#L1075-1 assume !(1 == ~E_2~0); 18427#L1080-1 assume !(1 == ~E_3~0); 18415#L1085-1 assume !(1 == ~E_4~0); 18416#L1090-1 assume !(1 == ~E_5~0); 18615#L1095-1 assume !(1 == ~E_6~0); 18449#L1100-1 assume !(1 == ~E_7~0); 18450#L1105-1 assume !(1 == ~E_8~0); 17738#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 17739#L1115-1 assume { :end_inline_reset_delta_events } true; 17902#L1396-2 [2021-12-06 17:44:56,400 INFO L793 eck$LassoCheckResult]: Loop: 17902#L1396-2 assume !false; 17983#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18012#L897 assume !false; 18655#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 18562#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 17610#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17611#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18610#L766 assume !(0 != eval_~tmp~0#1); 18596#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17680#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17681#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18194#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17924#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17925#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18103#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17730#L942-3 assume !(0 == ~T5_E~0); 17731#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18104#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18105#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18606#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18497#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18498#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18418#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18419#L982-3 assume !(0 == ~E_4~0); 18667#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18054#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18055#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18049#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 18050#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 17767#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17768#L443-30 assume 1 == ~m_pc~0; 17801#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17802#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18085#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18633#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18552#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18185#L462-30 assume 1 == ~t1_pc~0; 18029#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18031#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18532#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18533#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18574#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18172#L481-30 assume 1 == ~t2_pc~0; 17891#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17892#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17945#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17858#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17859#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18139#L500-30 assume 1 == ~t3_pc~0; 17896#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17897#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17959#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17960#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18122#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18123#L519-30 assume 1 == ~t4_pc~0; 18458#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18274#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17636#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17637#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18286#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18399#L538-30 assume 1 == ~t5_pc~0; 17777#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17778#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18076#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18077#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17854#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17855#L557-30 assume 1 == ~t6_pc~0; 17575#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17576#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18253#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18310#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 17879#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17880#L576-30 assume 1 == ~t7_pc~0; 18392#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17662#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18247#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18613#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18039#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18002#L595-30 assume !(1 == ~t8_pc~0); 18003#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 17938#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17671#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17672#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18614#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18650#L614-30 assume 1 == ~t9_pc~0; 17940#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17941#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18075#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17769#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17770#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18378#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18163#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18164#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18348#L1035-3 assume !(1 == ~T3_E~0); 18623#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18663#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18619#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18534#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17669#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17670#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18554#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18400#L1075-3 assume !(1 == ~E_2~0); 18401#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18624#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18545#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18546#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18565#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18566#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17817#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17818#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 18579#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 17686#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17678#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 17679#L1415 assume !(0 == start_simulation_~tmp~3#1); 18279#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 18280#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 17726#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 18288#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 18467#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18668#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18338#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 17901#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 17902#L1396-2 [2021-12-06 17:44:56,400 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:44:56,400 INFO L85 PathProgramCache]: Analyzing trace with hash 760149089, now seen corresponding path program 1 times [2021-12-06 17:44:56,400 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:44:56,400 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1193996465] [2021-12-06 17:44:56,400 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:44:56,400 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:44:56,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:44:56,427 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:44:56,427 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:44:56,427 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1193996465] [2021-12-06 17:44:56,427 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1193996465] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:44:56,427 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:44:56,427 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:44:56,427 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1984514941] [2021-12-06 17:44:56,427 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:44:56,428 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:44:56,428 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:44:56,428 INFO L85 PathProgramCache]: Analyzing trace with hash 1361732948, now seen corresponding path program 1 times [2021-12-06 17:44:56,428 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:44:56,428 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [150503559] [2021-12-06 17:44:56,428 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:44:56,428 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:44:56,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:44:56,453 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:44:56,453 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:44:56,453 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [150503559] [2021-12-06 17:44:56,453 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [150503559] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:44:56,453 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:44:56,454 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:44:56,454 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1950016386] [2021-12-06 17:44:56,454 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:44:56,454 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:44:56,454 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:44:56,454 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 17:44:56,454 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 17:44:56,455 INFO L87 Difference]: Start difference. First operand 1094 states and 1623 transitions. cyclomatic complexity: 530 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:44:56,556 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:44:56,556 INFO L93 Difference]: Finished difference Result 2081 states and 3081 transitions. [2021-12-06 17:44:56,557 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 17:44:56,557 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2081 states and 3081 transitions. [2021-12-06 17:44:56,564 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1938 [2021-12-06 17:44:56,576 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2081 states to 2081 states and 3081 transitions. [2021-12-06 17:44:56,576 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2081 [2021-12-06 17:44:56,577 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2081 [2021-12-06 17:44:56,577 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2081 states and 3081 transitions. [2021-12-06 17:44:56,580 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:44:56,580 INFO L681 BuchiCegarLoop]: Abstraction has 2081 states and 3081 transitions. [2021-12-06 17:44:56,582 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2081 states and 3081 transitions. [2021-12-06 17:44:56,606 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2081 to 2081. [2021-12-06 17:44:56,610 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2081 states, 2081 states have (on average 1.4805382027871217) internal successors, (3081), 2080 states have internal predecessors, (3081), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:44:56,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2081 states to 2081 states and 3081 transitions. [2021-12-06 17:44:56,615 INFO L704 BuchiCegarLoop]: Abstraction has 2081 states and 3081 transitions. [2021-12-06 17:44:56,615 INFO L587 BuchiCegarLoop]: Abstraction has 2081 states and 3081 transitions. [2021-12-06 17:44:56,615 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-06 17:44:56,615 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2081 states and 3081 transitions. [2021-12-06 17:44:56,620 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1938 [2021-12-06 17:44:56,620 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:44:56,620 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:44:56,621 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:44:56,621 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:44:56,622 INFO L791 eck$LassoCheckResult]: Stem: 21605#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 21606#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 21199#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21200#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21761#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 21762#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21740#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21553#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21554#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21366#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21367#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 21833#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 21723#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 21421#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21205#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21206#L922 assume !(0 == ~M_E~0); 21907#L922-2 assume !(0 == ~T1_E~0); 21908#L927-1 assume !(0 == ~T2_E~0); 21613#L932-1 assume !(0 == ~T3_E~0); 21492#L937-1 assume !(0 == ~T4_E~0); 21493#L942-1 assume !(0 == ~T5_E~0); 21552#L947-1 assume !(0 == ~T6_E~0); 21617#L952-1 assume !(0 == ~T7_E~0); 21618#L957-1 assume !(0 == ~T8_E~0); 21680#L962-1 assume !(0 == ~T9_E~0); 21467#L967-1 assume !(0 == ~E_1~0); 21468#L972-1 assume !(0 == ~E_2~0); 21745#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 21746#L982-1 assume !(0 == ~E_4~0); 20974#L987-1 assume !(0 == ~E_5~0); 20975#L992-1 assume !(0 == ~E_6~0); 20983#L997-1 assume !(0 == ~E_7~0); 21398#L1002-1 assume !(0 == ~E_8~0); 21385#L1007-1 assume !(0 == ~E_9~0); 20772#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20773#L443 assume !(1 == ~m_pc~0); 21633#L443-2 is_master_triggered_~__retres1~0#1 := 0; 21624#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21625#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 21138#L1140 assume !(0 != activate_threads_~tmp~1#1); 20887#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20888#L462 assume 1 == ~t1_pc~0; 21518#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21485#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20858#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20859#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 21347#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21348#L481 assume !(1 == ~t2_pc~0); 21133#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21132#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21489#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21227#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 21228#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21320#L500 assume 1 == ~t3_pc~0; 21533#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21534#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21732#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21733#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 20774#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20775#L519 assume 1 == ~t4_pc~0; 21073#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21074#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21319#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21178#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 21179#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20941#L538 assume !(1 == ~t5_pc~0); 20942#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 20848#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20849#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21117#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21118#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21664#L557 assume 1 == ~t6_pc~0; 21455#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21155#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21055#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21056#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 21180#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21873#L576 assume !(1 == ~t7_pc~0); 21142#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 21143#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21388#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21389#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 21715#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21264#L595 assume 1 == ~t8_pc~0; 21265#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21734#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21735#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21579#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 21580#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21066#L614 assume !(1 == ~t9_pc~0); 21067#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 20966#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20967#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21146#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 21229#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21230#L1025 assume !(1 == ~M_E~0); 21476#L1025-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21531#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21778#L1035-1 assume !(1 == ~T3_E~0); 21223#L1040-1 assume !(1 == ~T4_E~0); 21224#L1045-1 assume !(1 == ~T5_E~0); 21128#L1050-1 assume !(1 == ~T6_E~0); 21129#L1055-1 assume !(1 == ~T7_E~0); 20950#L1060-1 assume !(1 == ~T8_E~0); 20951#L1065-1 assume !(1 == ~T9_E~0); 21014#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 21970#L1075-1 assume !(1 == ~E_2~0); 21961#L1080-1 assume !(1 == ~E_3~0); 21960#L1085-1 assume !(1 == ~E_4~0); 21827#L1090-1 assume !(1 == ~E_5~0); 21828#L1095-1 assume !(1 == ~E_6~0); 21642#L1100-1 assume !(1 == ~E_7~0); 21643#L1105-1 assume !(1 == ~E_8~0); 20923#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 20924#L1115-1 assume { :end_inline_reset_delta_events } true; 21085#L1396-2 [2021-12-06 17:44:56,622 INFO L793 eck$LassoCheckResult]: Loop: 21085#L1396-2 assume !false; 21168#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21887#L897 assume !false; 21888#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 21914#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 21919#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 21853#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 21854#L766 assume !(0 != eval_~tmp~0#1); 21801#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20865#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20866#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21381#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21109#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21110#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21289#L937-3 assume !(0 == ~T4_E~0); 20915#L942-3 assume !(0 == ~T5_E~0); 20916#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21290#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21291#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21813#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22338#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22337#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22336#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22335#L982-3 assume !(0 == ~E_4~0); 22334#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22333#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22332#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 22331#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22330#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22329#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22328#L443-30 assume 1 == ~m_pc~0; 22326#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 22325#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22324#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 22323#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22322#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22321#L462-30 assume 1 == ~t1_pc~0; 22320#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22318#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22317#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22316#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22315#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22314#L481-30 assume 1 == ~t2_pc~0; 22312#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22311#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22310#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22309#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22308#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22307#L500-30 assume !(1 == ~t3_pc~0); 22305#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 22304#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22303#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22302#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22301#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22300#L519-30 assume 1 == ~t4_pc~0; 22298#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22297#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22296#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22295#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22294#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22293#L538-30 assume !(1 == ~t5_pc~0); 22291#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 22290#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22289#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22288#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22287#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22286#L557-30 assume 1 == ~t6_pc~0; 22284#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22283#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22282#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22281#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 22280#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22279#L576-30 assume 1 == ~t7_pc~0; 22277#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22276#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22275#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22274#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22273#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22272#L595-30 assume 1 == ~t8_pc~0; 22270#L596-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22269#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22268#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22267#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22266#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22265#L614-30 assume 1 == ~t9_pc~0; 21125#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21126#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21261#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20954#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 20955#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21569#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21349#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21350#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21537#L1035-3 assume !(1 == ~T3_E~0); 21836#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21905#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21910#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 22195#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22193#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22191#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21753#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21593#L1075-3 assume !(1 == ~E_2~0); 21594#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21837#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21742#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21743#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21767#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21768#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21002#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21003#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 21781#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 20871#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 20860#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 20861#L1415 assume !(0 == start_simulation_~tmp~3#1); 21463#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 21464#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 20911#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 21474#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 21661#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21916#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21523#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 21084#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 21085#L1396-2 [2021-12-06 17:44:56,622 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:44:56,622 INFO L85 PathProgramCache]: Analyzing trace with hash 1392361629, now seen corresponding path program 1 times [2021-12-06 17:44:56,622 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:44:56,622 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1223710188] [2021-12-06 17:44:56,623 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:44:56,623 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:44:56,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:44:56,646 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:44:56,646 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:44:56,646 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1223710188] [2021-12-06 17:44:56,646 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1223710188] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:44:56,646 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:44:56,646 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:44:56,647 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [798247740] [2021-12-06 17:44:56,647 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:44:56,647 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:44:56,647 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:44:56,647 INFO L85 PathProgramCache]: Analyzing trace with hash -144451535, now seen corresponding path program 1 times [2021-12-06 17:44:56,647 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:44:56,647 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1648602076] [2021-12-06 17:44:56,648 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:44:56,648 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:44:56,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:44:56,672 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:44:56,672 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:44:56,673 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1648602076] [2021-12-06 17:44:56,673 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1648602076] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:44:56,673 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:44:56,673 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:44:56,673 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1746034773] [2021-12-06 17:44:56,673 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:44:56,673 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:44:56,673 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:44:56,674 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 17:44:56,674 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 17:44:56,674 INFO L87 Difference]: Start difference. First operand 2081 states and 3081 transitions. cyclomatic complexity: 1002 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:44:56,805 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:44:56,805 INFO L93 Difference]: Finished difference Result 3899 states and 5768 transitions. [2021-12-06 17:44:56,805 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 17:44:56,806 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3899 states and 5768 transitions. [2021-12-06 17:44:56,821 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3732 [2021-12-06 17:44:56,843 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3899 states to 3899 states and 5768 transitions. [2021-12-06 17:44:56,843 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3899 [2021-12-06 17:44:56,846 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3899 [2021-12-06 17:44:56,846 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3899 states and 5768 transitions. [2021-12-06 17:44:56,851 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:44:56,851 INFO L681 BuchiCegarLoop]: Abstraction has 3899 states and 5768 transitions. [2021-12-06 17:44:56,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3899 states and 5768 transitions. [2021-12-06 17:44:56,905 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3899 to 3897. [2021-12-06 17:44:56,911 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3897 states, 3897 states have (on average 1.4795996920708236) internal successors, (5766), 3896 states have internal predecessors, (5766), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:44:56,922 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3897 states to 3897 states and 5766 transitions. [2021-12-06 17:44:56,922 INFO L704 BuchiCegarLoop]: Abstraction has 3897 states and 5766 transitions. [2021-12-06 17:44:56,922 INFO L587 BuchiCegarLoop]: Abstraction has 3897 states and 5766 transitions. [2021-12-06 17:44:56,922 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-06 17:44:56,922 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3897 states and 5766 transitions. [2021-12-06 17:44:56,931 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3732 [2021-12-06 17:44:56,931 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:44:56,931 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:44:56,932 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:44:56,932 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:44:56,932 INFO L791 eck$LassoCheckResult]: Stem: 27631#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 27632#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 27189#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27190#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27806#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 27807#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27782#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27574#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27575#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27368#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27369#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27886#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 27765#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 27430#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27195#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27196#L922 assume !(0 == ~M_E~0); 27967#L922-2 assume !(0 == ~T1_E~0); 27968#L927-1 assume !(0 == ~T2_E~0); 27639#L932-1 assume !(0 == ~T3_E~0); 27508#L937-1 assume !(0 == ~T4_E~0); 27509#L942-1 assume !(0 == ~T5_E~0); 27573#L947-1 assume !(0 == ~T6_E~0); 27643#L952-1 assume !(0 == ~T7_E~0); 27644#L957-1 assume !(0 == ~T8_E~0); 27717#L962-1 assume !(0 == ~T9_E~0); 27481#L967-1 assume !(0 == ~E_1~0); 27482#L972-1 assume !(0 == ~E_2~0); 27790#L977-1 assume !(0 == ~E_3~0); 27791#L982-1 assume !(0 == ~E_4~0); 26964#L987-1 assume !(0 == ~E_5~0); 26965#L992-1 assume !(0 == ~E_6~0); 26973#L997-1 assume !(0 == ~E_7~0); 27405#L1002-1 assume !(0 == ~E_8~0); 27391#L1007-1 assume !(0 == ~E_9~0); 26762#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26763#L443 assume !(1 == ~m_pc~0); 27660#L443-2 is_master_triggered_~__retres1~0#1 := 0; 27650#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27651#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 27129#L1140 assume !(0 != activate_threads_~tmp~1#1); 26877#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26878#L462 assume 1 == ~t1_pc~0; 27536#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27502#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26848#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26849#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 27348#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27349#L481 assume !(1 == ~t2_pc~0); 27124#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 27123#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27505#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27219#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 27220#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27322#L500 assume 1 == ~t3_pc~0; 27552#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27553#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27774#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27775#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 26767#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26768#L519 assume 1 == ~t4_pc~0; 27067#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27068#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27319#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27171#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 27172#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26931#L538 assume !(1 == ~t5_pc~0); 26932#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 26838#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26839#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27108#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 27109#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27698#L557 assume 1 == ~t6_pc~0; 27468#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27146#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27048#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27049#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 27173#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27924#L576 assume !(1 == ~t7_pc~0); 27133#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 27134#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27393#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27394#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 27755#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27258#L595 assume 1 == ~t8_pc~0; 27259#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 27776#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27777#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27600#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 27601#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27057#L614 assume !(1 == ~t9_pc~0); 27058#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 26956#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26957#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27137#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 27221#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27222#L1025 assume !(1 == ~M_E~0); 27491#L1025-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27550#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27690#L1035-1 assume !(1 == ~T3_E~0); 27823#L1040-1 assume !(1 == ~T4_E~0); 28146#L1045-1 assume !(1 == ~T5_E~0); 28142#L1050-1 assume !(1 == ~T6_E~0); 27311#L1055-1 assume !(1 == ~T7_E~0); 26940#L1060-1 assume !(1 == ~T8_E~0); 26941#L1065-1 assume !(1 == ~T9_E~0); 27004#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 28116#L1075-1 assume !(1 == ~E_2~0); 28115#L1080-1 assume !(1 == ~E_3~0); 28086#L1085-1 assume !(1 == ~E_4~0); 28066#L1090-1 assume !(1 == ~E_5~0); 28064#L1095-1 assume !(1 == ~E_6~0); 28062#L1100-1 assume !(1 == ~E_7~0); 28048#L1105-1 assume !(1 == ~E_8~0); 28046#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 28037#L1115-1 assume { :end_inline_reset_delta_events } true; 28030#L1396-2 [2021-12-06 17:44:56,933 INFO L793 eck$LassoCheckResult]: Loop: 28030#L1396-2 assume !false; 28024#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28019#L897 assume !false; 28018#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 28017#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 28007#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 28006#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 28004#L766 assume !(0 != eval_~tmp~0#1); 28003#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28002#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28001#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 27999#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28000#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29678#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29676#L937-3 assume !(0 == ~T4_E~0); 29674#L942-3 assume !(0 == ~T5_E~0); 29672#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29670#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29668#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29606#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29604#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29602#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29600#L977-3 assume !(0 == ~E_3~0); 29599#L982-3 assume !(0 == ~E_4~0); 29411#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29406#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 29401#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 29396#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29391#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29390#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29389#L443-30 assume 1 == ~m_pc~0; 29387#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 29386#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29385#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 29384#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 29383#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29382#L462-30 assume !(1 == ~t1_pc~0); 29380#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 29379#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27772#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 27773#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 27821#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27360#L481-30 assume 1 == ~t2_pc~0; 27064#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 27065#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27121#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27034#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27035#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27325#L500-30 assume 1 == ~t3_pc~0; 27072#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27073#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27135#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27136#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27965#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28857#L519-30 assume 1 == ~t4_pc~0; 27680#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27473#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26811#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26812#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 27486#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27614#L538-30 assume 1 == ~t5_pc~0; 26952#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26953#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28740#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28738#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28736#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28733#L557-30 assume 1 == ~t6_pc~0; 28730#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28651#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28649#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28647#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 28645#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28644#L576-30 assume 1 == ~t7_pc~0; 28642#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28559#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28556#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28554#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28553#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28552#L595-30 assume 1 == ~t8_pc~0; 28549#L596-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28547#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28492#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28489#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28487#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28485#L614-30 assume 1 == ~t9_pc~0; 28481#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28479#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28476#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28474#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 28472#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28470#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28468#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27351#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28386#L1035-3 assume !(1 == ~T3_E~0); 28305#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28302#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 28300#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28298#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 28296#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28294#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28292#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28290#L1075-3 assume !(1 == ~E_2~0); 28289#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28287#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28286#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 28285#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28284#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28283#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28282#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28281#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 28234#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 28209#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 28207#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 28177#L1415 assume !(0 == start_simulation_~tmp~3#1); 28139#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 28110#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 28082#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 28065#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 28063#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 28049#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28047#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 28038#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 28030#L1396-2 [2021-12-06 17:44:56,933 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:44:56,933 INFO L85 PathProgramCache]: Analyzing trace with hash 397667931, now seen corresponding path program 1 times [2021-12-06 17:44:56,933 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:44:56,933 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [908258042] [2021-12-06 17:44:56,933 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:44:56,933 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:44:56,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:44:56,959 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:44:56,959 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:44:56,959 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [908258042] [2021-12-06 17:44:56,959 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [908258042] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:44:56,959 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:44:56,959 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:44:56,960 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1792443205] [2021-12-06 17:44:56,960 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:44:56,960 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:44:56,960 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:44:56,961 INFO L85 PathProgramCache]: Analyzing trace with hash -811879920, now seen corresponding path program 1 times [2021-12-06 17:44:56,961 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:44:56,961 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [145527280] [2021-12-06 17:44:56,961 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:44:56,961 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:44:56,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:44:56,997 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:44:56,998 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:44:56,998 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [145527280] [2021-12-06 17:44:56,998 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [145527280] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:44:56,998 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:44:56,998 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:44:56,998 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1287623718] [2021-12-06 17:44:56,998 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:44:56,999 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:44:56,999 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:44:56,999 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 17:44:56,999 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 17:44:57,000 INFO L87 Difference]: Start difference. First operand 3897 states and 5766 transitions. cyclomatic complexity: 1873 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:44:57,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:44:57,226 INFO L93 Difference]: Finished difference Result 10905 states and 15920 transitions. [2021-12-06 17:44:57,226 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 17:44:57,227 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10905 states and 15920 transitions. [2021-12-06 17:44:57,268 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10426 [2021-12-06 17:44:57,324 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10905 states to 10905 states and 15920 transitions. [2021-12-06 17:44:57,324 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10905 [2021-12-06 17:44:57,333 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10905 [2021-12-06 17:44:57,333 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10905 states and 15920 transitions. [2021-12-06 17:44:57,345 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:44:57,345 INFO L681 BuchiCegarLoop]: Abstraction has 10905 states and 15920 transitions. [2021-12-06 17:44:57,353 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10905 states and 15920 transitions. [2021-12-06 17:44:57,489 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10905 to 10353. [2021-12-06 17:44:57,506 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10353 states, 10353 states have (on average 1.4643098618757848) internal successors, (15160), 10352 states have internal predecessors, (15160), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:44:57,552 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10353 states to 10353 states and 15160 transitions. [2021-12-06 17:44:57,552 INFO L704 BuchiCegarLoop]: Abstraction has 10353 states and 15160 transitions. [2021-12-06 17:44:57,552 INFO L587 BuchiCegarLoop]: Abstraction has 10353 states and 15160 transitions. [2021-12-06 17:44:57,552 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-06 17:44:57,553 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10353 states and 15160 transitions. [2021-12-06 17:44:57,574 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10170 [2021-12-06 17:44:57,575 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:44:57,575 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:44:57,576 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:44:57,576 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:44:57,576 INFO L791 eck$LassoCheckResult]: Stem: 42467#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 42468#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 42013#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42014#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42682#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 42683#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 42652#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42403#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42404#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42192#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 42193#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 42773#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 42628#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 42256#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 42020#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42021#L922 assume !(0 == ~M_E~0); 42876#L922-2 assume !(0 == ~T1_E~0); 42877#L927-1 assume !(0 == ~T2_E~0); 42476#L932-1 assume !(0 == ~T3_E~0); 42338#L937-1 assume !(0 == ~T4_E~0); 42339#L942-1 assume !(0 == ~T5_E~0); 42402#L947-1 assume !(0 == ~T6_E~0); 42480#L952-1 assume !(0 == ~T7_E~0); 42481#L957-1 assume !(0 == ~T8_E~0); 42569#L962-1 assume !(0 == ~T9_E~0); 42312#L967-1 assume !(0 == ~E_1~0); 42313#L972-1 assume !(0 == ~E_2~0); 42660#L977-1 assume !(0 == ~E_3~0); 42661#L982-1 assume !(0 == ~E_4~0); 41781#L987-1 assume !(0 == ~E_5~0); 41782#L992-1 assume !(0 == ~E_6~0); 41788#L997-1 assume !(0 == ~E_7~0); 42234#L1002-1 assume !(0 == ~E_8~0); 42218#L1007-1 assume !(0 == ~E_9~0); 41574#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41575#L443 assume !(1 == ~m_pc~0); 42497#L443-2 is_master_triggered_~__retres1~0#1 := 0; 42486#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42487#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 41951#L1140 assume !(0 != activate_threads_~tmp~1#1); 41689#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41690#L462 assume !(1 == ~t1_pc~0); 42332#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 42333#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41660#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 41661#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 42170#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42171#L481 assume !(1 == ~t2_pc~0); 41945#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 41944#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42335#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 42044#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 42045#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42145#L500 assume 1 == ~t3_pc~0; 42380#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 42381#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42640#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 42641#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 41579#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41580#L519 assume 1 == ~t4_pc~0; 41886#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41887#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42142#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41994#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 41995#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41746#L538 assume !(1 == ~t5_pc~0); 41747#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 41650#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41651#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41929#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 41930#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42545#L557 assume 1 == ~t6_pc~0; 42295#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41969#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41869#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41870#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 41996#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42824#L576 assume !(1 == ~t7_pc~0); 41955#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 41956#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42220#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42221#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 42615#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42084#L595 assume 1 == ~t8_pc~0; 42085#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 42642#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42643#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42434#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 42435#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41876#L614 assume !(1 == ~t9_pc~0); 41877#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 41771#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41772#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41959#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 42046#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42047#L1025 assume !(1 == ~M_E~0); 42320#L1025-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42378#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42538#L1035-1 assume !(1 == ~T3_E~0); 42041#L1040-1 assume !(1 == ~T4_E~0); 42042#L1045-1 assume !(1 == ~T5_E~0); 41940#L1050-1 assume !(1 == ~T6_E~0); 41941#L1055-1 assume !(1 == ~T7_E~0); 41755#L1060-1 assume !(1 == ~T8_E~0); 41756#L1065-1 assume !(1 == ~T9_E~0); 41821#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 42482#L1075-1 assume !(1 == ~E_2~0); 42483#L1080-1 assume !(1 == ~E_3~0); 42471#L1085-1 assume !(1 == ~E_4~0); 42472#L1090-1 assume !(1 == ~E_5~0); 42762#L1095-1 assume !(1 == ~E_6~0); 42516#L1100-1 assume !(1 == ~E_7~0); 42517#L1105-1 assume !(1 == ~E_8~0); 41727#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 41728#L1115-1 assume { :end_inline_reset_delta_events } true; 42095#L1396-2 [2021-12-06 17:44:57,576 INFO L793 eck$LassoCheckResult]: Loop: 42095#L1396-2 assume !false; 43221#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 43213#L897 assume !false; 43209#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 43204#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 43192#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 43189#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 43185#L766 assume !(0 != eval_~tmp~0#1); 43187#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50716#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50715#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50713#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 50714#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 51359#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 42469#L937-3 assume !(0 == ~T4_E~0); 41717#L942-3 assume !(0 == ~T5_E~0); 41718#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 42111#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 42112#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 42744#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 42581#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 42582#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 42474#L977-3 assume !(0 == ~E_3~0); 42475#L982-3 assume !(0 == ~E_4~0); 42882#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42059#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 42060#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 42054#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 42055#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 41757#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41758#L443-30 assume !(1 == ~m_pc~0); 42105#L443-32 is_master_triggered_~__retres1~0#1 := 0; 42089#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42090#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 42795#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 42666#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42200#L462-30 assume !(1 == ~t1_pc~0); 42201#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 42658#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42637#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 42638#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42699#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42183#L481-30 assume 1 == ~t2_pc~0; 41883#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41884#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51314#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 51312#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 51309#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51307#L500-30 assume !(1 == ~t3_pc~0); 51304#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 51303#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51302#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 51301#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 51300#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51299#L519-30 assume 1 == ~t4_pc~0; 51297#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 51291#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41623#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41624#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 42314#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 42452#L538-30 assume 1 == ~t5_pc~0; 41767#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41768#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42080#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 42081#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 41847#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41848#L557-30 assume 1 == ~t6_pc~0; 51256#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 42277#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42278#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 51255#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 51254#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51253#L576-30 assume 1 == ~t7_pc~0; 51251#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 51250#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 51249#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51248#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 51247#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 51246#L595-30 assume 1 == ~t8_pc~0; 51244#L596-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 51243#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51242#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51241#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 51240#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51239#L614-30 assume 1 == ~t9_pc~0; 51237#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 51236#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42079#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41759#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 41760#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42421#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 42422#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42173#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42775#L1035-3 assume !(1 == ~T3_E~0); 42776#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 42868#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 42879#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42639#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41656#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41657#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42668#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 42454#L1075-3 assume !(1 == ~E_2~0); 42455#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 42777#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 42653#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 42654#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 42689#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 42690#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41809#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 41810#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 42721#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 51191#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 51189#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 42665#L1415 assume !(0 == start_simulation_~tmp~3#1); 42307#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 42308#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 43242#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 43239#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 43235#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 43231#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43228#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 43225#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 42095#L1396-2 [2021-12-06 17:44:57,577 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:44:57,577 INFO L85 PathProgramCache]: Analyzing trace with hash 2064787514, now seen corresponding path program 1 times [2021-12-06 17:44:57,577 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:44:57,577 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [770211381] [2021-12-06 17:44:57,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:44:57,577 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:44:57,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:44:57,604 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:44:57,604 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:44:57,604 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [770211381] [2021-12-06 17:44:57,604 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [770211381] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:44:57,604 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:44:57,605 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:44:57,605 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1706783069] [2021-12-06 17:44:57,605 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:44:57,605 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:44:57,605 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:44:57,605 INFO L85 PathProgramCache]: Analyzing trace with hash -771290098, now seen corresponding path program 1 times [2021-12-06 17:44:57,605 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:44:57,605 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1549611023] [2021-12-06 17:44:57,606 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:44:57,606 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:44:57,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:44:57,632 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:44:57,664 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:44:57,664 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1549611023] [2021-12-06 17:44:57,665 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1549611023] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:44:57,665 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:44:57,665 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:44:57,665 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1307579521] [2021-12-06 17:44:57,665 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:44:57,666 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:44:57,666 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:44:57,666 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 17:44:57,667 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 17:44:57,667 INFO L87 Difference]: Start difference. First operand 10353 states and 15160 transitions. cyclomatic complexity: 4815 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:44:58,009 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:44:58,009 INFO L93 Difference]: Finished difference Result 29296 states and 42487 transitions. [2021-12-06 17:44:58,009 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 17:44:58,010 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29296 states and 42487 transitions. [2021-12-06 17:44:58,183 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 28430 [2021-12-06 17:44:58,305 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29296 states to 29296 states and 42487 transitions. [2021-12-06 17:44:58,305 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29296 [2021-12-06 17:44:58,322 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29296 [2021-12-06 17:44:58,322 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29296 states and 42487 transitions. [2021-12-06 17:44:58,338 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:44:58,338 INFO L681 BuchiCegarLoop]: Abstraction has 29296 states and 42487 transitions. [2021-12-06 17:44:58,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29296 states and 42487 transitions. [2021-12-06 17:44:58,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29296 to 28052. [2021-12-06 17:44:58,684 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28052 states, 28052 states have (on average 1.4542635106231285) internal successors, (40795), 28051 states have internal predecessors, (40795), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:44:58,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28052 states to 28052 states and 40795 transitions. [2021-12-06 17:44:58,746 INFO L704 BuchiCegarLoop]: Abstraction has 28052 states and 40795 transitions. [2021-12-06 17:44:58,746 INFO L587 BuchiCegarLoop]: Abstraction has 28052 states and 40795 transitions. [2021-12-06 17:44:58,746 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-06 17:44:58,746 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28052 states and 40795 transitions. [2021-12-06 17:44:58,859 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27830 [2021-12-06 17:44:58,859 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:44:58,859 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:44:58,861 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:44:58,861 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:44:58,861 INFO L791 eck$LassoCheckResult]: Stem: 82132#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 82133#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 81672#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 81673#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 82334#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 82335#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 82310#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 82073#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 82074#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 81858#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 81859#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 82440#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 82282#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 81926#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 81678#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 81679#L922 assume !(0 == ~M_E~0); 82546#L922-2 assume !(0 == ~T1_E~0); 82547#L927-1 assume !(0 == ~T2_E~0); 82140#L932-1 assume !(0 == ~T3_E~0); 82007#L937-1 assume !(0 == ~T4_E~0); 82008#L942-1 assume !(0 == ~T5_E~0); 82072#L947-1 assume !(0 == ~T6_E~0); 82145#L952-1 assume !(0 == ~T7_E~0); 82146#L957-1 assume !(0 == ~T8_E~0); 82227#L962-1 assume !(0 == ~T9_E~0); 81982#L967-1 assume !(0 == ~E_1~0); 81983#L972-1 assume !(0 == ~E_2~0); 82318#L977-1 assume !(0 == ~E_3~0); 82319#L982-1 assume !(0 == ~E_4~0); 81441#L987-1 assume !(0 == ~E_5~0); 81442#L992-1 assume !(0 == ~E_6~0); 81448#L997-1 assume !(0 == ~E_7~0); 81899#L1002-1 assume !(0 == ~E_8~0); 81885#L1007-1 assume !(0 == ~E_9~0); 81233#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 81234#L443 assume !(1 == ~m_pc~0); 82166#L443-2 is_master_triggered_~__retres1~0#1 := 0; 82152#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82153#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 81610#L1140 assume !(0 != activate_threads_~tmp~1#1); 81349#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 81350#L462 assume !(1 == ~t1_pc~0); 81998#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 81999#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 81319#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 81320#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 81837#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 81838#L481 assume !(1 == ~t2_pc~0); 81605#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 81604#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 82004#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 81702#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 81703#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81810#L500 assume !(1 == ~t3_pc~0); 82392#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 82351#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 82299#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 82300#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 81235#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 81236#L519 assume 1 == ~t4_pc~0; 81545#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 81546#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81809#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 81653#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 81654#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 81406#L538 assume !(1 == ~t5_pc~0); 81407#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 81309#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 81310#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 81588#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 81589#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 82209#L557 assume 1 == ~t6_pc~0; 81966#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 81627#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 81528#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 81529#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 81655#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 82498#L576 assume !(1 == ~t7_pc~0); 81614#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 81615#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 81888#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 81889#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 82271#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 81744#L595 assume 1 == ~t8_pc~0; 81745#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 82301#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 82302#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 82099#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 82100#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 81535#L614 assume !(1 == ~t9_pc~0); 81536#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 81431#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 81432#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 81618#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 81704#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81705#L1025 assume !(1 == ~M_E~0); 81989#L1025-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 82048#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 82202#L1035-1 assume !(1 == ~T3_E~0); 81699#L1040-1 assume !(1 == ~T4_E~0); 81700#L1045-1 assume !(1 == ~T5_E~0); 82342#L1050-1 assume !(1 == ~T6_E~0); 81802#L1055-1 assume !(1 == ~T7_E~0); 81803#L1060-1 assume !(1 == ~T8_E~0); 81481#L1065-1 assume !(1 == ~T9_E~0); 81482#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 82147#L1075-1 assume !(1 == ~E_2~0); 82148#L1080-1 assume !(1 == ~E_3~0); 82567#L1085-1 assume !(1 == ~E_4~0); 102174#L1090-1 assume !(1 == ~E_5~0); 102173#L1095-1 assume !(1 == ~E_6~0); 102172#L1100-1 assume !(1 == ~E_7~0); 102171#L1105-1 assume !(1 == ~E_8~0); 102170#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 102168#L1115-1 assume { :end_inline_reset_delta_events } true; 102166#L1396-2 [2021-12-06 17:44:58,862 INFO L793 eck$LassoCheckResult]: Loop: 102166#L1396-2 assume !false; 102164#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 102160#L897 assume !false; 102153#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 102154#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 108321#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 108320#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 108319#L766 assume !(0 != eval_~tmp~0#1); 107490#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 107488#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 107486#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 107484#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 107481#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 107479#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 107477#L937-3 assume !(0 == ~T4_E~0); 107475#L942-3 assume !(0 == ~T5_E~0); 107473#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 107471#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 107468#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 107466#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 107464#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 107462#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 107460#L977-3 assume !(0 == ~E_3~0); 107458#L982-3 assume !(0 == ~E_4~0); 107455#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 107453#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 107451#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 107449#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 107447#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 107445#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 107442#L443-30 assume !(1 == ~m_pc~0); 107440#L443-32 is_master_triggered_~__retres1~0#1 := 0; 107438#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 107100#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 106296#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 105898#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 104318#L462-30 assume !(1 == ~t1_pc~0); 104317#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 104316#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 104315#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 104314#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 104313#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 104312#L481-30 assume !(1 == ~t2_pc~0); 104311#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 104309#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 104308#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 104307#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 104306#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 104305#L500-30 assume !(1 == ~t3_pc~0); 104303#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 104301#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 104299#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 104297#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 104295#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 104293#L519-30 assume 1 == ~t4_pc~0; 104231#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 104228#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 104226#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 104224#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 104222#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 104220#L538-30 assume !(1 == ~t5_pc~0); 104217#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 104214#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 104212#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 104210#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 104208#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 104206#L557-30 assume 1 == ~t6_pc~0; 104203#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 104200#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 104198#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 104196#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 104194#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 104192#L576-30 assume 1 == ~t7_pc~0; 104189#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 104186#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 104184#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 104182#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 104180#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 104178#L595-30 assume !(1 == ~t8_pc~0); 104176#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 104172#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 104170#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 104168#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 104166#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 104164#L614-30 assume 1 == ~t9_pc~0; 104161#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 104158#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 104156#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 104154#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 104152#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 104150#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 104148#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 104146#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 104145#L1035-3 assume !(1 == ~T3_E~0); 104143#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 104141#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 104140#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 104138#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 104136#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 104134#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 104132#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 104130#L1075-3 assume !(1 == ~E_2~0); 104128#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 104126#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 104125#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 104123#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 104121#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 104119#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 104117#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 104114#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 104097#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 104095#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 104093#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 104090#L1415 assume !(0 == start_simulation_~tmp~3#1); 104087#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 103906#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 103895#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 103892#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 103889#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 103886#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 102280#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 102169#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 102166#L1396-2 [2021-12-06 17:44:58,862 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:44:58,862 INFO L85 PathProgramCache]: Analyzing trace with hash -410453863, now seen corresponding path program 1 times [2021-12-06 17:44:58,862 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:44:58,862 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [669576656] [2021-12-06 17:44:58,862 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:44:58,863 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:44:58,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:44:58,899 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:44:58,899 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:44:58,900 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [669576656] [2021-12-06 17:44:58,900 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [669576656] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:44:58,900 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:44:58,900 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 17:44:58,900 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [900810889] [2021-12-06 17:44:58,900 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:44:58,900 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:44:58,901 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:44:58,901 INFO L85 PathProgramCache]: Analyzing trace with hash 790261035, now seen corresponding path program 1 times [2021-12-06 17:44:58,901 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:44:58,901 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1708071740] [2021-12-06 17:44:58,901 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:44:58,901 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:44:58,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:44:58,935 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:44:58,935 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:44:58,935 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1708071740] [2021-12-06 17:44:58,935 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1708071740] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:44:58,935 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:44:58,935 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:44:58,935 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [790156056] [2021-12-06 17:44:58,936 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:44:58,936 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:44:58,936 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:44:58,936 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:44:58,936 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:44:58,937 INFO L87 Difference]: Start difference. First operand 28052 states and 40795 transitions. cyclomatic complexity: 12759 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 2 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:44:59,151 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:44:59,151 INFO L93 Difference]: Finished difference Result 53107 states and 76965 transitions. [2021-12-06 17:44:59,151 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:44:59,152 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53107 states and 76965 transitions. [2021-12-06 17:44:59,390 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 52754 [2021-12-06 17:44:59,538 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53107 states to 53107 states and 76965 transitions. [2021-12-06 17:44:59,539 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 53107 [2021-12-06 17:44:59,555 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 53107 [2021-12-06 17:44:59,556 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53107 states and 76965 transitions. [2021-12-06 17:44:59,571 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:44:59,572 INFO L681 BuchiCegarLoop]: Abstraction has 53107 states and 76965 transitions. [2021-12-06 17:44:59,587 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53107 states and 76965 transitions. [2021-12-06 17:45:00,093 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53107 to 53035. [2021-12-06 17:45:00,138 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 53035 states, 53035 states have (on average 1.4498538700857924) internal successors, (76893), 53034 states have internal predecessors, (76893), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:00,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53035 states to 53035 states and 76893 transitions. [2021-12-06 17:45:00,240 INFO L704 BuchiCegarLoop]: Abstraction has 53035 states and 76893 transitions. [2021-12-06 17:45:00,240 INFO L587 BuchiCegarLoop]: Abstraction has 53035 states and 76893 transitions. [2021-12-06 17:45:00,240 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-06 17:45:00,240 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 53035 states and 76893 transitions. [2021-12-06 17:45:00,423 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 52682 [2021-12-06 17:45:00,423 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:45:00,423 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:45:00,425 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:00,425 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:00,425 INFO L791 eck$LassoCheckResult]: Stem: 163253#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 163254#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 162823#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 162824#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 163418#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 163419#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 163400#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 163195#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 163196#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 162999#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 163000#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 163497#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 163380#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 163060#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 162829#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 162830#L922 assume !(0 == ~M_E~0); 163574#L922-2 assume !(0 == ~T1_E~0); 163575#L927-1 assume !(0 == ~T2_E~0); 163261#L932-1 assume !(0 == ~T3_E~0); 163136#L937-1 assume !(0 == ~T4_E~0); 163137#L942-1 assume !(0 == ~T5_E~0); 163194#L947-1 assume !(0 == ~T6_E~0); 163265#L952-1 assume !(0 == ~T7_E~0); 163266#L957-1 assume !(0 == ~T8_E~0); 163336#L962-1 assume !(0 == ~T9_E~0); 163112#L967-1 assume !(0 == ~E_1~0); 163113#L972-1 assume !(0 == ~E_2~0); 163404#L977-1 assume !(0 == ~E_3~0); 163405#L982-1 assume !(0 == ~E_4~0); 162603#L987-1 assume !(0 == ~E_5~0); 162604#L992-1 assume !(0 == ~E_6~0); 162610#L997-1 assume !(0 == ~E_7~0); 163037#L1002-1 assume !(0 == ~E_8~0); 163022#L1007-1 assume !(0 == ~E_9~0); 162399#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 162400#L443 assume !(1 == ~m_pc~0); 163282#L443-2 is_master_triggered_~__retres1~0#1 := 0; 163272#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 163273#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 162762#L1140 assume !(0 != activate_threads_~tmp~1#1); 162514#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 162515#L462 assume !(1 == ~t1_pc~0); 163128#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 163129#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 162485#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 162486#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 162978#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 162979#L481 assume !(1 == ~t2_pc~0); 162757#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 162756#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 163133#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 162852#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 162853#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 162953#L500 assume !(1 == ~t3_pc~0); 163464#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 163433#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 163389#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 163390#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 162404#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 162405#L519 assume !(1 == ~t4_pc~0); 163180#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 162949#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 162950#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 162805#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 162806#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 162568#L538 assume !(1 == ~t5_pc~0); 162569#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 162475#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 162476#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 162741#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 162742#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 163319#L557 assume 1 == ~t6_pc~0; 163097#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 162779#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 162684#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 162685#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 162807#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 163540#L576 assume !(1 == ~t7_pc~0); 162766#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 162767#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 163025#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 163026#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 163372#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 162894#L595 assume 1 == ~t8_pc~0; 162895#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 163391#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 163392#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 163223#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 163224#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 162693#L614 assume !(1 == ~t9_pc~0); 162694#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 162593#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 162594#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 162770#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 162854#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 162855#L1025 assume !(1 == ~M_E~0); 163119#L1025-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 163172#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 163310#L1035-1 assume !(1 == ~T3_E~0); 162849#L1040-1 assume !(1 == ~T4_E~0); 162850#L1045-1 assume !(1 == ~T5_E~0); 182666#L1050-1 assume !(1 == ~T6_E~0); 182665#L1055-1 assume !(1 == ~T7_E~0); 182664#L1060-1 assume !(1 == ~T8_E~0); 182663#L1065-1 assume !(1 == ~T9_E~0); 182662#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 163267#L1075-1 assume !(1 == ~E_2~0); 163268#L1080-1 assume !(1 == ~E_3~0); 163584#L1085-1 assume !(1 == ~E_4~0); 183496#L1090-1 assume !(1 == ~E_5~0); 183494#L1095-1 assume !(1 == ~E_6~0); 183491#L1100-1 assume !(1 == ~E_7~0); 183489#L1105-1 assume !(1 == ~E_8~0); 183487#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 183483#L1115-1 assume { :end_inline_reset_delta_events } true; 183481#L1396-2 [2021-12-06 17:45:00,425 INFO L793 eck$LassoCheckResult]: Loop: 183481#L1396-2 assume !false; 183478#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 183472#L897 assume !false; 183470#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 182820#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 182773#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 182767#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 182760#L766 assume !(0 != eval_~tmp~0#1); 182761#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 186207#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 186206#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 186205#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 186204#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 186203#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 186202#L937-3 assume !(0 == ~T4_E~0); 186201#L942-3 assume !(0 == ~T5_E~0); 186200#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 186199#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 186198#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 186197#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 186196#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 186195#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 186194#L977-3 assume !(0 == ~E_3~0); 186193#L982-3 assume !(0 == ~E_4~0); 186192#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 186191#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 186190#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 186189#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 186188#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 186187#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 186185#L443-30 assume !(1 == ~m_pc~0); 186183#L443-32 is_master_triggered_~__retres1~0#1 := 0; 186181#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 186179#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 186177#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 186175#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 186173#L462-30 assume !(1 == ~t1_pc~0); 186170#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 186166#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 186163#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 186161#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 186159#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 186156#L481-30 assume 1 == ~t2_pc~0; 186151#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 186148#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 186145#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 186142#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 186139#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 186136#L500-30 assume !(1 == ~t3_pc~0); 186133#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 186130#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 186127#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 186124#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 186121#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 186117#L519-30 assume !(1 == ~t4_pc~0); 186112#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 186108#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 186104#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 186100#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 186096#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 186092#L538-30 assume !(1 == ~t5_pc~0); 186087#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 186083#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 186079#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 186074#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 186068#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 186063#L557-30 assume 1 == ~t6_pc~0; 186055#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 186050#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 186045#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 186040#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 186036#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 186032#L576-30 assume 1 == ~t7_pc~0; 186027#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 186022#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 186017#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 186012#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 186006#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 186001#L595-30 assume 1 == ~t8_pc~0; 185994#L596-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 185989#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 185984#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 185980#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 185977#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 185939#L614-30 assume 1 == ~t9_pc~0; 185931#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 185926#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 185921#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 185916#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 185911#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 185906#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 185899#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 170035#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 185886#L1035-3 assume !(1 == ~T3_E~0); 185879#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 184346#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 185870#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 185866#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 185861#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 185856#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 185851#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 185845#L1075-3 assume !(1 == ~E_2~0); 185840#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 177110#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 185831#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 185826#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 185819#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 185815#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 185812#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 185809#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 185782#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 185779#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 185776#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 185767#L1415 assume !(0 == start_simulation_~tmp~3#1); 185765#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 185071#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 185062#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 184836#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 184834#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 184830#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 184825#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 183484#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 183481#L1396-2 [2021-12-06 17:45:00,425 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:00,425 INFO L85 PathProgramCache]: Analyzing trace with hash -402703304, now seen corresponding path program 1 times [2021-12-06 17:45:00,425 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:00,426 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1806363700] [2021-12-06 17:45:00,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:00,426 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:00,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:45:00,457 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:45:00,457 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:45:00,457 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1806363700] [2021-12-06 17:45:00,457 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1806363700] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:45:00,457 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:45:00,457 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 17:45:00,457 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [203565212] [2021-12-06 17:45:00,457 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:45:00,458 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:45:00,458 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:00,458 INFO L85 PathProgramCache]: Analyzing trace with hash -1408718452, now seen corresponding path program 1 times [2021-12-06 17:45:00,458 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:00,458 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [496512922] [2021-12-06 17:45:00,459 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:00,459 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:00,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:45:00,483 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:45:00,483 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:45:00,483 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [496512922] [2021-12-06 17:45:00,483 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [496512922] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:45:00,483 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:45:00,483 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:45:00,483 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1912334751] [2021-12-06 17:45:00,483 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:45:00,483 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:45:00,484 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:45:00,484 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-06 17:45:00,484 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-06 17:45:00,484 INFO L87 Difference]: Start difference. First operand 53035 states and 76893 transitions. cyclomatic complexity: 23890 Second operand has 5 states, 5 states have (on average 23.0) internal successors, (115), 5 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:00,956 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:45:00,956 INFO L93 Difference]: Finished difference Result 134550 states and 196416 transitions. [2021-12-06 17:45:00,956 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-06 17:45:00,956 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 134550 states and 196416 transitions. [2021-12-06 17:45:01,486 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 133656 [2021-12-06 17:45:01,855 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 134550 states to 134550 states and 196416 transitions. [2021-12-06 17:45:01,855 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 134550 [2021-12-06 17:45:01,904 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 134550 [2021-12-06 17:45:01,904 INFO L73 IsDeterministic]: Start isDeterministic. Operand 134550 states and 196416 transitions. [2021-12-06 17:45:01,970 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:45:01,970 INFO L681 BuchiCegarLoop]: Abstraction has 134550 states and 196416 transitions. [2021-12-06 17:45:02,011 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134550 states and 196416 transitions. [2021-12-06 17:45:02,594 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134550 to 54790. [2021-12-06 17:45:02,627 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54790 states, 54790 states have (on average 1.4354444241649935) internal successors, (78648), 54789 states have internal predecessors, (78648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:02,719 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54790 states to 54790 states and 78648 transitions. [2021-12-06 17:45:02,719 INFO L704 BuchiCegarLoop]: Abstraction has 54790 states and 78648 transitions. [2021-12-06 17:45:02,719 INFO L587 BuchiCegarLoop]: Abstraction has 54790 states and 78648 transitions. [2021-12-06 17:45:02,719 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-06 17:45:02,719 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54790 states and 78648 transitions. [2021-12-06 17:45:02,836 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 54434 [2021-12-06 17:45:02,836 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:45:02,836 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:45:02,838 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:02,838 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:02,838 INFO L791 eck$LassoCheckResult]: Stem: 350870#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 350871#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 350429#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 350430#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 351057#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 351058#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 351036#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 350809#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 350810#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 350612#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 350613#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 351143#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 351015#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 350672#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 350435#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 350436#L922 assume !(0 == ~M_E~0); 351235#L922-2 assume !(0 == ~T1_E~0); 351236#L927-1 assume !(0 == ~T2_E~0); 350878#L932-1 assume !(0 == ~T3_E~0); 350748#L937-1 assume !(0 == ~T4_E~0); 350749#L942-1 assume !(0 == ~T5_E~0); 350808#L947-1 assume !(0 == ~T6_E~0); 350882#L952-1 assume !(0 == ~T7_E~0); 350883#L957-1 assume !(0 == ~T8_E~0); 350963#L962-1 assume !(0 == ~T9_E~0); 350725#L967-1 assume !(0 == ~E_1~0); 350726#L972-1 assume !(0 == ~E_2~0); 351041#L977-1 assume !(0 == ~E_3~0); 351042#L982-1 assume !(0 == ~E_4~0); 350202#L987-1 assume !(0 == ~E_5~0); 350203#L992-1 assume !(0 == ~E_6~0); 350209#L997-1 assume !(0 == ~E_7~0); 350650#L1002-1 assume !(0 == ~E_8~0); 350635#L1007-1 assume !(0 == ~E_9~0); 349997#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 349998#L443 assume !(1 == ~m_pc~0); 350904#L443-2 is_master_triggered_~__retres1~0#1 := 0; 350890#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 350891#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 350367#L1140 assume !(0 != activate_threads_~tmp~1#1); 350113#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 350114#L462 assume !(1 == ~t1_pc~0); 350740#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 350741#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 350083#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 350084#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 350592#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 350593#L481 assume !(1 == ~t2_pc~0); 350361#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 350360#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 350745#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 350458#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 350459#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 350567#L500 assume !(1 == ~t3_pc~0); 351103#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 351072#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 351027#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 351028#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 350002#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 350003#L519 assume !(1 == ~t4_pc~0); 350795#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 350563#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 350564#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 350410#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 350411#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 350167#L538 assume !(1 == ~t5_pc~0); 350168#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 350073#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 350074#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 350345#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 350346#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 350945#L557 assume 1 == ~t6_pc~0; 350710#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 350384#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 350286#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 350287#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 350412#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 351198#L576 assume !(1 == ~t7_pc~0); 350371#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 350372#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 350638#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 350639#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 351005#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 350498#L595 assume 1 == ~t8_pc~0; 350499#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 351029#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 351030#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 350839#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 350840#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 350295#L614 assume !(1 == ~t9_pc~0); 350296#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 350192#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 350193#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 350375#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 350460#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 350461#L1025 assume !(1 == ~M_E~0); 350732#L1025-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 350786#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 350936#L1035-1 assume !(1 == ~T3_E~0); 350455#L1040-1 assume !(1 == ~T4_E~0); 350456#L1045-1 assume !(1 == ~T5_E~0); 350356#L1050-1 assume !(1 == ~T6_E~0); 350357#L1055-1 assume !(1 == ~T7_E~0); 350176#L1060-1 assume !(1 == ~T8_E~0); 350177#L1065-1 assume !(1 == ~T9_E~0); 351208#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 350884#L1075-1 assume !(1 == ~E_2~0); 350885#L1080-1 assume !(1 == ~E_3~0); 351259#L1085-1 assume !(1 == ~E_4~0); 371752#L1090-1 assume !(1 == ~E_5~0); 371750#L1095-1 assume !(1 == ~E_6~0); 371748#L1100-1 assume !(1 == ~E_7~0); 371746#L1105-1 assume !(1 == ~E_8~0); 371744#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 371713#L1115-1 assume { :end_inline_reset_delta_events } true; 371701#L1396-2 [2021-12-06 17:45:02,839 INFO L793 eck$LassoCheckResult]: Loop: 371701#L1396-2 assume !false; 371694#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 371688#L897 assume !false; 371687#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 371676#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 371665#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 371663#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 371659#L766 assume !(0 != eval_~tmp~0#1); 371660#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 375477#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 375474#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 375471#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 375466#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 375463#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 375460#L937-3 assume !(0 == ~T4_E~0); 375457#L942-3 assume !(0 == ~T5_E~0); 375454#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 375451#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 375446#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 375443#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 375440#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 375437#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 375434#L977-3 assume !(0 == ~E_3~0); 375431#L982-3 assume !(0 == ~E_4~0); 375428#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 375425#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 375422#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 375421#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 375420#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 375419#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 375418#L443-30 assume !(1 == ~m_pc~0); 375417#L443-32 is_master_triggered_~__retres1~0#1 := 0; 375416#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 375415#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 375414#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 375413#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 375412#L462-30 assume !(1 == ~t1_pc~0); 375411#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 375410#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 375409#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 375408#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 375407#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 375406#L481-30 assume !(1 == ~t2_pc~0); 375405#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 375403#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 375402#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 375401#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 375400#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 375399#L500-30 assume !(1 == ~t3_pc~0); 375398#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 375397#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 375396#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 375395#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 375394#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 375393#L519-30 assume !(1 == ~t4_pc~0); 375392#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 375391#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 375390#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 375389#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 375388#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 375387#L538-30 assume 1 == ~t5_pc~0; 375385#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 375383#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 375381#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 375379#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 375376#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 375374#L557-30 assume !(1 == ~t6_pc~0); 375372#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 375369#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 375367#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 375365#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 375363#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 375361#L576-30 assume !(1 == ~t7_pc~0); 375359#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 375357#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 375355#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 375353#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 375351#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 375349#L595-30 assume !(1 == ~t8_pc~0); 375344#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 375341#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 375339#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 375337#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 375335#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 375333#L614-30 assume !(1 == ~t9_pc~0); 375331#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 375328#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 375326#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 375325#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 375323#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 375321#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 375309#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 370770#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 375304#L1035-3 assume !(1 == ~T3_E~0); 375300#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 373942#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 375288#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 375286#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 375284#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 375282#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 375244#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 375198#L1075-3 assume !(1 == ~E_2~0); 375193#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 372342#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 375178#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 375174#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 375173#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 375172#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 373395#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 372059#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 371892#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 371883#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 371877#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 371869#L1415 assume !(0 == start_simulation_~tmp~3#1); 371865#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 371762#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 371753#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 371751#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 371749#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 371747#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 371745#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 371714#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 371701#L1396-2 [2021-12-06 17:45:02,839 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:02,839 INFO L85 PathProgramCache]: Analyzing trace with hash 1525569398, now seen corresponding path program 1 times [2021-12-06 17:45:02,839 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:02,839 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [529710482] [2021-12-06 17:45:02,839 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:02,839 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:02,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:45:02,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:45:02,870 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:45:02,870 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [529710482] [2021-12-06 17:45:02,870 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [529710482] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:45:02,870 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:45:02,870 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:45:02,870 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1668244898] [2021-12-06 17:45:02,870 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:45:02,870 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:45:02,870 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:02,871 INFO L85 PathProgramCache]: Analyzing trace with hash -390917688, now seen corresponding path program 1 times [2021-12-06 17:45:02,871 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:02,871 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1824026751] [2021-12-06 17:45:02,871 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:02,871 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:02,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:45:02,893 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:45:02,893 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:45:02,893 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1824026751] [2021-12-06 17:45:02,893 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1824026751] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:45:02,893 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:45:02,893 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:45:02,893 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [843010208] [2021-12-06 17:45:02,893 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:45:02,894 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:45:02,894 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:45:02,894 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 17:45:02,894 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 17:45:02,895 INFO L87 Difference]: Start difference. First operand 54790 states and 78648 transitions. cyclomatic complexity: 23890 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:03,369 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:45:03,369 INFO L93 Difference]: Finished difference Result 154073 states and 219805 transitions. [2021-12-06 17:45:03,369 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 17:45:03,370 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 154073 states and 219805 transitions. [2021-12-06 17:45:03,996 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 150598 [2021-12-06 17:45:04,346 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 154073 states to 154073 states and 219805 transitions. [2021-12-06 17:45:04,346 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 154073 [2021-12-06 17:45:04,403 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 154073 [2021-12-06 17:45:04,403 INFO L73 IsDeterministic]: Start isDeterministic. Operand 154073 states and 219805 transitions. [2021-12-06 17:45:04,454 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:45:04,454 INFO L681 BuchiCegarLoop]: Abstraction has 154073 states and 219805 transitions. [2021-12-06 17:45:04,506 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 154073 states and 219805 transitions. [2021-12-06 17:45:05,531 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 154073 to 149169. [2021-12-06 17:45:05,628 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 149169 states, 149169 states have (on average 1.4300893617306545) internal successors, (213325), 149168 states have internal predecessors, (213325), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:06,022 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149169 states to 149169 states and 213325 transitions. [2021-12-06 17:45:06,022 INFO L704 BuchiCegarLoop]: Abstraction has 149169 states and 213325 transitions. [2021-12-06 17:45:06,022 INFO L587 BuchiCegarLoop]: Abstraction has 149169 states and 213325 transitions. [2021-12-06 17:45:06,022 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-06 17:45:06,022 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 149169 states and 213325 transitions. [2021-12-06 17:45:06,422 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 148510 [2021-12-06 17:45:06,422 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:45:06,422 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:45:06,424 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:06,424 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:06,424 INFO L791 eck$LassoCheckResult]: Stem: 559770#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 559771#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 559304#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 559305#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 559985#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 559986#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 559958#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 559710#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 559711#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 559490#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 559491#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 560084#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 559938#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 559559#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 559310#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 559311#L922 assume !(0 == ~M_E~0); 560197#L922-2 assume !(0 == ~T1_E~0); 560198#L927-1 assume !(0 == ~T2_E~0); 559778#L932-1 assume !(0 == ~T3_E~0); 559640#L937-1 assume !(0 == ~T4_E~0); 559641#L942-1 assume !(0 == ~T5_E~0); 559709#L947-1 assume !(0 == ~T6_E~0); 559783#L952-1 assume !(0 == ~T7_E~0); 559784#L957-1 assume !(0 == ~T8_E~0); 559873#L962-1 assume !(0 == ~T9_E~0); 559610#L967-1 assume !(0 == ~E_1~0); 559611#L972-1 assume !(0 == ~E_2~0); 559963#L977-1 assume !(0 == ~E_3~0); 559964#L982-1 assume !(0 == ~E_4~0); 559073#L987-1 assume !(0 == ~E_5~0); 559074#L992-1 assume !(0 == ~E_6~0); 559082#L997-1 assume !(0 == ~E_7~0); 559534#L1002-1 assume !(0 == ~E_8~0); 559518#L1007-1 assume !(0 == ~E_9~0); 558870#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 558871#L443 assume !(1 == ~m_pc~0); 559806#L443-2 is_master_triggered_~__retres1~0#1 := 0; 559790#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 559791#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 559242#L1140 assume !(0 != activate_threads_~tmp~1#1); 558986#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 558987#L462 assume !(1 == ~t1_pc~0); 559635#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 559636#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 558956#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 558957#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 559468#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 559469#L481 assume !(1 == ~t2_pc~0); 559236#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 559235#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 559637#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 559334#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 559335#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 559441#L500 assume !(1 == ~t3_pc~0); 560041#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 560003#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 559947#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 559948#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 558875#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 558876#L519 assume !(1 == ~t4_pc~0); 559692#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 559439#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 559440#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 559282#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 559283#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 559041#L538 assume !(1 == ~t5_pc~0); 559042#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 558946#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 558947#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 559218#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 559219#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 559848#L557 assume !(1 == ~t6_pc~0); 559258#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 559259#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 559156#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 559157#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 559284#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 560143#L576 assume !(1 == ~t7_pc~0); 559246#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 559247#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 559521#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 559522#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 559925#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 559376#L595 assume 1 == ~t8_pc~0; 559377#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 559949#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 559950#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 559738#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 559739#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 559169#L614 assume !(1 == ~t9_pc~0); 559170#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 559066#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 559067#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 559250#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 559336#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 559337#L1025 assume !(1 == ~M_E~0); 559621#L1025-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 559684#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 559840#L1035-1 assume !(1 == ~T3_E~0); 559330#L1040-1 assume !(1 == ~T4_E~0); 559331#L1045-1 assume !(1 == ~T5_E~0); 677161#L1050-1 assume !(1 == ~T6_E~0); 677160#L1055-1 assume !(1 == ~T7_E~0); 677159#L1060-1 assume !(1 == ~T8_E~0); 677158#L1065-1 assume !(1 == ~T9_E~0); 677157#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 677156#L1075-1 assume !(1 == ~E_2~0); 677155#L1080-1 assume !(1 == ~E_3~0); 677021#L1085-1 assume !(1 == ~E_4~0); 681935#L1090-1 assume !(1 == ~E_5~0); 681933#L1095-1 assume !(1 == ~E_6~0); 681931#L1100-1 assume !(1 == ~E_7~0); 681929#L1105-1 assume !(1 == ~E_8~0); 681927#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 681306#L1115-1 assume { :end_inline_reset_delta_events } true; 681307#L1396-2 [2021-12-06 17:45:06,424 INFO L793 eck$LassoCheckResult]: Loop: 681307#L1396-2 assume !false; 681298#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 681294#L897 assume !false; 681289#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 681290#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 691859#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 691857#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 691855#L766 assume !(0 != eval_~tmp~0#1); 681583#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 681580#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 681578#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 681576#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 681574#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 681572#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 681570#L937-3 assume !(0 == ~T4_E~0); 681567#L942-3 assume !(0 == ~T5_E~0); 681565#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 681563#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 681561#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 681559#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 681557#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 681554#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 681552#L977-3 assume !(0 == ~E_3~0); 681550#L982-3 assume !(0 == ~E_4~0); 681548#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 681546#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 681544#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 681543#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 681542#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 681541#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 681540#L443-30 assume !(1 == ~m_pc~0); 681539#L443-32 is_master_triggered_~__retres1~0#1 := 0; 681537#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 681535#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 681534#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 681533#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 681532#L462-30 assume !(1 == ~t1_pc~0); 681530#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 681529#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 681527#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 681528#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 681523#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 681524#L481-30 assume !(1 == ~t2_pc~0); 692162#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 692160#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 692159#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 692158#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 692157#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 692156#L500-30 assume !(1 == ~t3_pc~0); 692155#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 692154#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 692153#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 692152#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 692151#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 692150#L519-30 assume !(1 == ~t4_pc~0); 692149#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 692148#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 692147#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 692146#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 681485#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 681486#L538-30 assume 1 == ~t5_pc~0; 692086#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 692087#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 692088#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 692081#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 692080#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 692079#L557-30 assume !(1 == ~t6_pc~0); 692078#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 692077#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 692076#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 692075#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 692074#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 692073#L576-30 assume !(1 == ~t7_pc~0); 692072#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 692070#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 692069#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 692068#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 692067#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 692066#L595-30 assume 1 == ~t8_pc~0; 692064#L596-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 692063#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 692062#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 692061#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 692060#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 692059#L614-30 assume !(1 == ~t9_pc~0); 692058#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 692056#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 692055#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 692054#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 692053#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 692052#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 692051#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 676814#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 692048#L1035-3 assume !(1 == ~T3_E~0); 692047#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 692045#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 692044#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 692043#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 692042#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 692041#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 692040#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 692039#L1075-3 assume !(1 == ~E_2~0); 692038#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 691126#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 692037#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 692036#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 692035#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 692034#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 692033#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 692032#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 691901#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 691900#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 691899#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 691897#L1415 assume !(0 == start_simulation_~tmp~3#1); 691895#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 691893#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 691884#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 691883#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 691882#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 681319#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 681320#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 681308#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 681307#L1396-2 [2021-12-06 17:45:06,425 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:06,425 INFO L85 PathProgramCache]: Analyzing trace with hash 250466709, now seen corresponding path program 1 times [2021-12-06 17:45:06,425 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:06,425 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [813403581] [2021-12-06 17:45:06,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:06,425 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:06,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:45:06,452 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:45:06,452 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:45:06,452 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [813403581] [2021-12-06 17:45:06,452 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [813403581] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:45:06,452 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:45:06,452 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 17:45:06,452 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [869804750] [2021-12-06 17:45:06,452 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:45:06,452 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:45:06,453 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:06,453 INFO L85 PathProgramCache]: Analyzing trace with hash 884185001, now seen corresponding path program 1 times [2021-12-06 17:45:06,453 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:06,453 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1769678805] [2021-12-06 17:45:06,453 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:06,453 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:06,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:45:06,474 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:45:06,475 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:45:06,475 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1769678805] [2021-12-06 17:45:06,475 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1769678805] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:45:06,475 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:45:06,475 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:45:06,475 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [101436772] [2021-12-06 17:45:06,475 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:45:06,476 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:45:06,476 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:45:06,476 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:45:06,476 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:45:06,476 INFO L87 Difference]: Start difference. First operand 149169 states and 213325 transitions. cyclomatic complexity: 64220 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 2 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:07,193 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:45:07,194 INFO L93 Difference]: Finished difference Result 281090 states and 401274 transitions. [2021-12-06 17:45:07,194 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:45:07,194 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 281090 states and 401274 transitions. [2021-12-06 17:45:08,345 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 279504 [2021-12-06 17:45:08,871 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 281090 states to 281090 states and 401274 transitions. [2021-12-06 17:45:08,871 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 281090 [2021-12-06 17:45:09,068 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 281090 [2021-12-06 17:45:09,069 INFO L73 IsDeterministic]: Start isDeterministic. Operand 281090 states and 401274 transitions. [2021-12-06 17:45:09,133 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:45:09,133 INFO L681 BuchiCegarLoop]: Abstraction has 281090 states and 401274 transitions. [2021-12-06 17:45:09,205 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 281090 states and 401274 transitions. [2021-12-06 17:45:10,871 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 281090 to 280658. [2021-12-06 17:45:11,036 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 280658 states, 280658 states have (on average 1.4282222491430852) internal successors, (400842), 280657 states have internal predecessors, (400842), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:11,820 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280658 states to 280658 states and 400842 transitions. [2021-12-06 17:45:11,820 INFO L704 BuchiCegarLoop]: Abstraction has 280658 states and 400842 transitions. [2021-12-06 17:45:11,820 INFO L587 BuchiCegarLoop]: Abstraction has 280658 states and 400842 transitions. [2021-12-06 17:45:11,820 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-06 17:45:11,820 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 280658 states and 400842 transitions. [2021-12-06 17:45:12,426 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 279072 [2021-12-06 17:45:12,426 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:45:12,426 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:45:12,428 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:12,428 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:12,428 INFO L791 eck$LassoCheckResult]: Stem: 990016#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 990017#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 989569#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 989570#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 990199#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 990200#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 990176#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 989963#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 989964#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 989752#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 989753#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 990292#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 990155#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 989821#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 989575#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 989576#L922 assume !(0 == ~M_E~0); 990370#L922-2 assume !(0 == ~T1_E~0); 990371#L927-1 assume !(0 == ~T2_E~0); 990025#L932-1 assume !(0 == ~T3_E~0); 989895#L937-1 assume !(0 == ~T4_E~0); 989896#L942-1 assume !(0 == ~T5_E~0); 989962#L947-1 assume !(0 == ~T6_E~0); 990029#L952-1 assume !(0 == ~T7_E~0); 990030#L957-1 assume !(0 == ~T8_E~0); 990101#L962-1 assume !(0 == ~T9_E~0); 989868#L967-1 assume !(0 == ~E_1~0); 989869#L972-1 assume !(0 == ~E_2~0); 990182#L977-1 assume !(0 == ~E_3~0); 990183#L982-1 assume !(0 == ~E_4~0); 989340#L987-1 assume !(0 == ~E_5~0); 989341#L992-1 assume !(0 == ~E_6~0); 989349#L997-1 assume !(0 == ~E_7~0); 989794#L1002-1 assume !(0 == ~E_8~0); 989780#L1007-1 assume !(0 == ~E_9~0); 989136#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 989137#L443 assume !(1 == ~m_pc~0); 990048#L443-2 is_master_triggered_~__retres1~0#1 := 0; 990035#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 990036#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 989508#L1140 assume !(0 != activate_threads_~tmp~1#1); 989253#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 989254#L462 assume !(1 == ~t1_pc~0); 989886#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 989887#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 989222#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 989223#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 989733#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 989734#L481 assume !(1 == ~t2_pc~0); 989503#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 989502#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 989892#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 989600#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 989601#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 989706#L500 assume !(1 == ~t3_pc~0); 990252#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 990215#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 990166#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 990167#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 989138#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 989139#L519 assume !(1 == ~t4_pc~0); 989947#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 989704#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 989705#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 989548#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 989549#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 989308#L538 assume !(1 == ~t5_pc~0); 989309#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 989212#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 989213#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 989486#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 989487#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 990083#L557 assume !(1 == ~t6_pc~0); 989524#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 989525#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 989419#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 989420#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 989550#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 990336#L576 assume !(1 == ~t7_pc~0); 989512#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 989513#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 989784#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 989785#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 990147#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 989641#L595 assume !(1 == ~t8_pc~0); 989642#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 990168#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 990169#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 989990#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 989991#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 989435#L614 assume !(1 == ~t9_pc~0); 989436#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 989332#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 989333#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 989516#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 989602#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 989603#L1025 assume !(1 == ~M_E~0); 989878#L1025-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 989938#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 990077#L1035-1 assume !(1 == ~T3_E~0); 989596#L1040-1 assume !(1 == ~T4_E~0); 989597#L1045-1 assume !(1 == ~T5_E~0); 1077162#L1050-1 assume !(1 == ~T6_E~0); 1077161#L1055-1 assume !(1 == ~T7_E~0); 1077160#L1060-1 assume !(1 == ~T8_E~0); 1077159#L1065-1 assume !(1 == ~T9_E~0); 1077158#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1077157#L1075-1 assume !(1 == ~E_2~0); 1077156#L1080-1 assume !(1 == ~E_3~0); 990381#L1085-1 assume !(1 == ~E_4~0); 1077155#L1090-1 assume !(1 == ~E_5~0); 1077144#L1095-1 assume !(1 == ~E_6~0); 1077142#L1100-1 assume !(1 == ~E_7~0); 1077140#L1105-1 assume !(1 == ~E_8~0); 1077137#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 1076128#L1115-1 assume { :end_inline_reset_delta_events } true; 1076126#L1396-2 [2021-12-06 17:45:12,428 INFO L793 eck$LassoCheckResult]: Loop: 1076126#L1396-2 assume !false; 1076124#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1076118#L897 assume !false; 1076116#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1076112#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1076101#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1076098#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1076095#L766 assume !(0 != eval_~tmp~0#1); 1076096#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1076406#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1076404#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1076402#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1076400#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1076398#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1076396#L937-3 assume !(0 == ~T4_E~0); 1076394#L942-3 assume !(0 == ~T5_E~0); 1076392#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1076390#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1076388#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1076386#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1076384#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1076382#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1076380#L977-3 assume !(0 == ~E_3~0); 1076378#L982-3 assume !(0 == ~E_4~0); 1076376#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1076374#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1076372#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1076370#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1076368#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1076365#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1076363#L443-30 assume !(1 == ~m_pc~0); 1076361#L443-32 is_master_triggered_~__retres1~0#1 := 0; 1076359#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1076357#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1076355#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1076353#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1076351#L462-30 assume !(1 == ~t1_pc~0); 1076349#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1076347#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1076345#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1076343#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1076341#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1076339#L481-30 assume 1 == ~t2_pc~0; 1076336#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1076334#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1076332#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1076328#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1076326#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1076324#L500-30 assume !(1 == ~t3_pc~0); 1076322#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1076319#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1076317#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1076315#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1076313#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1076311#L519-30 assume !(1 == ~t4_pc~0); 1076309#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1076307#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1076305#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1076303#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1076300#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1076298#L538-30 assume !(1 == ~t5_pc~0); 1076294#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1076292#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1076290#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1076288#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 1076285#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1076283#L557-30 assume !(1 == ~t6_pc~0); 1076281#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1076279#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1076277#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1076275#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 1076272#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1076270#L576-30 assume 1 == ~t7_pc~0; 1076267#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1076265#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1076263#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1076261#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1076259#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1076257#L595-30 assume !(1 == ~t8_pc~0); 1076255#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1076254#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1076253#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1076252#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1076251#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1076248#L614-30 assume 1 == ~t9_pc~0; 1076245#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1076242#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1076241#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1076239#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1076237#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1076235#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1076233#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1076229#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1076227#L1035-3 assume !(1 == ~T3_E~0); 1076225#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1076221#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1076219#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1076217#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1076215#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1076213#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1076211#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1076208#L1075-3 assume !(1 == ~E_2~0); 1076206#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1076202#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1076200#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1076198#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1076196#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1076194#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1076192#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1076190#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1076167#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1076165#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1076162#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1076159#L1415 assume !(0 == start_simulation_~tmp~3#1); 1076156#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1076150#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1076140#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1076138#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1076135#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1076133#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1076131#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1076129#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 1076126#L1396-2 [2021-12-06 17:45:12,429 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:12,429 INFO L85 PathProgramCache]: Analyzing trace with hash 1169441332, now seen corresponding path program 1 times [2021-12-06 17:45:12,429 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:12,429 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1512394752] [2021-12-06 17:45:12,429 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:12,429 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:12,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:45:12,611 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:45:12,611 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:45:12,611 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1512394752] [2021-12-06 17:45:12,611 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1512394752] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:45:12,611 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:45:12,611 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 17:45:12,611 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1926337814] [2021-12-06 17:45:12,611 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:45:12,612 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:45:12,612 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:12,612 INFO L85 PathProgramCache]: Analyzing trace with hash 2052625800, now seen corresponding path program 1 times [2021-12-06 17:45:12,612 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:12,612 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1908141442] [2021-12-06 17:45:12,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:12,612 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:12,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:45:12,636 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:45:12,636 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:45:12,636 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1908141442] [2021-12-06 17:45:12,636 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1908141442] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:45:12,636 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:45:12,636 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:45:12,636 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2091392197] [2021-12-06 17:45:12,637 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:45:12,637 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:45:12,637 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:45:12,637 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:45:12,637 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:45:12,637 INFO L87 Difference]: Start difference. First operand 280658 states and 400842 transitions. cyclomatic complexity: 120312 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 2 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:13,327 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:45:13,328 INFO L93 Difference]: Finished difference Result 280647 states and 399847 transitions. [2021-12-06 17:45:13,328 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:45:13,328 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 280647 states and 399847 transitions. [2021-12-06 17:45:14,387 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 279072 [2021-12-06 17:45:14,988 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 280647 states to 280647 states and 399847 transitions. [2021-12-06 17:45:14,988 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 280647 [2021-12-06 17:45:15,093 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 280647 [2021-12-06 17:45:15,093 INFO L73 IsDeterministic]: Start isDeterministic. Operand 280647 states and 399847 transitions. [2021-12-06 17:45:15,179 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:45:15,180 INFO L681 BuchiCegarLoop]: Abstraction has 280647 states and 399847 transitions. [2021-12-06 17:45:15,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 280647 states and 399847 transitions. [2021-12-06 17:45:16,372 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 280647 to 74096. [2021-12-06 17:45:16,418 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 74096 states, 74096 states have (on average 1.419104944936299) internal successors, (105150), 74095 states have internal predecessors, (105150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:16,562 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74096 states to 74096 states and 105150 transitions. [2021-12-06 17:45:16,562 INFO L704 BuchiCegarLoop]: Abstraction has 74096 states and 105150 transitions. [2021-12-06 17:45:16,562 INFO L587 BuchiCegarLoop]: Abstraction has 74096 states and 105150 transitions. [2021-12-06 17:45:16,562 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-06 17:45:16,562 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 74096 states and 105150 transitions. [2021-12-06 17:45:16,871 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 73618 [2021-12-06 17:45:16,871 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:45:16,871 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:45:16,872 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:16,872 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:16,872 INFO L791 eck$LassoCheckResult]: Stem: 1551340#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 1551341#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1550881#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1550882#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1551517#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 1551518#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1551496#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1551281#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1551282#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1551064#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1551065#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1551607#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1551477#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1551135#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1550887#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1550888#L922 assume !(0 == ~M_E~0); 1551683#L922-2 assume !(0 == ~T1_E~0); 1551684#L927-1 assume !(0 == ~T2_E~0); 1551349#L932-1 assume !(0 == ~T3_E~0); 1551214#L937-1 assume !(0 == ~T4_E~0); 1551215#L942-1 assume !(0 == ~T5_E~0); 1551280#L947-1 assume !(0 == ~T6_E~0); 1551353#L952-1 assume !(0 == ~T7_E~0); 1551354#L957-1 assume !(0 == ~T8_E~0); 1551423#L962-1 assume !(0 == ~T9_E~0); 1551186#L967-1 assume !(0 == ~E_1~0); 1551187#L972-1 assume !(0 == ~E_2~0); 1551502#L977-1 assume !(0 == ~E_3~0); 1551503#L982-1 assume !(0 == ~E_4~0); 1550652#L987-1 assume !(0 == ~E_5~0); 1550653#L992-1 assume !(0 == ~E_6~0); 1550661#L997-1 assume !(0 == ~E_7~0); 1551108#L1002-1 assume !(0 == ~E_8~0); 1551090#L1007-1 assume !(0 == ~E_9~0); 1550448#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1550449#L443 assume !(1 == ~m_pc~0); 1551374#L443-2 is_master_triggered_~__retres1~0#1 := 0; 1551360#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1551361#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1550820#L1140 assume !(0 != activate_threads_~tmp~1#1); 1550564#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1550565#L462 assume !(1 == ~t1_pc~0); 1551204#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1551205#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1550534#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1550535#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 1551045#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1551046#L481 assume !(1 == ~t2_pc~0); 1550815#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1550814#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1551211#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1550911#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 1550912#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1551019#L500 assume !(1 == ~t3_pc~0); 1551569#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1551532#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1551487#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1551488#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 1550450#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1550451#L519 assume !(1 == ~t4_pc~0); 1551263#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1551017#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1551018#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1550861#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 1550862#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1550620#L538 assume !(1 == ~t5_pc~0); 1550621#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1550524#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1550525#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1550797#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 1550798#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1551407#L557 assume !(1 == ~t6_pc~0); 1550836#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1550837#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1550731#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1550732#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 1550863#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1551653#L576 assume !(1 == ~t7_pc~0); 1550824#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1550825#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1551094#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1551095#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 1551469#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1550953#L595 assume !(1 == ~t8_pc~0); 1550954#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1551489#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1551490#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1551309#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 1551310#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1550747#L614 assume !(1 == ~t9_pc~0); 1550748#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1550644#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1550645#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1550828#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 1550913#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1550914#L1025 assume !(1 == ~M_E~0); 1551196#L1025-2 assume !(1 == ~T1_E~0); 1551255#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1551402#L1035-1 assume !(1 == ~T3_E~0); 1550907#L1040-1 assume !(1 == ~T4_E~0); 1550908#L1045-1 assume !(1 == ~T5_E~0); 1550810#L1050-1 assume !(1 == ~T6_E~0); 1550811#L1055-1 assume !(1 == ~T7_E~0); 1550629#L1060-1 assume !(1 == ~T8_E~0); 1550630#L1065-1 assume !(1 == ~T9_E~0); 1550692#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1551355#L1075-1 assume !(1 == ~E_2~0); 1551356#L1080-1 assume !(1 == ~E_3~0); 1551344#L1085-1 assume !(1 == ~E_4~0); 1551345#L1090-1 assume !(1 == ~E_5~0); 1551598#L1095-1 assume !(1 == ~E_6~0); 1551386#L1100-1 assume !(1 == ~E_7~0); 1551387#L1105-1 assume !(1 == ~E_8~0); 1550602#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 1550603#L1115-1 assume { :end_inline_reset_delta_events } true; 1550965#L1396-2 [2021-12-06 17:45:16,872 INFO L793 eck$LassoCheckResult]: Loop: 1550965#L1396-2 assume !false; 1589080#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1589074#L897 assume !false; 1589072#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1589069#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1589030#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1589020#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1589014#L766 assume !(0 != eval_~tmp~0#1); 1589015#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1589346#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1589343#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1589341#L922-5 assume !(0 == ~T1_E~0); 1589339#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1589337#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1589335#L937-3 assume !(0 == ~T4_E~0); 1589333#L942-3 assume !(0 == ~T5_E~0); 1589331#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1589329#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1589327#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1589324#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1589322#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1589320#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1589318#L977-3 assume !(0 == ~E_3~0); 1589316#L982-3 assume !(0 == ~E_4~0); 1589314#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1589312#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1589310#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1589308#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1589306#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1589304#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1589302#L443-30 assume !(1 == ~m_pc~0); 1589299#L443-32 is_master_triggered_~__retres1~0#1 := 0; 1589297#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1589295#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1589293#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1589291#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1589289#L462-30 assume !(1 == ~t1_pc~0); 1589287#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1589285#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1589283#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1589281#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1589279#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1589277#L481-30 assume 1 == ~t2_pc~0; 1589274#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1589272#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1589270#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1589268#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1589266#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1589264#L500-30 assume !(1 == ~t3_pc~0); 1589262#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1589260#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1589258#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1589256#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1589254#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1589252#L519-30 assume !(1 == ~t4_pc~0); 1589251#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1589250#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1589249#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1589248#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1589247#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1589246#L538-30 assume !(1 == ~t5_pc~0); 1589242#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1589241#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1589240#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1589238#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 1589236#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1589235#L557-30 assume !(1 == ~t6_pc~0); 1589234#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1589233#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1589231#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1589229#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 1589227#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1589225#L576-30 assume 1 == ~t7_pc~0; 1589222#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1589220#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1589218#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1589216#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1589214#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1589212#L595-30 assume !(1 == ~t8_pc~0); 1589210#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1589206#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1589204#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1589202#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1589200#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1589197#L614-30 assume 1 == ~t9_pc~0; 1589194#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1589192#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1589190#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1589188#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1589186#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1589184#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1589182#L1025-5 assume !(1 == ~T1_E~0); 1589180#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1589177#L1035-3 assume !(1 == ~T3_E~0); 1589175#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1589173#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1589171#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1589169#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1589167#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1589165#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1589163#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1589161#L1075-3 assume !(1 == ~E_2~0); 1589159#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1589157#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1589155#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1589152#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1589150#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1589148#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1589146#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1589144#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1589122#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1589120#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1589117#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1589114#L1415 assume !(0 == start_simulation_~tmp~3#1); 1589111#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1589104#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1589094#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1589092#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1589090#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1589088#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1589086#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1589083#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 1550965#L1396-2 [2021-12-06 17:45:16,872 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:16,873 INFO L85 PathProgramCache]: Analyzing trace with hash -519502410, now seen corresponding path program 1 times [2021-12-06 17:45:16,873 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:16,873 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [295302662] [2021-12-06 17:45:16,873 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:16,873 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:16,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:45:16,898 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:45:16,898 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:45:16,898 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [295302662] [2021-12-06 17:45:16,898 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [295302662] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:45:16,898 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:45:16,898 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 17:45:16,898 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2018841286] [2021-12-06 17:45:16,898 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:45:16,899 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:45:16,899 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:16,899 INFO L85 PathProgramCache]: Analyzing trace with hash 1106862732, now seen corresponding path program 1 times [2021-12-06 17:45:16,899 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:16,899 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [641597294] [2021-12-06 17:45:16,899 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:16,899 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:16,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:45:16,919 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:45:16,919 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:45:16,919 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [641597294] [2021-12-06 17:45:16,919 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [641597294] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:45:16,919 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:45:16,919 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:45:16,919 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2041452697] [2021-12-06 17:45:16,919 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:45:16,920 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:45:16,920 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:45:16,920 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:45:16,920 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:45:16,920 INFO L87 Difference]: Start difference. First operand 74096 states and 105150 transitions. cyclomatic complexity: 31086 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 2 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:17,088 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:45:17,088 INFO L93 Difference]: Finished difference Result 74096 states and 104824 transitions. [2021-12-06 17:45:17,089 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:45:17,089 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 74096 states and 104824 transitions. [2021-12-06 17:45:17,327 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 73618 [2021-12-06 17:45:17,481 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 74096 states to 74096 states and 104824 transitions. [2021-12-06 17:45:17,481 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 74096 [2021-12-06 17:45:17,517 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 74096 [2021-12-06 17:45:17,517 INFO L73 IsDeterministic]: Start isDeterministic. Operand 74096 states and 104824 transitions. [2021-12-06 17:45:17,549 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:45:17,549 INFO L681 BuchiCegarLoop]: Abstraction has 74096 states and 104824 transitions. [2021-12-06 17:45:17,581 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74096 states and 104824 transitions. [2021-12-06 17:45:18,064 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74096 to 74096. [2021-12-06 17:45:18,110 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 74096 states, 74096 states have (on average 1.414705247246815) internal successors, (104824), 74095 states have internal predecessors, (104824), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:18,228 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74096 states to 74096 states and 104824 transitions. [2021-12-06 17:45:18,228 INFO L704 BuchiCegarLoop]: Abstraction has 74096 states and 104824 transitions. [2021-12-06 17:45:18,228 INFO L587 BuchiCegarLoop]: Abstraction has 74096 states and 104824 transitions. [2021-12-06 17:45:18,228 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-06 17:45:18,228 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 74096 states and 104824 transitions. [2021-12-06 17:45:18,402 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 73618 [2021-12-06 17:45:18,402 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:45:18,403 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:45:18,404 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:18,404 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:18,404 INFO L791 eck$LassoCheckResult]: Stem: 1699516#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 1699517#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1699080#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1699081#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1699703#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 1699704#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1699684#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1699460#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1699461#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1699255#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1699256#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1699786#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1699662#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1699317#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1699086#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1699087#L922 assume !(0 == ~M_E~0); 1699870#L922-2 assume !(0 == ~T1_E~0); 1699871#L927-1 assume !(0 == ~T2_E~0); 1699525#L932-1 assume !(0 == ~T3_E~0); 1699396#L937-1 assume !(0 == ~T4_E~0); 1699397#L942-1 assume !(0 == ~T5_E~0); 1699459#L947-1 assume !(0 == ~T6_E~0); 1699529#L952-1 assume !(0 == ~T7_E~0); 1699530#L957-1 assume !(0 == ~T8_E~0); 1699602#L962-1 assume !(0 == ~T9_E~0); 1699368#L967-1 assume !(0 == ~E_1~0); 1699369#L972-1 assume !(0 == ~E_2~0); 1699690#L977-1 assume !(0 == ~E_3~0); 1699691#L982-1 assume !(0 == ~E_4~0); 1698849#L987-1 assume !(0 == ~E_5~0); 1698850#L992-1 assume !(0 == ~E_6~0); 1698858#L997-1 assume !(0 == ~E_7~0); 1699290#L1002-1 assume !(0 == ~E_8~0); 1699277#L1007-1 assume !(0 == ~E_9~0); 1698647#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1698648#L443 assume !(1 == ~m_pc~0); 1699550#L443-2 is_master_triggered_~__retres1~0#1 := 0; 1699536#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1699537#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1699016#L1140 assume !(0 != activate_threads_~tmp~1#1); 1698763#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1698764#L462 assume !(1 == ~t1_pc~0); 1699387#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1699388#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1698733#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1698734#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 1699235#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1699236#L481 assume !(1 == ~t2_pc~0); 1699011#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1699010#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1699393#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1699109#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 1699110#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1699209#L500 assume !(1 == ~t3_pc~0); 1699754#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1699719#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1699674#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1699675#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 1698649#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1698650#L519 assume !(1 == ~t4_pc~0); 1699443#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1699207#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1699208#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1699058#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 1699059#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1698817#L538 assume !(1 == ~t5_pc~0); 1698818#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1698723#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1698724#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1698994#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 1698995#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1699583#L557 assume !(1 == ~t6_pc~0); 1699033#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1699034#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1698928#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1698929#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 1699060#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1699835#L576 assume !(1 == ~t7_pc~0); 1699020#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1699021#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1699280#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1699281#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 1699652#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1699150#L595 assume !(1 == ~t8_pc~0); 1699151#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1699676#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1699677#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1699489#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 1699490#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1698944#L614 assume !(1 == ~t9_pc~0); 1698945#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1698841#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1698842#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1699024#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 1699111#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1699112#L1025 assume !(1 == ~M_E~0); 1699378#L1025-2 assume !(1 == ~T1_E~0); 1699436#L1030-1 assume !(1 == ~T2_E~0); 1699578#L1035-1 assume !(1 == ~T3_E~0); 1699105#L1040-1 assume !(1 == ~T4_E~0); 1699106#L1045-1 assume !(1 == ~T5_E~0); 1699006#L1050-1 assume !(1 == ~T6_E~0); 1699007#L1055-1 assume !(1 == ~T7_E~0); 1698826#L1060-1 assume !(1 == ~T8_E~0); 1698827#L1065-1 assume !(1 == ~T9_E~0); 1698889#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1699531#L1075-1 assume !(1 == ~E_2~0); 1699532#L1080-1 assume !(1 == ~E_3~0); 1699520#L1085-1 assume !(1 == ~E_4~0); 1699521#L1090-1 assume !(1 == ~E_5~0); 1699779#L1095-1 assume !(1 == ~E_6~0); 1699561#L1100-1 assume !(1 == ~E_7~0); 1699562#L1105-1 assume !(1 == ~E_8~0); 1698799#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 1698800#L1115-1 assume { :end_inline_reset_delta_events } true; 1699162#L1396-2 [2021-12-06 17:45:18,405 INFO L793 eck$LassoCheckResult]: Loop: 1699162#L1396-2 assume !false; 1726809#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1726804#L897 assume !false; 1726802#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1726799#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1726788#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1726786#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1726783#L766 assume !(0 != eval_~tmp~0#1); 1726784#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1727080#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1727078#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1727076#L922-5 assume !(0 == ~T1_E~0); 1727074#L927-3 assume !(0 == ~T2_E~0); 1727072#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1727070#L937-3 assume !(0 == ~T4_E~0); 1727068#L942-3 assume !(0 == ~T5_E~0); 1727066#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1727064#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1727062#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1727060#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1727057#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1727055#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1727053#L977-3 assume !(0 == ~E_3~0); 1727051#L982-3 assume !(0 == ~E_4~0); 1727049#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1727047#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1727045#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1727043#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1727041#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1727039#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1727037#L443-30 assume !(1 == ~m_pc~0); 1727035#L443-32 is_master_triggered_~__retres1~0#1 := 0; 1727033#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1727031#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1727029#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1727027#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1727025#L462-30 assume !(1 == ~t1_pc~0); 1727023#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1727020#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1727018#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1727016#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1727013#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1727011#L481-30 assume 1 == ~t2_pc~0; 1727008#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1727006#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1727004#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1727002#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1727000#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1726998#L500-30 assume !(1 == ~t3_pc~0); 1726996#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1726993#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1726991#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1726989#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1726987#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1726985#L519-30 assume !(1 == ~t4_pc~0); 1726983#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1726981#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1726979#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1726977#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1726975#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1726973#L538-30 assume 1 == ~t5_pc~0; 1726971#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1726972#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1727086#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1726961#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1726959#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1726957#L557-30 assume !(1 == ~t6_pc~0); 1726955#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1726953#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1726951#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1726949#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 1726947#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1726945#L576-30 assume 1 == ~t7_pc~0; 1726942#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1726940#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1726938#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1726936#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1726934#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1726932#L595-30 assume !(1 == ~t8_pc~0); 1726930#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1726928#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1726926#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1726924#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1726922#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1726920#L614-30 assume !(1 == ~t9_pc~0); 1726918#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 1726916#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1726915#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1726914#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1726913#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1726911#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1726909#L1025-5 assume !(1 == ~T1_E~0); 1726907#L1030-3 assume !(1 == ~T2_E~0); 1726905#L1035-3 assume !(1 == ~T3_E~0); 1726903#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1726901#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1726899#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1726897#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1726895#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1726893#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1726891#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1726889#L1075-3 assume !(1 == ~E_2~0); 1726887#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1726884#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1726882#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1726880#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1726878#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1726876#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1726874#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1726872#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1726852#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1726848#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1726846#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1726843#L1415 assume !(0 == start_simulation_~tmp~3#1); 1726840#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1726833#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1726823#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1726821#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1726819#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1726817#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1726815#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1726812#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 1699162#L1396-2 [2021-12-06 17:45:18,405 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:18,405 INFO L85 PathProgramCache]: Analyzing trace with hash 1781320180, now seen corresponding path program 1 times [2021-12-06 17:45:18,405 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:18,405 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [745733626] [2021-12-06 17:45:18,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:18,406 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:18,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:45:18,437 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:45:18,437 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:45:18,437 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [745733626] [2021-12-06 17:45:18,437 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [745733626] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:45:18,437 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:45:18,437 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:45:18,437 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2075440380] [2021-12-06 17:45:18,438 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:45:18,438 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:45:18,438 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:18,438 INFO L85 PathProgramCache]: Analyzing trace with hash 1562977226, now seen corresponding path program 1 times [2021-12-06 17:45:18,438 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:18,438 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1625257218] [2021-12-06 17:45:18,439 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:18,439 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:18,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:45:18,460 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:45:18,460 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:45:18,460 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1625257218] [2021-12-06 17:45:18,460 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1625257218] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:45:18,460 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:45:18,460 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:45:18,460 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1385638442] [2021-12-06 17:45:18,460 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:45:18,461 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:45:18,461 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:45:18,461 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 17:45:18,461 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 17:45:18,461 INFO L87 Difference]: Start difference. First operand 74096 states and 104824 transitions. cyclomatic complexity: 30760 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:18,977 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:45:18,977 INFO L93 Difference]: Finished difference Result 156450 states and 220615 transitions. [2021-12-06 17:45:18,977 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 17:45:18,978 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 156450 states and 220615 transitions. [2021-12-06 17:45:19,468 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 155484 [2021-12-06 17:45:19,942 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 156450 states to 156450 states and 220615 transitions. [2021-12-06 17:45:19,942 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 156450 [2021-12-06 17:45:19,982 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 156450 [2021-12-06 17:45:19,982 INFO L73 IsDeterministic]: Start isDeterministic. Operand 156450 states and 220615 transitions. [2021-12-06 17:45:20,029 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:45:20,029 INFO L681 BuchiCegarLoop]: Abstraction has 156450 states and 220615 transitions. [2021-12-06 17:45:20,077 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 156450 states and 220615 transitions. [2021-12-06 17:45:20,847 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 156450 to 83791. [2021-12-06 17:45:20,901 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 83791 states, 83791 states have (on average 1.4109868601639795) internal successors, (118228), 83790 states have internal predecessors, (118228), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:21,175 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83791 states to 83791 states and 118228 transitions. [2021-12-06 17:45:21,176 INFO L704 BuchiCegarLoop]: Abstraction has 83791 states and 118228 transitions. [2021-12-06 17:45:21,176 INFO L587 BuchiCegarLoop]: Abstraction has 83791 states and 118228 transitions. [2021-12-06 17:45:21,176 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-06 17:45:21,176 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 83791 states and 118228 transitions. [2021-12-06 17:45:21,333 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 83226 [2021-12-06 17:45:21,333 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:45:21,334 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:45:21,335 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:21,335 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:21,335 INFO L791 eck$LassoCheckResult]: Stem: 1930079#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 1930080#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1929636#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1929637#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1930266#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 1930267#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1930245#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1930019#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1930020#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1929810#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1929811#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1930351#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1930226#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1929874#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1929642#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1929643#L922 assume !(0 == ~M_E~0); 1930435#L922-2 assume !(0 == ~T1_E~0); 1930436#L927-1 assume !(0 == ~T2_E~0); 1930087#L932-1 assume !(0 == ~T3_E~0); 1929951#L937-1 assume !(0 == ~T4_E~0); 1929952#L942-1 assume !(0 == ~T5_E~0); 1930018#L947-1 assume !(0 == ~T6_E~0); 1930091#L952-1 assume !(0 == ~T7_E~0); 1930092#L957-1 assume !(0 == ~T8_E~0); 1930171#L962-1 assume !(0 == ~T9_E~0); 1929923#L967-1 assume 0 == ~E_1~0;~E_1~0 := 1; 1929924#L972-1 assume !(0 == ~E_2~0); 1930250#L977-1 assume !(0 == ~E_3~0); 1930251#L982-1 assume !(0 == ~E_4~0); 1929407#L987-1 assume !(0 == ~E_5~0); 1929408#L992-1 assume !(0 == ~E_6~0); 1929850#L997-1 assume !(0 == ~E_7~0); 1929851#L1002-1 assume !(0 == ~E_8~0); 1930371#L1007-1 assume !(0 == ~E_9~0); 1929203#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1929204#L443 assume !(1 == ~m_pc~0); 1930369#L443-2 is_master_triggered_~__retres1~0#1 := 0; 1930097#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1930098#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1929573#L1140 assume !(0 != activate_threads_~tmp~1#1); 1929319#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1929320#L462 assume !(1 == ~t1_pc~0); 1929943#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1929944#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1930410#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1930119#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 1930120#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1930527#L481 assume !(1 == ~t2_pc~0); 1930525#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1930074#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1929948#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1929663#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 1929664#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1930459#L500 assume !(1 == ~t3_pc~0); 1930317#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1930283#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1930236#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1930237#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 1929208#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1929209#L519 assume !(1 == ~t4_pc~0); 1930001#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1930002#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1930125#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1929617#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 1929618#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1929373#L538 assume !(1 == ~t5_pc~0); 1929374#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1929279#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1929280#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1929551#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 1929552#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1930155#L557 assume !(1 == ~t6_pc~0); 1930501#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1930500#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1930499#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1930498#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 1930497#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1930444#L576 assume !(1 == ~t7_pc~0); 1929577#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1929578#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1929838#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1929839#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 1930492#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1930491#L595 assume !(1 == ~t8_pc~0); 1930490#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1930489#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1930488#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1930487#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 1930486#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1930485#L614 assume !(1 == ~t9_pc~0); 1930483#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1930482#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1930481#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1930480#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 1930479#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1930478#L1025 assume !(1 == ~M_E~0); 1930477#L1025-2 assume !(1 == ~T1_E~0); 1930476#L1030-1 assume !(1 == ~T2_E~0); 1930475#L1035-1 assume !(1 == ~T3_E~0); 1930474#L1040-1 assume !(1 == ~T4_E~0); 1930473#L1045-1 assume !(1 == ~T5_E~0); 1930472#L1050-1 assume !(1 == ~T6_E~0); 1930471#L1055-1 assume !(1 == ~T7_E~0); 1930470#L1060-1 assume !(1 == ~T8_E~0); 1930469#L1065-1 assume !(1 == ~T9_E~0); 1930468#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1930093#L1075-1 assume !(1 == ~E_2~0); 1930094#L1080-1 assume !(1 == ~E_3~0); 1930082#L1085-1 assume !(1 == ~E_4~0); 1930083#L1090-1 assume !(1 == ~E_5~0); 1930344#L1095-1 assume !(1 == ~E_6~0); 1930123#L1100-1 assume !(1 == ~E_7~0); 1930124#L1105-1 assume !(1 == ~E_8~0); 1929355#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 1929356#L1115-1 assume { :end_inline_reset_delta_events } true; 1929716#L1396-2 [2021-12-06 17:45:21,335 INFO L793 eck$LassoCheckResult]: Loop: 1929716#L1396-2 assume !false; 1989557#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1989550#L897 assume !false; 1989548#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1989545#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1989534#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1989532#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1989529#L766 assume !(0 != eval_~tmp~0#1); 1989530#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1989841#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1989840#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1989839#L922-5 assume !(0 == ~T1_E~0); 1989837#L927-3 assume !(0 == ~T2_E~0); 1989835#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1989833#L937-3 assume !(0 == ~T4_E~0); 1989831#L942-3 assume !(0 == ~T5_E~0); 1989829#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1989827#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1989825#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1989823#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1989820#L967-3 assume !(0 == ~E_1~0); 1989821#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2000707#L977-3 assume !(0 == ~E_3~0); 2000698#L982-3 assume !(0 == ~E_4~0); 2000689#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2000662#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2000661#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2000660#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2000659#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2000658#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2000657#L443-30 assume !(1 == ~m_pc~0); 2000656#L443-32 is_master_triggered_~__retres1~0#1 := 0; 2000655#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2000654#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2000653#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2000652#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2000641#L462-30 assume !(1 == ~t1_pc~0); 2000639#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 2000637#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2000634#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2000633#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2000620#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2000619#L481-30 assume !(1 == ~t2_pc~0); 2000618#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 2000616#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2000615#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2000614#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2000613#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2000612#L500-30 assume !(1 == ~t3_pc~0); 2000611#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 2000610#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2000609#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2000608#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2000607#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2000606#L519-30 assume !(1 == ~t4_pc~0); 2000604#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2000603#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2000602#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2000601#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2000600#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2000598#L538-30 assume 1 == ~t5_pc~0; 2000596#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2000597#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2000605#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2000586#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2000584#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2000582#L557-30 assume !(1 == ~t6_pc~0); 2000580#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 2000578#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2000576#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2000574#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 2000572#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2000570#L576-30 assume !(1 == ~t7_pc~0); 2000568#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 2000564#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2000562#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2000560#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2000558#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2000556#L595-30 assume !(1 == ~t8_pc~0); 2000554#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2000519#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2000518#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2000517#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2000515#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2000514#L614-30 assume 1 == ~t9_pc~0; 2000511#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2000507#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2000505#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2000503#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2000501#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2000498#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2000496#L1025-5 assume !(1 == ~T1_E~0); 2000495#L1030-3 assume !(1 == ~T2_E~0); 2000494#L1035-3 assume !(1 == ~T3_E~0); 2000492#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2000490#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2000489#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2000488#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2000486#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2000484#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1989733#L1070-3 assume !(1 == ~E_1~0); 1989730#L1075-3 assume !(1 == ~E_2~0); 1989728#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1989726#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1989724#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1989721#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1989719#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1989717#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1989715#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1989713#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1989596#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1989594#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1989592#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1989590#L1415 assume !(0 == start_simulation_~tmp~3#1); 1989588#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1989580#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1989570#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1989568#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1989566#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1989564#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1989562#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1989560#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 1929716#L1396-2 [2021-12-06 17:45:21,336 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:21,336 INFO L85 PathProgramCache]: Analyzing trace with hash -95743050, now seen corresponding path program 1 times [2021-12-06 17:45:21,336 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:21,336 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [965784895] [2021-12-06 17:45:21,336 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:21,336 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:21,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:45:21,357 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:45:21,358 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:45:21,358 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [965784895] [2021-12-06 17:45:21,358 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [965784895] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:45:21,358 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:45:21,358 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:45:21,358 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [583026107] [2021-12-06 17:45:21,358 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:45:21,358 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:45:21,359 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:21,359 INFO L85 PathProgramCache]: Analyzing trace with hash -1321606555, now seen corresponding path program 1 times [2021-12-06 17:45:21,359 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:21,359 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1520504268] [2021-12-06 17:45:21,359 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:21,359 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:21,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:45:21,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:45:21,378 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:45:21,378 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1520504268] [2021-12-06 17:45:21,378 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1520504268] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:45:21,378 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:45:21,378 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:45:21,378 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1986200481] [2021-12-06 17:45:21,378 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:45:21,379 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:45:21,379 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:45:21,379 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 17:45:21,379 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 17:45:21,379 INFO L87 Difference]: Start difference. First operand 83791 states and 118228 transitions. cyclomatic complexity: 34469 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:21,644 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:45:21,645 INFO L93 Difference]: Finished difference Result 96992 states and 136766 transitions. [2021-12-06 17:45:21,645 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 17:45:21,645 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 96992 states and 136766 transitions. [2021-12-06 17:45:21,949 INFO L131 ngComponentsAnalysis]: Automaton has 36 accepting balls. 96386 [2021-12-06 17:45:22,281 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 96992 states to 96992 states and 136766 transitions. [2021-12-06 17:45:22,282 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 96992 [2021-12-06 17:45:22,315 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 96992 [2021-12-06 17:45:22,316 INFO L73 IsDeterministic]: Start isDeterministic. Operand 96992 states and 136766 transitions. [2021-12-06 17:45:22,347 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:45:22,347 INFO L681 BuchiCegarLoop]: Abstraction has 96992 states and 136766 transitions. [2021-12-06 17:45:22,380 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96992 states and 136766 transitions. [2021-12-06 17:45:22,877 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96992 to 74096. [2021-12-06 17:45:22,922 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 74096 states, 74096 states have (on average 1.4065806521269704) internal successors, (104222), 74095 states have internal predecessors, (104222), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:23,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74096 states to 74096 states and 104222 transitions. [2021-12-06 17:45:23,179 INFO L704 BuchiCegarLoop]: Abstraction has 74096 states and 104222 transitions. [2021-12-06 17:45:23,179 INFO L587 BuchiCegarLoop]: Abstraction has 74096 states and 104222 transitions. [2021-12-06 17:45:23,179 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-06 17:45:23,179 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 74096 states and 104222 transitions. [2021-12-06 17:45:23,297 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 73618 [2021-12-06 17:45:23,297 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:45:23,297 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:45:23,298 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:23,298 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:23,298 INFO L791 eck$LassoCheckResult]: Stem: 2110861#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 2110862#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 2110425#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2110426#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2111065#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 2111066#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2111038#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2110805#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2110806#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2110599#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2110600#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2111157#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2111012#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2110669#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2110431#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2110432#L922 assume !(0 == ~M_E~0); 2111240#L922-2 assume !(0 == ~T1_E~0); 2111241#L927-1 assume !(0 == ~T2_E~0); 2110870#L932-1 assume !(0 == ~T3_E~0); 2110744#L937-1 assume !(0 == ~T4_E~0); 2110745#L942-1 assume !(0 == ~T5_E~0); 2110804#L947-1 assume !(0 == ~T6_E~0); 2110875#L952-1 assume !(0 == ~T7_E~0); 2110876#L957-1 assume !(0 == ~T8_E~0); 2110957#L962-1 assume !(0 == ~T9_E~0); 2110719#L967-1 assume !(0 == ~E_1~0); 2110720#L972-1 assume !(0 == ~E_2~0); 2111049#L977-1 assume !(0 == ~E_3~0); 2111050#L982-1 assume !(0 == ~E_4~0); 2110198#L987-1 assume !(0 == ~E_5~0); 2110199#L992-1 assume !(0 == ~E_6~0); 2110207#L997-1 assume !(0 == ~E_7~0); 2110644#L1002-1 assume !(0 == ~E_8~0); 2110625#L1007-1 assume !(0 == ~E_9~0); 2109996#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2109997#L443 assume !(1 == ~m_pc~0); 2110896#L443-2 is_master_triggered_~__retres1~0#1 := 0; 2110885#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2110886#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2110363#L1140 assume !(0 != activate_threads_~tmp~1#1); 2110112#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2110113#L462 assume !(1 == ~t1_pc~0); 2110736#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2110737#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2110082#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2110083#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 2110581#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2110582#L481 assume !(1 == ~t2_pc~0); 2110358#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2110357#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2110741#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2110453#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 2110454#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2110554#L500 assume !(1 == ~t3_pc~0); 2111117#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2111082#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2111026#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2111027#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 2109998#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2109999#L519 assume !(1 == ~t4_pc~0); 2110788#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2110552#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2110553#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2110408#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 2110409#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2110166#L538 assume !(1 == ~t5_pc~0); 2110167#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2110072#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2110073#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2110340#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 2110341#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2110940#L557 assume !(1 == ~t6_pc~0); 2110380#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2110381#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2110280#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2110281#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 2110407#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2111205#L576 assume !(1 == ~t7_pc~0); 2110367#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2110368#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2110629#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2110630#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 2111003#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2110494#L595 assume !(1 == ~t8_pc~0); 2110495#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2111028#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2111029#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2110832#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 2110833#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2110291#L614 assume !(1 == ~t9_pc~0); 2110292#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2110191#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2110192#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2110371#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 2110455#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2110456#L1025 assume !(1 == ~M_E~0); 2110729#L1025-2 assume !(1 == ~T1_E~0); 2110781#L1030-1 assume !(1 == ~T2_E~0); 2110928#L1035-1 assume !(1 == ~T3_E~0); 2110450#L1040-1 assume !(1 == ~T4_E~0); 2110451#L1045-1 assume !(1 == ~T5_E~0); 2110352#L1050-1 assume !(1 == ~T6_E~0); 2110353#L1055-1 assume !(1 == ~T7_E~0); 2110175#L1060-1 assume !(1 == ~T8_E~0); 2110176#L1065-1 assume !(1 == ~T9_E~0); 2110238#L1070-1 assume !(1 == ~E_1~0); 2110877#L1075-1 assume !(1 == ~E_2~0); 2110878#L1080-1 assume !(1 == ~E_3~0); 2110865#L1085-1 assume !(1 == ~E_4~0); 2110866#L1090-1 assume !(1 == ~E_5~0); 2111150#L1095-1 assume !(1 == ~E_6~0); 2110907#L1100-1 assume !(1 == ~E_7~0); 2110908#L1105-1 assume !(1 == ~E_8~0); 2110148#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 2110149#L1115-1 assume { :end_inline_reset_delta_events } true; 2110506#L1396-2 [2021-12-06 17:45:23,299 INFO L793 eck$LassoCheckResult]: Loop: 2110506#L1396-2 assume !false; 2118511#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2152297#L897 assume !false; 2152296#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2152295#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2118253#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2118241#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2118228#L766 assume !(0 != eval_~tmp~0#1); 2118230#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2158646#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2158645#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2158644#L922-5 assume !(0 == ~T1_E~0); 2158643#L927-3 assume !(0 == ~T2_E~0); 2158642#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2158641#L937-3 assume !(0 == ~T4_E~0); 2158640#L942-3 assume !(0 == ~T5_E~0); 2158639#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2158638#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2158637#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2158636#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2158635#L967-3 assume !(0 == ~E_1~0); 2158634#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2158633#L977-3 assume !(0 == ~E_3~0); 2158632#L982-3 assume !(0 == ~E_4~0); 2158631#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2158630#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2158629#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2158628#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2158627#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2158626#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2158625#L443-30 assume !(1 == ~m_pc~0); 2158624#L443-32 is_master_triggered_~__retres1~0#1 := 0; 2158623#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2158622#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2158621#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2158620#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2158619#L462-30 assume !(1 == ~t1_pc~0); 2158618#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 2158617#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2158616#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2158615#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2158614#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2158613#L481-30 assume 1 == ~t2_pc~0; 2158611#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2158610#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2158609#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2158608#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2158607#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2158606#L500-30 assume !(1 == ~t3_pc~0); 2158605#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 2158604#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2158603#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2158602#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2158601#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2158600#L519-30 assume !(1 == ~t4_pc~0); 2158599#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2158598#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2158597#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2158596#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2158595#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2158594#L538-30 assume 1 == ~t5_pc~0; 2158592#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2158593#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2158647#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2158587#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2158586#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2158585#L557-30 assume !(1 == ~t6_pc~0); 2158584#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 2158583#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2158582#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2158581#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 2158580#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2158579#L576-30 assume 1 == ~t7_pc~0; 2158577#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2158576#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2158575#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2158574#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2158573#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2158572#L595-30 assume !(1 == ~t8_pc~0); 2158571#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2158570#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2158569#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2158568#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2158567#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2158566#L614-30 assume 1 == ~t9_pc~0; 2158564#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2158563#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2158562#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2158561#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2158560#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2158559#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2158558#L1025-5 assume !(1 == ~T1_E~0); 2158557#L1030-3 assume !(1 == ~T2_E~0); 2158556#L1035-3 assume !(1 == ~T3_E~0); 2158555#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2158554#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2158553#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2158552#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2158551#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2158550#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2158549#L1070-3 assume !(1 == ~E_1~0); 2158548#L1075-3 assume !(1 == ~E_2~0); 2158547#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2158546#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2158545#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2158544#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2158543#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2158542#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2158541#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2158540#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2157902#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2157900#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2157898#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2157895#L1415 assume !(0 == start_simulation_~tmp~3#1); 2157891#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2118614#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2118603#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2118602#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 2118600#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2118601#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2118523#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2118524#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 2110506#L1396-2 [2021-12-06 17:45:23,299 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:23,299 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293170, now seen corresponding path program 1 times [2021-12-06 17:45:23,299 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:23,299 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1981113996] [2021-12-06 17:45:23,299 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:23,299 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:23,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:45:23,327 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:45:23,327 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:45:23,327 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1981113996] [2021-12-06 17:45:23,327 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1981113996] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:45:23,327 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:45:23,327 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:45:23,327 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1983696703] [2021-12-06 17:45:23,327 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:45:23,328 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:45:23,328 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:23,328 INFO L85 PathProgramCache]: Analyzing trace with hash -608197401, now seen corresponding path program 1 times [2021-12-06 17:45:23,328 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:23,328 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [199751777] [2021-12-06 17:45:23,328 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:23,328 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:23,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:45:23,347 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:45:23,347 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:45:23,347 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [199751777] [2021-12-06 17:45:23,347 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [199751777] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:45:23,347 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:45:23,347 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:45:23,347 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1372506411] [2021-12-06 17:45:23,347 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:45:23,347 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:45:23,348 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:45:23,348 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 17:45:23,348 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 17:45:23,348 INFO L87 Difference]: Start difference. First operand 74096 states and 104222 transitions. cyclomatic complexity: 30158 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:23,750 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:45:23,750 INFO L93 Difference]: Finished difference Result 154327 states and 215607 transitions. [2021-12-06 17:45:23,750 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 17:45:23,751 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 154327 states and 215607 transitions. [2021-12-06 17:45:24,388 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 153327 [2021-12-06 17:45:24,669 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 154327 states to 154327 states and 215607 transitions. [2021-12-06 17:45:24,669 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 154327 [2021-12-06 17:45:24,723 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 154327 [2021-12-06 17:45:24,723 INFO L73 IsDeterministic]: Start isDeterministic. Operand 154327 states and 215607 transitions. [2021-12-06 17:45:24,782 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:45:24,782 INFO L681 BuchiCegarLoop]: Abstraction has 154327 states and 215607 transitions. [2021-12-06 17:45:24,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 154327 states and 215607 transitions. [2021-12-06 17:45:25,623 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 154327 to 83827. [2021-12-06 17:45:25,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 83827 states, 83827 states have (on average 1.397723883712885) internal successors, (117167), 83826 states have internal predecessors, (117167), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:25,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83827 states to 83827 states and 117167 transitions. [2021-12-06 17:45:25,805 INFO L704 BuchiCegarLoop]: Abstraction has 83827 states and 117167 transitions. [2021-12-06 17:45:25,805 INFO L587 BuchiCegarLoop]: Abstraction has 83827 states and 117167 transitions. [2021-12-06 17:45:25,805 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-06 17:45:25,805 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 83827 states and 117167 transitions. [2021-12-06 17:45:25,996 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 83262 [2021-12-06 17:45:25,996 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:45:25,996 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:45:25,997 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:25,997 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:25,998 INFO L791 eck$LassoCheckResult]: Stem: 2339292#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 2339293#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 2338858#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2338859#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2339480#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 2339481#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2339458#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2339231#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2339232#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2339032#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2339033#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2339563#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2339435#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2339099#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2338864#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2338865#L922 assume !(0 == ~M_E~0); 2339650#L922-2 assume !(0 == ~T1_E~0); 2339651#L927-1 assume !(0 == ~T2_E~0); 2339301#L932-1 assume !(0 == ~T3_E~0); 2339172#L937-1 assume !(0 == ~T4_E~0); 2339173#L942-1 assume !(0 == ~T5_E~0); 2339230#L947-1 assume !(0 == ~T6_E~0); 2339305#L952-1 assume !(0 == ~T7_E~0); 2339306#L957-1 assume !(0 == ~T8_E~0); 2339380#L962-1 assume !(0 == ~T9_E~0); 2339145#L967-1 assume !(0 == ~E_1~0); 2339146#L972-1 assume !(0 == ~E_2~0); 2339464#L977-1 assume !(0 == ~E_3~0); 2339465#L982-1 assume !(0 == ~E_4~0); 2338630#L987-1 assume !(0 == ~E_5~0); 2338631#L992-1 assume !(0 == ~E_6~0); 2338639#L997-1 assume !(0 == ~E_7~0); 2339073#L1002-1 assume !(0 == ~E_8~0); 2339059#L1007-1 assume 0 == ~E_9~0;~E_9~0 := 1; 2338429#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2338430#L443 assume !(1 == ~m_pc~0); 2339324#L443-2 is_master_triggered_~__retres1~0#1 := 0; 2339325#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2339753#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2339752#L1140 assume !(0 != activate_threads_~tmp~1#1); 2339751#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2339750#L462 assume !(1 == ~t1_pc~0); 2339749#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2339748#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2339747#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2339333#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 2339013#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2339014#L481 assume !(1 == ~t2_pc~0); 2338790#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2338789#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2339742#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2339741#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 2338987#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2338988#L500 assume !(1 == ~t3_pc~0); 2339740#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2339739#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2339738#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2339736#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 2339734#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2339733#L519 assume !(1 == ~t4_pc~0); 2339732#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2339731#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2339339#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2338836#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 2338837#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2338598#L538 assume !(1 == ~t5_pc~0); 2338599#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2338504#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2338505#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2338774#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 2338775#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2339360#L557 assume !(1 == ~t6_pc~0); 2338812#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2338813#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2339544#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2339715#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 2339714#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2339657#L576 assume !(1 == ~t7_pc~0); 2338799#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2338800#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2339063#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2339064#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 2339709#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2339708#L595 assume !(1 == ~t8_pc~0); 2339707#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2339706#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2339705#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2339704#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 2339703#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2339702#L614 assume !(1 == ~t9_pc~0); 2339700#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2339699#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2339698#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2339697#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 2339696#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2339695#L1025 assume !(1 == ~M_E~0); 2339694#L1025-2 assume !(1 == ~T1_E~0); 2339693#L1030-1 assume !(1 == ~T2_E~0); 2339692#L1035-1 assume !(1 == ~T3_E~0); 2339691#L1040-1 assume !(1 == ~T4_E~0); 2339690#L1045-1 assume !(1 == ~T5_E~0); 2339689#L1050-1 assume !(1 == ~T6_E~0); 2339688#L1055-1 assume !(1 == ~T7_E~0); 2339687#L1060-1 assume !(1 == ~T8_E~0); 2339686#L1065-1 assume !(1 == ~T9_E~0); 2339685#L1070-1 assume !(1 == ~E_1~0); 2339684#L1075-1 assume !(1 == ~E_2~0); 2339683#L1080-1 assume !(1 == ~E_3~0); 2339682#L1085-1 assume !(1 == ~E_4~0); 2339681#L1090-1 assume !(1 == ~E_5~0); 2339680#L1095-1 assume !(1 == ~E_6~0); 2339679#L1100-1 assume !(1 == ~E_7~0); 2339678#L1105-1 assume !(1 == ~E_8~0); 2339677#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 2338581#L1115-1 assume { :end_inline_reset_delta_events } true; 2338937#L1396-2 [2021-12-06 17:45:25,998 INFO L793 eck$LassoCheckResult]: Loop: 2338937#L1396-2 assume !false; 2396691#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2396686#L897 assume !false; 2396685#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2395828#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2395812#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2395806#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2395800#L766 assume !(0 != eval_~tmp~0#1); 2395801#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2402945#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2402943#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2402941#L922-5 assume !(0 == ~T1_E~0); 2402940#L927-3 assume !(0 == ~T2_E~0); 2402938#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2402936#L937-3 assume !(0 == ~T4_E~0); 2402934#L942-3 assume !(0 == ~T5_E~0); 2402932#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2402930#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2402927#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2402925#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2402923#L967-3 assume !(0 == ~E_1~0); 2402921#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2402919#L977-3 assume !(0 == ~E_3~0); 2402917#L982-3 assume !(0 == ~E_4~0); 2402914#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2402912#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2402910#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2402908#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2402905#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2402904#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2402903#L443-30 assume !(1 == ~m_pc~0); 2402902#L443-32 is_master_triggered_~__retres1~0#1 := 0; 2402901#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2402900#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2402899#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2402898#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2402897#L462-30 assume !(1 == ~t1_pc~0); 2402896#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 2402895#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2402894#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2402893#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2402892#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2402891#L481-30 assume 1 == ~t2_pc~0; 2402889#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2402888#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2402887#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2402886#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2402885#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2402884#L500-30 assume !(1 == ~t3_pc~0); 2402883#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 2402882#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2402881#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2402880#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2402879#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2402878#L519-30 assume !(1 == ~t4_pc~0); 2402877#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2402876#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2402875#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2402874#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2402873#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2402872#L538-30 assume 1 == ~t5_pc~0; 2402870#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2402868#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2402866#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2402864#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2402863#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2402862#L557-30 assume !(1 == ~t6_pc~0); 2402861#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 2402860#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2402859#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2402858#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 2402857#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2402856#L576-30 assume 1 == ~t7_pc~0; 2402854#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2402853#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2402852#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2402851#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2402850#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2402849#L595-30 assume !(1 == ~t8_pc~0); 2402848#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2402847#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2402846#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2402845#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2402844#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2402843#L614-30 assume 1 == ~t9_pc~0; 2402840#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2402839#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2402838#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2402837#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2402836#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2402835#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2402834#L1025-5 assume !(1 == ~T1_E~0); 2402833#L1030-3 assume !(1 == ~T2_E~0); 2402832#L1035-3 assume !(1 == ~T3_E~0); 2402831#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2402830#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2402829#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2402828#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2402827#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2402826#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2402825#L1070-3 assume !(1 == ~E_1~0); 2402824#L1075-3 assume !(1 == ~E_2~0); 2402823#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2402822#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2402821#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2402820#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2402819#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2402818#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2402816#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2402814#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2402453#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2402451#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2402449#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2402445#L1415 assume !(0 == start_simulation_~tmp~3#1); 2402442#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2402434#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2402424#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2402422#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 2402420#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2402418#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2396699#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2396695#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 2338937#L1396-2 [2021-12-06 17:45:25,998 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:25,998 INFO L85 PathProgramCache]: Analyzing trace with hash -178464780, now seen corresponding path program 1 times [2021-12-06 17:45:25,998 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:25,998 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [294293758] [2021-12-06 17:45:25,999 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:25,999 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:26,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:45:26,022 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:45:26,022 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:45:26,022 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [294293758] [2021-12-06 17:45:26,022 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [294293758] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:45:26,022 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:45:26,022 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:45:26,022 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [31246728] [2021-12-06 17:45:26,022 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:45:26,022 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:45:26,023 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:26,023 INFO L85 PathProgramCache]: Analyzing trace with hash -608197401, now seen corresponding path program 2 times [2021-12-06 17:45:26,023 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:26,023 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1720523848] [2021-12-06 17:45:26,023 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:26,023 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:26,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:45:26,043 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:45:26,043 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:45:26,043 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1720523848] [2021-12-06 17:45:26,043 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1720523848] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:45:26,043 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:45:26,043 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:45:26,044 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [438234322] [2021-12-06 17:45:26,044 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:45:26,044 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:45:26,044 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:45:26,044 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 17:45:26,044 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 17:45:26,044 INFO L87 Difference]: Start difference. First operand 83827 states and 117167 transitions. cyclomatic complexity: 33372 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:26,348 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:45:26,348 INFO L93 Difference]: Finished difference Result 109463 states and 152803 transitions. [2021-12-06 17:45:26,348 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 17:45:26,348 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 109463 states and 152803 transitions. [2021-12-06 17:45:26,902 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 108807 [2021-12-06 17:45:27,096 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 109463 states to 109463 states and 152803 transitions. [2021-12-06 17:45:27,096 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 109463 [2021-12-06 17:45:27,136 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 109463 [2021-12-06 17:45:27,136 INFO L73 IsDeterministic]: Start isDeterministic. Operand 109463 states and 152803 transitions. [2021-12-06 17:45:27,171 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:45:27,171 INFO L681 BuchiCegarLoop]: Abstraction has 109463 states and 152803 transitions. [2021-12-06 17:45:27,206 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 109463 states and 152803 transitions. [2021-12-06 17:45:27,827 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 109463 to 74096. [2021-12-06 17:45:27,857 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 74096 states, 74096 states have (on average 1.392261390628374) internal successors, (103161), 74095 states have internal predecessors, (103161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:27,979 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74096 states to 74096 states and 103161 transitions. [2021-12-06 17:45:27,979 INFO L704 BuchiCegarLoop]: Abstraction has 74096 states and 103161 transitions. [2021-12-06 17:45:27,979 INFO L587 BuchiCegarLoop]: Abstraction has 74096 states and 103161 transitions. [2021-12-06 17:45:27,979 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-12-06 17:45:27,979 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 74096 states and 103161 transitions. [2021-12-06 17:45:28,142 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 73618 [2021-12-06 17:45:28,142 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:45:28,142 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:45:28,144 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:28,144 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:28,144 INFO L791 eck$LassoCheckResult]: Stem: 2532599#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 2532600#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 2532158#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2532159#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2532780#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 2532781#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2532759#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2532541#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2532542#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2532334#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2532335#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2532863#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2532738#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2532402#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2532164#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2532165#L922 assume !(0 == ~M_E~0); 2532949#L922-2 assume !(0 == ~T1_E~0); 2532950#L927-1 assume !(0 == ~T2_E~0); 2532608#L932-1 assume !(0 == ~T3_E~0); 2532478#L937-1 assume !(0 == ~T4_E~0); 2532479#L942-1 assume !(0 == ~T5_E~0); 2532540#L947-1 assume !(0 == ~T6_E~0); 2532612#L952-1 assume !(0 == ~T7_E~0); 2532613#L957-1 assume !(0 == ~T8_E~0); 2532681#L962-1 assume !(0 == ~T9_E~0); 2532451#L967-1 assume !(0 == ~E_1~0); 2532452#L972-1 assume !(0 == ~E_2~0); 2532765#L977-1 assume !(0 == ~E_3~0); 2532766#L982-1 assume !(0 == ~E_4~0); 2531930#L987-1 assume !(0 == ~E_5~0); 2531931#L992-1 assume !(0 == ~E_6~0); 2531939#L997-1 assume !(0 == ~E_7~0); 2532374#L1002-1 assume !(0 == ~E_8~0); 2532360#L1007-1 assume !(0 == ~E_9~0); 2531729#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2531730#L443 assume !(1 == ~m_pc~0); 2532631#L443-2 is_master_triggered_~__retres1~0#1 := 0; 2532618#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2532619#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2532095#L1140 assume !(0 != activate_threads_~tmp~1#1); 2531844#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2531845#L462 assume !(1 == ~t1_pc~0); 2532469#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2532470#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2531814#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2531815#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 2532315#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2532316#L481 assume !(1 == ~t2_pc~0); 2532090#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2532089#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2532475#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2532187#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 2532188#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2532289#L500 assume !(1 == ~t3_pc~0); 2532827#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2532795#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2532749#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2532750#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 2531731#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2531732#L519 assume !(1 == ~t4_pc~0); 2532525#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2532287#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2532288#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2532136#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 2532137#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2531898#L538 assume !(1 == ~t5_pc~0); 2531899#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2531804#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2531805#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2532074#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 2532075#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2532661#L557 assume !(1 == ~t6_pc~0); 2532111#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2532112#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2532010#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2532011#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 2532138#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2532916#L576 assume !(1 == ~t7_pc~0); 2532099#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2532100#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2532364#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2532365#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 2532730#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2532229#L595 assume !(1 == ~t8_pc~0); 2532230#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2532751#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2532752#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2532571#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 2532572#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2532025#L614 assume !(1 == ~t9_pc~0); 2532026#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2531922#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2531923#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2532103#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 2532189#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2532190#L1025 assume !(1 == ~M_E~0); 2532461#L1025-2 assume !(1 == ~T1_E~0); 2532517#L1030-1 assume !(1 == ~T2_E~0); 2532656#L1035-1 assume !(1 == ~T3_E~0); 2532183#L1040-1 assume !(1 == ~T4_E~0); 2532184#L1045-1 assume !(1 == ~T5_E~0); 2532085#L1050-1 assume !(1 == ~T6_E~0); 2532086#L1055-1 assume !(1 == ~T7_E~0); 2531907#L1060-1 assume !(1 == ~T8_E~0); 2531908#L1065-1 assume !(1 == ~T9_E~0); 2531969#L1070-1 assume !(1 == ~E_1~0); 2532614#L1075-1 assume !(1 == ~E_2~0); 2532615#L1080-1 assume !(1 == ~E_3~0); 2532603#L1085-1 assume !(1 == ~E_4~0); 2532604#L1090-1 assume !(1 == ~E_5~0); 2532854#L1095-1 assume !(1 == ~E_6~0); 2532640#L1100-1 assume !(1 == ~E_7~0); 2532641#L1105-1 assume !(1 == ~E_8~0); 2531880#L1110-1 assume !(1 == ~E_9~0); 2531881#L1115-1 assume { :end_inline_reset_delta_events } true; 2532240#L1396-2 [2021-12-06 17:45:28,144 INFO L793 eck$LassoCheckResult]: Loop: 2532240#L1396-2 assume !false; 2546410#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2546405#L897 assume !false; 2546404#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2546403#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2546393#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2546392#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2546387#L766 assume !(0 != eval_~tmp~0#1); 2546388#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2547355#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2547352#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2547350#L922-5 assume !(0 == ~T1_E~0); 2547348#L927-3 assume !(0 == ~T2_E~0); 2547346#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2547344#L937-3 assume !(0 == ~T4_E~0); 2547342#L942-3 assume !(0 == ~T5_E~0); 2547340#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2547338#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2547336#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2547335#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2547334#L967-3 assume !(0 == ~E_1~0); 2547333#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2547332#L977-3 assume !(0 == ~E_3~0); 2547330#L982-3 assume !(0 == ~E_4~0); 2547328#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2547327#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2547326#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2547324#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2547323#L1007-3 assume !(0 == ~E_9~0); 2547322#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2547321#L443-30 assume !(1 == ~m_pc~0); 2547320#L443-32 is_master_triggered_~__retres1~0#1 := 0; 2547319#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2547317#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2547315#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2547313#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2547311#L462-30 assume !(1 == ~t1_pc~0); 2547309#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 2547307#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2547305#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2547303#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2547301#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2547299#L481-30 assume 1 == ~t2_pc~0; 2547296#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2547294#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2547292#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2547289#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2547287#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2547285#L500-30 assume !(1 == ~t3_pc~0); 2547283#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 2547281#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2547279#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2547277#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2547275#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2547273#L519-30 assume !(1 == ~t4_pc~0); 2547271#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2547269#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2547267#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2547265#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2547263#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2547261#L538-30 assume 1 == ~t5_pc~0; 2547259#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2547260#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2547325#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2547249#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2547247#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2547245#L557-30 assume !(1 == ~t6_pc~0); 2547242#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 2547240#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2547238#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2547236#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 2547234#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2547232#L576-30 assume !(1 == ~t7_pc~0); 2547230#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 2547227#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2547225#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2547224#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2547221#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2547219#L595-30 assume !(1 == ~t8_pc~0); 2547217#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2547215#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2547213#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2547211#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2547209#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2547207#L614-30 assume !(1 == ~t9_pc~0); 2547204#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 2547202#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2547200#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2547199#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2547196#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2547194#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2547192#L1025-5 assume !(1 == ~T1_E~0); 2547190#L1030-3 assume !(1 == ~T2_E~0); 2547188#L1035-3 assume !(1 == ~T3_E~0); 2547186#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2547184#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2547182#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2547180#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2547178#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2547176#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2547174#L1070-3 assume !(1 == ~E_1~0); 2547172#L1075-3 assume !(1 == ~E_2~0); 2547170#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2547168#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2547166#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2547164#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2547162#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2547160#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2547158#L1110-3 assume !(1 == ~E_9~0); 2547156#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2547026#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2547016#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2547007#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2546997#L1415 assume !(0 == start_simulation_~tmp~3#1); 2546990#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2546898#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2546885#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2546879#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 2546875#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2546872#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2546419#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2546414#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 2532240#L1396-2 [2021-12-06 17:45:28,144 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:28,145 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 1 times [2021-12-06 17:45:28,145 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:28,145 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1218261065] [2021-12-06 17:45:28,145 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:28,145 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:28,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:45:28,153 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:45:28,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:45:28,209 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:45:28,209 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:28,209 INFO L85 PathProgramCache]: Analyzing trace with hash -150338655, now seen corresponding path program 1 times [2021-12-06 17:45:28,209 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:28,209 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [281157245] [2021-12-06 17:45:28,209 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:28,210 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:28,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:45:28,229 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:45:28,229 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:45:28,229 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [281157245] [2021-12-06 17:45:28,229 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [281157245] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:45:28,229 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:45:28,229 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:45:28,229 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [788888665] [2021-12-06 17:45:28,229 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:45:28,230 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:45:28,230 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:45:28,230 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:45:28,230 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:45:28,230 INFO L87 Difference]: Start difference. First operand 74096 states and 103161 transitions. cyclomatic complexity: 29097 Second operand has 3 states, 3 states have (on average 40.666666666666664) internal successors, (122), 3 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:28,426 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:45:28,426 INFO L93 Difference]: Finished difference Result 83827 states and 116513 transitions. [2021-12-06 17:45:28,427 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:45:28,427 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 83827 states and 116513 transitions. [2021-12-06 17:45:28,686 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 83262 [2021-12-06 17:45:28,850 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 83827 states to 83827 states and 116513 transitions. [2021-12-06 17:45:28,851 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 83827 [2021-12-06 17:45:28,889 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 83827 [2021-12-06 17:45:28,889 INFO L73 IsDeterministic]: Start isDeterministic. Operand 83827 states and 116513 transitions. [2021-12-06 17:45:29,107 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:45:29,107 INFO L681 BuchiCegarLoop]: Abstraction has 83827 states and 116513 transitions. [2021-12-06 17:45:29,136 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83827 states and 116513 transitions. [2021-12-06 17:45:29,671 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83827 to 83827. [2021-12-06 17:45:29,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 83827 states, 83827 states have (on average 1.3899221014708865) internal successors, (116513), 83826 states have internal predecessors, (116513), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:29,885 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83827 states to 83827 states and 116513 transitions. [2021-12-06 17:45:29,885 INFO L704 BuchiCegarLoop]: Abstraction has 83827 states and 116513 transitions. [2021-12-06 17:45:29,886 INFO L587 BuchiCegarLoop]: Abstraction has 83827 states and 116513 transitions. [2021-12-06 17:45:29,886 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-12-06 17:45:29,886 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 83827 states and 116513 transitions. [2021-12-06 17:45:30,116 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 83262 [2021-12-06 17:45:30,116 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:45:30,116 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:45:30,118 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:30,118 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:30,118 INFO L791 eck$LassoCheckResult]: Stem: 2690523#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 2690524#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 2690090#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2690091#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2690720#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 2690721#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2690698#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2690470#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2690471#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2690264#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2690265#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2690807#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2690680#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2690330#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2690096#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2690097#L922 assume !(0 == ~M_E~0); 2690896#L922-2 assume !(0 == ~T1_E~0); 2690897#L927-1 assume !(0 == ~T2_E~0); 2690531#L932-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2690406#L937-1 assume !(0 == ~T4_E~0); 2690407#L942-1 assume !(0 == ~T5_E~0); 2690724#L947-1 assume !(0 == ~T6_E~0); 2690725#L952-1 assume !(0 == ~T7_E~0); 2690619#L957-1 assume !(0 == ~T8_E~0); 2690620#L962-1 assume !(0 == ~T9_E~0); 2690381#L967-1 assume !(0 == ~E_1~0); 2690382#L972-1 assume !(0 == ~E_2~0); 2690703#L977-1 assume !(0 == ~E_3~0); 2690704#L982-1 assume !(0 == ~E_4~0); 2689863#L987-1 assume !(0 == ~E_5~0); 2689864#L992-1 assume !(0 == ~E_6~0); 2690306#L997-1 assume !(0 == ~E_7~0); 2690307#L1002-1 assume !(0 == ~E_8~0); 2690289#L1007-1 assume !(0 == ~E_9~0); 2689658#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2689659#L443 assume !(1 == ~m_pc~0); 2690825#L443-2 is_master_triggered_~__retres1~0#1 := 0; 2690542#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2690543#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2690875#L1140 assume !(0 != activate_threads_~tmp~1#1); 2690983#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2690982#L462 assume !(1 == ~t1_pc~0); 2690981#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2690980#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2690979#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2690569#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 2690570#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2690978#L481 assume !(1 == ~t2_pc~0); 2690976#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2690519#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2690403#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2690117#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 2690118#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2690917#L500 assume !(1 == ~t3_pc~0); 2690770#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2690738#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2690689#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2690690#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 2690754#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2690969#L519 assume !(1 == ~t4_pc~0); 2690968#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2690215#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2690216#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2690967#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 2690966#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2690964#L538 assume !(1 == ~t5_pc~0); 2690961#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2690959#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2690957#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2690955#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 2690954#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2690926#L557 assume !(1 == ~t6_pc~0); 2690043#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2690044#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2689946#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2689947#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 2690072#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2690855#L576 assume !(1 == ~t7_pc~0); 2690947#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2690946#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2690945#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2690906#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 2690670#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2690158#L595 assume !(1 == ~t8_pc~0); 2690159#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2690691#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2690692#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2690495#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 2690496#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2689957#L614 assume !(1 == ~t9_pc~0); 2689958#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2689854#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2689855#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2690035#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 2690119#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2690120#L1025 assume !(1 == ~M_E~0); 2690388#L1025-2 assume !(1 == ~T1_E~0); 2690445#L1030-1 assume !(1 == ~T2_E~0); 2690594#L1035-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2690114#L1040-1 assume !(1 == ~T4_E~0); 2690115#L1045-1 assume !(1 == ~T5_E~0); 2690017#L1050-1 assume !(1 == ~T6_E~0); 2690018#L1055-1 assume !(1 == ~T7_E~0); 2689838#L1060-1 assume !(1 == ~T8_E~0); 2689839#L1065-1 assume !(1 == ~T9_E~0); 2689901#L1070-1 assume !(1 == ~E_1~0); 2690538#L1075-1 assume !(1 == ~E_2~0); 2690539#L1080-1 assume !(1 == ~E_3~0); 2690526#L1085-1 assume !(1 == ~E_4~0); 2690527#L1090-1 assume !(1 == ~E_5~0); 2690799#L1095-1 assume !(1 == ~E_6~0); 2690575#L1100-1 assume !(1 == ~E_7~0); 2690576#L1105-1 assume !(1 == ~E_8~0); 2689811#L1110-1 assume !(1 == ~E_9~0); 2689812#L1115-1 assume { :end_inline_reset_delta_events } true; 2690167#L1396-2 [2021-12-06 17:45:30,118 INFO L793 eck$LassoCheckResult]: Loop: 2690167#L1396-2 assume !false; 2728472#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2728461#L897 assume !false; 2728456#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2728017#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2728000#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2727996#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2727991#L766 assume !(0 != eval_~tmp~0#1); 2727992#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2729207#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2729205#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2729203#L922-5 assume !(0 == ~T1_E~0); 2729201#L927-3 assume !(0 == ~T2_E~0); 2729198#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2729196#L937-3 assume !(0 == ~T4_E~0); 2729194#L942-3 assume !(0 == ~T5_E~0); 2729192#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2729190#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2729188#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2729185#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2729183#L967-3 assume !(0 == ~E_1~0); 2729181#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2729179#L977-3 assume !(0 == ~E_3~0); 2729177#L982-3 assume !(0 == ~E_4~0); 2729175#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2729173#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2729171#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2729169#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2729167#L1007-3 assume !(0 == ~E_9~0); 2729165#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2729163#L443-30 assume !(1 == ~m_pc~0); 2729161#L443-32 is_master_triggered_~__retres1~0#1 := 0; 2729159#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2729157#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2729155#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2729153#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2729149#L462-30 assume !(1 == ~t1_pc~0); 2729147#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 2729145#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2729143#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2729140#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2729138#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2729136#L481-30 assume 1 == ~t2_pc~0; 2729133#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2729131#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2729129#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2729127#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2729125#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2729123#L500-30 assume !(1 == ~t3_pc~0); 2729120#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 2729118#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2729116#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2729114#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2729112#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2729110#L519-30 assume !(1 == ~t4_pc~0); 2729108#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2729106#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2729104#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2729102#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2729100#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2729097#L538-30 assume !(1 == ~t5_pc~0); 2729093#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 2729091#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2729089#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2729087#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 2729084#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2729082#L557-30 assume !(1 == ~t6_pc~0); 2729080#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 2729078#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2729077#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2729076#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 2729075#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2729074#L576-30 assume !(1 == ~t7_pc~0); 2729073#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 2729071#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2729069#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2729066#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2729064#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2729062#L595-30 assume !(1 == ~t8_pc~0); 2729060#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2729058#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2729056#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2729055#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2729053#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2729051#L614-30 assume !(1 == ~t9_pc~0); 2729048#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 2729046#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2729044#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2729041#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2729039#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2729037#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2729035#L1025-5 assume !(1 == ~T1_E~0); 2729033#L1030-3 assume !(1 == ~T2_E~0); 2729030#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2729026#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2729024#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2729022#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2729020#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2729018#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2729016#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2729013#L1070-3 assume !(1 == ~E_1~0); 2729011#L1075-3 assume !(1 == ~E_2~0); 2729009#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2729007#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2729005#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2729004#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2729000#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2728998#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2728996#L1110-3 assume !(1 == ~E_9~0); 2728994#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2728969#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2728967#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2728965#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2728962#L1415 assume !(0 == start_simulation_~tmp~3#1); 2728959#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2728952#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2728942#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2728939#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 2728937#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2728935#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2728933#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2728931#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 2690167#L1396-2 [2021-12-06 17:45:30,119 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:30,119 INFO L85 PathProgramCache]: Analyzing trace with hash 1375570028, now seen corresponding path program 1 times [2021-12-06 17:45:30,119 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:30,119 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1525691226] [2021-12-06 17:45:30,119 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:30,119 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:30,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:45:30,146 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:45:30,147 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:45:30,147 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1525691226] [2021-12-06 17:45:30,147 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1525691226] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:45:30,147 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:45:30,147 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:45:30,147 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [760982085] [2021-12-06 17:45:30,147 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:45:30,147 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:45:30,148 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:30,148 INFO L85 PathProgramCache]: Analyzing trace with hash 716912956, now seen corresponding path program 1 times [2021-12-06 17:45:30,148 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:30,148 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [689923947] [2021-12-06 17:45:30,148 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:30,148 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:30,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:45:30,170 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:45:30,170 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:45:30,170 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [689923947] [2021-12-06 17:45:30,170 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [689923947] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:45:30,170 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:45:30,170 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:45:30,170 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1798398058] [2021-12-06 17:45:30,170 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:45:30,171 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:45:30,171 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:45:30,171 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 17:45:30,171 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 17:45:30,171 INFO L87 Difference]: Start difference. First operand 83827 states and 116513 transitions. cyclomatic complexity: 32718 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:30,655 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:45:30,655 INFO L93 Difference]: Finished difference Result 148086 states and 205965 transitions. [2021-12-06 17:45:30,656 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 17:45:30,656 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 148086 states and 205965 transitions. [2021-12-06 17:45:31,143 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 147236 [2021-12-06 17:45:31,459 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 148086 states to 148086 states and 205965 transitions. [2021-12-06 17:45:31,459 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 148086 [2021-12-06 17:45:31,533 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 148086 [2021-12-06 17:45:31,533 INFO L73 IsDeterministic]: Start isDeterministic. Operand 148086 states and 205965 transitions. [2021-12-06 17:45:31,768 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:45:31,768 INFO L681 BuchiCegarLoop]: Abstraction has 148086 states and 205965 transitions. [2021-12-06 17:45:31,816 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148086 states and 205965 transitions. [2021-12-06 17:45:32,480 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148086 to 74096. [2021-12-06 17:45:32,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 74096 states, 74096 states have (on average 1.3907903260634853) internal successors, (103052), 74095 states have internal predecessors, (103052), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:32,633 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74096 states to 74096 states and 103052 transitions. [2021-12-06 17:45:32,633 INFO L704 BuchiCegarLoop]: Abstraction has 74096 states and 103052 transitions. [2021-12-06 17:45:32,633 INFO L587 BuchiCegarLoop]: Abstraction has 74096 states and 103052 transitions. [2021-12-06 17:45:32,633 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-12-06 17:45:32,633 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 74096 states and 103052 transitions. [2021-12-06 17:45:32,805 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 73618 [2021-12-06 17:45:32,805 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:45:32,805 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:45:32,806 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:32,806 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:32,806 INFO L791 eck$LassoCheckResult]: Stem: 2922465#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 2922466#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 2922012#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2922013#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2922659#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 2922660#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2922638#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2922405#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2922406#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2922190#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2922191#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2922742#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2922617#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2922260#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2922018#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2922019#L922 assume !(0 == ~M_E~0); 2922821#L922-2 assume !(0 == ~T1_E~0); 2922822#L927-1 assume !(0 == ~T2_E~0); 2922473#L932-1 assume !(0 == ~T3_E~0); 2922336#L937-1 assume !(0 == ~T4_E~0); 2922337#L942-1 assume !(0 == ~T5_E~0); 2922404#L947-1 assume !(0 == ~T6_E~0); 2922477#L952-1 assume !(0 == ~T7_E~0); 2922478#L957-1 assume !(0 == ~T8_E~0); 2922555#L962-1 assume !(0 == ~T9_E~0); 2922308#L967-1 assume !(0 == ~E_1~0); 2922309#L972-1 assume !(0 == ~E_2~0); 2922644#L977-1 assume !(0 == ~E_3~0); 2922645#L982-1 assume !(0 == ~E_4~0); 2921783#L987-1 assume !(0 == ~E_5~0); 2921784#L992-1 assume !(0 == ~E_6~0); 2921792#L997-1 assume !(0 == ~E_7~0); 2922232#L1002-1 assume !(0 == ~E_8~0); 2922217#L1007-1 assume !(0 == ~E_9~0); 2921581#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2921582#L443 assume !(1 == ~m_pc~0); 2922497#L443-2 is_master_triggered_~__retres1~0#1 := 0; 2922483#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2922484#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2921949#L1140 assume !(0 != activate_threads_~tmp~1#1); 2921696#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2921697#L462 assume !(1 == ~t1_pc~0); 2922328#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2922329#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2921666#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2921667#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 2922172#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2922173#L481 assume !(1 == ~t2_pc~0); 2921944#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2921943#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2922333#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2922040#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 2922041#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2922147#L500 assume !(1 == ~t3_pc~0); 2922710#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2922675#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2922629#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2922630#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 2921586#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2921587#L519 assume !(1 == ~t4_pc~0); 2922387#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2922145#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2922146#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2921991#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 2921992#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2921751#L538 assume !(1 == ~t5_pc~0); 2921752#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2921656#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2921657#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2921928#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 2921929#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2922537#L557 assume !(1 == ~t6_pc~0); 2921966#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2921967#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2921865#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2921866#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 2921993#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2922790#L576 assume !(1 == ~t7_pc~0); 2921953#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2921954#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2922220#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2922221#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 2922605#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2922086#L595 assume !(1 == ~t8_pc~0); 2922087#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2922631#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2922632#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2922435#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 2922436#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2921878#L614 assume !(1 == ~t9_pc~0); 2921879#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2921776#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2921777#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2921957#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 2922042#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2922043#L1025 assume !(1 == ~M_E~0); 2922318#L1025-2 assume !(1 == ~T1_E~0); 2922379#L1030-1 assume !(1 == ~T2_E~0); 2922529#L1035-1 assume !(1 == ~T3_E~0); 2922036#L1040-1 assume !(1 == ~T4_E~0); 2922037#L1045-1 assume !(1 == ~T5_E~0); 2921939#L1050-1 assume !(1 == ~T6_E~0); 2921940#L1055-1 assume !(1 == ~T7_E~0); 2921760#L1060-1 assume !(1 == ~T8_E~0); 2921761#L1065-1 assume !(1 == ~T9_E~0); 2921823#L1070-1 assume !(1 == ~E_1~0); 2922479#L1075-1 assume !(1 == ~E_2~0); 2922480#L1080-1 assume !(1 == ~E_3~0); 2922468#L1085-1 assume !(1 == ~E_4~0); 2922469#L1090-1 assume !(1 == ~E_5~0); 2922736#L1095-1 assume !(1 == ~E_6~0); 2922508#L1100-1 assume !(1 == ~E_7~0); 2922509#L1105-1 assume !(1 == ~E_8~0); 2921733#L1110-1 assume !(1 == ~E_9~0); 2921734#L1115-1 assume { :end_inline_reset_delta_events } true; 2922096#L1396-2 [2021-12-06 17:45:32,807 INFO L793 eck$LassoCheckResult]: Loop: 2922096#L1396-2 assume !false; 2960465#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2960454#L897 assume !false; 2960449#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2959874#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2959863#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2959861#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2959858#L766 assume !(0 != eval_~tmp~0#1); 2959859#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2960788#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2960781#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2960779#L922-5 assume !(0 == ~T1_E~0); 2960778#L927-3 assume !(0 == ~T2_E~0); 2960777#L932-3 assume !(0 == ~T3_E~0); 2960776#L937-3 assume !(0 == ~T4_E~0); 2960775#L942-3 assume !(0 == ~T5_E~0); 2960774#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2960773#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2960772#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2960770#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2960769#L967-3 assume !(0 == ~E_1~0); 2960768#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2960766#L977-3 assume !(0 == ~E_3~0); 2960764#L982-3 assume !(0 == ~E_4~0); 2960763#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2960762#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2960761#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2960760#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2960759#L1007-3 assume !(0 == ~E_9~0); 2960757#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2960755#L443-30 assume !(1 == ~m_pc~0); 2960753#L443-32 is_master_triggered_~__retres1~0#1 := 0; 2960751#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2960749#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2960747#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2960745#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2960743#L462-30 assume !(1 == ~t1_pc~0); 2960741#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 2960739#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2960737#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2960735#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2960733#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2960730#L481-30 assume !(1 == ~t2_pc~0); 2960728#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 2960725#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2960723#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2960721#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2960719#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2960717#L500-30 assume !(1 == ~t3_pc~0); 2960715#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 2960713#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2960711#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2960709#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2960707#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2960705#L519-30 assume !(1 == ~t4_pc~0); 2960703#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2960701#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2960699#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2960697#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2960695#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2960692#L538-30 assume !(1 == ~t5_pc~0); 2960688#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 2960686#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2960683#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2960681#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 2960678#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2960676#L557-30 assume !(1 == ~t6_pc~0); 2960674#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 2960672#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2960670#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2960668#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 2960666#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2960663#L576-30 assume !(1 == ~t7_pc~0); 2960661#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 2960658#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2960656#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2960654#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2960652#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2960650#L595-30 assume !(1 == ~t8_pc~0); 2960648#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2960646#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2960644#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2960642#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2960641#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2960640#L614-30 assume !(1 == ~t9_pc~0); 2960636#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 2960634#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2960632#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2960630#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2960628#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2960626#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2960624#L1025-5 assume !(1 == ~T1_E~0); 2960622#L1030-3 assume !(1 == ~T2_E~0); 2960620#L1035-3 assume !(1 == ~T3_E~0); 2960618#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2960616#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2960614#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2960612#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2960610#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2960608#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2960606#L1070-3 assume !(1 == ~E_1~0); 2960604#L1075-3 assume !(1 == ~E_2~0); 2960602#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2960600#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2960598#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2960596#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2960594#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2960592#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2960590#L1110-3 assume !(1 == ~E_9~0); 2960588#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2960577#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2960575#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2960573#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2960570#L1415 assume !(0 == start_simulation_~tmp~3#1); 2960567#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2960553#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2960533#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2960531#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 2960528#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2960524#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2960520#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2960515#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 2922096#L1396-2 [2021-12-06 17:45:32,807 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:32,807 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 2 times [2021-12-06 17:45:32,807 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:32,807 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2030851906] [2021-12-06 17:45:32,808 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:32,808 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:32,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:45:32,819 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:45:32,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:45:32,851 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:45:32,852 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:32,852 INFO L85 PathProgramCache]: Analyzing trace with hash 2081459679, now seen corresponding path program 1 times [2021-12-06 17:45:32,852 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:32,852 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1985741275] [2021-12-06 17:45:32,852 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:32,852 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:32,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:45:32,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:45:32,869 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:45:32,870 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1985741275] [2021-12-06 17:45:32,870 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1985741275] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:45:32,870 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:45:32,870 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:45:32,870 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1021604659] [2021-12-06 17:45:32,870 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:45:32,870 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:45:32,870 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:45:32,871 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:45:32,871 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:45:32,871 INFO L87 Difference]: Start difference. First operand 74096 states and 103052 transitions. cyclomatic complexity: 28988 Second operand has 3 states, 3 states have (on average 40.666666666666664) internal successors, (122), 3 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:33,321 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:45:33,321 INFO L93 Difference]: Finished difference Result 138617 states and 190504 transitions. [2021-12-06 17:45:33,321 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:45:33,322 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 138617 states and 190504 transitions. [2021-12-06 17:45:33,855 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 137696 [2021-12-06 17:45:34,170 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 138617 states to 138617 states and 190504 transitions. [2021-12-06 17:45:34,170 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 138617 [2021-12-06 17:45:34,235 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 138617 [2021-12-06 17:45:34,235 INFO L73 IsDeterministic]: Start isDeterministic. Operand 138617 states and 190504 transitions. [2021-12-06 17:45:34,294 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:45:34,295 INFO L681 BuchiCegarLoop]: Abstraction has 138617 states and 190504 transitions. [2021-12-06 17:45:34,355 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138617 states and 190504 transitions. [2021-12-06 17:45:35,233 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138617 to 138581. [2021-12-06 17:45:35,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 138581 states, 138581 states have (on average 1.3744164062894624) internal successors, (190468), 138580 states have internal predecessors, (190468), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:35,557 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 138581 states to 138581 states and 190468 transitions. [2021-12-06 17:45:35,557 INFO L704 BuchiCegarLoop]: Abstraction has 138581 states and 190468 transitions. [2021-12-06 17:45:35,557 INFO L587 BuchiCegarLoop]: Abstraction has 138581 states and 190468 transitions. [2021-12-06 17:45:35,557 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-12-06 17:45:35,557 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 138581 states and 190468 transitions. [2021-12-06 17:45:35,985 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 137660 [2021-12-06 17:45:35,985 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:45:35,985 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:45:35,986 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:35,986 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:35,986 INFO L791 eck$LassoCheckResult]: Stem: 3135180#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 3135181#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 3134733#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3134734#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3135388#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 3135389#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3135361#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3135116#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3135117#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3134909#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3134910#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3135491#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3135341#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3134979#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3134739#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3134740#L922 assume !(0 == ~M_E~0); 3135593#L922-2 assume !(0 == ~T1_E~0); 3135594#L927-1 assume !(0 == ~T2_E~0); 3135191#L932-1 assume !(0 == ~T3_E~0); 3135054#L937-1 assume !(0 == ~T4_E~0); 3135055#L942-1 assume !(0 == ~T5_E~0); 3135115#L947-1 assume !(0 == ~T6_E~0); 3135195#L952-1 assume !(0 == ~T7_E~0); 3135196#L957-1 assume !(0 == ~T8_E~0); 3135281#L962-1 assume !(0 == ~T9_E~0); 3135028#L967-1 assume !(0 == ~E_1~0); 3135029#L972-1 assume 0 == ~E_2~0;~E_2~0 := 1; 3135550#L977-1 assume !(0 == ~E_3~0); 3135597#L982-1 assume !(0 == ~E_4~0); 3135598#L987-1 assume !(0 == ~E_5~0); 3134513#L992-1 assume !(0 == ~E_6~0); 3134514#L997-1 assume !(0 == ~E_7~0); 3135520#L1002-1 assume !(0 == ~E_8~0); 3135521#L1007-1 assume !(0 == ~E_9~0); 3134300#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3134301#L443 assume !(1 == ~m_pc~0); 3135214#L443-2 is_master_triggered_~__retres1~0#1 := 0; 3135215#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3135567#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3135568#L1140 assume !(0 != activate_threads_~tmp~1#1); 3134416#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3134417#L462 assume !(1 == ~t1_pc~0); 3135046#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3135047#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3134385#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3134386#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 3134888#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3134889#L481 assume !(1 == ~t2_pc~0); 3135432#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3134662#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3135684#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3135683#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 3134860#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3134861#L500 assume !(1 == ~t3_pc~0); 3135449#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3135450#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3135352#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3135353#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 3135682#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3135681#L519 assume !(1 == ~t4_pc~0); 3135680#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3134858#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3134859#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3135679#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 3135678#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3135676#L538 assume !(1 == ~t5_pc~0); 3135673#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3135671#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3135669#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3135667#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 3135666#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3135632#L557 assume !(1 == ~t6_pc~0); 3134685#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3134686#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3135468#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3135663#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 3135662#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3135605#L576 assume !(1 == ~t7_pc~0); 3134672#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3134673#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3134940#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3134941#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 3135657#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3135656#L595 assume !(1 == ~t8_pc~0); 3135655#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3135654#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3135653#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3135652#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 3135651#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3135649#L614 assume !(1 == ~t9_pc~0); 3135648#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3135647#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3135646#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3135645#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 3135644#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3135643#L1025 assume !(1 == ~M_E~0); 3135642#L1025-2 assume !(1 == ~T1_E~0); 3135641#L1030-1 assume !(1 == ~T2_E~0); 3135640#L1035-1 assume !(1 == ~T3_E~0); 3135639#L1040-1 assume !(1 == ~T4_E~0); 3135638#L1045-1 assume !(1 == ~T5_E~0); 3135637#L1050-1 assume !(1 == ~T6_E~0); 3135636#L1055-1 assume !(1 == ~T7_E~0); 3135635#L1060-1 assume !(1 == ~T8_E~0); 3135634#L1065-1 assume !(1 == ~T9_E~0); 3135633#L1070-1 assume !(1 == ~E_1~0); 3135197#L1075-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3135198#L1080-1 assume !(1 == ~E_3~0); 3135186#L1085-1 assume !(1 == ~E_4~0); 3135187#L1090-1 assume !(1 == ~E_5~0); 3135483#L1095-1 assume !(1 == ~E_6~0); 3135232#L1100-1 assume !(1 == ~E_7~0); 3135233#L1105-1 assume !(1 == ~E_8~0); 3134454#L1110-1 assume !(1 == ~E_9~0); 3134455#L1115-1 assume { :end_inline_reset_delta_events } true; 3134812#L1396-2 [2021-12-06 17:45:35,987 INFO L793 eck$LassoCheckResult]: Loop: 3134812#L1396-2 assume !false; 3227030#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3227024#L897 assume !false; 3227022#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3227019#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 3227008#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3227006#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3227003#L766 assume !(0 != eval_~tmp~0#1); 3227004#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3227316#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3227315#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3227314#L922-5 assume !(0 == ~T1_E~0); 3227312#L927-3 assume !(0 == ~T2_E~0); 3227311#L932-3 assume !(0 == ~T3_E~0); 3227310#L937-3 assume !(0 == ~T4_E~0); 3227308#L942-3 assume !(0 == ~T5_E~0); 3227306#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3227305#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3227304#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3227303#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3227301#L967-3 assume !(0 == ~E_1~0); 3227271#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3227269#L977-3 assume !(0 == ~E_3~0); 3227267#L982-3 assume !(0 == ~E_4~0); 3227265#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3227261#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3227260#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3227259#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3227257#L1007-3 assume !(0 == ~E_9~0); 3227255#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3227253#L443-30 assume !(1 == ~m_pc~0); 3227251#L443-32 is_master_triggered_~__retres1~0#1 := 0; 3227249#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3227247#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3227245#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3227243#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3227241#L462-30 assume !(1 == ~t1_pc~0); 3227239#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 3227237#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3227235#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3227234#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3227230#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3227228#L481-30 assume 1 == ~t2_pc~0; 3227225#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3227223#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3227221#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3227219#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3227217#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3227215#L500-30 assume !(1 == ~t3_pc~0); 3227213#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 3227211#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3227209#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3227207#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3227205#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3227203#L519-30 assume !(1 == ~t4_pc~0); 3227201#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 3227199#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3227197#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3227195#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3227193#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3227190#L538-30 assume !(1 == ~t5_pc~0); 3227186#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 3227184#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3227181#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3227179#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 3227176#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3227174#L557-30 assume !(1 == ~t6_pc~0); 3227172#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 3227170#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3227168#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3227166#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 3227164#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3227161#L576-30 assume !(1 == ~t7_pc~0); 3227159#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 3227156#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3227154#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3227152#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3227150#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3227148#L595-30 assume !(1 == ~t8_pc~0); 3227146#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 3227144#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3227142#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3227140#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3227139#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3227138#L614-30 assume !(1 == ~t9_pc~0); 3227134#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 3227132#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3227130#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3227128#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3227126#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3227124#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3227122#L1025-5 assume !(1 == ~T1_E~0); 3227120#L1030-3 assume !(1 == ~T2_E~0); 3227118#L1035-3 assume !(1 == ~T3_E~0); 3227116#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3227114#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3227112#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3227110#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3227108#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3227106#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3227104#L1070-3 assume !(1 == ~E_1~0); 3227102#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3227098#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3227096#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3227094#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3227092#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3227090#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3227088#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3227086#L1110-3 assume !(1 == ~E_9~0); 3227084#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3227070#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 3227068#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3227066#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 3227063#L1415 assume !(0 == start_simulation_~tmp~3#1); 3227060#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3227052#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 3227042#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3227040#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 3227038#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3227036#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3227034#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 3227032#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 3134812#L1396-2 [2021-12-06 17:45:35,987 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:35,987 INFO L85 PathProgramCache]: Analyzing trace with hash 1478968428, now seen corresponding path program 1 times [2021-12-06 17:45:35,987 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:35,987 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [560791121] [2021-12-06 17:45:35,987 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:35,987 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:35,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:45:36,004 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:45:36,004 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:45:36,005 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [560791121] [2021-12-06 17:45:36,005 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [560791121] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:45:36,005 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:45:36,005 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 17:45:36,005 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1028486838] [2021-12-06 17:45:36,005 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:45:36,005 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:45:36,005 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:36,005 INFO L85 PathProgramCache]: Analyzing trace with hash 641829950, now seen corresponding path program 1 times [2021-12-06 17:45:36,006 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:36,006 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1246964601] [2021-12-06 17:45:36,006 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:36,006 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:36,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:45:36,026 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:45:36,026 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:45:36,027 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1246964601] [2021-12-06 17:45:36,027 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1246964601] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:45:36,027 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:45:36,027 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 17:45:36,027 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [178784936] [2021-12-06 17:45:36,027 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:45:36,027 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:45:36,027 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:45:36,027 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:45:36,027 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:45:36,028 INFO L87 Difference]: Start difference. First operand 138581 states and 190468 transitions. cyclomatic complexity: 51919 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 2 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:36,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:45:36,209 INFO L93 Difference]: Finished difference Result 74096 states and 101937 transitions. [2021-12-06 17:45:36,209 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:45:36,209 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 74096 states and 101937 transitions. [2021-12-06 17:45:36,451 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 73618 [2021-12-06 17:45:36,603 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 74096 states to 74096 states and 101937 transitions. [2021-12-06 17:45:36,603 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 74096 [2021-12-06 17:45:36,640 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 74096 [2021-12-06 17:45:36,640 INFO L73 IsDeterministic]: Start isDeterministic. Operand 74096 states and 101937 transitions. [2021-12-06 17:45:36,671 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:45:36,672 INFO L681 BuchiCegarLoop]: Abstraction has 74096 states and 101937 transitions. [2021-12-06 17:45:36,705 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74096 states and 101937 transitions. [2021-12-06 17:45:37,227 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74096 to 74096. [2021-12-06 17:45:37,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 74096 states, 74096 states have (on average 1.3757422802850356) internal successors, (101937), 74095 states have internal predecessors, (101937), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:37,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74096 states to 74096 states and 101937 transitions. [2021-12-06 17:45:37,395 INFO L704 BuchiCegarLoop]: Abstraction has 74096 states and 101937 transitions. [2021-12-06 17:45:37,395 INFO L587 BuchiCegarLoop]: Abstraction has 74096 states and 101937 transitions. [2021-12-06 17:45:37,395 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-12-06 17:45:37,395 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 74096 states and 101937 transitions. [2021-12-06 17:45:37,572 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 73618 [2021-12-06 17:45:37,572 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:45:37,572 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:45:37,573 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:37,573 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:37,573 INFO L791 eck$LassoCheckResult]: Stem: 3347865#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 3347866#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 3347414#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3347415#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3348059#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 3348060#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3348038#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3347802#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3347803#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3347593#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3347594#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3348150#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3348019#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3347661#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3347420#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3347421#L922 assume !(0 == ~M_E~0); 3348234#L922-2 assume !(0 == ~T1_E~0); 3348235#L927-1 assume !(0 == ~T2_E~0); 3347873#L932-1 assume !(0 == ~T3_E~0); 3347738#L937-1 assume !(0 == ~T4_E~0); 3347739#L942-1 assume !(0 == ~T5_E~0); 3347801#L947-1 assume !(0 == ~T6_E~0); 3347877#L952-1 assume !(0 == ~T7_E~0); 3347878#L957-1 assume !(0 == ~T8_E~0); 3347957#L962-1 assume !(0 == ~T9_E~0); 3347712#L967-1 assume !(0 == ~E_1~0); 3347713#L972-1 assume !(0 == ~E_2~0); 3348046#L977-1 assume !(0 == ~E_3~0); 3348047#L982-1 assume !(0 == ~E_4~0); 3347190#L987-1 assume !(0 == ~E_5~0); 3347191#L992-1 assume !(0 == ~E_6~0); 3347197#L997-1 assume !(0 == ~E_7~0); 3347636#L1002-1 assume !(0 == ~E_8~0); 3347618#L1007-1 assume !(0 == ~E_9~0); 3346986#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3346987#L443 assume !(1 == ~m_pc~0); 3347897#L443-2 is_master_triggered_~__retres1~0#1 := 0; 3347883#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3347884#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3347351#L1140 assume !(0 != activate_threads_~tmp~1#1); 3347102#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3347103#L462 assume !(1 == ~t1_pc~0); 3347732#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3347733#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3347071#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3347072#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 3347574#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3347575#L481 assume !(1 == ~t2_pc~0); 3347346#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3347861#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3347735#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3347442#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 3347443#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3347549#L500 assume !(1 == ~t3_pc~0); 3348113#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3348074#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3348028#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3348029#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 3346991#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3346992#L519 assume !(1 == ~t4_pc~0); 3347786#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3347545#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3347546#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3347395#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 3347396#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3347156#L538 assume !(1 == ~t5_pc~0); 3347157#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3347061#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3347062#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3347331#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 3347332#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3347937#L557 assume !(1 == ~t6_pc~0); 3347367#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3347368#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3347274#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3347275#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 3347394#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3348197#L576 assume !(1 == ~t7_pc~0); 3347355#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3347356#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3347620#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3347621#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 3348006#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3347484#L595 assume !(1 == ~t8_pc~0); 3347485#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3348030#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3348031#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3347830#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 3347831#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3347283#L614 assume !(1 == ~t9_pc~0); 3347284#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3347181#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3347182#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3347359#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 3347444#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3347445#L1025 assume !(1 == ~M_E~0); 3347719#L1025-2 assume !(1 == ~T1_E~0); 3347779#L1030-1 assume !(1 == ~T2_E~0); 3347926#L1035-1 assume !(1 == ~T3_E~0); 3347439#L1040-1 assume !(1 == ~T4_E~0); 3347440#L1045-1 assume !(1 == ~T5_E~0); 3347342#L1050-1 assume !(1 == ~T6_E~0); 3347343#L1055-1 assume !(1 == ~T7_E~0); 3347165#L1060-1 assume !(1 == ~T8_E~0); 3347166#L1065-1 assume !(1 == ~T9_E~0); 3347227#L1070-1 assume !(1 == ~E_1~0); 3347879#L1075-1 assume !(1 == ~E_2~0); 3347880#L1080-1 assume !(1 == ~E_3~0); 3347868#L1085-1 assume !(1 == ~E_4~0); 3347869#L1090-1 assume !(1 == ~E_5~0); 3348142#L1095-1 assume !(1 == ~E_6~0); 3347908#L1100-1 assume !(1 == ~E_7~0); 3347909#L1105-1 assume !(1 == ~E_8~0); 3347138#L1110-1 assume !(1 == ~E_9~0); 3347139#L1115-1 assume { :end_inline_reset_delta_events } true; 3347495#L1396-2 [2021-12-06 17:45:37,574 INFO L793 eck$LassoCheckResult]: Loop: 3347495#L1396-2 assume !false; 3383147#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3383141#L897 assume !false; 3383140#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3383137#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 3383126#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3383124#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3383121#L766 assume !(0 != eval_~tmp~0#1); 3383122#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3383394#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3383393#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3383392#L922-5 assume !(0 == ~T1_E~0); 3383391#L927-3 assume !(0 == ~T2_E~0); 3383390#L932-3 assume !(0 == ~T3_E~0); 3383389#L937-3 assume !(0 == ~T4_E~0); 3383388#L942-3 assume !(0 == ~T5_E~0); 3383387#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3383386#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3383385#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3383383#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3383382#L967-3 assume !(0 == ~E_1~0); 3383381#L972-3 assume !(0 == ~E_2~0); 3383379#L977-3 assume !(0 == ~E_3~0); 3383377#L982-3 assume !(0 == ~E_4~0); 3383376#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3383375#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3383374#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3383373#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3383371#L1007-3 assume !(0 == ~E_9~0); 3383369#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3383367#L443-30 assume !(1 == ~m_pc~0); 3383365#L443-32 is_master_triggered_~__retres1~0#1 := 0; 3383363#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3383361#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3383359#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3383357#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3383355#L462-30 assume !(1 == ~t1_pc~0); 3383353#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 3383351#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3383349#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3383348#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3383345#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3383343#L481-30 assume !(1 == ~t2_pc~0); 3383340#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 3383338#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3383336#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3383334#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3383332#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3383330#L500-30 assume !(1 == ~t3_pc~0); 3383328#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 3383326#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3383324#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3383322#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3383320#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3383318#L519-30 assume !(1 == ~t4_pc~0); 3383316#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 3383314#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3383312#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3383310#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3383308#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3383305#L538-30 assume 1 == ~t5_pc~0; 3383303#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3383304#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3383384#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3383293#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3383291#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3383289#L557-30 assume !(1 == ~t6_pc~0); 3383287#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 3383285#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3383283#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3383281#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 3383279#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3383276#L576-30 assume !(1 == ~t7_pc~0); 3383274#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 3383271#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3383269#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3383267#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3383265#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3383263#L595-30 assume !(1 == ~t8_pc~0); 3383261#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 3383259#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3383257#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3383255#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3383254#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3383253#L614-30 assume !(1 == ~t9_pc~0); 3383249#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 3383247#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3383245#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3383243#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3383241#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3383239#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3383237#L1025-5 assume !(1 == ~T1_E~0); 3383235#L1030-3 assume !(1 == ~T2_E~0); 3383233#L1035-3 assume !(1 == ~T3_E~0); 3383231#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3383229#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3383227#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3383225#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3383223#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3383221#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3383219#L1070-3 assume !(1 == ~E_1~0); 3383217#L1075-3 assume !(1 == ~E_2~0); 3383215#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3383213#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3383211#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3383209#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3383207#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3383205#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3383203#L1110-3 assume !(1 == ~E_9~0); 3383201#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3383189#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 3383187#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3383185#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 3383182#L1415 assume !(0 == start_simulation_~tmp~3#1); 3383179#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3383173#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 3383163#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3383161#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 3383157#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3383155#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3383153#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 3383151#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 3347495#L1396-2 [2021-12-06 17:45:37,574 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:37,574 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 3 times [2021-12-06 17:45:37,574 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:37,574 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2014994995] [2021-12-06 17:45:37,574 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:37,574 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:37,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:45:37,581 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:45:37,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:45:37,608 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:45:37,608 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:37,609 INFO L85 PathProgramCache]: Analyzing trace with hash -1479137724, now seen corresponding path program 1 times [2021-12-06 17:45:37,609 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:37,609 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1096441791] [2021-12-06 17:45:37,609 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:37,609 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:37,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:45:37,628 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:45:37,628 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:45:37,628 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1096441791] [2021-12-06 17:45:37,628 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1096441791] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:45:37,628 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:45:37,628 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 17:45:37,628 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [438643140] [2021-12-06 17:45:37,628 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:45:37,628 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:45:37,629 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:45:37,629 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-06 17:45:37,629 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-06 17:45:37,629 INFO L87 Difference]: Start difference. First operand 74096 states and 101937 transitions. cyclomatic complexity: 27873 Second operand has 5 states, 5 states have (on average 24.4) internal successors, (122), 5 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:38,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:45:38,002 INFO L93 Difference]: Finished difference Result 134538 states and 183021 transitions. [2021-12-06 17:45:38,003 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-06 17:45:38,003 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 134538 states and 183021 transitions. [2021-12-06 17:45:38,624 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 133704 [2021-12-06 17:45:38,891 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 134538 states to 134538 states and 183021 transitions. [2021-12-06 17:45:38,891 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 134538 [2021-12-06 17:45:38,941 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 134538 [2021-12-06 17:45:38,941 INFO L73 IsDeterministic]: Start isDeterministic. Operand 134538 states and 183021 transitions. [2021-12-06 17:45:38,993 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:45:38,993 INFO L681 BuchiCegarLoop]: Abstraction has 134538 states and 183021 transitions. [2021-12-06 17:45:39,046 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134538 states and 183021 transitions. [2021-12-06 17:45:39,751 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134538 to 74420. [2021-12-06 17:45:39,791 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 74420 states, 74420 states have (on average 1.3741064230045688) internal successors, (102261), 74419 states have internal predecessors, (102261), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:39,913 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74420 states to 74420 states and 102261 transitions. [2021-12-06 17:45:39,913 INFO L704 BuchiCegarLoop]: Abstraction has 74420 states and 102261 transitions. [2021-12-06 17:45:39,913 INFO L587 BuchiCegarLoop]: Abstraction has 74420 states and 102261 transitions. [2021-12-06 17:45:39,913 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-12-06 17:45:39,913 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 74420 states and 102261 transitions. [2021-12-06 17:45:40,085 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 73942 [2021-12-06 17:45:40,085 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:45:40,085 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:45:40,086 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:40,086 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:40,087 INFO L791 eck$LassoCheckResult]: Stem: 3556507#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 3556508#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 3556063#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3556064#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3556702#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 3556703#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3556682#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3556453#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3556454#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3556240#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3556241#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3556786#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3556661#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3556309#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3556069#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3556070#L922 assume !(0 == ~M_E~0); 3556871#L922-2 assume !(0 == ~T1_E~0); 3556872#L927-1 assume !(0 == ~T2_E~0); 3556517#L932-1 assume !(0 == ~T3_E~0); 3556385#L937-1 assume !(0 == ~T4_E~0); 3556386#L942-1 assume !(0 == ~T5_E~0); 3556452#L947-1 assume !(0 == ~T6_E~0); 3556521#L952-1 assume !(0 == ~T7_E~0); 3556522#L957-1 assume !(0 == ~T8_E~0); 3556604#L962-1 assume !(0 == ~T9_E~0); 3556358#L967-1 assume !(0 == ~E_1~0); 3556359#L972-1 assume !(0 == ~E_2~0); 3556688#L977-1 assume !(0 == ~E_3~0); 3556689#L982-1 assume !(0 == ~E_4~0); 3555838#L987-1 assume !(0 == ~E_5~0); 3555839#L992-1 assume !(0 == ~E_6~0); 3555847#L997-1 assume !(0 == ~E_7~0); 3556283#L1002-1 assume !(0 == ~E_8~0); 3556268#L1007-1 assume !(0 == ~E_9~0); 3555636#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3555637#L443 assume !(1 == ~m_pc~0); 3556540#L443-2 is_master_triggered_~__retres1~0#1 := 0; 3556527#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3556528#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3556001#L1140 assume !(0 != activate_threads_~tmp~1#1); 3555751#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3555752#L462 assume !(1 == ~t1_pc~0); 3556376#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3556377#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3555721#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3555722#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 3556220#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3556221#L481 assume !(1 == ~t2_pc~0); 3555996#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3556504#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3556382#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3556092#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 3556093#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3556195#L500 assume !(1 == ~t3_pc~0); 3556751#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3556717#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3556673#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3556674#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 3555638#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3555639#L519 assume !(1 == ~t4_pc~0); 3556434#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3556193#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3556194#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3556043#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 3556044#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3555806#L538 assume !(1 == ~t5_pc~0); 3555807#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3555711#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3555712#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3555981#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 3555982#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3556583#L557 assume !(1 == ~t6_pc~0); 3556017#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3556018#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3555916#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3555917#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 3556042#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3556840#L576 assume !(1 == ~t7_pc~0); 3556005#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3556006#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3556272#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3556273#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 3556651#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3556136#L595 assume !(1 == ~t8_pc~0); 3556137#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3556675#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3556676#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3556481#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 3556482#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3555931#L614 assume !(1 == ~t9_pc~0); 3555932#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3555830#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3555831#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3556009#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 3556094#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3556095#L1025 assume !(1 == ~M_E~0); 3556368#L1025-2 assume !(1 == ~T1_E~0); 3556426#L1030-1 assume !(1 == ~T2_E~0); 3556575#L1035-1 assume !(1 == ~T3_E~0); 3556088#L1040-1 assume !(1 == ~T4_E~0); 3556089#L1045-1 assume !(1 == ~T5_E~0); 3555992#L1050-1 assume !(1 == ~T6_E~0); 3555993#L1055-1 assume !(1 == ~T7_E~0); 3555815#L1060-1 assume !(1 == ~T8_E~0); 3555816#L1065-1 assume !(1 == ~T9_E~0); 3555877#L1070-1 assume !(1 == ~E_1~0); 3556523#L1075-1 assume !(1 == ~E_2~0); 3556524#L1080-1 assume !(1 == ~E_3~0); 3556512#L1085-1 assume !(1 == ~E_4~0); 3556513#L1090-1 assume !(1 == ~E_5~0); 3556779#L1095-1 assume !(1 == ~E_6~0); 3556551#L1100-1 assume !(1 == ~E_7~0); 3556552#L1105-1 assume !(1 == ~E_8~0); 3555788#L1110-1 assume !(1 == ~E_9~0); 3555789#L1115-1 assume { :end_inline_reset_delta_events } true; 3555949#L1396-2 [2021-12-06 17:45:40,087 INFO L793 eck$LassoCheckResult]: Loop: 3555949#L1396-2 assume !false; 3556035#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3556062#L897 assume !false; 3556853#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3556704#L699 assume !(0 == ~m_st~0); 3556705#L703 assume !(0 == ~t1_st~0); 3556469#L707 assume !(0 == ~t2_st~0); 3555945#L711 assume !(0 == ~t3_st~0); 3555947#L715 assume !(0 == ~t4_st~0); 3556455#L719 assume !(0 == ~t5_st~0); 3556456#L723 assume !(0 == ~t6_st~0); 3556383#L727 assume !(0 == ~t7_st~0); 3556384#L731 assume !(0 == ~t8_st~0); 3556514#L735 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 3555658#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3555659#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3596275#L766 assume !(0 != eval_~tmp~0#1); 3629675#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3629868#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3629867#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3629866#L922-5 assume !(0 == ~T1_E~0); 3629865#L927-3 assume !(0 == ~T2_E~0); 3629864#L932-3 assume !(0 == ~T3_E~0); 3629863#L937-3 assume !(0 == ~T4_E~0); 3629862#L942-3 assume !(0 == ~T5_E~0); 3629861#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3629860#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3629859#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3629858#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3629857#L967-3 assume !(0 == ~E_1~0); 3629856#L972-3 assume !(0 == ~E_2~0); 3629855#L977-3 assume !(0 == ~E_3~0); 3629854#L982-3 assume !(0 == ~E_4~0); 3629853#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3629852#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3629851#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3629850#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3629849#L1007-3 assume !(0 == ~E_9~0); 3629848#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3629847#L443-30 assume !(1 == ~m_pc~0); 3629846#L443-32 is_master_triggered_~__retres1~0#1 := 0; 3629845#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3629844#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3629843#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3629842#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3629841#L462-30 assume !(1 == ~t1_pc~0); 3629840#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 3629839#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3629838#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3629837#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3629836#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3629835#L481-30 assume !(1 == ~t2_pc~0); 3629833#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 3629832#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3629831#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3629830#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3629829#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3629828#L500-30 assume !(1 == ~t3_pc~0); 3629827#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 3629826#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3629825#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3629824#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3629823#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3629822#L519-30 assume !(1 == ~t4_pc~0); 3629821#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 3629820#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3629819#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3629818#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3629817#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3629816#L538-30 assume 1 == ~t5_pc~0; 3629815#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3629814#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3629813#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3629812#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3629811#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3629810#L557-30 assume !(1 == ~t6_pc~0); 3629809#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 3629808#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3629807#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3629806#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 3629805#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3629804#L576-30 assume !(1 == ~t7_pc~0); 3629803#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 3629801#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3629800#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3629799#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3629798#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3629797#L595-30 assume !(1 == ~t8_pc~0); 3629796#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 3629795#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3629794#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3629793#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3629792#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3629791#L614-30 assume !(1 == ~t9_pc~0); 3629789#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 3629788#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3629787#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3629786#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3629785#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3629784#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3629783#L1025-5 assume !(1 == ~T1_E~0); 3629782#L1030-3 assume !(1 == ~T2_E~0); 3629781#L1035-3 assume !(1 == ~T3_E~0); 3629780#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3629779#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3629778#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3629777#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3629776#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3629775#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3629774#L1070-3 assume !(1 == ~E_1~0); 3629773#L1075-3 assume !(1 == ~E_2~0); 3629772#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3629771#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3629770#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3629769#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3629768#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3629767#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3629766#L1110-3 assume !(1 == ~E_9~0); 3556740#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3556741#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 3629755#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3629753#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 3629751#L1415 assume !(0 == start_simulation_~tmp~3#1); 3629729#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3629727#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 3629717#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3629715#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 3629713#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3556885#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3556421#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 3555948#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 3555949#L1396-2 [2021-12-06 17:45:40,087 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:40,087 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 4 times [2021-12-06 17:45:40,087 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:40,088 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1723954665] [2021-12-06 17:45:40,088 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:40,088 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:40,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:45:40,094 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:45:40,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:45:40,119 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:45:40,119 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:40,119 INFO L85 PathProgramCache]: Analyzing trace with hash -1108007923, now seen corresponding path program 1 times [2021-12-06 17:45:40,119 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:40,119 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1270593150] [2021-12-06 17:45:40,119 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:40,119 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:40,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:45:40,161 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:45:40,161 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:45:40,162 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1270593150] [2021-12-06 17:45:40,162 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1270593150] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:45:40,162 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:45:40,162 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 17:45:40,162 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [150614864] [2021-12-06 17:45:40,162 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:45:40,162 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:45:40,162 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:45:40,162 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-06 17:45:40,162 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-06 17:45:40,162 INFO L87 Difference]: Start difference. First operand 74420 states and 102261 transitions. cyclomatic complexity: 27873 Second operand has 5 states, 5 states have (on average 26.2) internal successors, (131), 5 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:40,546 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:45:40,547 INFO L93 Difference]: Finished difference Result 122532 states and 167616 transitions. [2021-12-06 17:45:40,547 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-06 17:45:40,547 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 122532 states and 167616 transitions. [2021-12-06 17:45:41,099 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 121926 [2021-12-06 17:45:41,287 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 122532 states to 122532 states and 167616 transitions. [2021-12-06 17:45:41,287 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 122532 [2021-12-06 17:45:41,327 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 122532 [2021-12-06 17:45:41,327 INFO L73 IsDeterministic]: Start isDeterministic. Operand 122532 states and 167616 transitions. [2021-12-06 17:45:41,363 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:45:41,363 INFO L681 BuchiCegarLoop]: Abstraction has 122532 states and 167616 transitions. [2021-12-06 17:45:41,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122532 states and 167616 transitions. [2021-12-06 17:45:41,933 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122532 to 75236. [2021-12-06 17:45:41,980 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 75236 states, 75236 states have (on average 1.3631772024031048) internal successors, (102560), 75235 states have internal predecessors, (102560), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:42,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75236 states to 75236 states and 102560 transitions. [2021-12-06 17:45:42,259 INFO L704 BuchiCegarLoop]: Abstraction has 75236 states and 102560 transitions. [2021-12-06 17:45:42,259 INFO L587 BuchiCegarLoop]: Abstraction has 75236 states and 102560 transitions. [2021-12-06 17:45:42,259 INFO L425 BuchiCegarLoop]: ======== Iteration 29============ [2021-12-06 17:45:42,259 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 75236 states and 102560 transitions. [2021-12-06 17:45:42,386 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 74758 [2021-12-06 17:45:42,386 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:45:42,386 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:45:42,387 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:42,387 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:42,388 INFO L791 eck$LassoCheckResult]: Stem: 3753469#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 3753470#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 3753026#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3753027#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3753672#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 3753673#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3753652#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3753415#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3753416#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3753202#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3753203#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3753766#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3753629#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3753270#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3753033#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3753034#L922 assume !(0 == ~M_E~0); 3753859#L922-2 assume !(0 == ~T1_E~0); 3753860#L927-1 assume !(0 == ~T2_E~0); 3753479#L932-1 assume !(0 == ~T3_E~0); 3753346#L937-1 assume !(0 == ~T4_E~0); 3753347#L942-1 assume !(0 == ~T5_E~0); 3753414#L947-1 assume !(0 == ~T6_E~0); 3753483#L952-1 assume !(0 == ~T7_E~0); 3753484#L957-1 assume !(0 == ~T8_E~0); 3753565#L962-1 assume !(0 == ~T9_E~0); 3753323#L967-1 assume !(0 == ~E_1~0); 3753324#L972-1 assume !(0 == ~E_2~0); 3753657#L977-1 assume !(0 == ~E_3~0); 3753658#L982-1 assume !(0 == ~E_4~0); 3752804#L987-1 assume !(0 == ~E_5~0); 3752805#L992-1 assume !(0 == ~E_6~0); 3752811#L997-1 assume !(0 == ~E_7~0); 3753245#L1002-1 assume !(0 == ~E_8~0); 3753227#L1007-1 assume !(0 == ~E_9~0); 3752601#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3752602#L443 assume !(1 == ~m_pc~0); 3753502#L443-2 is_master_triggered_~__retres1~0#1 := 0; 3753490#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3753491#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3752963#L1140 assume !(0 != activate_threads_~tmp~1#1); 3752716#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3752717#L462 assume !(1 == ~t1_pc~0); 3753341#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3753342#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3752686#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3752687#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 3753184#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3753185#L481 assume !(1 == ~t2_pc~0); 3752958#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3753465#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3753343#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3753054#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 3753055#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3753160#L500 assume !(1 == ~t3_pc~0); 3753727#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3753691#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3753642#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3753643#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 3752606#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3752607#L519 assume !(1 == ~t4_pc~0); 3753399#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3753156#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3753157#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3753007#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 3753008#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3752770#L538 assume !(1 == ~t5_pc~0); 3752771#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3752676#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3752677#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3752944#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 3752945#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3753545#L557 assume !(1 == ~t6_pc~0); 3752979#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3752980#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3752887#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3752888#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 3753006#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3753816#L576 assume !(1 == ~t7_pc~0); 3752967#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3752968#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3753230#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3753231#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 3753618#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3753096#L595 assume !(1 == ~t8_pc~0); 3753097#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3753644#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3753645#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3753440#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 3753441#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3752896#L614 assume !(1 == ~t9_pc~0); 3752897#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3752795#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3752796#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3752971#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 3753056#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3753057#L1025 assume !(1 == ~M_E~0); 3753330#L1025-2 assume !(1 == ~T1_E~0); 3753391#L1030-1 assume !(1 == ~T2_E~0); 3753537#L1035-1 assume !(1 == ~T3_E~0); 3753051#L1040-1 assume !(1 == ~T4_E~0); 3753052#L1045-1 assume !(1 == ~T5_E~0); 3752954#L1050-1 assume !(1 == ~T6_E~0); 3752955#L1055-1 assume !(1 == ~T7_E~0); 3752779#L1060-1 assume !(1 == ~T8_E~0); 3752780#L1065-1 assume !(1 == ~T9_E~0); 3752842#L1070-1 assume !(1 == ~E_1~0); 3753485#L1075-1 assume !(1 == ~E_2~0); 3753486#L1080-1 assume !(1 == ~E_3~0); 3753473#L1085-1 assume !(1 == ~E_4~0); 3753474#L1090-1 assume !(1 == ~E_5~0); 3753757#L1095-1 assume !(1 == ~E_6~0); 3753517#L1100-1 assume !(1 == ~E_7~0); 3753518#L1105-1 assume !(1 == ~E_8~0); 3752752#L1110-1 assume !(1 == ~E_9~0); 3752753#L1115-1 assume { :end_inline_reset_delta_events } true; 3753106#L1396-2 [2021-12-06 17:45:42,388 INFO L793 eck$LassoCheckResult]: Loop: 3753106#L1396-2 assume !false; 3783111#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3783106#L897 assume !false; 3783105#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3783104#L699 assume !(0 == ~m_st~0); 3783103#L703 assume !(0 == ~t1_st~0); 3783102#L707 assume !(0 == ~t2_st~0); 3783101#L711 assume !(0 == ~t3_st~0); 3783100#L715 assume !(0 == ~t4_st~0); 3783099#L719 assume !(0 == ~t5_st~0); 3783098#L723 assume !(0 == ~t6_st~0); 3783097#L727 assume !(0 == ~t7_st~0); 3783096#L731 assume !(0 == ~t8_st~0); 3783094#L735 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 3783093#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3783092#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3783090#L766 assume !(0 != eval_~tmp~0#1); 3783091#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3783250#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3783249#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3783248#L922-5 assume !(0 == ~T1_E~0); 3783247#L927-3 assume !(0 == ~T2_E~0); 3783246#L932-3 assume !(0 == ~T3_E~0); 3783245#L937-3 assume !(0 == ~T4_E~0); 3783244#L942-3 assume !(0 == ~T5_E~0); 3783243#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3783242#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3783241#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3783240#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3783239#L967-3 assume !(0 == ~E_1~0); 3783238#L972-3 assume !(0 == ~E_2~0); 3783237#L977-3 assume !(0 == ~E_3~0); 3783236#L982-3 assume !(0 == ~E_4~0); 3783235#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3783234#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3783233#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3783232#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3783231#L1007-3 assume !(0 == ~E_9~0); 3783230#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3783229#L443-30 assume !(1 == ~m_pc~0); 3783228#L443-32 is_master_triggered_~__retres1~0#1 := 0; 3783227#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3783226#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3783225#L1140-30 assume !(0 != activate_threads_~tmp~1#1); 3783224#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3783223#L462-30 assume !(1 == ~t1_pc~0); 3783222#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 3783221#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3783220#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3783219#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3783218#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3783217#L481-30 assume !(1 == ~t2_pc~0); 3783215#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 3783214#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3783213#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3783212#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3783211#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3783210#L500-30 assume !(1 == ~t3_pc~0); 3783209#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 3783208#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3783207#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3783206#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3783205#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3783204#L519-30 assume !(1 == ~t4_pc~0); 3783203#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 3783202#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3783201#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3783200#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3783199#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3783198#L538-30 assume !(1 == ~t5_pc~0); 3783195#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 3783194#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3783193#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3783192#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 3783190#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3783189#L557-30 assume !(1 == ~t6_pc~0); 3783188#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 3783187#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3783186#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3783185#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 3783184#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3783183#L576-30 assume 1 == ~t7_pc~0; 3783181#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3783180#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3783179#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3783178#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3783177#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3783176#L595-30 assume !(1 == ~t8_pc~0); 3783175#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 3783174#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3783173#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3783172#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3783171#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3783170#L614-30 assume !(1 == ~t9_pc~0); 3783168#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 3783167#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3783166#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3783165#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3783164#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3783163#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3783162#L1025-5 assume !(1 == ~T1_E~0); 3783161#L1030-3 assume !(1 == ~T2_E~0); 3783160#L1035-3 assume !(1 == ~T3_E~0); 3783159#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3783158#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3783157#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3783156#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3783155#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3783154#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3783153#L1070-3 assume !(1 == ~E_1~0); 3783152#L1075-3 assume !(1 == ~E_2~0); 3783151#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3783150#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3783149#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3783148#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3783147#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3783146#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3783145#L1110-3 assume !(1 == ~E_9~0); 3783144#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3783134#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 3783133#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3783132#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 3783130#L1415 assume !(0 == start_simulation_~tmp~3#1); 3783128#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3783126#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 3783117#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3783116#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 3783115#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3783114#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3783113#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 3783112#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 3753106#L1396-2 [2021-12-06 17:45:42,388 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:42,388 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 5 times [2021-12-06 17:45:42,388 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:42,388 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [101580544] [2021-12-06 17:45:42,389 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:42,389 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:42,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:45:42,401 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:45:42,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:45:42,432 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:45:42,432 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:42,432 INFO L85 PathProgramCache]: Analyzing trace with hash 1881090441, now seen corresponding path program 1 times [2021-12-06 17:45:42,432 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:42,432 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [646974637] [2021-12-06 17:45:42,432 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:42,432 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:42,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:45:42,452 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:45:42,452 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:45:42,452 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [646974637] [2021-12-06 17:45:42,452 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [646974637] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:45:42,452 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:45:42,452 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:45:42,453 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1111411427] [2021-12-06 17:45:42,453 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:45:42,453 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-06 17:45:42,453 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:45:42,453 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:45:42,453 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:45:42,453 INFO L87 Difference]: Start difference. First operand 75236 states and 102560 transitions. cyclomatic complexity: 27356 Second operand has 3 states, 3 states have (on average 43.666666666666664) internal successors, (131), 3 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:42,762 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:45:42,763 INFO L93 Difference]: Finished difference Result 129116 states and 173470 transitions. [2021-12-06 17:45:42,763 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:45:42,764 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 129116 states and 173470 transitions. [2021-12-06 17:45:43,198 INFO L131 ngComponentsAnalysis]: Automaton has 60 accepting balls. 128420 [2021-12-06 17:45:43,646 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 129116 states to 129116 states and 173470 transitions. [2021-12-06 17:45:43,647 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 129116 [2021-12-06 17:45:43,679 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 129116 [2021-12-06 17:45:43,679 INFO L73 IsDeterministic]: Start isDeterministic. Operand 129116 states and 173470 transitions. [2021-12-06 17:45:43,716 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:45:43,716 INFO L681 BuchiCegarLoop]: Abstraction has 129116 states and 173470 transitions. [2021-12-06 17:45:43,756 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 129116 states and 173470 transitions. [2021-12-06 17:45:44,592 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 129116 to 126956. [2021-12-06 17:45:44,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 126956 states, 126956 states have (on average 1.344324017769936) internal successors, (170670), 126955 states have internal predecessors, (170670), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:45,034 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 126956 states to 126956 states and 170670 transitions. [2021-12-06 17:45:45,034 INFO L704 BuchiCegarLoop]: Abstraction has 126956 states and 170670 transitions. [2021-12-06 17:45:45,034 INFO L587 BuchiCegarLoop]: Abstraction has 126956 states and 170670 transitions. [2021-12-06 17:45:45,034 INFO L425 BuchiCegarLoop]: ======== Iteration 30============ [2021-12-06 17:45:45,034 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 126956 states and 170670 transitions. [2021-12-06 17:45:45,278 INFO L131 ngComponentsAnalysis]: Automaton has 60 accepting balls. 126260 [2021-12-06 17:45:45,278 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:45:45,278 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:45:45,279 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:45,279 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:45,279 INFO L791 eck$LassoCheckResult]: Stem: 3957861#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 3957862#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 3957390#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3957391#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3958063#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 3958064#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3958042#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3957799#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3957800#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3957576#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3957577#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3958165#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3958018#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3957650#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3957397#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3957398#L922 assume !(0 == ~M_E~0); 3958273#L922-2 assume !(0 == ~T1_E~0); 3958274#L927-1 assume !(0 == ~T2_E~0); 3957871#L932-1 assume !(0 == ~T3_E~0); 3957730#L937-1 assume !(0 == ~T4_E~0); 3957731#L942-1 assume !(0 == ~T5_E~0); 3957798#L947-1 assume !(0 == ~T6_E~0); 3957876#L952-1 assume !(0 == ~T7_E~0); 3957877#L957-1 assume !(0 == ~T8_E~0); 3957953#L962-1 assume !(0 == ~T9_E~0); 3957701#L967-1 assume !(0 == ~E_1~0); 3957702#L972-1 assume !(0 == ~E_2~0); 3958047#L977-1 assume !(0 == ~E_3~0); 3958048#L982-1 assume !(0 == ~E_4~0); 3957162#L987-1 assume !(0 == ~E_5~0); 3957163#L992-1 assume !(0 == ~E_6~0); 3957171#L997-1 assume !(0 == ~E_7~0); 3957621#L1002-1 assume !(0 == ~E_8~0); 3957604#L1007-1 assume !(0 == ~E_9~0); 3956959#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3956960#L443 assume !(1 == ~m_pc~0); 3957897#L443-2 is_master_triggered_~__retres1~0#1 := 0; 3957882#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3957883#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3957329#L1140 assume !(0 != activate_threads_~tmp~1#1); 3957074#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3957075#L462 assume !(1 == ~t1_pc~0); 3957724#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3957725#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3957044#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3957045#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 3957557#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3957558#L481 assume !(1 == ~t2_pc~0); 3957324#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3957857#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3957727#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3957420#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 3957421#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3957531#L500 assume !(1 == ~t3_pc~0); 3958121#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3958080#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3958033#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3958034#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 3956964#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3956965#L519 assume !(1 == ~t4_pc~0); 3957783#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3957529#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3957530#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3957370#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 3957371#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3957130#L538 assume !(1 == ~t5_pc~0); 3957131#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3957034#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3957035#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3957309#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 3957310#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3957935#L557 assume !(1 == ~t6_pc~0); 3957345#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3957346#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3957245#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3957246#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 3957372#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3958230#L576 assume !(1 == ~t7_pc~0); 3957333#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3957334#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3957606#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3957607#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 3958007#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3957467#L595 assume !(1 == ~t8_pc~0); 3957468#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3958035#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3958036#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3957828#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 3957829#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3957258#L614 assume !(1 == ~t9_pc~0); 3957259#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3957155#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3957156#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3957337#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 3957422#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3957423#L1025 assume !(1 == ~M_E~0); 3957712#L1025-2 assume !(1 == ~T1_E~0); 3957774#L1030-1 assume !(1 == ~T2_E~0); 3957930#L1035-1 assume !(1 == ~T3_E~0); 3957416#L1040-1 assume !(1 == ~T4_E~0); 3957417#L1045-1 assume !(1 == ~T5_E~0); 3957320#L1050-1 assume !(1 == ~T6_E~0); 3957321#L1055-1 assume !(1 == ~T7_E~0); 3957139#L1060-1 assume !(1 == ~T8_E~0); 3957140#L1065-1 assume !(1 == ~T9_E~0); 3957204#L1070-1 assume !(1 == ~E_1~0); 3957878#L1075-1 assume !(1 == ~E_2~0); 3957879#L1080-1 assume !(1 == ~E_3~0); 3957866#L1085-1 assume !(1 == ~E_4~0); 3957867#L1090-1 assume !(1 == ~E_5~0); 3958159#L1095-1 assume !(1 == ~E_6~0); 3957909#L1100-1 assume !(1 == ~E_7~0); 3957910#L1105-1 assume !(1 == ~E_8~0); 3957112#L1110-1 assume !(1 == ~E_9~0); 3957113#L1115-1 assume { :end_inline_reset_delta_events } true; 3957478#L1396-2 assume !false; 4008195#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4008191#L897 [2021-12-06 17:45:45,279 INFO L793 eck$LassoCheckResult]: Loop: 4008191#L897 assume !false; 4008190#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 4008187#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4008185#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4008183#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4008181#L766 assume 0 != eval_~tmp~0#1; 4008178#L766-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 4008179#L774 assume !(0 != eval_~tmp_ndt_1~0#1); 4008172#L771 assume !(0 == ~t1_st~0); 4008171#L785 assume !(0 == ~t2_st~0); 3992586#L799 assume !(0 == ~t3_st~0); 3982377#L813 assume !(0 == ~t4_st~0); 3999412#L827 assume !(0 == ~t5_st~0); 3999407#L841 assume !(0 == ~t6_st~0); 3986511#L855 assume !(0 == ~t7_st~0); 3999400#L869 assume !(0 == ~t8_st~0); 3999398#L883 assume !(0 == ~t9_st~0); 4008191#L897 [2021-12-06 17:45:45,279 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:45,279 INFO L85 PathProgramCache]: Analyzing trace with hash -1585015822, now seen corresponding path program 1 times [2021-12-06 17:45:45,280 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:45,280 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [873513735] [2021-12-06 17:45:45,280 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:45,280 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:45,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:45:45,287 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:45:45,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:45:45,310 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:45:45,310 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:45,310 INFO L85 PathProgramCache]: Analyzing trace with hash -2124561948, now seen corresponding path program 1 times [2021-12-06 17:45:45,310 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:45,311 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [49820401] [2021-12-06 17:45:45,311 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:45,311 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:45,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:45:45,313 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:45:45,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:45:45,315 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:45:45,316 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:45,316 INFO L85 PathProgramCache]: Analyzing trace with hash 784690707, now seen corresponding path program 1 times [2021-12-06 17:45:45,316 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:45,316 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [714859531] [2021-12-06 17:45:45,316 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:45,316 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:45,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:45:45,336 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:45:45,336 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:45:45,336 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [714859531] [2021-12-06 17:45:45,337 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [714859531] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:45:45,337 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:45:45,337 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:45:45,337 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1510036042] [2021-12-06 17:45:45,337 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:45:45,414 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:45:45,415 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:45:45,415 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:45:45,415 INFO L87 Difference]: Start difference. First operand 126956 states and 170670 transitions. cyclomatic complexity: 43774 Second operand has 3 states, 3 states have (on average 44.666666666666664) internal successors, (134), 3 states have internal predecessors, (134), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:45,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:45:45,958 INFO L93 Difference]: Finished difference Result 245414 states and 327453 transitions. [2021-12-06 17:45:45,958 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:45:45,958 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 245414 states and 327453 transitions. [2021-12-06 17:45:46,898 INFO L131 ngComponentsAnalysis]: Automaton has 92 accepting balls. 237428 [2021-12-06 17:45:47,330 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 245414 states to 245414 states and 327453 transitions. [2021-12-06 17:45:47,330 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 245414 [2021-12-06 17:45:47,427 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 245414 [2021-12-06 17:45:47,427 INFO L73 IsDeterministic]: Start isDeterministic. Operand 245414 states and 327453 transitions. [2021-12-06 17:45:47,504 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:45:47,504 INFO L681 BuchiCegarLoop]: Abstraction has 245414 states and 327453 transitions. [2021-12-06 17:45:47,602 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 245414 states and 327453 transitions. [2021-12-06 17:45:49,307 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 245414 to 241046. [2021-12-06 17:45:49,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 241046 states, 241046 states have (on average 1.3351683910954755) internal successors, (321837), 241045 states have internal predecessors, (321837), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:49,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 241046 states to 241046 states and 321837 transitions. [2021-12-06 17:45:49,900 INFO L704 BuchiCegarLoop]: Abstraction has 241046 states and 321837 transitions. [2021-12-06 17:45:49,900 INFO L587 BuchiCegarLoop]: Abstraction has 241046 states and 321837 transitions. [2021-12-06 17:45:49,900 INFO L425 BuchiCegarLoop]: ======== Iteration 31============ [2021-12-06 17:45:49,900 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 241046 states and 321837 transitions. [2021-12-06 17:45:50,635 INFO L131 ngComponentsAnalysis]: Automaton has 92 accepting balls. 233060 [2021-12-06 17:45:50,635 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:45:50,635 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:45:50,636 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:50,636 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:50,637 INFO L791 eck$LassoCheckResult]: Stem: 4330239#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 4330240#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 4329772#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4329773#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4330452#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 4330453#L641-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 4330503#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4330177#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4330178#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4329958#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4329959#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4330577#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4330578#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4330026#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4330027#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4330733#L922 assume !(0 == ~M_E~0); 4330734#L922-2 assume !(0 == ~T1_E~0); 4330703#L927-1 assume !(0 == ~T2_E~0); 4330704#L932-1 assume !(0 == ~T3_E~0); 4330111#L937-1 assume !(0 == ~T4_E~0); 4330112#L942-1 assume !(0 == ~T5_E~0); 4330456#L947-1 assume !(0 == ~T6_E~0); 4330457#L952-1 assume !(0 == ~T7_E~0); 4330339#L957-1 assume !(0 == ~T8_E~0); 4330340#L962-1 assume !(0 == ~T9_E~0); 4330084#L967-1 assume !(0 == ~E_1~0); 4330085#L972-1 assume !(0 == ~E_2~0); 4330438#L977-1 assume !(0 == ~E_3~0); 4330439#L982-1 assume !(0 == ~E_4~0); 4329540#L987-1 assume !(0 == ~E_5~0); 4329541#L992-1 assume !(0 == ~E_6~0); 4330001#L997-1 assume !(0 == ~E_7~0); 4330002#L1002-1 assume !(0 == ~E_8~0); 4329985#L1007-1 assume !(0 == ~E_9~0); 4329986#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4330603#L443 assume !(1 == ~m_pc~0); 4330604#L443-2 is_master_triggered_~__retres1~0#1 := 0; 4330261#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4330262#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4329706#L1140 assume !(0 != activate_threads_~tmp~1#1); 4329707#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4330618#L462 assume !(1 == ~t1_pc~0); 4330619#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4330650#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4330651#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4330283#L1148 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4329938#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4329939#L481 assume !(1 == ~t2_pc~0); 4330508#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4330509#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4330107#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4330108#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 4329911#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4329912#L500 assume !(1 == ~t3_pc~0); 4330525#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4330526#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4330420#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4330421#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 4329342#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4329343#L519 assume !(1 == ~t4_pc~0); 4330158#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4330159#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4330290#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4330291#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 4330204#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4330205#L538 assume !(1 == ~t5_pc~0); 4329936#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4330554#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4330662#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4330663#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 4330319#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4330320#L557 assume !(1 == ~t6_pc~0); 4329725#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4329726#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4329626#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4329627#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 4330638#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4330639#L576 assume !(1 == ~t7_pc~0); 4329711#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4329712#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4329988#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4329989#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 4330389#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4330390#L595 assume !(1 == ~t8_pc~0); 4330689#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4330690#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4330573#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4330574#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 4330641#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4330642#L614 assume !(1 == ~t9_pc~0); 4330137#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4330138#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4329715#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4329716#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 4329803#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4329804#L1025 assume !(1 == ~M_E~0); 4330150#L1025-2 assume !(1 == ~T1_E~0); 4330151#L1030-1 assume !(1 == ~T2_E~0); 4330479#L1035-1 assume !(1 == ~T3_E~0); 4330480#L1040-1 assume !(1 == ~T4_E~0); 4330461#L1045-1 assume !(1 == ~T5_E~0); 4330462#L1050-1 assume !(1 == ~T6_E~0); 4329900#L1055-1 assume !(1 == ~T7_E~0); 4329901#L1060-1 assume !(1 == ~T8_E~0); 4329580#L1065-1 assume !(1 == ~T9_E~0); 4329581#L1070-1 assume !(1 == ~E_1~0); 4330257#L1075-1 assume !(1 == ~E_2~0); 4330258#L1080-1 assume !(1 == ~E_3~0); 4330244#L1085-1 assume !(1 == ~E_4~0); 4330245#L1090-1 assume !(1 == ~E_5~0); 4330669#L1095-1 assume !(1 == ~E_6~0); 4330670#L1100-1 assume !(1 == ~E_7~0); 4330299#L1105-1 assume !(1 == ~E_8~0); 4330300#L1110-1 assume !(1 == ~E_9~0); 4329856#L1115-1 assume { :end_inline_reset_delta_events } true; 4329857#L1396-2 assume !false; 4335983#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4335976#L897 [2021-12-06 17:45:50,637 INFO L793 eck$LassoCheckResult]: Loop: 4335976#L897 assume !false; 4335973#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 4335969#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4335964#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4335965#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4335955#L766 assume 0 != eval_~tmp~0#1; 4335956#L766-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 4335947#L774 assume !(0 != eval_~tmp_ndt_1~0#1); 4335949#L771 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 4369416#L788 assume !(0 != eval_~tmp_ndt_2~0#1); 4369417#L785 assume !(0 == ~t2_st~0); 4336195#L799 assume !(0 == ~t3_st~0); 4334939#L813 assume !(0 == ~t4_st~0); 4336823#L827 assume !(0 == ~t5_st~0); 4336820#L841 assume !(0 == ~t6_st~0); 4369557#L855 assume !(0 == ~t7_st~0); 4369553#L869 assume !(0 == ~t8_st~0); 4335982#L883 assume !(0 == ~t9_st~0); 4335976#L897 [2021-12-06 17:45:50,637 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:50,637 INFO L85 PathProgramCache]: Analyzing trace with hash -1190560270, now seen corresponding path program 1 times [2021-12-06 17:45:50,637 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:50,637 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1837078314] [2021-12-06 17:45:50,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:50,637 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:50,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:45:50,652 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:45:50,652 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:45:50,652 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1837078314] [2021-12-06 17:45:50,652 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1837078314] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:45:50,652 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:45:50,652 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:45:50,652 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1431849235] [2021-12-06 17:45:50,652 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:45:50,653 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-06 17:45:50,653 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:50,653 INFO L85 PathProgramCache]: Analyzing trace with hash 224313463, now seen corresponding path program 1 times [2021-12-06 17:45:50,653 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:50,653 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [652741656] [2021-12-06 17:45:50,653 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:50,653 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:50,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:45:50,655 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:45:50,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:45:50,658 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:45:50,746 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:45:50,746 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:45:50,747 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:45:50,747 INFO L87 Difference]: Start difference. First operand 241046 states and 321837 transitions. cyclomatic complexity: 80883 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:51,224 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:45:51,224 INFO L93 Difference]: Finished difference Result 197656 states and 263705 transitions. [2021-12-06 17:45:51,224 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:45:51,225 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 197656 states and 263705 transitions. [2021-12-06 17:45:52,114 INFO L131 ngComponentsAnalysis]: Automaton has 60 accepting balls. 196552 [2021-12-06 17:45:52,521 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 197656 states to 197656 states and 263705 transitions. [2021-12-06 17:45:52,521 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 197656 [2021-12-06 17:45:52,623 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 197656 [2021-12-06 17:45:52,623 INFO L73 IsDeterministic]: Start isDeterministic. Operand 197656 states and 263705 transitions. [2021-12-06 17:45:52,700 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:45:52,700 INFO L681 BuchiCegarLoop]: Abstraction has 197656 states and 263705 transitions. [2021-12-06 17:45:52,793 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 197656 states and 263705 transitions. [2021-12-06 17:45:54,063 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 197656 to 197656. [2021-12-06 17:45:54,194 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 197656 states, 197656 states have (on average 1.3341613712712996) internal successors, (263705), 197655 states have internal predecessors, (263705), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:54,714 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 197656 states to 197656 states and 263705 transitions. [2021-12-06 17:45:54,714 INFO L704 BuchiCegarLoop]: Abstraction has 197656 states and 263705 transitions. [2021-12-06 17:45:54,714 INFO L587 BuchiCegarLoop]: Abstraction has 197656 states and 263705 transitions. [2021-12-06 17:45:54,714 INFO L425 BuchiCegarLoop]: ======== Iteration 32============ [2021-12-06 17:45:54,714 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 197656 states and 263705 transitions. [2021-12-06 17:45:55,102 INFO L131 ngComponentsAnalysis]: Automaton has 60 accepting balls. 196552 [2021-12-06 17:45:55,102 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:45:55,102 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:45:55,103 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:55,103 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:45:55,103 INFO L791 eck$LassoCheckResult]: Stem: 4768930#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 4768931#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 4768477#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4768478#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4769126#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 4769127#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4769102#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4768867#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4768868#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4768657#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4768658#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4769225#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4769083#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4768728#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4768483#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4768484#L922 assume !(0 == ~M_E~0); 4769331#L922-2 assume !(0 == ~T1_E~0); 4769332#L927-1 assume !(0 == ~T2_E~0); 4768941#L932-1 assume !(0 == ~T3_E~0); 4768806#L937-1 assume !(0 == ~T4_E~0); 4768807#L942-1 assume !(0 == ~T5_E~0); 4768866#L947-1 assume !(0 == ~T6_E~0); 4768946#L952-1 assume !(0 == ~T7_E~0); 4768947#L957-1 assume !(0 == ~T8_E~0); 4769025#L962-1 assume !(0 == ~T9_E~0); 4768776#L967-1 assume !(0 == ~E_1~0); 4768777#L972-1 assume !(0 == ~E_2~0); 4769112#L977-1 assume !(0 == ~E_3~0); 4769113#L982-1 assume !(0 == ~E_4~0); 4768246#L987-1 assume !(0 == ~E_5~0); 4768247#L992-1 assume !(0 == ~E_6~0); 4768255#L997-1 assume !(0 == ~E_7~0); 4768701#L1002-1 assume !(0 == ~E_8~0); 4768684#L1007-1 assume !(0 == ~E_9~0); 4768045#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4768046#L443 assume !(1 == ~m_pc~0); 4768966#L443-2 is_master_triggered_~__retres1~0#1 := 0; 4768952#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4768953#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4768415#L1140 assume !(0 != activate_threads_~tmp~1#1); 4768160#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4768161#L462 assume !(1 == ~t1_pc~0); 4768798#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4768799#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4768130#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4768131#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 4768639#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4768640#L481 assume !(1 == ~t2_pc~0); 4768409#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4768926#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4768803#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4768507#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 4768508#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4768612#L500 assume !(1 == ~t3_pc~0); 4769185#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4769145#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4769093#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4769094#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 4768050#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4768051#L519 assume !(1 == ~t4_pc~0); 4768853#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4768610#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4768611#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4768455#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 4768456#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4768214#L538 assume !(1 == ~t5_pc~0); 4768215#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4768120#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4768121#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4768394#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 4768395#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4769004#L557 assume !(1 == ~t6_pc~0); 4768431#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4768432#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4768330#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4768331#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 4768457#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4769276#L576 assume !(1 == ~t7_pc~0); 4768419#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4768420#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4768686#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4768687#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 4769071#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4768550#L595 assume !(1 == ~t8_pc~0); 4768551#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4769095#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4769096#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4768894#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 4768895#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4768343#L614 assume !(1 == ~t9_pc~0); 4768344#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4768239#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4768240#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4768423#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 4768509#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4768510#L1025 assume !(1 == ~M_E~0); 4768788#L1025-2 assume !(1 == ~T1_E~0); 4768846#L1030-1 assume !(1 == ~T2_E~0); 4769000#L1035-1 assume !(1 == ~T3_E~0); 4768503#L1040-1 assume !(1 == ~T4_E~0); 4768504#L1045-1 assume !(1 == ~T5_E~0); 4768405#L1050-1 assume !(1 == ~T6_E~0); 4768406#L1055-1 assume !(1 == ~T7_E~0); 4768223#L1060-1 assume !(1 == ~T8_E~0); 4768224#L1065-1 assume !(1 == ~T9_E~0); 4768287#L1070-1 assume !(1 == ~E_1~0); 4768948#L1075-1 assume !(1 == ~E_2~0); 4768949#L1080-1 assume !(1 == ~E_3~0); 4768935#L1085-1 assume !(1 == ~E_4~0); 4768936#L1090-1 assume !(1 == ~E_5~0); 4769216#L1095-1 assume !(1 == ~E_6~0); 4768980#L1100-1 assume !(1 == ~E_7~0); 4768981#L1105-1 assume !(1 == ~E_8~0); 4768196#L1110-1 assume !(1 == ~E_9~0); 4768197#L1115-1 assume { :end_inline_reset_delta_events } true; 4768562#L1396-2 assume !false; 4900137#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4900131#L897 [2021-12-06 17:45:55,104 INFO L793 eck$LassoCheckResult]: Loop: 4900131#L897 assume !false; 4900129#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 4900126#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4900124#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4900122#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4900121#L766 assume 0 != eval_~tmp~0#1; 4900116#L766-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 4900117#L774 assume !(0 != eval_~tmp_ndt_1~0#1); 4839098#L771 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 4839099#L788 assume !(0 != eval_~tmp_ndt_2~0#1); 4867302#L785 assume !(0 == ~t2_st~0); 4867297#L799 assume !(0 == ~t3_st~0); 4867291#L813 assume !(0 == ~t4_st~0); 4867285#L827 assume !(0 == ~t5_st~0); 4867279#L841 assume !(0 == ~t6_st~0); 4866726#L855 assume !(0 == ~t7_st~0); 4900145#L869 assume !(0 == ~t8_st~0); 4900136#L883 assume !(0 == ~t9_st~0); 4900131#L897 [2021-12-06 17:45:55,104 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:55,104 INFO L85 PathProgramCache]: Analyzing trace with hash -1585015822, now seen corresponding path program 2 times [2021-12-06 17:45:55,104 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:55,104 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1595413636] [2021-12-06 17:45:55,104 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:55,104 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:55,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:45:55,111 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:45:55,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:45:55,135 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:45:55,135 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:55,135 INFO L85 PathProgramCache]: Analyzing trace with hash 224313463, now seen corresponding path program 2 times [2021-12-06 17:45:55,136 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:55,136 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [753529354] [2021-12-06 17:45:55,136 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:55,136 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:55,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:45:55,138 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:45:55,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:45:55,140 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:45:55,141 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:45:55,141 INFO L85 PathProgramCache]: Analyzing trace with hash 216832552, now seen corresponding path program 1 times [2021-12-06 17:45:55,141 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:45:55,141 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1242797641] [2021-12-06 17:45:55,141 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:45:55,141 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:45:55,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:45:55,160 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:45:55,160 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:45:55,160 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1242797641] [2021-12-06 17:45:55,160 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1242797641] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:45:55,160 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:45:55,160 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:45:55,161 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1333375208] [2021-12-06 17:45:55,161 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:45:55,244 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:45:55,244 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:45:55,245 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:45:55,245 INFO L87 Difference]: Start difference. First operand 197656 states and 263705 transitions. cyclomatic complexity: 66109 Second operand has 3 states, 3 states have (on average 45.0) internal successors, (135), 3 states have internal predecessors, (135), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:45:56,396 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:45:56,396 INFO L93 Difference]: Finished difference Result 380320 states and 506069 transitions. [2021-12-06 17:45:56,396 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:45:56,397 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 380320 states and 506069 transitions. [2021-12-06 17:45:57,819 INFO L131 ngComponentsAnalysis]: Automaton has 60 accepting balls. 378236 [2021-12-06 17:45:58,437 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 380320 states to 380320 states and 506069 transitions. [2021-12-06 17:45:58,437 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 380320 [2021-12-06 17:45:58,581 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 380320 [2021-12-06 17:45:58,582 INFO L73 IsDeterministic]: Start isDeterministic. Operand 380320 states and 506069 transitions. [2021-12-06 17:45:58,701 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:45:58,701 INFO L681 BuchiCegarLoop]: Abstraction has 380320 states and 506069 transitions. [2021-12-06 17:45:58,841 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 380320 states and 506069 transitions. [2021-12-06 17:46:00,994 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 380320 to 361000. [2021-12-06 17:46:01,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 361000 states, 361000 states have (on average 1.33304432132964) internal successors, (481229), 360999 states have internal predecessors, (481229), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:46:02,152 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 361000 states to 361000 states and 481229 transitions. [2021-12-06 17:46:02,152 INFO L704 BuchiCegarLoop]: Abstraction has 361000 states and 481229 transitions. [2021-12-06 17:46:02,152 INFO L587 BuchiCegarLoop]: Abstraction has 361000 states and 481229 transitions. [2021-12-06 17:46:02,152 INFO L425 BuchiCegarLoop]: ======== Iteration 33============ [2021-12-06 17:46:02,152 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 361000 states and 481229 transitions. [2021-12-06 17:46:03,250 INFO L131 ngComponentsAnalysis]: Automaton has 60 accepting balls. 358916 [2021-12-06 17:46:03,250 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:46:03,250 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:46:03,251 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:46:03,251 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:46:03,251 INFO L791 eck$LassoCheckResult]: Stem: 5346926#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 5346927#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 5346461#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5346462#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5347122#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 5347123#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5347100#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5346866#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5346867#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5346645#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5346646#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 5347223#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 5347077#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 5346717#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5346468#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5346469#L922 assume !(0 == ~M_E~0); 5347330#L922-2 assume !(0 == ~T1_E~0); 5347331#L927-1 assume !(0 == ~T2_E~0); 5346935#L932-1 assume !(0 == ~T3_E~0); 5346798#L937-1 assume !(0 == ~T4_E~0); 5346799#L942-1 assume !(0 == ~T5_E~0); 5346865#L947-1 assume !(0 == ~T6_E~0); 5346939#L952-1 assume !(0 == ~T7_E~0); 5346940#L957-1 assume !(0 == ~T8_E~0); 5347015#L962-1 assume !(0 == ~T9_E~0); 5346766#L967-1 assume !(0 == ~E_1~0); 5346767#L972-1 assume !(0 == ~E_2~0); 5347105#L977-1 assume !(0 == ~E_3~0); 5347106#L982-1 assume !(0 == ~E_4~0); 5346234#L987-1 assume !(0 == ~E_5~0); 5346235#L992-1 assume !(0 == ~E_6~0); 5346243#L997-1 assume !(0 == ~E_7~0); 5346688#L1002-1 assume !(0 == ~E_8~0); 5346672#L1007-1 assume !(0 == ~E_9~0); 5346029#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5346030#L443 assume !(1 == ~m_pc~0); 5346959#L443-2 is_master_triggered_~__retres1~0#1 := 0; 5346945#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5346946#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5346400#L1140 assume !(0 != activate_threads_~tmp~1#1); 5346146#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5346147#L462 assume !(1 == ~t1_pc~0); 5346790#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5346791#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5346114#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5346115#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 5346625#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5346626#L481 assume !(1 == ~t2_pc~0); 5346395#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5346922#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5346795#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5346490#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 5346491#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5346599#L500 assume !(1 == ~t3_pc~0); 5347183#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5347140#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5347091#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5347092#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 5346034#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5346035#L519 assume !(1 == ~t4_pc~0); 5346850#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5346597#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5346598#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5346441#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 5346442#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5346202#L538 assume !(1 == ~t5_pc~0); 5346203#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5346104#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5346105#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5346380#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 5346381#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5346997#L557 assume !(1 == ~t6_pc~0); 5346416#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5346417#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5346319#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5346320#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 5346443#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5347280#L576 assume !(1 == ~t7_pc~0); 5346404#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5346405#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5346674#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5346675#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 5347065#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5346535#L595 assume !(1 == ~t8_pc~0); 5346536#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5347093#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5347094#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5346894#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 5346895#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5346330#L614 assume !(1 == ~t9_pc~0); 5346331#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 5346227#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5346228#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5346408#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 5346492#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5346493#L1025 assume !(1 == ~M_E~0); 5346778#L1025-2 assume !(1 == ~T1_E~0); 5346842#L1030-1 assume !(1 == ~T2_E~0); 5346991#L1035-1 assume !(1 == ~T3_E~0); 5346487#L1040-1 assume !(1 == ~T4_E~0); 5346488#L1045-1 assume !(1 == ~T5_E~0); 5346391#L1050-1 assume !(1 == ~T6_E~0); 5346392#L1055-1 assume !(1 == ~T7_E~0); 5346211#L1060-1 assume !(1 == ~T8_E~0); 5346212#L1065-1 assume !(1 == ~T9_E~0); 5346275#L1070-1 assume !(1 == ~E_1~0); 5346941#L1075-1 assume !(1 == ~E_2~0); 5346942#L1080-1 assume !(1 == ~E_3~0); 5346929#L1085-1 assume !(1 == ~E_4~0); 5346930#L1090-1 assume !(1 == ~E_5~0); 5347215#L1095-1 assume !(1 == ~E_6~0); 5346972#L1100-1 assume !(1 == ~E_7~0); 5346973#L1105-1 assume !(1 == ~E_8~0); 5346183#L1110-1 assume !(1 == ~E_9~0); 5346184#L1115-1 assume { :end_inline_reset_delta_events } true; 5346546#L1396-2 assume !false; 5357759#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5357760#L897 [2021-12-06 17:46:03,251 INFO L793 eck$LassoCheckResult]: Loop: 5357760#L897 assume !false; 5441788#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5441785#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 5441783#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 5441781#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5441779#L766 assume 0 != eval_~tmp~0#1; 5441776#L766-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 5441774#L774 assume !(0 != eval_~tmp_ndt_1~0#1); 5441772#L771 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 5441770#L788 assume !(0 != eval_~tmp_ndt_2~0#1); 5441768#L785 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 5437434#L802 assume !(0 != eval_~tmp_ndt_3~0#1); 5441764#L799 assume !(0 == ~t3_st~0); 5441358#L813 assume !(0 == ~t4_st~0); 5441813#L827 assume !(0 == ~t5_st~0); 5441807#L841 assume !(0 == ~t6_st~0); 5441803#L855 assume !(0 == ~t7_st~0); 5441798#L869 assume !(0 == ~t8_st~0); 5441794#L883 assume !(0 == ~t9_st~0); 5357760#L897 [2021-12-06 17:46:03,252 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:46:03,252 INFO L85 PathProgramCache]: Analyzing trace with hash -1585015822, now seen corresponding path program 3 times [2021-12-06 17:46:03,252 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:46:03,252 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [468077251] [2021-12-06 17:46:03,252 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:46:03,252 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:46:03,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:46:03,264 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:46:03,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:46:03,291 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:46:03,292 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:46:03,292 INFO L85 PathProgramCache]: Analyzing trace with hash -1998261183, now seen corresponding path program 1 times [2021-12-06 17:46:03,292 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:46:03,292 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1213587230] [2021-12-06 17:46:03,292 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:46:03,292 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:46:03,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:46:03,294 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:46:03,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:46:03,297 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:46:03,298 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:46:03,298 INFO L85 PathProgramCache]: Analyzing trace with hash 2064797872, now seen corresponding path program 1 times [2021-12-06 17:46:03,298 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:46:03,298 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [877437665] [2021-12-06 17:46:03,298 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:46:03,298 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:46:03,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:46:03,320 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:46:03,320 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:46:03,321 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [877437665] [2021-12-06 17:46:03,321 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [877437665] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:46:03,321 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:46:03,321 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:46:03,321 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [632001074] [2021-12-06 17:46:03,321 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:46:03,421 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:46:03,421 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:46:03,421 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:46:03,421 INFO L87 Difference]: Start difference. First operand 361000 states and 481229 transitions. cyclomatic complexity: 120289 Second operand has 3 states, 3 states have (on average 45.333333333333336) internal successors, (136), 3 states have internal predecessors, (136), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:46:04,950 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:46:04,950 INFO L93 Difference]: Finished difference Result 588132 states and 782925 transitions. [2021-12-06 17:46:04,950 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:46:04,951 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 588132 states and 782925 transitions. [2021-12-06 17:46:07,232 INFO L131 ngComponentsAnalysis]: Automaton has 60 accepting balls. 584688 [2021-12-06 17:46:08,183 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 588132 states to 588132 states and 782925 transitions. [2021-12-06 17:46:08,183 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 588132 [2021-12-06 17:46:08,382 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 588132 [2021-12-06 17:46:08,383 INFO L73 IsDeterministic]: Start isDeterministic. Operand 588132 states and 782925 transitions. [2021-12-06 17:46:08,731 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:46:08,731 INFO L681 BuchiCegarLoop]: Abstraction has 588132 states and 782925 transitions. [2021-12-06 17:46:08,915 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 588132 states and 782925 transitions. [2021-12-06 17:46:12,356 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 588132 to 576772. [2021-12-06 17:46:12,603 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 576772 states, 576772 states have (on average 1.3320428176125054) internal successors, (768285), 576771 states have internal predecessors, (768285), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:46:14,056 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 576772 states to 576772 states and 768285 transitions. [2021-12-06 17:46:14,056 INFO L704 BuchiCegarLoop]: Abstraction has 576772 states and 768285 transitions. [2021-12-06 17:46:14,056 INFO L587 BuchiCegarLoop]: Abstraction has 576772 states and 768285 transitions. [2021-12-06 17:46:14,056 INFO L425 BuchiCegarLoop]: ======== Iteration 34============ [2021-12-06 17:46:14,056 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 576772 states and 768285 transitions. [2021-12-06 17:46:15,485 INFO L131 ngComponentsAnalysis]: Automaton has 60 accepting balls. 573328 [2021-12-06 17:46:15,485 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:46:15,485 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:46:15,486 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:46:15,486 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:46:15,487 INFO L791 eck$LassoCheckResult]: Stem: 6296051#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 6296052#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 6295598#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6295599#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6296238#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 6296239#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6296216#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6295992#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6295993#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6295773#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6295774#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 6296335#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 6296194#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 6295838#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 6295604#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6295605#L922 assume !(0 == ~M_E~0); 6296429#L922-2 assume !(0 == ~T1_E~0); 6296430#L927-1 assume !(0 == ~T2_E~0); 6296062#L932-1 assume !(0 == ~T3_E~0); 6295917#L937-1 assume !(0 == ~T4_E~0); 6295918#L942-1 assume !(0 == ~T5_E~0); 6295991#L947-1 assume !(0 == ~T6_E~0); 6296066#L952-1 assume !(0 == ~T7_E~0); 6296067#L957-1 assume !(0 == ~T8_E~0); 6296137#L962-1 assume !(0 == ~T9_E~0); 6295888#L967-1 assume !(0 == ~E_1~0); 6295889#L972-1 assume !(0 == ~E_2~0); 6296223#L977-1 assume !(0 == ~E_3~0); 6296224#L982-1 assume !(0 == ~E_4~0); 6295371#L987-1 assume !(0 == ~E_5~0); 6295372#L992-1 assume !(0 == ~E_6~0); 6295380#L997-1 assume !(0 == ~E_7~0); 6295812#L1002-1 assume !(0 == ~E_8~0); 6295798#L1007-1 assume !(0 == ~E_9~0); 6295169#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6295170#L443 assume !(1 == ~m_pc~0); 6296087#L443-2 is_master_triggered_~__retres1~0#1 := 0; 6296073#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6296074#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6295535#L1140 assume !(0 != activate_threads_~tmp~1#1); 6295284#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6295285#L462 assume !(1 == ~t1_pc~0); 6295907#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6295908#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6295254#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6295255#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 6295754#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6295755#L481 assume !(1 == ~t2_pc~0); 6295530#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6296048#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6295913#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6295626#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 6295627#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6295728#L500 assume !(1 == ~t3_pc~0); 6296291#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6296254#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6296206#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6296207#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 6295171#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6295172#L519 assume !(1 == ~t4_pc~0); 6295971#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6295726#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6295727#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6295576#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 6295577#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6295339#L538 assume !(1 == ~t5_pc~0); 6295340#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 6295244#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6295245#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6295515#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 6295516#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6296121#L557 assume !(1 == ~t6_pc~0); 6295551#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6295552#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6295452#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6295453#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 6295578#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6296391#L576 assume !(1 == ~t7_pc~0); 6295539#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 6295540#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6295801#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6295802#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 6296184#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6295665#L595 assume !(1 == ~t8_pc~0); 6295666#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 6296208#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6296209#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6296020#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 6296021#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6295467#L614 assume !(1 == ~t9_pc~0); 6295468#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 6295363#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6295364#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6295543#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 6295628#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6295629#L1025 assume !(1 == ~M_E~0); 6295899#L1025-2 assume !(1 == ~T1_E~0); 6295961#L1030-1 assume !(1 == ~T2_E~0); 6296114#L1035-1 assume !(1 == ~T3_E~0); 6295621#L1040-1 assume !(1 == ~T4_E~0); 6295622#L1045-1 assume !(1 == ~T5_E~0); 6295526#L1050-1 assume !(1 == ~T6_E~0); 6295527#L1055-1 assume !(1 == ~T7_E~0); 6295348#L1060-1 assume !(1 == ~T8_E~0); 6295349#L1065-1 assume !(1 == ~T9_E~0); 6295412#L1070-1 assume !(1 == ~E_1~0); 6296068#L1075-1 assume !(1 == ~E_2~0); 6296069#L1080-1 assume !(1 == ~E_3~0); 6296056#L1085-1 assume !(1 == ~E_4~0); 6296057#L1090-1 assume !(1 == ~E_5~0); 6296327#L1095-1 assume !(1 == ~E_6~0); 6296098#L1100-1 assume !(1 == ~E_7~0); 6296099#L1105-1 assume !(1 == ~E_8~0); 6295321#L1110-1 assume !(1 == ~E_9~0); 6295322#L1115-1 assume { :end_inline_reset_delta_events } true; 6295677#L1396-2 assume !false; 6764767#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6764678#L897 [2021-12-06 17:46:15,487 INFO L793 eck$LassoCheckResult]: Loop: 6764678#L897 assume !false; 6764667#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 6764660#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 6764653#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 6764645#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6764640#L766 assume 0 != eval_~tmp~0#1; 6764637#L766-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 6761776#L774 assume !(0 != eval_~tmp_ndt_1~0#1); 6555308#L771 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 6555309#L788 assume !(0 != eval_~tmp_ndt_2~0#1); 6610042#L785 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 6610015#L802 assume !(0 != eval_~tmp_ndt_3~0#1); 6610036#L799 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 6610534#L816 assume !(0 != eval_~tmp_ndt_4~0#1); 6610533#L813 assume !(0 == ~t4_st~0); 6610530#L827 assume !(0 == ~t5_st~0); 6610526#L841 assume !(0 == ~t6_st~0); 6610525#L855 assume !(0 == ~t7_st~0); 6683377#L869 assume !(0 == ~t8_st~0); 6683375#L883 assume !(0 == ~t9_st~0); 6764678#L897 [2021-12-06 17:46:15,487 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:46:15,487 INFO L85 PathProgramCache]: Analyzing trace with hash -1585015822, now seen corresponding path program 4 times [2021-12-06 17:46:15,487 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:46:15,488 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [494367296] [2021-12-06 17:46:15,488 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:46:15,488 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:46:15,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:46:15,496 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:46:15,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:46:15,518 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:46:15,519 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:46:15,519 INFO L85 PathProgramCache]: Analyzing trace with hash -2105317862, now seen corresponding path program 1 times [2021-12-06 17:46:15,519 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:46:15,519 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [330329099] [2021-12-06 17:46:15,519 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:46:15,519 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:46:15,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:46:15,522 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:46:15,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:46:15,525 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:46:15,525 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:46:15,525 INFO L85 PathProgramCache]: Analyzing trace with hash -704538741, now seen corresponding path program 1 times [2021-12-06 17:46:15,525 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:46:15,525 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2088910658] [2021-12-06 17:46:15,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:46:15,525 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:46:15,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:46:15,548 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:46:15,549 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:46:15,549 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2088910658] [2021-12-06 17:46:15,549 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2088910658] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:46:15,549 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:46:15,549 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:46:15,549 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1467415435] [2021-12-06 17:46:15,549 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:46:15,661 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:46:15,661 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:46:15,661 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:46:15,661 INFO L87 Difference]: Start difference. First operand 576772 states and 768285 transitions. cyclomatic complexity: 191573 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:46:17,871 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:46:17,871 INFO L93 Difference]: Finished difference Result 802710 states and 1066435 transitions. [2021-12-06 17:46:17,872 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:46:17,872 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 802710 states and 1066435 transitions. [2021-12-06 17:46:21,021 INFO L131 ngComponentsAnalysis]: Automaton has 60 accepting balls. 798206 [2021-12-06 17:46:22,735 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 802710 states to 802710 states and 1066435 transitions. [2021-12-06 17:46:22,736 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 802710 [2021-12-06 17:46:23,035 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 802710 [2021-12-06 17:46:23,035 INFO L73 IsDeterministic]: Start isDeterministic. Operand 802710 states and 1066435 transitions. [2021-12-06 17:46:23,264 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:46:23,264 INFO L681 BuchiCegarLoop]: Abstraction has 802710 states and 1066435 transitions. [2021-12-06 17:46:23,559 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 802710 states and 1066435 transitions. [2021-12-06 17:46:28,367 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 802710 to 778210. [2021-12-06 17:46:28,659 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 778210 states, 778210 states have (on average 1.3298916744837512) internal successors, (1034935), 778209 states have internal predecessors, (1034935), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:46:30,556 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 778210 states to 778210 states and 1034935 transitions. [2021-12-06 17:46:30,556 INFO L704 BuchiCegarLoop]: Abstraction has 778210 states and 1034935 transitions. [2021-12-06 17:46:30,556 INFO L587 BuchiCegarLoop]: Abstraction has 778210 states and 1034935 transitions. [2021-12-06 17:46:30,556 INFO L425 BuchiCegarLoop]: ======== Iteration 35============ [2021-12-06 17:46:30,556 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 778210 states and 1034935 transitions. [2021-12-06 17:46:32,181 INFO L131 ngComponentsAnalysis]: Automaton has 60 accepting balls. 773706 [2021-12-06 17:46:32,181 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-06 17:46:32,181 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-06 17:46:32,182 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:46:32,182 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 17:46:32,182 INFO L791 eck$LassoCheckResult]: Stem: 7675549#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 7675550#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 7675086#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7675087#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7675749#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 7675750#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7675729#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7675486#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7675487#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7675265#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7675266#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 7675848#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 7675707#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 7675332#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7675092#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7675093#L922 assume !(0 == ~M_E~0); 7675940#L922-2 assume !(0 == ~T1_E~0); 7675941#L927-1 assume !(0 == ~T2_E~0); 7675561#L932-1 assume !(0 == ~T3_E~0); 7675417#L937-1 assume !(0 == ~T4_E~0); 7675418#L942-1 assume !(0 == ~T5_E~0); 7675485#L947-1 assume !(0 == ~T6_E~0); 7675565#L952-1 assume !(0 == ~T7_E~0); 7675566#L957-1 assume !(0 == ~T8_E~0); 7675643#L962-1 assume !(0 == ~T9_E~0); 7675386#L967-1 assume !(0 == ~E_1~0); 7675387#L972-1 assume !(0 == ~E_2~0); 7675735#L977-1 assume !(0 == ~E_3~0); 7675736#L982-1 assume !(0 == ~E_4~0); 7674859#L987-1 assume !(0 == ~E_5~0); 7674860#L992-1 assume !(0 == ~E_6~0); 7674868#L997-1 assume !(0 == ~E_7~0); 7675306#L1002-1 assume !(0 == ~E_8~0); 7675291#L1007-1 assume !(0 == ~E_9~0); 7674659#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7674660#L443 assume !(1 == ~m_pc~0); 7675586#L443-2 is_master_triggered_~__retres1~0#1 := 0; 7675573#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7675574#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7675022#L1140 assume !(0 != activate_threads_~tmp~1#1); 7674773#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7674774#L462 assume !(1 == ~t1_pc~0); 7675407#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7675408#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7674743#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7674744#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 7675245#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7675246#L481 assume !(1 == ~t2_pc~0); 7675017#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7675546#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7675413#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7675114#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 7675115#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7675219#L500 assume !(1 == ~t3_pc~0); 7675806#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7675765#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7675721#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7675722#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 7674661#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7674662#L519 assume !(1 == ~t4_pc~0); 7675471#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7675217#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7675218#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7675064#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 7675065#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7674827#L538 assume !(1 == ~t5_pc~0); 7674828#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7674733#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7674734#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7675002#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 7675003#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7675625#L557 assume !(1 == ~t6_pc~0); 7675038#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7675039#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7674939#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7674940#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 7675066#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7675904#L576 assume !(1 == ~t7_pc~0); 7675026#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 7675027#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7675295#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7675296#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 7675695#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7675154#L595 assume !(1 == ~t8_pc~0); 7675155#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7675723#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7675724#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7675517#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 7675518#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7674954#L614 assume !(1 == ~t9_pc~0); 7674955#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 7674851#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7674852#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7675030#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 7675116#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7675117#L1025 assume !(1 == ~M_E~0); 7675398#L1025-2 assume !(1 == ~T1_E~0); 7675462#L1030-1 assume !(1 == ~T2_E~0); 7675618#L1035-1 assume !(1 == ~T3_E~0); 7675109#L1040-1 assume !(1 == ~T4_E~0); 7675110#L1045-1 assume !(1 == ~T5_E~0); 7675013#L1050-1 assume !(1 == ~T6_E~0); 7675014#L1055-1 assume !(1 == ~T7_E~0); 7674836#L1060-1 assume !(1 == ~T8_E~0); 7674837#L1065-1 assume !(1 == ~T9_E~0); 7674900#L1070-1 assume !(1 == ~E_1~0); 7675567#L1075-1 assume !(1 == ~E_2~0); 7675568#L1080-1 assume !(1 == ~E_3~0); 7675555#L1085-1 assume !(1 == ~E_4~0); 7675556#L1090-1 assume !(1 == ~E_5~0); 7675840#L1095-1 assume !(1 == ~E_6~0); 7675601#L1100-1 assume !(1 == ~E_7~0); 7675602#L1105-1 assume !(1 == ~E_8~0); 7674809#L1110-1 assume !(1 == ~E_9~0); 7674810#L1115-1 assume { :end_inline_reset_delta_events } true; 7675169#L1396-2 assume !false; 8161762#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8161756#L897 [2021-12-06 17:46:32,182 INFO L793 eck$LassoCheckResult]: Loop: 8161756#L897 assume !false; 8161754#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 8161751#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 8161749#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 8161747#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8161745#L766 assume 0 != eval_~tmp~0#1; 8161742#L766-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 8161740#L774 assume !(0 != eval_~tmp_ndt_1~0#1); 8161738#L771 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 8161736#L788 assume !(0 != eval_~tmp_ndt_2~0#1); 8161733#L785 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 8161719#L802 assume !(0 != eval_~tmp_ndt_3~0#1); 8161731#L799 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 8161234#L816 assume !(0 != eval_~tmp_ndt_4~0#1); 8161232#L813 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 8161229#L830 assume !(0 != eval_~tmp_ndt_5~0#1); 8161227#L827 assume !(0 == ~t5_st~0); 8161222#L841 assume !(0 == ~t6_st~0); 8161220#L855 assume !(0 == ~t7_st~0); 8161770#L869 assume !(0 == ~t8_st~0); 8161761#L883 assume !(0 == ~t9_st~0); 8161756#L897 [2021-12-06 17:46:32,182 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:46:32,182 INFO L85 PathProgramCache]: Analyzing trace with hash -1585015822, now seen corresponding path program 5 times [2021-12-06 17:46:32,183 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:46:32,183 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [522304116] [2021-12-06 17:46:32,183 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:46:32,183 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:46:32,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:46:32,189 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:46:32,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:46:32,208 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:46:32,208 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:46:32,208 INFO L85 PathProgramCache]: Analyzing trace with hash 1367108254, now seen corresponding path program 1 times [2021-12-06 17:46:32,208 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:46:32,208 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1209922582] [2021-12-06 17:46:32,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:46:32,208 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:46:32,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:46:32,210 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-06 17:46:32,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-06 17:46:32,213 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-06 17:46:32,213 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 17:46:32,214 INFO L85 PathProgramCache]: Analyzing trace with hash 1841588045, now seen corresponding path program 1 times [2021-12-06 17:46:32,214 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 17:46:32,214 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1742697292] [2021-12-06 17:46:32,214 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 17:46:32,214 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 17:46:32,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 17:46:32,234 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 17:46:32,235 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 17:46:32,235 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1742697292] [2021-12-06 17:46:32,235 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1742697292] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 17:46:32,235 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 17:46:32,235 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 17:46:32,235 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [442731491] [2021-12-06 17:46:32,235 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 17:46:32,359 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 17:46:32,359 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 17:46:32,359 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 17:46:32,359 INFO L87 Difference]: Start difference. First operand 778210 states and 1034935 transitions. cyclomatic complexity: 256785 Second operand has 3 states, 3 states have (on average 46.0) internal successors, (138), 3 states have internal predecessors, (138), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 17:46:36,280 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 17:46:36,280 INFO L93 Difference]: Finished difference Result 1458012 states and 1938841 transitions. [2021-12-06 17:46:36,280 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 17:46:36,281 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1458012 states and 1938841 transitions. [2021-12-06 17:46:41,742 INFO L131 ngComponentsAnalysis]: Automaton has 60 accepting balls. 1449128 [2021-12-06 17:46:44,511 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1458012 states to 1458012 states and 1938841 transitions. [2021-12-06 17:46:44,511 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1458012 [2021-12-06 17:46:45,251 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1458012 [2021-12-06 17:46:45,251 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1458012 states and 1938841 transitions. [2021-12-06 17:46:45,641 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 17:46:45,641 INFO L681 BuchiCegarLoop]: Abstraction has 1458012 states and 1938841 transitions. [2021-12-06 17:46:46,165 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1458012 states and 1938841 transitions. [2021-12-06 17:46:55,379 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1458012 to 1402512. [2021-12-06 17:46:55,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1402512 states, 1402512 states have (on average 1.3317112438253649) internal successors, (1867741), 1402511 states have internal predecessors, (1867741), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)