./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread/fib_safe-5.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 839c364b Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/bin/uautomizer-DrprNOufMa/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/bin/uautomizer-DrprNOufMa/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/bin/uautomizer-DrprNOufMa/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/bin/uautomizer-DrprNOufMa/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread/fib_safe-5.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/bin/uautomizer-DrprNOufMa/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/bin/uautomizer-DrprNOufMa --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 40fcfd4444bd180f6e5508f0972ed92e70894b01f23e03dc2e761819c6d5a859 --- Real Ultimate output --- This is Ultimate 0.2.2-hotfix-svcomp22-839c364 [2021-12-06 19:07:39,523 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-06 19:07:39,525 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-06 19:07:39,555 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-06 19:07:39,556 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-06 19:07:39,557 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-06 19:07:39,558 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-06 19:07:39,561 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-06 19:07:39,563 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-06 19:07:39,564 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-06 19:07:39,565 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-06 19:07:39,566 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-06 19:07:39,567 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-06 19:07:39,568 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-06 19:07:39,569 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-06 19:07:39,571 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-06 19:07:39,572 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-06 19:07:39,573 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-06 19:07:39,575 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-06 19:07:39,578 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-06 19:07:39,579 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-06 19:07:39,581 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-06 19:07:39,582 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-06 19:07:39,583 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-06 19:07:39,587 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-06 19:07:39,587 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-06 19:07:39,588 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-06 19:07:39,589 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-06 19:07:39,589 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-06 19:07:39,590 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-06 19:07:39,591 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-06 19:07:39,592 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-06 19:07:39,592 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-06 19:07:39,593 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-06 19:07:39,594 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-06 19:07:39,595 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-06 19:07:39,596 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-06 19:07:39,596 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-06 19:07:39,596 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-06 19:07:39,597 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-06 19:07:39,598 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-06 19:07:39,598 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/bin/uautomizer-DrprNOufMa/config/svcomp-Reach-32bit-Automizer_Default.epf [2021-12-06 19:07:39,621 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-06 19:07:39,621 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-06 19:07:39,622 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-06 19:07:39,622 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-06 19:07:39,622 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2021-12-06 19:07:39,623 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2021-12-06 19:07:39,623 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-06 19:07:39,623 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-06 19:07:39,624 INFO L138 SettingsManager]: * Use SBE=true [2021-12-06 19:07:39,624 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-06 19:07:39,624 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-06 19:07:39,624 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-06 19:07:39,624 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-06 19:07:39,624 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-06 19:07:39,625 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2021-12-06 19:07:39,625 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2021-12-06 19:07:39,625 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2021-12-06 19:07:39,625 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-06 19:07:39,625 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-06 19:07:39,625 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-06 19:07:39,626 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2021-12-06 19:07:39,626 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-06 19:07:39,626 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-06 19:07:39,626 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2021-12-06 19:07:39,626 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2021-12-06 19:07:39,627 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-06 19:07:39,627 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2021-12-06 19:07:39,627 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2021-12-06 19:07:39,627 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-06 19:07:39,627 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2021-12-06 19:07:39,627 INFO L138 SettingsManager]: * Large block encoding in concurrent analysis=OFF [2021-12-06 19:07:39,628 INFO L138 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2021-12-06 19:07:39,628 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2021-12-06 19:07:39,628 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-06 19:07:39,628 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/bin/uautomizer-DrprNOufMa/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/bin/uautomizer-DrprNOufMa Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 40fcfd4444bd180f6e5508f0972ed92e70894b01f23e03dc2e761819c6d5a859 [2021-12-06 19:07:39,847 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-06 19:07:39,868 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-06 19:07:39,870 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-06 19:07:39,871 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-06 19:07:39,872 INFO L275 PluginConnector]: CDTParser initialized [2021-12-06 19:07:39,873 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/bin/uautomizer-DrprNOufMa/../../sv-benchmarks/c/pthread/fib_safe-5.i [2021-12-06 19:07:39,919 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/bin/uautomizer-DrprNOufMa/data/392d7d457/e4d95d4fab58437593e389f9a296541e/FLAG41dbcd412 [2021-12-06 19:07:40,302 INFO L306 CDTParser]: Found 1 translation units. [2021-12-06 19:07:40,303 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/sv-benchmarks/c/pthread/fib_safe-5.i [2021-12-06 19:07:40,317 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/bin/uautomizer-DrprNOufMa/data/392d7d457/e4d95d4fab58437593e389f9a296541e/FLAG41dbcd412 [2021-12-06 19:07:40,660 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/bin/uautomizer-DrprNOufMa/data/392d7d457/e4d95d4fab58437593e389f9a296541e [2021-12-06 19:07:40,662 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-06 19:07:40,663 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-06 19:07:40,664 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-06 19:07:40,665 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-06 19:07:40,668 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-06 19:07:40,668 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 07:07:40" (1/1) ... [2021-12-06 19:07:40,669 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@26c8a2ae and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:07:40, skipping insertion in model container [2021-12-06 19:07:40,670 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 07:07:40" (1/1) ... [2021-12-06 19:07:40,676 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-06 19:07:40,709 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-06 19:07:40,957 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/sv-benchmarks/c/pthread/fib_safe-5.i[30813,30826] [2021-12-06 19:07:40,960 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-06 19:07:40,968 INFO L203 MainTranslator]: Completed pre-run [2021-12-06 19:07:41,008 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/sv-benchmarks/c/pthread/fib_safe-5.i[30813,30826] [2021-12-06 19:07:41,010 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-06 19:07:41,045 INFO L208 MainTranslator]: Completed translation [2021-12-06 19:07:41,045 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:07:41 WrapperNode [2021-12-06 19:07:41,046 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-06 19:07:41,046 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-06 19:07:41,047 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-06 19:07:41,047 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-06 19:07:41,053 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:07:41" (1/1) ... [2021-12-06 19:07:41,066 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:07:41" (1/1) ... [2021-12-06 19:07:41,087 INFO L137 Inliner]: procedures = 164, calls = 26, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 71 [2021-12-06 19:07:41,087 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-06 19:07:41,088 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-06 19:07:41,088 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-06 19:07:41,088 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-06 19:07:41,096 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:07:41" (1/1) ... [2021-12-06 19:07:41,096 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:07:41" (1/1) ... [2021-12-06 19:07:41,099 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:07:41" (1/1) ... [2021-12-06 19:07:41,100 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:07:41" (1/1) ... [2021-12-06 19:07:41,105 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:07:41" (1/1) ... [2021-12-06 19:07:41,109 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:07:41" (1/1) ... [2021-12-06 19:07:41,111 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:07:41" (1/1) ... [2021-12-06 19:07:41,114 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-06 19:07:41,115 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-06 19:07:41,115 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-06 19:07:41,115 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-06 19:07:41,116 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:07:41" (1/1) ... [2021-12-06 19:07:41,124 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2021-12-06 19:07:41,134 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 19:07:41,146 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2021-12-06 19:07:41,148 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2021-12-06 19:07:41,183 INFO L130 BoogieDeclarations]: Found specification of procedure t1 [2021-12-06 19:07:41,183 INFO L138 BoogieDeclarations]: Found implementation of procedure t1 [2021-12-06 19:07:41,183 INFO L130 BoogieDeclarations]: Found specification of procedure t2 [2021-12-06 19:07:41,183 INFO L138 BoogieDeclarations]: Found implementation of procedure t2 [2021-12-06 19:07:41,183 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2021-12-06 19:07:41,183 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2021-12-06 19:07:41,184 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-06 19:07:41,184 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-12-06 19:07:41,184 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2021-12-06 19:07:41,184 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-06 19:07:41,184 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2021-12-06 19:07:41,184 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-06 19:07:41,184 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-06 19:07:41,185 WARN L209 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2021-12-06 19:07:41,286 INFO L236 CfgBuilder]: Building ICFG [2021-12-06 19:07:41,288 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-06 19:07:41,432 INFO L277 CfgBuilder]: Performing block encoding [2021-12-06 19:07:41,440 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-06 19:07:41,440 INFO L301 CfgBuilder]: Removed 3 assume(true) statements. [2021-12-06 19:07:41,442 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 07:07:41 BoogieIcfgContainer [2021-12-06 19:07:41,443 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-06 19:07:41,445 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2021-12-06 19:07:41,445 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2021-12-06 19:07:41,448 INFO L275 PluginConnector]: TraceAbstraction initialized [2021-12-06 19:07:41,449 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 06.12 07:07:40" (1/3) ... [2021-12-06 19:07:41,449 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1283838e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.12 07:07:41, skipping insertion in model container [2021-12-06 19:07:41,450 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 07:07:41" (2/3) ... [2021-12-06 19:07:41,450 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1283838e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.12 07:07:41, skipping insertion in model container [2021-12-06 19:07:41,450 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 07:07:41" (3/3) ... [2021-12-06 19:07:41,452 INFO L111 eAbstractionObserver]: Analyzing ICFG fib_safe-5.i [2021-12-06 19:07:41,457 WARN L149 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2021-12-06 19:07:41,457 INFO L204 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2021-12-06 19:07:41,457 INFO L163 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2021-12-06 19:07:41,458 INFO L513 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2021-12-06 19:07:41,483 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,483 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,483 WARN L322 ript$VariableManager]: TermVariabe t1Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,484 WARN L322 ript$VariableManager]: TermVariabe t1Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,484 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,484 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,484 WARN L322 ript$VariableManager]: TermVariabe t1Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,484 WARN L322 ript$VariableManager]: TermVariabe t1Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,485 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,485 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,485 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,486 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,486 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#t~post1| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,486 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#t~post1| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,486 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#t~post1| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,487 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#t~post1| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,487 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#t~post1| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,487 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#t~post1| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,487 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,487 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,487 WARN L322 ript$VariableManager]: TermVariabe t2Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,488 WARN L322 ript$VariableManager]: TermVariabe t2Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,488 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,488 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,488 WARN L322 ript$VariableManager]: TermVariabe t2Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,488 WARN L322 ript$VariableManager]: TermVariabe t2Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,489 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,489 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,489 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,489 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,490 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#t~post2| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,490 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#t~post2| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,490 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#t~post2| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,490 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#t~post2| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,490 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#t~post2| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,490 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#t~post2| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,493 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#t~post1| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,493 WARN L322 ript$VariableManager]: TermVariabe t1Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,494 WARN L322 ript$VariableManager]: TermVariabe t1Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,494 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,494 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,497 WARN L322 ript$VariableManager]: TermVariabe t2Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,498 WARN L322 ript$VariableManager]: TermVariabe t2Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,498 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,498 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#t~post2| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,498 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 19:07:41,499 INFO L148 ThreadInstanceAdder]: Constructed 0 joinOtherThreadTransitions. [2021-12-06 19:07:41,540 INFO L338 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2021-12-06 19:07:41,547 INFO L339 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mLoopAccelerationTechnique=FAST_UPR [2021-12-06 19:07:41,548 INFO L340 AbstractCegarLoop]: Starting to check reachability of 3 error locations. [2021-12-06 19:07:41,561 INFO L74 FinitePrefix]: Start finitePrefix. Operand has 96 places, 96 transitions, 202 flow [2021-12-06 19:07:41,603 INFO L129 PetriNetUnfolder]: 7/94 cut-off events. [2021-12-06 19:07:41,604 INFO L130 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2021-12-06 19:07:41,608 INFO L84 FinitePrefix]: Finished finitePrefix Result has 101 conditions, 94 events. 7/94 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 3. Compared 73 event pairs, 0 based on Foata normal form. 0/86 useless extension candidates. Maximal degree in co-relation 64. Up to 2 conditions per place. [2021-12-06 19:07:41,608 INFO L82 GeneralOperation]: Start removeDead. Operand has 96 places, 96 transitions, 202 flow [2021-12-06 19:07:41,613 INFO L88 GeneralOperation]: Finished RemoveDead, result has has 94 places, 94 transitions, 194 flow [2021-12-06 19:07:41,636 INFO L129 PetriNetUnfolder]: 7/85 cut-off events. [2021-12-06 19:07:41,637 INFO L130 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2021-12-06 19:07:41,637 INFO L246 CegarLoopForPetriNet]: Found error trace [2021-12-06 19:07:41,638 INFO L254 CegarLoopForPetriNet]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:41,638 INFO L402 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION] === [2021-12-06 19:07:41,642 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:41,643 INFO L85 PathProgramCache]: Analyzing trace with hash -1927097680, now seen corresponding path program 1 times [2021-12-06 19:07:41,650 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:41,650 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1487178159] [2021-12-06 19:07:41,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:41,651 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:41,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:41,814 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:41,814 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:41,814 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1487178159] [2021-12-06 19:07:41,815 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1487178159] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:07:41,815 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:07:41,815 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 19:07:41,816 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2032278972] [2021-12-06 19:07:41,817 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:07:41,824 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2021-12-06 19:07:41,824 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:07:41,845 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-12-06 19:07:41,847 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-12-06 19:07:41,850 INFO L499 CegarLoopForPetriNet]: Number of universal loopers: 89 out of 96 [2021-12-06 19:07:41,853 INFO L92 encePairwiseOnDemand]: Start differencePairwiseOnDemand. First operand has 94 places, 94 transitions, 194 flow. Second operand has 2 states, 2 states have (on average 90.5) internal successors, (181), 2 states have internal predecessors, (181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:41,853 INFO L101 encePairwiseOnDemand]: Universal subtrahend loopers provided by user. [2021-12-06 19:07:41,854 INFO L102 encePairwiseOnDemand]: Number of universal subtrahend loopers: 89 of 96 [2021-12-06 19:07:41,855 INFO L74 FinitePrefix]: Start finitePrefix. Operand will be constructed on-demand [2021-12-06 19:07:41,885 INFO L129 PetriNetUnfolder]: 3/89 cut-off events. [2021-12-06 19:07:41,885 INFO L130 PetriNetUnfolder]: For 2/2 co-relation queries the response was YES. [2021-12-06 19:07:41,886 INFO L84 FinitePrefix]: Finished finitePrefix Result has 99 conditions, 89 events. 3/89 cut-off events. For 2/2 co-relation queries the response was YES. Maximal size of possible extension queue 3. Compared 62 event pairs, 0 based on Foata normal form. 5/90 useless extension candidates. Maximal degree in co-relation 60. Up to 3 conditions per place. [2021-12-06 19:07:41,888 INFO L132 encePairwiseOnDemand]: 92/96 looper letters, 2 selfloop transitions, 0 changer transitions 0/89 dead transitions. [2021-12-06 19:07:41,888 INFO L138 encePairwiseOnDemand]: Finished differencePairwiseOnDemand. Result has 94 places, 89 transitions, 188 flow [2021-12-06 19:07:41,889 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-12-06 19:07:41,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2 states. [2021-12-06 19:07:41,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 184 transitions. [2021-12-06 19:07:41,899 INFO L544 CegarLoopForPetriNet]: DFA transition density 0.9583333333333334 [2021-12-06 19:07:41,899 INFO L72 ComplementDD]: Start complementDD. Operand 2 states and 184 transitions. [2021-12-06 19:07:41,900 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2 states and 184 transitions. [2021-12-06 19:07:41,901 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:07:41,903 INFO L117 ReachableStatesCopy]: Start reachableStatesCopy. Operand 2 states and 184 transitions. [2021-12-06 19:07:41,905 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends has 3 states, 2 states have (on average 92.0) internal successors, (184), 2 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:41,909 INFO L131 ReachableStatesCopy]: Finished reachableStatesCopy Result has 3 states, 3 states have (on average 96.0) internal successors, (288), 3 states have internal predecessors, (288), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:41,909 INFO L81 ComplementDD]: Finished complementDD. Result has 3 states, 3 states have (on average 96.0) internal successors, (288), 3 states have internal predecessors, (288), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:41,910 INFO L186 Difference]: Start difference. First operand has 94 places, 94 transitions, 194 flow. Second operand 2 states and 184 transitions. [2021-12-06 19:07:41,911 INFO L82 GeneralOperation]: Start removeRedundantFlow. Operand has 94 places, 89 transitions, 188 flow [2021-12-06 19:07:41,914 INFO L88 GeneralOperation]: Finished removeRedundantFlow, result has has 92 places, 89 transitions, 186 flow, removed 0 selfloop flow, removed 2 redundant places. [2021-12-06 19:07:41,917 INFO L242 Difference]: Finished difference. Result has 92 places, 89 transitions, 182 flow [2021-12-06 19:07:41,918 INFO L317 CegarLoopForPetriNet]: {PETRI_ALPHABET=96, PETRI_DIFFERENCE_MINUEND_FLOW=182, PETRI_DIFFERENCE_MINUEND_PLACES=91, PETRI_DIFFERENCE_MINUEND_TRANSITIONS=89, PETRI_DIFFERENCE_SUBTRAHEND_LETTERS_WITH_MORE_CHANGERS_THAN_LOOPERS=0, PETRI_DIFFERENCE_SUBTRAHEND_LOOPER_ONLY_LETTERS=89, PETRI_DIFFERENCE_SUBTRAHEND_STATES=2, PETRI_FLOW=182, PETRI_PLACES=92, PETRI_TRANSITIONS=89} [2021-12-06 19:07:41,921 INFO L334 CegarLoopForPetriNet]: 94 programPoint places, -2 predicate places. [2021-12-06 19:07:41,921 INFO L470 AbstractCegarLoop]: Abstraction has has 92 places, 89 transitions, 182 flow [2021-12-06 19:07:41,922 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 90.5) internal successors, (181), 2 states have internal predecessors, (181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:41,922 INFO L246 CegarLoopForPetriNet]: Found error trace [2021-12-06 19:07:41,922 INFO L254 CegarLoopForPetriNet]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:41,922 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2021-12-06 19:07:41,922 INFO L402 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION] === [2021-12-06 19:07:41,923 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:41,923 INFO L85 PathProgramCache]: Analyzing trace with hash 560415153, now seen corresponding path program 1 times [2021-12-06 19:07:41,923 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:41,923 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [805218494] [2021-12-06 19:07:41,923 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:41,924 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:41,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:41,995 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:41,995 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:41,995 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [805218494] [2021-12-06 19:07:41,996 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [805218494] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 19:07:42,004 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 19:07:42,004 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 19:07:42,004 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2022216158] [2021-12-06 19:07:42,004 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 19:07:42,006 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2021-12-06 19:07:42,006 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:07:42,007 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 19:07:42,007 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 19:07:42,008 INFO L499 CegarLoopForPetriNet]: Number of universal loopers: 83 out of 96 [2021-12-06 19:07:42,009 INFO L92 encePairwiseOnDemand]: Start differencePairwiseOnDemand. First operand has 92 places, 89 transitions, 182 flow. Second operand has 3 states, 3 states have (on average 84.66666666666667) internal successors, (254), 3 states have internal predecessors, (254), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:42,009 INFO L101 encePairwiseOnDemand]: Universal subtrahend loopers provided by user. [2021-12-06 19:07:42,009 INFO L102 encePairwiseOnDemand]: Number of universal subtrahend loopers: 83 of 96 [2021-12-06 19:07:42,009 INFO L74 FinitePrefix]: Start finitePrefix. Operand will be constructed on-demand [2021-12-06 19:07:42,045 INFO L129 PetriNetUnfolder]: 3/95 cut-off events. [2021-12-06 19:07:42,045 INFO L130 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2021-12-06 19:07:42,046 INFO L84 FinitePrefix]: Finished finitePrefix Result has 113 conditions, 95 events. 3/95 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 3. Compared 60 event pairs, 0 based on Foata normal form. 0/91 useless extension candidates. Maximal degree in co-relation 110. Up to 6 conditions per place. [2021-12-06 19:07:42,047 INFO L132 encePairwiseOnDemand]: 93/96 looper letters, 9 selfloop transitions, 2 changer transitions 0/92 dead transitions. [2021-12-06 19:07:42,047 INFO L138 encePairwiseOnDemand]: Finished differencePairwiseOnDemand. Result has 94 places, 92 transitions, 210 flow [2021-12-06 19:07:42,047 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 19:07:42,048 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2021-12-06 19:07:42,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 261 transitions. [2021-12-06 19:07:42,051 INFO L544 CegarLoopForPetriNet]: DFA transition density 0.90625 [2021-12-06 19:07:42,051 INFO L72 ComplementDD]: Start complementDD. Operand 3 states and 261 transitions. [2021-12-06 19:07:42,051 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3 states and 261 transitions. [2021-12-06 19:07:42,052 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:07:42,052 INFO L117 ReachableStatesCopy]: Start reachableStatesCopy. Operand 3 states and 261 transitions. [2021-12-06 19:07:42,054 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends has 4 states, 3 states have (on average 87.0) internal successors, (261), 3 states have internal predecessors, (261), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:42,055 INFO L131 ReachableStatesCopy]: Finished reachableStatesCopy Result has 4 states, 4 states have (on average 96.0) internal successors, (384), 4 states have internal predecessors, (384), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:42,056 INFO L81 ComplementDD]: Finished complementDD. Result has 4 states, 4 states have (on average 96.0) internal successors, (384), 4 states have internal predecessors, (384), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:42,056 INFO L186 Difference]: Start difference. First operand has 92 places, 89 transitions, 182 flow. Second operand 3 states and 261 transitions. [2021-12-06 19:07:42,056 INFO L82 GeneralOperation]: Start removeRedundantFlow. Operand has 94 places, 92 transitions, 210 flow [2021-12-06 19:07:42,057 INFO L88 GeneralOperation]: Finished removeRedundantFlow, result has has 94 places, 92 transitions, 210 flow, removed 0 selfloop flow, removed 0 redundant places. [2021-12-06 19:07:42,058 INFO L242 Difference]: Finished difference. Result has 95 places, 90 transitions, 194 flow [2021-12-06 19:07:42,059 INFO L317 CegarLoopForPetriNet]: {PETRI_ALPHABET=96, PETRI_DIFFERENCE_MINUEND_FLOW=182, PETRI_DIFFERENCE_MINUEND_PLACES=92, PETRI_DIFFERENCE_MINUEND_TRANSITIONS=89, PETRI_DIFFERENCE_SUBTRAHEND_LETTERS_WITH_MORE_CHANGERS_THAN_LOOPERS=1, PETRI_DIFFERENCE_SUBTRAHEND_LOOPER_ONLY_LETTERS=87, PETRI_DIFFERENCE_SUBTRAHEND_STATES=3, PETRI_FLOW=194, PETRI_PLACES=95, PETRI_TRANSITIONS=90} [2021-12-06 19:07:42,059 INFO L334 CegarLoopForPetriNet]: 94 programPoint places, 1 predicate places. [2021-12-06 19:07:42,059 INFO L470 AbstractCegarLoop]: Abstraction has has 95 places, 90 transitions, 194 flow [2021-12-06 19:07:42,060 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 84.66666666666667) internal successors, (254), 3 states have internal predecessors, (254), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:42,060 INFO L246 CegarLoopForPetriNet]: Found error trace [2021-12-06 19:07:42,060 INFO L254 CegarLoopForPetriNet]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:42,060 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2021-12-06 19:07:42,060 INFO L402 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION] === [2021-12-06 19:07:42,061 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:42,061 INFO L85 PathProgramCache]: Analyzing trace with hash -951035470, now seen corresponding path program 1 times [2021-12-06 19:07:42,061 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:42,061 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2100318188] [2021-12-06 19:07:42,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:42,061 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:42,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:42,147 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:42,147 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:42,147 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2100318188] [2021-12-06 19:07:42,148 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2100318188] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 19:07:42,148 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [759859030] [2021-12-06 19:07:42,148 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:42,148 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 19:07:42,148 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 19:07:42,149 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 19:07:42,150 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2021-12-06 19:07:42,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:42,226 INFO L263 TraceCheckSpWp]: Trace formula consists of 152 conjuncts, 4 conjunts are in the unsatisfiable core [2021-12-06 19:07:42,230 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 19:07:42,357 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:42,358 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 19:07:42,460 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:42,460 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [759859030] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 19:07:42,460 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 19:07:42,460 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 10 [2021-12-06 19:07:42,461 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1054432351] [2021-12-06 19:07:42,461 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 19:07:42,462 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2021-12-06 19:07:42,462 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:07:42,462 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2021-12-06 19:07:42,462 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2021-12-06 19:07:42,465 INFO L499 CegarLoopForPetriNet]: Number of universal loopers: 81 out of 96 [2021-12-06 19:07:42,466 INFO L92 encePairwiseOnDemand]: Start differencePairwiseOnDemand. First operand has 95 places, 90 transitions, 194 flow. Second operand has 10 states, 10 states have (on average 83.0) internal successors, (830), 10 states have internal predecessors, (830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:42,467 INFO L101 encePairwiseOnDemand]: Universal subtrahend loopers provided by user. [2021-12-06 19:07:42,467 INFO L102 encePairwiseOnDemand]: Number of universal subtrahend loopers: 81 of 96 [2021-12-06 19:07:42,467 INFO L74 FinitePrefix]: Start finitePrefix. Operand will be constructed on-demand [2021-12-06 19:07:42,548 INFO L129 PetriNetUnfolder]: 3/104 cut-off events. [2021-12-06 19:07:42,549 INFO L130 PetriNetUnfolder]: For 3/3 co-relation queries the response was YES. [2021-12-06 19:07:42,550 INFO L84 FinitePrefix]: Finished finitePrefix Result has 138 conditions, 104 events. 3/104 cut-off events. For 3/3 co-relation queries the response was YES. Maximal size of possible extension queue 3. Compared 51 event pairs, 0 based on Foata normal form. 2/103 useless extension candidates. Maximal degree in co-relation 133. Up to 6 conditions per place. [2021-12-06 19:07:42,551 INFO L132 encePairwiseOnDemand]: 90/96 looper letters, 10 selfloop transitions, 9 changer transitions 0/98 dead transitions. [2021-12-06 19:07:42,551 INFO L138 encePairwiseOnDemand]: Finished differencePairwiseOnDemand. Result has 103 places, 98 transitions, 250 flow [2021-12-06 19:07:42,552 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2021-12-06 19:07:42,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9 states. [2021-12-06 19:07:42,555 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 750 transitions. [2021-12-06 19:07:42,556 INFO L544 CegarLoopForPetriNet]: DFA transition density 0.8680555555555556 [2021-12-06 19:07:42,557 INFO L72 ComplementDD]: Start complementDD. Operand 9 states and 750 transitions. [2021-12-06 19:07:42,557 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9 states and 750 transitions. [2021-12-06 19:07:42,557 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:07:42,558 INFO L117 ReachableStatesCopy]: Start reachableStatesCopy. Operand 9 states and 750 transitions. [2021-12-06 19:07:42,561 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends has 10 states, 9 states have (on average 83.33333333333333) internal successors, (750), 9 states have internal predecessors, (750), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:42,566 INFO L131 ReachableStatesCopy]: Finished reachableStatesCopy Result has 10 states, 10 states have (on average 96.0) internal successors, (960), 10 states have internal predecessors, (960), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:42,567 INFO L81 ComplementDD]: Finished complementDD. Result has 10 states, 10 states have (on average 96.0) internal successors, (960), 10 states have internal predecessors, (960), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:42,567 INFO L186 Difference]: Start difference. First operand has 95 places, 90 transitions, 194 flow. Second operand 9 states and 750 transitions. [2021-12-06 19:07:42,567 INFO L82 GeneralOperation]: Start removeRedundantFlow. Operand has 103 places, 98 transitions, 250 flow [2021-12-06 19:07:42,569 INFO L88 GeneralOperation]: Finished removeRedundantFlow, result has has 102 places, 98 transitions, 248 flow, removed 0 selfloop flow, removed 1 redundant places. [2021-12-06 19:07:42,571 INFO L242 Difference]: Finished difference. Result has 105 places, 96 transitions, 242 flow [2021-12-06 19:07:42,572 INFO L317 CegarLoopForPetriNet]: {PETRI_ALPHABET=96, PETRI_DIFFERENCE_MINUEND_FLOW=192, PETRI_DIFFERENCE_MINUEND_PLACES=94, PETRI_DIFFERENCE_MINUEND_TRANSITIONS=90, PETRI_DIFFERENCE_SUBTRAHEND_LETTERS_WITH_MORE_CHANGERS_THAN_LOOPERS=5, PETRI_DIFFERENCE_SUBTRAHEND_LOOPER_ONLY_LETTERS=84, PETRI_DIFFERENCE_SUBTRAHEND_STATES=9, PETRI_FLOW=242, PETRI_PLACES=105, PETRI_TRANSITIONS=96} [2021-12-06 19:07:42,573 INFO L334 CegarLoopForPetriNet]: 94 programPoint places, 11 predicate places. [2021-12-06 19:07:42,573 INFO L470 AbstractCegarLoop]: Abstraction has has 105 places, 96 transitions, 242 flow [2021-12-06 19:07:42,574 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 83.0) internal successors, (830), 10 states have internal predecessors, (830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:42,574 INFO L246 CegarLoopForPetriNet]: Found error trace [2021-12-06 19:07:42,574 INFO L254 CegarLoopForPetriNet]: trace histogram [3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:42,606 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2021-12-06 19:07:42,776 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2,2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 19:07:42,776 INFO L402 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION] === [2021-12-06 19:07:42,777 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:42,777 INFO L85 PathProgramCache]: Analyzing trace with hash 1666707666, now seen corresponding path program 2 times [2021-12-06 19:07:42,777 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:42,777 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2013379337] [2021-12-06 19:07:42,777 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:42,777 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:42,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:42,895 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:42,895 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:42,895 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2013379337] [2021-12-06 19:07:42,896 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2013379337] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 19:07:42,896 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1730773131] [2021-12-06 19:07:42,896 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-12-06 19:07:42,896 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 19:07:42,897 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 19:07:42,897 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 19:07:42,899 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2021-12-06 19:07:42,965 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-12-06 19:07:42,965 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 19:07:42,967 INFO L263 TraceCheckSpWp]: Trace formula consists of 176 conjuncts, 8 conjunts are in the unsatisfiable core [2021-12-06 19:07:42,969 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 19:07:43,079 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:43,080 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 19:07:43,194 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:43,194 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1730773131] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 19:07:43,194 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 19:07:43,194 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9] total 18 [2021-12-06 19:07:43,194 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1172851405] [2021-12-06 19:07:43,195 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 19:07:43,195 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2021-12-06 19:07:43,195 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:07:43,196 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2021-12-06 19:07:43,196 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=90, Invalid=216, Unknown=0, NotChecked=0, Total=306 [2021-12-06 19:07:43,198 INFO L499 CegarLoopForPetriNet]: Number of universal loopers: 81 out of 96 [2021-12-06 19:07:43,201 INFO L92 encePairwiseOnDemand]: Start differencePairwiseOnDemand. First operand has 105 places, 96 transitions, 242 flow. Second operand has 18 states, 18 states have (on average 83.0) internal successors, (1494), 18 states have internal predecessors, (1494), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:43,201 INFO L101 encePairwiseOnDemand]: Universal subtrahend loopers provided by user. [2021-12-06 19:07:43,201 INFO L102 encePairwiseOnDemand]: Number of universal subtrahend loopers: 81 of 96 [2021-12-06 19:07:43,201 INFO L74 FinitePrefix]: Start finitePrefix. Operand will be constructed on-demand [2021-12-06 19:07:43,344 INFO L129 PetriNetUnfolder]: 3/132 cut-off events. [2021-12-06 19:07:43,344 INFO L130 PetriNetUnfolder]: For 30/30 co-relation queries the response was YES. [2021-12-06 19:07:43,345 INFO L84 FinitePrefix]: Finished finitePrefix Result has 231 conditions, 132 events. 3/132 cut-off events. For 30/30 co-relation queries the response was YES. Maximal size of possible extension queue 3. Compared 51 event pairs, 0 based on Foata normal form. 4/133 useless extension candidates. Maximal degree in co-relation 224. Up to 11 conditions per place. [2021-12-06 19:07:43,346 INFO L132 encePairwiseOnDemand]: 90/96 looper letters, 14 selfloop transitions, 21 changer transitions 0/114 dead transitions. [2021-12-06 19:07:43,346 INFO L138 encePairwiseOnDemand]: Finished differencePairwiseOnDemand. Result has 125 places, 114 transitions, 408 flow [2021-12-06 19:07:43,346 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2021-12-06 19:07:43,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2021-12-06 19:07:43,349 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 1740 transitions. [2021-12-06 19:07:43,350 INFO L544 CegarLoopForPetriNet]: DFA transition density 0.8630952380952381 [2021-12-06 19:07:43,350 INFO L72 ComplementDD]: Start complementDD. Operand 21 states and 1740 transitions. [2021-12-06 19:07:43,350 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21 states and 1740 transitions. [2021-12-06 19:07:43,351 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:07:43,352 INFO L117 ReachableStatesCopy]: Start reachableStatesCopy. Operand 21 states and 1740 transitions. [2021-12-06 19:07:43,356 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends has 22 states, 21 states have (on average 82.85714285714286) internal successors, (1740), 21 states have internal predecessors, (1740), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:43,360 INFO L131 ReachableStatesCopy]: Finished reachableStatesCopy Result has 22 states, 22 states have (on average 96.0) internal successors, (2112), 22 states have internal predecessors, (2112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:43,361 INFO L81 ComplementDD]: Finished complementDD. Result has 22 states, 22 states have (on average 96.0) internal successors, (2112), 22 states have internal predecessors, (2112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:43,362 INFO L186 Difference]: Start difference. First operand has 105 places, 96 transitions, 242 flow. Second operand 21 states and 1740 transitions. [2021-12-06 19:07:43,362 INFO L82 GeneralOperation]: Start removeRedundantFlow. Operand has 125 places, 114 transitions, 408 flow [2021-12-06 19:07:43,365 INFO L88 GeneralOperation]: Finished removeRedundantFlow, result has has 124 places, 114 transitions, 394 flow, removed 6 selfloop flow, removed 1 redundant places. [2021-12-06 19:07:43,367 INFO L242 Difference]: Finished difference. Result has 129 places, 109 transitions, 366 flow [2021-12-06 19:07:43,367 INFO L317 CegarLoopForPetriNet]: {PETRI_ALPHABET=96, PETRI_DIFFERENCE_MINUEND_FLOW=236, PETRI_DIFFERENCE_MINUEND_PLACES=104, PETRI_DIFFERENCE_MINUEND_TRANSITIONS=96, PETRI_DIFFERENCE_SUBTRAHEND_LETTERS_WITH_MORE_CHANGERS_THAN_LOOPERS=10, PETRI_DIFFERENCE_SUBTRAHEND_LOOPER_ONLY_LETTERS=85, PETRI_DIFFERENCE_SUBTRAHEND_STATES=21, PETRI_FLOW=366, PETRI_PLACES=129, PETRI_TRANSITIONS=109} [2021-12-06 19:07:43,368 INFO L334 CegarLoopForPetriNet]: 94 programPoint places, 35 predicate places. [2021-12-06 19:07:43,368 INFO L470 AbstractCegarLoop]: Abstraction has has 129 places, 109 transitions, 366 flow [2021-12-06 19:07:43,369 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 83.0) internal successors, (1494), 18 states have internal predecessors, (1494), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:43,369 INFO L246 CegarLoopForPetriNet]: Found error trace [2021-12-06 19:07:43,370 INFO L254 CegarLoopForPetriNet]: trace histogram [7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:43,403 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Ended with exit code 0 [2021-12-06 19:07:43,570 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3,3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 19:07:43,571 INFO L402 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION] === [2021-12-06 19:07:43,571 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:43,571 INFO L85 PathProgramCache]: Analyzing trace with hash -1283180782, now seen corresponding path program 3 times [2021-12-06 19:07:43,571 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:43,572 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1422530341] [2021-12-06 19:07:43,572 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:43,572 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:43,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:43,737 INFO L134 CoverageAnalysis]: Checked inductivity of 154 backedges. 0 proven. 154 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:43,738 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:43,738 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1422530341] [2021-12-06 19:07:43,738 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1422530341] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 19:07:43,738 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1796189286] [2021-12-06 19:07:43,738 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-12-06 19:07:43,738 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 19:07:43,738 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 19:07:43,739 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 19:07:43,740 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2021-12-06 19:07:43,809 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2021-12-06 19:07:43,809 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 19:07:43,810 INFO L263 TraceCheckSpWp]: Trace formula consists of 224 conjuncts, 16 conjunts are in the unsatisfiable core [2021-12-06 19:07:43,814 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 19:07:43,965 INFO L134 CoverageAnalysis]: Checked inductivity of 154 backedges. 0 proven. 154 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:43,966 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 19:07:44,158 INFO L134 CoverageAnalysis]: Checked inductivity of 154 backedges. 0 proven. 154 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:44,158 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1796189286] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 19:07:44,158 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 19:07:44,158 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17] total 27 [2021-12-06 19:07:44,159 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [253303298] [2021-12-06 19:07:44,159 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 19:07:44,159 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 27 states [2021-12-06 19:07:44,159 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:07:44,160 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2021-12-06 19:07:44,160 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=195, Invalid=507, Unknown=0, NotChecked=0, Total=702 [2021-12-06 19:07:44,162 INFO L499 CegarLoopForPetriNet]: Number of universal loopers: 81 out of 96 [2021-12-06 19:07:44,165 INFO L92 encePairwiseOnDemand]: Start differencePairwiseOnDemand. First operand has 129 places, 109 transitions, 366 flow. Second operand has 27 states, 27 states have (on average 83.07407407407408) internal successors, (2243), 27 states have internal predecessors, (2243), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:44,165 INFO L101 encePairwiseOnDemand]: Universal subtrahend loopers provided by user. [2021-12-06 19:07:44,165 INFO L102 encePairwiseOnDemand]: Number of universal subtrahend loopers: 81 of 96 [2021-12-06 19:07:44,165 INFO L74 FinitePrefix]: Start finitePrefix. Operand will be constructed on-demand [2021-12-06 19:07:44,497 INFO L129 PetriNetUnfolder]: 3/167 cut-off events. [2021-12-06 19:07:44,498 INFO L130 PetriNetUnfolder]: For 184/184 co-relation queries the response was YES. [2021-12-06 19:07:44,499 INFO L84 FinitePrefix]: Finished finitePrefix Result has 381 conditions, 167 events. 3/167 cut-off events. For 184/184 co-relation queries the response was YES. Maximal size of possible extension queue 3. Compared 51 event pairs, 0 based on Foata normal form. 5/169 useless extension candidates. Maximal degree in co-relation 369. Up to 21 conditions per place. [2021-12-06 19:07:44,501 INFO L132 encePairwiseOnDemand]: 90/96 looper letters, 19 selfloop transitions, 36 changer transitions 0/134 dead transitions. [2021-12-06 19:07:44,501 INFO L138 encePairwiseOnDemand]: Finished differencePairwiseOnDemand. Result has 164 places, 134 transitions, 668 flow [2021-12-06 19:07:44,501 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2021-12-06 19:07:44,501 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2021-12-06 19:07:44,509 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 2976 transitions. [2021-12-06 19:07:44,510 INFO L544 CegarLoopForPetriNet]: DFA transition density 0.8611111111111112 [2021-12-06 19:07:44,511 INFO L72 ComplementDD]: Start complementDD. Operand 36 states and 2976 transitions. [2021-12-06 19:07:44,511 INFO L73 IsDeterministic]: Start isDeterministic. Operand 36 states and 2976 transitions. [2021-12-06 19:07:44,514 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 19:07:44,514 INFO L117 ReachableStatesCopy]: Start reachableStatesCopy. Operand 36 states and 2976 transitions. [2021-12-06 19:07:44,523 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends has 37 states, 36 states have (on average 82.66666666666667) internal successors, (2976), 36 states have internal predecessors, (2976), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:44,533 INFO L131 ReachableStatesCopy]: Finished reachableStatesCopy Result has 37 states, 37 states have (on average 96.0) internal successors, (3552), 37 states have internal predecessors, (3552), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:44,535 INFO L81 ComplementDD]: Finished complementDD. Result has 37 states, 37 states have (on average 96.0) internal successors, (3552), 37 states have internal predecessors, (3552), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:44,535 INFO L186 Difference]: Start difference. First operand has 129 places, 109 transitions, 366 flow. Second operand 36 states and 2976 transitions. [2021-12-06 19:07:44,536 INFO L82 GeneralOperation]: Start removeRedundantFlow. Operand has 164 places, 134 transitions, 668 flow [2021-12-06 19:07:44,541 INFO L88 GeneralOperation]: Finished removeRedundantFlow, result has has 158 places, 134 transitions, 634 flow, removed 11 selfloop flow, removed 6 redundant places. [2021-12-06 19:07:44,545 INFO L242 Difference]: Finished difference. Result has 164 places, 125 transitions, 554 flow [2021-12-06 19:07:44,545 INFO L317 CegarLoopForPetriNet]: {PETRI_ALPHABET=96, PETRI_DIFFERENCE_MINUEND_FLOW=342, PETRI_DIFFERENCE_MINUEND_PLACES=123, PETRI_DIFFERENCE_MINUEND_TRANSITIONS=109, PETRI_DIFFERENCE_SUBTRAHEND_LETTERS_WITH_MORE_CHANGERS_THAN_LOOPERS=22, PETRI_DIFFERENCE_SUBTRAHEND_LOOPER_ONLY_LETTERS=86, PETRI_DIFFERENCE_SUBTRAHEND_STATES=36, PETRI_FLOW=554, PETRI_PLACES=164, PETRI_TRANSITIONS=125} [2021-12-06 19:07:44,546 INFO L334 CegarLoopForPetriNet]: 94 programPoint places, 70 predicate places. [2021-12-06 19:07:44,546 INFO L470 AbstractCegarLoop]: Abstraction has has 164 places, 125 transitions, 554 flow [2021-12-06 19:07:44,548 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 27 states, 27 states have (on average 83.07407407407408) internal successors, (2243), 27 states have internal predecessors, (2243), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:07:44,548 INFO L246 CegarLoopForPetriNet]: Found error trace [2021-12-06 19:07:44,548 INFO L254 CegarLoopForPetriNet]: trace histogram [12, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 19:07:44,582 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Ended with exit code 0 [2021-12-06 19:07:44,749 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 19:07:44,750 INFO L402 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION] === [2021-12-06 19:07:44,750 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 19:07:44,750 INFO L85 PathProgramCache]: Analyzing trace with hash 1938020081, now seen corresponding path program 4 times [2021-12-06 19:07:44,750 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 19:07:44,751 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1505105776] [2021-12-06 19:07:44,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 19:07:44,751 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 19:07:44,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 19:07:45,827 INFO L134 CoverageAnalysis]: Checked inductivity of 474 backedges. 0 proven. 474 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:45,828 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 19:07:45,828 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1505105776] [2021-12-06 19:07:45,828 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1505105776] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 19:07:45,828 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [809493196] [2021-12-06 19:07:45,828 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-12-06 19:07:45,828 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 19:07:45,828 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 19:07:45,829 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 19:07:45,830 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0305bf81-9136-45b7-9a08-244f5799a1b6/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2021-12-06 19:07:45,891 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-12-06 19:07:45,891 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 19:07:45,892 INFO L263 TraceCheckSpWp]: Trace formula consists of 267 conjuncts, 41 conjunts are in the unsatisfiable core [2021-12-06 19:07:45,897 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 19:07:48,058 INFO L134 CoverageAnalysis]: Checked inductivity of 474 backedges. 335 proven. 139 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:07:48,058 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 19:10:40,665 WARN L227 SmtUtils]: Spent 5.42s on a formula simplification that was a NOOP. DAG size: 53 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2021-12-06 19:11:43,737 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_~i~0_8 Int)) (or (< 1 v_~i~0_8) (forall ((v_~j~0_8 Int)) (or (< 1 v_~j~0_8) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse0 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 v_~j~0_8) (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse0 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 (* 2 aux_mod_v_~cur~0_22_51) 10 v_~j~0_8) (+ (* 3 v_~prev~0_24) .cse0 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse1 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse1 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 (* 2 aux_mod_v_~cur~0_22_51) 10 v_~i~0_8) (+ (* 3 v_~prev~0_24) .cse1 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 v_~i~0_8) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))))))))))) is different from false [2021-12-06 19:12:21,534 INFO L134 CoverageAnalysis]: Checked inductivity of 474 backedges. 0 proven. 472 refuted. 2 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 19:12:21,534 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [809493196] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 19:12:21,534 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 19:12:21,535 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 42, 42] total 121 [2021-12-06 19:12:21,535 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1418309272] [2021-12-06 19:12:21,535 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 19:12:21,536 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 121 states [2021-12-06 19:12:21,536 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 19:12:21,537 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 121 interpolants. [2021-12-06 19:12:21,544 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=948, Invalid=13271, Unknown=65, NotChecked=236, Total=14520 [2021-12-06 19:12:21,552 INFO L499 CegarLoopForPetriNet]: Number of universal loopers: 68 out of 96 [2021-12-06 19:12:21,562 INFO L92 encePairwiseOnDemand]: Start differencePairwiseOnDemand. First operand has 164 places, 125 transitions, 554 flow. Second operand has 121 states, 121 states have (on average 69.27272727272727) internal successors, (8382), 121 states have internal predecessors, (8382), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 19:12:21,562 INFO L101 encePairwiseOnDemand]: Universal subtrahend loopers provided by user. [2021-12-06 19:12:21,562 INFO L102 encePairwiseOnDemand]: Number of universal subtrahend loopers: 68 of 96 [2021-12-06 19:12:21,562 INFO L74 FinitePrefix]: Start finitePrefix. Operand will be constructed on-demand [2021-12-06 19:12:24,632 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse13 (* 2 c_~cur~0))) (let ((.cse5 (+ .cse13 c_~prev~0 3)) (.cse6 (* c_~i~0 (- 1))) (.cse1 (+ .cse13 c_~prev~0)) (.cse4 (* c_~j~0 (- 1))) (.cse7 (+ c_~prev~0 c_~cur~0 1))) (and (= c_~prev~0 0) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse0 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse0 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_div_v_~cur~0_22_51 (+ .cse0 c_~prev~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56)))))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (<= c_~j~0 .cse1) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_mod_v_~next~0_20_56 0))) (forall ((v_~j~0_8 Int)) (or (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse2 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 v_~j~0_8) (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse2 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 (* 2 aux_mod_v_~cur~0_22_51) 10 v_~j~0_8) (+ (* 3 v_~prev~0_24) .cse2 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse3 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse3 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse3 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0))))) (< 1 v_~j~0_8))) (<= (div (+ .cse4 c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse5) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0)))))) (= c_~cur~0 1) (<= (div (+ .cse6 c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse5) (<= (div (+ (- 2) .cse6 c_~cur~0) (- 2)) .cse7) (<= c_~i~0 .cse1) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse8 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse8 c_~prev~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse8 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))))) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse9 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse9 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse9 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse10 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse10 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse10 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse11 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse11 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse11 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse12 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse12 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse12 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (<= (div (+ .cse4 (- 2) c_~cur~0) (- 2)) .cse7)))) is different from false [2021-12-06 19:14:14,442 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse11 (* 2 c_~cur~0))) (let ((.cse3 (+ .cse11 c_~prev~0 3)) (.cse4 (* c_~i~0 (- 1))) (.cse1 (+ .cse11 c_~prev~0)) (.cse2 (* c_~j~0 (- 1))) (.cse5 (+ c_~prev~0 c_~cur~0 1))) (and (= c_~prev~0 0) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse0 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse0 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_div_v_~cur~0_22_51 (+ .cse0 c_~prev~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56)))))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (<= c_~j~0 .cse1) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_mod_v_~next~0_20_56 0))) (<= (div (+ .cse2 c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse3) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0)))))) (= c_~cur~0 1) (<= (div (+ .cse4 c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse3) (<= (div (+ (- 2) .cse4 c_~cur~0) (- 2)) .cse5) (= c_~i~0 1) (<= c_~i~0 .cse1) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse6 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse6 c_~prev~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse6 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))))) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse7 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse7 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse7 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse8 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse8 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse8 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse9 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse9 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse9 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse10 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse10 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse10 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (<= (div (+ .cse2 (- 2) c_~cur~0) (- 2)) .cse5)))) is different from false [2021-12-06 19:14:17,405 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse8 (* c_~j~0 (- 1))) (.cse5 (* c_~i~0 (- 1))) (.cse26 (* 2 c_~cur~0))) (let ((.cse1 (+ c_~next~0 1)) (.cse6 (+ c_~cur~0 4 (* 2 c_~next~0))) (.cse3 (+ c_~next~0 c_~cur~0 2)) (.cse9 (+ c_~next~0 c_~cur~0)) (.cse13 (+ .cse26 c_~prev~0 3)) (.cse0 (div (+ (- 2) .cse5 c_~cur~0) (- 2))) (.cse14 (div (+ .cse5 c_~next~0 (- 4)) (- 2))) (.cse10 (+ .cse26 c_~prev~0)) (.cse2 (div (+ .cse8 c_~next~0 (- 4)) (- 2))) (.cse19 (+ c_~next~0 c_~prev~0 2)) (.cse7 (div (+ .cse8 (- 2) c_~cur~0) (- 2))) (.cse17 (+ c_~prev~0 c_~cur~0 1))) (and (= c_~prev~0 0) (<= .cse0 .cse1) (<= .cse2 .cse3) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse4 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse4 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_div_v_~cur~0_22_51 (+ .cse4 c_~prev~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56)))))))) (<= (div (+ .cse5 c_~prev~0) (- 2)) c_~next~0) (<= (div (+ .cse5 c_~next~0 c_~cur~0 (- 8)) (- 2)) .cse6) (<= .cse7 .cse1) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (<= (div (+ .cse8 c_~next~0 c_~cur~0 (- 8)) (- 2)) .cse6) (<= c_~i~0 .cse9) (<= c_~j~0 .cse10) (<= (div (+ .cse8 c_~prev~0) (- 2)) c_~next~0) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_mod_v_~next~0_20_56 0))) (forall ((v_~j~0_8 Int)) (or (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse11 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 v_~j~0_8) (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse11 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 (* 2 aux_mod_v_~cur~0_22_51) 10 v_~j~0_8) (+ (* 3 v_~prev~0_24) .cse11 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse12 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse12 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse12 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0))))) (< 1 v_~j~0_8))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 c_~next~0) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (<= (div (+ .cse8 c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse13) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~prev~0_24 c_~next~0) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (<= .cse14 .cse3) (= c_~cur~0 1) (<= c_~j~0 .cse9) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse15 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse15 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse15 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse16 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse16 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse16 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))))) (<= (div (+ .cse5 c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse13) (<= .cse0 .cse17) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse18 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse18 c_~next~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse18 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (<= .cse14 .cse19) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse20 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse20 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse20 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0)))) (<= c_~i~0 .cse10) (<= .cse2 .cse19) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse21 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse21 c_~prev~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse21 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 c_~next~0) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56)))))))) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse22 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse22 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse22 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse23 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse23 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse23 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse24 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse24 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse24 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse25 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse25 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse25 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (<= .cse7 .cse17)))) is different from false [2021-12-06 19:14:20,431 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse4 (+ (* 2 c_~cur~0) c_~prev~0 3)) (.cse5 (* c_~i~0 (- 1))) (.cse3 (* c_~j~0 (- 1))) (.cse6 (+ c_~prev~0 c_~cur~0 1))) (and (= c_~prev~0 0) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse0 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse0 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_div_v_~cur~0_22_51 (+ .cse0 c_~prev~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56)))))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_mod_v_~next~0_20_56 0))) (forall ((v_~j~0_8 Int)) (or (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse1 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 v_~j~0_8) (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse1 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 (* 2 aux_mod_v_~cur~0_22_51) 10 v_~j~0_8) (+ (* 3 v_~prev~0_24) .cse1 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse2 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse2 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse2 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0))))) (< 1 v_~j~0_8))) (<= (div (+ .cse3 c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse4) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0)))))) (= c_~cur~0 1) (<= (div (+ .cse5 c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse4) (<= (div (+ (- 2) .cse5 c_~cur~0) (- 2)) .cse6) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse7 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse7 c_~prev~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse7 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))))) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse8 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse8 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse8 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse9 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse9 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse9 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse10 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse10 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse10 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse11 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse11 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse11 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (<= (div (+ .cse3 (- 2) c_~cur~0) (- 2)) .cse6))) is different from false [2021-12-06 19:14:23,132 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse8 (* c_~j~0 (- 1))) (.cse5 (* c_~i~0 (- 1))) (.cse24 (* 2 c_~cur~0))) (let ((.cse1 (+ c_~next~0 1)) (.cse6 (+ c_~cur~0 4 (* 2 c_~next~0))) (.cse3 (+ c_~next~0 c_~cur~0 2)) (.cse9 (+ c_~next~0 c_~cur~0)) (.cse11 (+ .cse24 c_~prev~0 3)) (.cse0 (div (+ (- 2) .cse5 c_~cur~0) (- 2))) (.cse12 (div (+ .cse5 c_~next~0 (- 4)) (- 2))) (.cse10 (+ .cse24 c_~prev~0)) (.cse2 (div (+ .cse8 c_~next~0 (- 4)) (- 2))) (.cse17 (+ c_~next~0 c_~prev~0 2)) (.cse7 (div (+ .cse8 (- 2) c_~cur~0) (- 2))) (.cse15 (+ c_~prev~0 c_~cur~0 1))) (and (= c_~prev~0 0) (<= .cse0 .cse1) (<= .cse2 .cse3) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse4 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse4 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_div_v_~cur~0_22_51 (+ .cse4 c_~prev~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56)))))))) (<= (div (+ .cse5 c_~prev~0) (- 2)) c_~next~0) (<= (div (+ .cse5 c_~next~0 c_~cur~0 (- 8)) (- 2)) .cse6) (<= .cse7 .cse1) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (<= (div (+ .cse8 c_~next~0 c_~cur~0 (- 8)) (- 2)) .cse6) (<= c_~i~0 .cse9) (<= c_~j~0 .cse10) (<= (div (+ .cse8 c_~prev~0) (- 2)) c_~next~0) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 c_~next~0) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (<= (div (+ .cse8 c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse11) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~prev~0_24 c_~next~0) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (<= .cse12 .cse3) (= c_~cur~0 1) (<= c_~j~0 .cse9) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse13 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse13 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse13 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse14 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse14 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse14 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))))) (<= (div (+ .cse5 c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse11) (<= .cse0 .cse15) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse16 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse16 c_~next~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse16 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (<= .cse12 .cse17) (= c_~i~0 1) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse18 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse18 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse18 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0)))) (<= c_~i~0 .cse10) (<= .cse2 .cse17) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse19 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse19 c_~prev~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse19 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 c_~next~0) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56)))))))) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse20 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse20 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse20 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse21 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse21 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse21 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse22 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse22 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse22 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse23 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse23 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse23 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (<= .cse7 .cse15)))) is different from false [2021-12-06 19:15:21,808 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse1 (+ c_~next~0 1)) (.cse2 (* c_~j~0 (- 1))) (.cse4 (+ c_~cur~0 4 (* 2 c_~next~0))) (.cse0 (* c_~i~0 (- 1))) (.cse3 (+ c_~next~0 c_~cur~0 2)) (.cse5 (+ c_~next~0 c_~cur~0))) (and (<= (div (+ (- 2) .cse0 c_~cur~0) (- 2)) .cse1) (<= (div (+ .cse2 c_~next~0 (- 4)) (- 2)) .cse3) (<= (div (+ .cse0 c_~next~0 c_~cur~0 (- 8)) (- 2)) .cse4) (<= (div (+ .cse2 (- 2) c_~cur~0) (- 2)) .cse1) (<= (div (+ .cse2 c_~next~0 c_~cur~0 (- 8)) (- 2)) .cse4) (<= c_~i~0 .cse5) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 c_~next~0) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~prev~0_24 c_~next~0) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (<= (div (+ .cse0 c_~next~0 (- 4)) (- 2)) .cse3) (<= c_~j~0 .cse5) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse6 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse6 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse6 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse7 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse7 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse7 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse8 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse8 c_~next~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse8 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse9 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse9 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse9 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 c_~next~0) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56)))))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))))))) is different from false [2021-12-06 19:16:25,670 WARN L227 SmtUtils]: Spent 9.06s on a formula simplification that was a NOOP. DAG size: 68 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2021-12-06 19:16:28,074 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse4 (+ c_~cur~0 4 (* 2 c_~next~0))) (.cse0 (* c_~j~0 (- 1))) (.cse1 (+ c_~next~0 c_~cur~0 2)) (.cse3 (* c_~i~0 (- 1))) (.cse7 (+ (* 2 c_~cur~0) c_~prev~0 3))) (and (= c_~prev~0 0) (<= (div (+ .cse0 c_~next~0 (- 4)) (- 2)) .cse1) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse2 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse2 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_div_v_~cur~0_22_51 (+ .cse2 c_~prev~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56)))))))) (<= (div (+ .cse3 c_~next~0 c_~cur~0 (- 8)) (- 2)) .cse4) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (<= (div (+ .cse0 c_~next~0 c_~cur~0 (- 8)) (- 2)) .cse4) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_mod_v_~next~0_20_56 0))) (forall ((v_~j~0_8 Int)) (or (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse5 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 v_~j~0_8) (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse5 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 (* 2 aux_mod_v_~cur~0_22_51) 10 v_~j~0_8) (+ (* 3 v_~prev~0_24) .cse5 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse6 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse6 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse6 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0))))) (< 1 v_~j~0_8))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 c_~next~0) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (<= (div (+ .cse0 c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse7) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~prev~0_24 c_~next~0) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (<= (div (+ .cse3 c_~next~0 (- 4)) (- 2)) .cse1) (= c_~cur~0 1) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse8 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse8 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse8 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse9 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse9 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse9 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))))) (<= (div (+ .cse3 c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse7) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse10 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse10 c_~next~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse10 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse11 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse11 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse11 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse12 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse12 c_~prev~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse12 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 c_~next~0) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56)))))))) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse13 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse13 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse13 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse14 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse14 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse14 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse15 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse15 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse15 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse16 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse16 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse16 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))))) is different from false [2021-12-06 19:16:30,200 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse5 (+ c_~next~0 c_~prev~0)) (.cse3 (* c_~i~0 (- 1))) (.cse4 (* c_~j~0 (- 1))) (.cse7 (+ c_~next~0 c_~prev~0 2))) (and (forall ((aux_div_v_~cur~0_21_56 Int) (aux_mod_v_~cur~0_21_56 Int)) (or (<= (+ c_~prev~0 (* 5 aux_div_v_~cur~0_21_56)) (+ (* 2 c_~j~0) 15 (* 2 aux_mod_v_~cur~0_21_56))) (<= 2 aux_mod_v_~cur~0_21_56) (< (+ 6 c_~j~0 aux_mod_v_~cur~0_21_56) (+ (* 2 aux_div_v_~cur~0_21_56) c_~next~0 c_~prev~0)) (< aux_mod_v_~cur~0_21_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse0 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse0 c_~next~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse0 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~cur~0_26 (+ c_~next~0 c_~prev~0))))) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse1 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse1 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ .cse1 c_~prev~0 1)) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~prev~0 v_~cur~0_26))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse2 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse2 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ .cse2 c_~prev~0 1)) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~prev~0 v_~cur~0_26)))))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) (* 3 c_~prev~0))) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) c_~prev~0) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0))) (<= (div (+ .cse3 c_~prev~0) (- 2)) c_~next~0) (<= (div (+ .cse4 c_~prev~0) (- 2)) c_~next~0) (<= c_~j~0 .cse5) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~prev~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 c_~next~0) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) c_~prev~0) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) (* 3 c_~prev~0))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~prev~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< v_~prev~0_24 c_~next~0) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 c_~next~0) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56)))))))) (<= c_~i~0 .cse5) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse6 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse6 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse6 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0) (< v_~cur~0_26 (+ c_~next~0 c_~prev~0))))) (<= (div (+ .cse3 c_~next~0 (- 4)) (- 2)) .cse7) (<= (div (+ .cse4 c_~next~0 (- 4)) (- 2)) .cse7) (forall ((aux_div_v_~cur~0_21_56 Int) (aux_mod_v_~cur~0_21_56 Int)) (or (<= (+ c_~prev~0 (* 5 aux_div_v_~cur~0_21_56)) (+ 15 (* 2 aux_mod_v_~cur~0_21_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~cur~0_21_56) (< (+ 6 c_~i~0 aux_mod_v_~cur~0_21_56) (+ (* 2 aux_div_v_~cur~0_21_56) c_~next~0 c_~prev~0)) (< aux_mod_v_~cur~0_21_56 0))))) is different from false [2021-12-06 19:16:32,689 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse8 (* c_~j~0 (- 1))) (.cse5 (* c_~i~0 (- 1)))) (let ((.cse1 (+ c_~next~0 1)) (.cse6 (+ c_~cur~0 4 (* 2 c_~next~0))) (.cse3 (+ c_~next~0 c_~cur~0 2)) (.cse11 (+ (* 2 c_~cur~0) c_~prev~0 3)) (.cse0 (div (+ (- 2) .cse5 c_~cur~0) (- 2))) (.cse12 (div (+ .cse5 c_~next~0 (- 4)) (- 2))) (.cse2 (div (+ .cse8 c_~next~0 (- 4)) (- 2))) (.cse17 (+ c_~next~0 c_~prev~0 2)) (.cse7 (div (+ .cse8 (- 2) c_~cur~0) (- 2))) (.cse15 (+ c_~prev~0 c_~cur~0 1))) (and (= c_~prev~0 0) (<= .cse0 .cse1) (<= .cse2 .cse3) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse4 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse4 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_div_v_~cur~0_22_51 (+ .cse4 c_~prev~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56)))))))) (<= (div (+ .cse5 c_~next~0 c_~cur~0 (- 8)) (- 2)) .cse6) (<= .cse7 .cse1) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (<= (div (+ .cse8 c_~next~0 c_~cur~0 (- 8)) (- 2)) .cse6) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_mod_v_~next~0_20_56 0))) (forall ((v_~j~0_8 Int)) (or (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse9 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 v_~j~0_8) (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse9 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 (* 2 aux_mod_v_~cur~0_22_51) 10 v_~j~0_8) (+ (* 3 v_~prev~0_24) .cse9 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse10 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse10 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse10 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0))))) (< 1 v_~j~0_8))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 c_~next~0) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (<= (div (+ .cse8 c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse11) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~prev~0_24 c_~next~0) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (<= .cse12 .cse3) (= c_~cur~0 1) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse13 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse13 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse13 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse14 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse14 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse14 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))))) (<= (div (+ .cse5 c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse11) (<= .cse0 .cse15) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse16 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse16 c_~next~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse16 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (<= .cse12 .cse17) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse18 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse18 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse18 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0)))) (<= .cse2 .cse17) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse19 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse19 c_~prev~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse19 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 c_~next~0) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56)))))))) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse20 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse20 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse20 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse21 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse21 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse21 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse22 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse22 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse22 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse23 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse23 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse23 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (<= .cse7 .cse15)))) is different from false [2021-12-06 19:17:35,187 WARN L227 SmtUtils]: Spent 18.75s on a formula simplification. DAG size of input: 101 DAG size of output: 57 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2021-12-06 19:17:38,479 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse11 (* c_~j~0 (- 1))) (.cse8 (* c_~i~0 (- 1))) (.cse20 (* 2 c_~cur~0))) (let ((.cse5 (+ c_~next~0 1)) (.cse9 (+ c_~cur~0 4 (* 2 c_~next~0))) (.cse3 (+ c_~prev~0 c_~cur~0)) (.cse7 (+ c_~next~0 c_~cur~0 2)) (.cse12 (+ c_~next~0 c_~cur~0)) (.cse15 (+ .cse20 c_~prev~0 3)) (.cse4 (div (+ (- 2) .cse8 c_~cur~0) (- 2))) (.cse14 (+ c_~next~0 c_~prev~0)) (.cse16 (div (+ .cse8 c_~next~0 (- 4)) (- 2))) (.cse13 (+ .cse20 c_~prev~0)) (.cse6 (div (+ .cse11 c_~next~0 (- 4)) (- 2))) (.cse19 (+ c_~next~0 c_~prev~0 2)) (.cse10 (div (+ .cse11 (- 2) c_~cur~0) (- 2))) (.cse17 (+ c_~prev~0 c_~cur~0 1))) (and (forall ((aux_div_v_~cur~0_21_56 Int) (aux_mod_v_~cur~0_21_56 Int)) (or (<= (+ c_~prev~0 (* 5 aux_div_v_~cur~0_21_56)) (+ (* 2 c_~j~0) 15 (* 2 aux_mod_v_~cur~0_21_56))) (<= 2 aux_mod_v_~cur~0_21_56) (< (+ 6 c_~j~0 aux_mod_v_~cur~0_21_56) (+ (* 2 aux_div_v_~cur~0_21_56) c_~next~0 c_~prev~0)) (< aux_mod_v_~cur~0_21_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse0 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse0 c_~next~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse0 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~cur~0_26 (+ c_~next~0 c_~prev~0))))) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse1 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse1 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ .cse1 c_~prev~0 1)) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~prev~0 v_~cur~0_26))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse2 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse2 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ .cse2 c_~prev~0 1)) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~prev~0 v_~cur~0_26)))))))) (<= c_~j~0 .cse3) (<= .cse4 .cse5) (<= .cse6 .cse7) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) (* 3 c_~prev~0))) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) c_~prev~0) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0))) (<= (div (+ .cse8 c_~prev~0) (- 2)) c_~next~0) (<= (div (+ .cse8 c_~next~0 c_~cur~0 (- 8)) (- 2)) .cse9) (<= 1 c_~cur~0) (<= .cse10 .cse5) (<= (div (+ .cse11 c_~next~0 c_~cur~0 (- 8)) (- 2)) .cse9) (<= c_~i~0 .cse12) (<= c_~j~0 .cse13) (<= (div (+ .cse11 c_~prev~0) (- 2)) c_~next~0) (<= c_~j~0 .cse14) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))))) (<= (div (+ .cse11 c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse15) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~prev~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 c_~next~0) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (<= c_~i~0 .cse3) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (<= 0 c_~prev~0) (<= .cse16 .cse7) (= c_~cur~0 1) (<= c_~i~0 1) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) c_~prev~0) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) (* 3 c_~prev~0))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~prev~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< v_~prev~0_24 c_~next~0) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (<= c_~j~0 .cse12) (<= (div (+ .cse8 c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse15) (<= .cse4 .cse17) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 c_~next~0) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56)))))))) (<= c_~i~0 .cse14) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse18 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse18 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse18 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0) (< v_~cur~0_26 (+ c_~next~0 c_~prev~0))))) (<= .cse16 .cse19) (<= c_~i~0 .cse13) (<= .cse6 .cse19) (forall ((aux_div_v_~cur~0_21_56 Int) (aux_mod_v_~cur~0_21_56 Int)) (or (<= (+ c_~prev~0 (* 5 aux_div_v_~cur~0_21_56)) (+ 15 (* 2 aux_mod_v_~cur~0_21_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~cur~0_21_56) (< (+ 6 c_~i~0 aux_mod_v_~cur~0_21_56) (+ (* 2 aux_div_v_~cur~0_21_56) c_~next~0 c_~prev~0)) (< aux_mod_v_~cur~0_21_56 0))) (<= .cse10 .cse17)))) is different from false [2021-12-06 19:17:40,717 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse10 (* 2 c_~cur~0))) (let ((.cse0 (+ c_~prev~0 c_~cur~0)) (.cse4 (+ .cse10 c_~prev~0 3)) (.cse5 (* c_~i~0 (- 1))) (.cse2 (+ .cse10 c_~prev~0)) (.cse3 (* c_~j~0 (- 1))) (.cse6 (+ c_~prev~0 c_~cur~0 1))) (and (<= c_~j~0 .cse0) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse1 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse1 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_div_v_~cur~0_22_51 (+ .cse1 c_~prev~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56)))))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (<= c_~j~0 .cse2) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_mod_v_~next~0_20_56 0))) (<= (div (+ .cse3 c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse4) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0)))))) (<= c_~i~0 .cse0) (<= (div (+ .cse5 c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse4) (<= (div (+ (- 2) .cse5 c_~cur~0) (- 2)) .cse6) (<= c_~i~0 .cse2) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse7 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse7 c_~prev~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse7 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))))) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse8 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse8 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse8 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse9 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse9 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse9 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (<= (div (+ .cse3 (- 2) c_~cur~0) (- 2)) .cse6)))) is different from false [2021-12-06 19:17:44,787 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse8 (* c_~j~0 (- 1))) (.cse5 (* c_~i~0 (- 1)))) (let ((.cse1 (+ c_~next~0 1)) (.cse6 (+ c_~cur~0 4 (* 2 c_~next~0))) (.cse3 (+ c_~next~0 c_~cur~0 2)) (.cse9 (+ (* 2 c_~cur~0) c_~prev~0 3)) (.cse0 (div (+ (- 2) .cse5 c_~cur~0) (- 2))) (.cse10 (div (+ .cse5 c_~next~0 (- 4)) (- 2))) (.cse2 (div (+ .cse8 c_~next~0 (- 4)) (- 2))) (.cse15 (+ c_~next~0 c_~prev~0 2)) (.cse7 (div (+ .cse8 (- 2) c_~cur~0) (- 2))) (.cse13 (+ c_~prev~0 c_~cur~0 1))) (and (= c_~prev~0 0) (<= .cse0 .cse1) (<= .cse2 .cse3) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse4 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse4 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_div_v_~cur~0_22_51 (+ .cse4 c_~prev~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56)))))))) (<= (div (+ .cse5 c_~next~0 c_~cur~0 (- 8)) (- 2)) .cse6) (<= .cse7 .cse1) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (<= (div (+ .cse8 c_~next~0 c_~cur~0 (- 8)) (- 2)) .cse6) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 c_~next~0) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (<= (div (+ .cse8 c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse9) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~prev~0_24 c_~next~0) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (<= .cse10 .cse3) (= c_~cur~0 1) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse11 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse11 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse11 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse12 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse12 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse12 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))))) (<= (div (+ .cse5 c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse9) (<= .cse0 .cse13) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse14 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse14 c_~next~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse14 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (<= .cse10 .cse15) (= c_~i~0 1) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse16 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse16 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse16 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0)))) (<= .cse2 .cse15) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse17 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse17 c_~prev~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse17 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 c_~next~0) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56)))))))) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse18 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse18 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse18 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse19 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse19 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse19 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse20 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse20 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse20 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse21 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse21 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse21 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (<= .cse7 .cse13)))) is different from false [2021-12-06 19:18:46,165 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse8 (* c_~j~0 (- 1))) (.cse5 (* c_~i~0 (- 1))) (.cse22 (* 2 c_~cur~0))) (let ((.cse2 (+ c_~next~0 1)) (.cse6 (+ c_~cur~0 4 (* 2 c_~next~0))) (.cse0 (+ c_~prev~0 c_~cur~0)) (.cse4 (+ c_~next~0 c_~cur~0 2)) (.cse9 (+ c_~next~0 c_~cur~0)) (.cse12 (+ .cse22 c_~prev~0 3)) (.cse1 (div (+ (- 2) .cse5 c_~cur~0) (- 2))) (.cse11 (+ c_~next~0 c_~prev~0)) (.cse13 (div (+ .cse5 c_~next~0 (- 4)) (- 2))) (.cse10 (+ .cse22 c_~prev~0)) (.cse3 (div (+ .cse8 c_~next~0 (- 4)) (- 2))) (.cse18 (+ c_~next~0 c_~prev~0 2)) (.cse7 (div (+ .cse8 (- 2) c_~cur~0) (- 2))) (.cse16 (+ c_~prev~0 c_~cur~0 1))) (and (<= c_~j~0 .cse0) (<= .cse1 .cse2) (<= .cse3 .cse4) (<= (div (+ .cse5 c_~prev~0) (- 2)) c_~next~0) (<= (div (+ .cse5 c_~next~0 c_~cur~0 (- 8)) (- 2)) .cse6) (<= 1 c_~cur~0) (<= .cse7 .cse2) (<= (div (+ .cse8 c_~next~0 c_~cur~0 (- 8)) (- 2)) .cse6) (<= c_~i~0 .cse9) (<= c_~j~0 .cse10) (<= (div (+ .cse8 c_~prev~0) (- 2)) c_~next~0) (<= c_~j~0 .cse11) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 c_~next~0) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (<= (div (+ .cse8 c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse12) (<= c_~i~0 c_~next~0) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~prev~0_24 c_~next~0) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (<= c_~i~0 .cse0) (<= 0 c_~prev~0) (<= .cse13 .cse4) (<= c_~j~0 c_~next~0) (<= c_~j~0 .cse9) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse14 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse14 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse14 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse15 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse15 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse15 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))))) (<= (div (+ .cse5 c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse12) (<= .cse1 .cse16) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse17 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse17 c_~next~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse17 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (<= c_~i~0 .cse11) (<= .cse13 .cse18) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse19 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse19 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse19 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0)))) (<= c_~i~0 .cse10) (<= .cse3 .cse18) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 c_~next~0) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56)))))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse20 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse20 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse20 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse21 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse21 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse21 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (<= .cse7 .cse16)))) is different from false [2021-12-06 19:18:49,017 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse8 (* c_~j~0 (- 1))) (.cse5 (* c_~i~0 (- 1))) (.cse22 (* 2 c_~cur~0))) (let ((.cse2 (+ c_~next~0 1)) (.cse6 (+ c_~cur~0 4 (* 2 c_~next~0))) (.cse0 (+ c_~prev~0 c_~cur~0)) (.cse4 (+ c_~next~0 c_~cur~0 2)) (.cse9 (+ c_~next~0 c_~cur~0)) (.cse12 (+ .cse22 c_~prev~0 3)) (.cse1 (div (+ (- 2) .cse5 c_~cur~0) (- 2))) (.cse11 (+ c_~next~0 c_~prev~0)) (.cse13 (div (+ .cse5 c_~next~0 (- 4)) (- 2))) (.cse10 (+ .cse22 c_~prev~0)) (.cse3 (div (+ .cse8 c_~next~0 (- 4)) (- 2))) (.cse18 (+ c_~next~0 c_~prev~0 2)) (.cse7 (div (+ .cse8 (- 2) c_~cur~0) (- 2))) (.cse16 (+ c_~prev~0 c_~cur~0 1))) (and (<= c_~j~0 .cse0) (<= .cse1 .cse2) (<= .cse3 .cse4) (<= (div (+ .cse5 c_~prev~0) (- 2)) c_~next~0) (<= (div (+ .cse5 c_~next~0 c_~cur~0 (- 8)) (- 2)) .cse6) (<= 1 c_~cur~0) (<= .cse7 .cse2) (<= (div (+ .cse8 c_~next~0 c_~cur~0 (- 8)) (- 2)) .cse6) (<= c_~i~0 .cse9) (<= c_~j~0 .cse10) (<= (div (+ .cse8 c_~prev~0) (- 2)) c_~next~0) (<= c_~j~0 .cse11) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 c_~next~0) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (<= (div (+ .cse8 c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse12) (<= c_~i~0 c_~next~0) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~prev~0_24 c_~next~0) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (<= c_~i~0 .cse0) (<= 0 c_~prev~0) (<= .cse13 .cse4) (<= c_~j~0 c_~next~0) (<= c_~i~0 1) (<= c_~j~0 .cse9) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse14 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse14 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse14 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse15 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse15 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse15 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))))) (<= (div (+ .cse5 c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse12) (<= .cse1 .cse16) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse17 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse17 c_~next~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse17 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (<= c_~i~0 .cse11) (<= .cse13 .cse18) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse19 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse19 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse19 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0)))) (<= c_~i~0 .cse10) (<= .cse3 .cse18) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 c_~next~0) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56)))))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse20 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse20 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse20 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse21 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse21 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse21 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (<= .cse7 .cse16)))) is different from false [2021-12-06 19:18:51,541 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse1 (+ c_~next~0 1)) (.cse2 (* c_~j~0 (- 1))) (.cse4 (+ c_~cur~0 4 (* 2 c_~next~0))) (.cse0 (* c_~i~0 (- 1))) (.cse3 (+ c_~next~0 c_~cur~0 2))) (and (<= (div (+ (- 2) .cse0 c_~cur~0) (- 2)) .cse1) (<= (div (+ .cse2 c_~next~0 (- 4)) (- 2)) .cse3) (<= (div (+ .cse0 c_~next~0 c_~cur~0 (- 8)) (- 2)) .cse4) (<= (div (+ .cse2 (- 2) c_~cur~0) (- 2)) .cse1) (<= (div (+ .cse2 c_~next~0 c_~cur~0 (- 8)) (- 2)) .cse4) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 c_~next~0) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~prev~0_24 c_~next~0) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (<= (div (+ .cse0 c_~next~0 (- 4)) (- 2)) .cse3) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse5 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse5 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse5 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse6 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse6 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse6 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse7 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse7 c_~next~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse7 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse8 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse8 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse8 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 c_~next~0) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56)))))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))))))) is different from false [2021-12-06 19:21:46,498 WARN L227 SmtUtils]: Spent 51.15s on a formula simplification that was a NOOP. DAG size: 156 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate)