./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread/fib_safe-6.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 839c364b Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/bin/uautomizer-DrprNOufMa/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/bin/uautomizer-DrprNOufMa/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/bin/uautomizer-DrprNOufMa/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/bin/uautomizer-DrprNOufMa/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread/fib_safe-6.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/bin/uautomizer-DrprNOufMa/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/bin/uautomizer-DrprNOufMa --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 6959d4f0e51834399b1f177b2907c6f040a7f82b22df70a4ffbb4c40805c24f4 --- Real Ultimate output --- This is Ultimate 0.2.2-hotfix-svcomp22-839c364 [2021-12-06 18:30:33,400 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-06 18:30:33,402 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-06 18:30:33,430 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-06 18:30:33,431 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-06 18:30:33,432 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-06 18:30:33,434 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-06 18:30:33,436 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-06 18:30:33,438 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-06 18:30:33,439 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-06 18:30:33,440 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-06 18:30:33,441 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-06 18:30:33,442 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-06 18:30:33,443 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-06 18:30:33,444 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-06 18:30:33,446 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-06 18:30:33,447 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-06 18:30:33,448 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-06 18:30:33,450 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-06 18:30:33,452 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-06 18:30:33,454 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-06 18:30:33,455 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-06 18:30:33,457 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-06 18:30:33,458 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-06 18:30:33,461 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-06 18:30:33,461 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-06 18:30:33,462 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-06 18:30:33,463 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-06 18:30:33,463 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-06 18:30:33,464 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-06 18:30:33,465 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-06 18:30:33,466 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-06 18:30:33,466 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-06 18:30:33,467 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-06 18:30:33,468 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-06 18:30:33,468 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-06 18:30:33,469 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-06 18:30:33,469 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-06 18:30:33,469 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-06 18:30:33,470 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-06 18:30:33,470 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-06 18:30:33,471 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/bin/uautomizer-DrprNOufMa/config/svcomp-Reach-32bit-Automizer_Default.epf [2021-12-06 18:30:33,492 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-06 18:30:33,492 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-06 18:30:33,492 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-06 18:30:33,493 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-06 18:30:33,493 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2021-12-06 18:30:33,493 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2021-12-06 18:30:33,494 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-06 18:30:33,494 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-06 18:30:33,494 INFO L138 SettingsManager]: * Use SBE=true [2021-12-06 18:30:33,494 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-06 18:30:33,494 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-06 18:30:33,494 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-06 18:30:33,494 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-06 18:30:33,495 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-06 18:30:33,495 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2021-12-06 18:30:33,495 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2021-12-06 18:30:33,495 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2021-12-06 18:30:33,495 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-06 18:30:33,495 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-06 18:30:33,495 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-06 18:30:33,496 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2021-12-06 18:30:33,496 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-06 18:30:33,496 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-06 18:30:33,496 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2021-12-06 18:30:33,496 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2021-12-06 18:30:33,496 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-06 18:30:33,496 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2021-12-06 18:30:33,496 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2021-12-06 18:30:33,497 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-06 18:30:33,497 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2021-12-06 18:30:33,497 INFO L138 SettingsManager]: * Large block encoding in concurrent analysis=OFF [2021-12-06 18:30:33,497 INFO L138 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2021-12-06 18:30:33,497 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2021-12-06 18:30:33,497 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-06 18:30:33,497 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/bin/uautomizer-DrprNOufMa/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/bin/uautomizer-DrprNOufMa Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 6959d4f0e51834399b1f177b2907c6f040a7f82b22df70a4ffbb4c40805c24f4 [2021-12-06 18:30:33,696 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-06 18:30:33,713 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-06 18:30:33,715 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-06 18:30:33,716 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-06 18:30:33,717 INFO L275 PluginConnector]: CDTParser initialized [2021-12-06 18:30:33,718 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/bin/uautomizer-DrprNOufMa/../../sv-benchmarks/c/pthread/fib_safe-6.i [2021-12-06 18:30:33,761 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/bin/uautomizer-DrprNOufMa/data/5a1c6c64b/e745eb9776524e3dbce5be45f516ae54/FLAG150ab2173 [2021-12-06 18:30:34,201 INFO L306 CDTParser]: Found 1 translation units. [2021-12-06 18:30:34,201 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/sv-benchmarks/c/pthread/fib_safe-6.i [2021-12-06 18:30:34,212 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/bin/uautomizer-DrprNOufMa/data/5a1c6c64b/e745eb9776524e3dbce5be45f516ae54/FLAG150ab2173 [2021-12-06 18:30:34,547 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/bin/uautomizer-DrprNOufMa/data/5a1c6c64b/e745eb9776524e3dbce5be45f516ae54 [2021-12-06 18:30:34,549 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-06 18:30:34,550 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-06 18:30:34,552 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-06 18:30:34,552 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-06 18:30:34,554 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-06 18:30:34,555 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 06:30:34" (1/1) ... [2021-12-06 18:30:34,556 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5a6b85c2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:30:34, skipping insertion in model container [2021-12-06 18:30:34,556 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 06:30:34" (1/1) ... [2021-12-06 18:30:34,562 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-06 18:30:34,587 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-06 18:30:34,795 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/sv-benchmarks/c/pthread/fib_safe-6.i[30813,30826] [2021-12-06 18:30:34,797 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-06 18:30:34,803 INFO L203 MainTranslator]: Completed pre-run [2021-12-06 18:30:34,833 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/sv-benchmarks/c/pthread/fib_safe-6.i[30813,30826] [2021-12-06 18:30:34,834 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-06 18:30:34,859 INFO L208 MainTranslator]: Completed translation [2021-12-06 18:30:34,859 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:30:34 WrapperNode [2021-12-06 18:30:34,859 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-06 18:30:34,860 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-06 18:30:34,860 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-06 18:30:34,860 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-06 18:30:34,865 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:30:34" (1/1) ... [2021-12-06 18:30:34,875 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:30:34" (1/1) ... [2021-12-06 18:30:34,894 INFO L137 Inliner]: procedures = 164, calls = 26, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 71 [2021-12-06 18:30:34,894 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-06 18:30:34,895 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-06 18:30:34,895 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-06 18:30:34,895 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-06 18:30:34,903 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:30:34" (1/1) ... [2021-12-06 18:30:34,903 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:30:34" (1/1) ... [2021-12-06 18:30:34,906 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:30:34" (1/1) ... [2021-12-06 18:30:34,907 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:30:34" (1/1) ... [2021-12-06 18:30:34,913 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:30:34" (1/1) ... [2021-12-06 18:30:34,916 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:30:34" (1/1) ... [2021-12-06 18:30:34,918 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:30:34" (1/1) ... [2021-12-06 18:30:34,922 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-06 18:30:34,923 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-06 18:30:34,923 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-06 18:30:34,923 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-06 18:30:34,924 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:30:34" (1/1) ... [2021-12-06 18:30:34,930 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2021-12-06 18:30:34,938 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:30:34,949 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2021-12-06 18:30:34,951 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2021-12-06 18:30:34,986 INFO L130 BoogieDeclarations]: Found specification of procedure t1 [2021-12-06 18:30:34,986 INFO L138 BoogieDeclarations]: Found implementation of procedure t1 [2021-12-06 18:30:34,986 INFO L130 BoogieDeclarations]: Found specification of procedure t2 [2021-12-06 18:30:34,986 INFO L138 BoogieDeclarations]: Found implementation of procedure t2 [2021-12-06 18:30:34,986 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2021-12-06 18:30:34,986 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2021-12-06 18:30:34,987 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-06 18:30:34,987 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-12-06 18:30:34,987 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2021-12-06 18:30:34,987 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-06 18:30:34,987 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2021-12-06 18:30:34,987 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-06 18:30:34,987 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-06 18:30:34,989 WARN L209 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2021-12-06 18:30:35,070 INFO L236 CfgBuilder]: Building ICFG [2021-12-06 18:30:35,072 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-06 18:30:35,191 INFO L277 CfgBuilder]: Performing block encoding [2021-12-06 18:30:35,197 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-06 18:30:35,197 INFO L301 CfgBuilder]: Removed 3 assume(true) statements. [2021-12-06 18:30:35,199 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 06:30:35 BoogieIcfgContainer [2021-12-06 18:30:35,199 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-06 18:30:35,200 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2021-12-06 18:30:35,200 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2021-12-06 18:30:35,203 INFO L275 PluginConnector]: TraceAbstraction initialized [2021-12-06 18:30:35,203 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 06.12 06:30:34" (1/3) ... [2021-12-06 18:30:35,203 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@15670511 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.12 06:30:35, skipping insertion in model container [2021-12-06 18:30:35,203 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:30:34" (2/3) ... [2021-12-06 18:30:35,204 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@15670511 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.12 06:30:35, skipping insertion in model container [2021-12-06 18:30:35,204 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 06:30:35" (3/3) ... [2021-12-06 18:30:35,205 INFO L111 eAbstractionObserver]: Analyzing ICFG fib_safe-6.i [2021-12-06 18:30:35,208 WARN L149 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2021-12-06 18:30:35,208 INFO L204 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2021-12-06 18:30:35,209 INFO L163 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2021-12-06 18:30:35,209 INFO L513 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2021-12-06 18:30:35,231 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,231 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,231 WARN L322 ript$VariableManager]: TermVariabe t1Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,231 WARN L322 ript$VariableManager]: TermVariabe t1Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,231 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,231 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,232 WARN L322 ript$VariableManager]: TermVariabe t1Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,232 WARN L322 ript$VariableManager]: TermVariabe t1Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,232 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,232 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,232 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,233 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,233 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#t~post1| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,233 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#t~post1| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,233 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#t~post1| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,233 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#t~post1| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,233 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#t~post1| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,234 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#t~post1| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,234 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,234 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,234 WARN L322 ript$VariableManager]: TermVariabe t2Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,234 WARN L322 ript$VariableManager]: TermVariabe t2Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,234 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,235 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,235 WARN L322 ript$VariableManager]: TermVariabe t2Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,235 WARN L322 ript$VariableManager]: TermVariabe t2Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,235 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,235 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,235 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,236 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,236 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#t~post2| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,236 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#t~post2| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,236 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#t~post2| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,236 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#t~post2| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,236 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#t~post2| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,237 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#t~post2| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,239 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#t~post1| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,239 WARN L322 ript$VariableManager]: TermVariabe t1Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,239 WARN L322 ript$VariableManager]: TermVariabe t1Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,240 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,240 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,242 WARN L322 ript$VariableManager]: TermVariabe t2Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,243 WARN L322 ript$VariableManager]: TermVariabe t2Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,243 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,243 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#t~post2| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,243 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 18:30:35,244 INFO L148 ThreadInstanceAdder]: Constructed 0 joinOtherThreadTransitions. [2021-12-06 18:30:35,281 INFO L338 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2021-12-06 18:30:35,286 INFO L339 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mLoopAccelerationTechnique=FAST_UPR [2021-12-06 18:30:35,286 INFO L340 AbstractCegarLoop]: Starting to check reachability of 3 error locations. [2021-12-06 18:30:35,296 INFO L74 FinitePrefix]: Start finitePrefix. Operand has 96 places, 96 transitions, 202 flow [2021-12-06 18:30:35,331 INFO L129 PetriNetUnfolder]: 7/94 cut-off events. [2021-12-06 18:30:35,331 INFO L130 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2021-12-06 18:30:35,334 INFO L84 FinitePrefix]: Finished finitePrefix Result has 101 conditions, 94 events. 7/94 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 3. Compared 73 event pairs, 0 based on Foata normal form. 0/86 useless extension candidates. Maximal degree in co-relation 64. Up to 2 conditions per place. [2021-12-06 18:30:35,335 INFO L82 GeneralOperation]: Start removeDead. Operand has 96 places, 96 transitions, 202 flow [2021-12-06 18:30:35,338 INFO L88 GeneralOperation]: Finished RemoveDead, result has has 94 places, 94 transitions, 194 flow [2021-12-06 18:30:35,355 INFO L129 PetriNetUnfolder]: 7/85 cut-off events. [2021-12-06 18:30:35,355 INFO L130 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2021-12-06 18:30:35,355 INFO L246 CegarLoopForPetriNet]: Found error trace [2021-12-06 18:30:35,356 INFO L254 CegarLoopForPetriNet]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:30:35,356 INFO L402 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION] === [2021-12-06 18:30:35,360 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:30:35,360 INFO L85 PathProgramCache]: Analyzing trace with hash -1927097680, now seen corresponding path program 1 times [2021-12-06 18:30:35,366 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:30:35,366 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [682959560] [2021-12-06 18:30:35,367 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:30:35,367 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:30:35,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:30:35,529 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:30:35,529 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:30:35,530 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [682959560] [2021-12-06 18:30:35,530 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [682959560] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:30:35,530 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:30:35,530 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 18:30:35,531 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [748517034] [2021-12-06 18:30:35,532 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:30:35,538 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2021-12-06 18:30:35,538 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:30:35,557 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-12-06 18:30:35,558 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-12-06 18:30:35,560 INFO L499 CegarLoopForPetriNet]: Number of universal loopers: 89 out of 96 [2021-12-06 18:30:35,563 INFO L92 encePairwiseOnDemand]: Start differencePairwiseOnDemand. First operand has 94 places, 94 transitions, 194 flow. Second operand has 2 states, 2 states have (on average 90.5) internal successors, (181), 2 states have internal predecessors, (181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:30:35,563 INFO L101 encePairwiseOnDemand]: Universal subtrahend loopers provided by user. [2021-12-06 18:30:35,563 INFO L102 encePairwiseOnDemand]: Number of universal subtrahend loopers: 89 of 96 [2021-12-06 18:30:35,564 INFO L74 FinitePrefix]: Start finitePrefix. Operand will be constructed on-demand [2021-12-06 18:30:35,588 INFO L129 PetriNetUnfolder]: 3/89 cut-off events. [2021-12-06 18:30:35,588 INFO L130 PetriNetUnfolder]: For 2/2 co-relation queries the response was YES. [2021-12-06 18:30:35,589 INFO L84 FinitePrefix]: Finished finitePrefix Result has 99 conditions, 89 events. 3/89 cut-off events. For 2/2 co-relation queries the response was YES. Maximal size of possible extension queue 3. Compared 62 event pairs, 0 based on Foata normal form. 5/90 useless extension candidates. Maximal degree in co-relation 60. Up to 3 conditions per place. [2021-12-06 18:30:35,590 INFO L132 encePairwiseOnDemand]: 92/96 looper letters, 2 selfloop transitions, 0 changer transitions 0/89 dead transitions. [2021-12-06 18:30:35,590 INFO L138 encePairwiseOnDemand]: Finished differencePairwiseOnDemand. Result has 94 places, 89 transitions, 188 flow [2021-12-06 18:30:35,591 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-12-06 18:30:35,593 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2 states. [2021-12-06 18:30:35,598 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 184 transitions. [2021-12-06 18:30:35,600 INFO L544 CegarLoopForPetriNet]: DFA transition density 0.9583333333333334 [2021-12-06 18:30:35,600 INFO L72 ComplementDD]: Start complementDD. Operand 2 states and 184 transitions. [2021-12-06 18:30:35,600 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2 states and 184 transitions. [2021-12-06 18:30:35,601 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:30:35,603 INFO L117 ReachableStatesCopy]: Start reachableStatesCopy. Operand 2 states and 184 transitions. [2021-12-06 18:30:35,605 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends has 3 states, 2 states have (on average 92.0) internal successors, (184), 2 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:30:35,608 INFO L131 ReachableStatesCopy]: Finished reachableStatesCopy Result has 3 states, 3 states have (on average 96.0) internal successors, (288), 3 states have internal predecessors, (288), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:30:35,608 INFO L81 ComplementDD]: Finished complementDD. Result has 3 states, 3 states have (on average 96.0) internal successors, (288), 3 states have internal predecessors, (288), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:30:35,610 INFO L186 Difference]: Start difference. First operand has 94 places, 94 transitions, 194 flow. Second operand 2 states and 184 transitions. [2021-12-06 18:30:35,610 INFO L82 GeneralOperation]: Start removeRedundantFlow. Operand has 94 places, 89 transitions, 188 flow [2021-12-06 18:30:35,613 INFO L88 GeneralOperation]: Finished removeRedundantFlow, result has has 92 places, 89 transitions, 186 flow, removed 0 selfloop flow, removed 2 redundant places. [2021-12-06 18:30:35,616 INFO L242 Difference]: Finished difference. Result has 92 places, 89 transitions, 182 flow [2021-12-06 18:30:35,617 INFO L317 CegarLoopForPetriNet]: {PETRI_ALPHABET=96, PETRI_DIFFERENCE_MINUEND_FLOW=182, PETRI_DIFFERENCE_MINUEND_PLACES=91, PETRI_DIFFERENCE_MINUEND_TRANSITIONS=89, PETRI_DIFFERENCE_SUBTRAHEND_LETTERS_WITH_MORE_CHANGERS_THAN_LOOPERS=0, PETRI_DIFFERENCE_SUBTRAHEND_LOOPER_ONLY_LETTERS=89, PETRI_DIFFERENCE_SUBTRAHEND_STATES=2, PETRI_FLOW=182, PETRI_PLACES=92, PETRI_TRANSITIONS=89} [2021-12-06 18:30:35,620 INFO L334 CegarLoopForPetriNet]: 94 programPoint places, -2 predicate places. [2021-12-06 18:30:35,620 INFO L470 AbstractCegarLoop]: Abstraction has has 92 places, 89 transitions, 182 flow [2021-12-06 18:30:35,620 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 90.5) internal successors, (181), 2 states have internal predecessors, (181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:30:35,620 INFO L246 CegarLoopForPetriNet]: Found error trace [2021-12-06 18:30:35,621 INFO L254 CegarLoopForPetriNet]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:30:35,621 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2021-12-06 18:30:35,621 INFO L402 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION] === [2021-12-06 18:30:35,621 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:30:35,622 INFO L85 PathProgramCache]: Analyzing trace with hash 560415153, now seen corresponding path program 1 times [2021-12-06 18:30:35,622 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:30:35,622 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [628669949] [2021-12-06 18:30:35,622 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:30:35,622 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:30:35,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:30:35,689 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:30:35,689 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:30:35,689 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [628669949] [2021-12-06 18:30:35,689 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [628669949] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:30:35,689 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:30:35,690 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:30:35,690 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [274421973] [2021-12-06 18:30:35,690 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:30:35,691 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2021-12-06 18:30:35,691 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:30:35,691 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 18:30:35,692 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 18:30:35,693 INFO L499 CegarLoopForPetriNet]: Number of universal loopers: 83 out of 96 [2021-12-06 18:30:35,693 INFO L92 encePairwiseOnDemand]: Start differencePairwiseOnDemand. First operand has 92 places, 89 transitions, 182 flow. Second operand has 3 states, 3 states have (on average 84.66666666666667) internal successors, (254), 3 states have internal predecessors, (254), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:30:35,693 INFO L101 encePairwiseOnDemand]: Universal subtrahend loopers provided by user. [2021-12-06 18:30:35,694 INFO L102 encePairwiseOnDemand]: Number of universal subtrahend loopers: 83 of 96 [2021-12-06 18:30:35,694 INFO L74 FinitePrefix]: Start finitePrefix. Operand will be constructed on-demand [2021-12-06 18:30:35,723 INFO L129 PetriNetUnfolder]: 3/95 cut-off events. [2021-12-06 18:30:35,723 INFO L130 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2021-12-06 18:30:35,724 INFO L84 FinitePrefix]: Finished finitePrefix Result has 113 conditions, 95 events. 3/95 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 3. Compared 60 event pairs, 0 based on Foata normal form. 0/91 useless extension candidates. Maximal degree in co-relation 110. Up to 6 conditions per place. [2021-12-06 18:30:35,724 INFO L132 encePairwiseOnDemand]: 93/96 looper letters, 9 selfloop transitions, 2 changer transitions 0/92 dead transitions. [2021-12-06 18:30:35,724 INFO L138 encePairwiseOnDemand]: Finished differencePairwiseOnDemand. Result has 94 places, 92 transitions, 210 flow [2021-12-06 18:30:35,725 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 18:30:35,725 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2021-12-06 18:30:35,726 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 261 transitions. [2021-12-06 18:30:35,727 INFO L544 CegarLoopForPetriNet]: DFA transition density 0.90625 [2021-12-06 18:30:35,727 INFO L72 ComplementDD]: Start complementDD. Operand 3 states and 261 transitions. [2021-12-06 18:30:35,727 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3 states and 261 transitions. [2021-12-06 18:30:35,728 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:30:35,728 INFO L117 ReachableStatesCopy]: Start reachableStatesCopy. Operand 3 states and 261 transitions. [2021-12-06 18:30:35,729 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends has 4 states, 3 states have (on average 87.0) internal successors, (261), 3 states have internal predecessors, (261), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:30:35,731 INFO L131 ReachableStatesCopy]: Finished reachableStatesCopy Result has 4 states, 4 states have (on average 96.0) internal successors, (384), 4 states have internal predecessors, (384), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:30:35,731 INFO L81 ComplementDD]: Finished complementDD. Result has 4 states, 4 states have (on average 96.0) internal successors, (384), 4 states have internal predecessors, (384), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:30:35,731 INFO L186 Difference]: Start difference. First operand has 92 places, 89 transitions, 182 flow. Second operand 3 states and 261 transitions. [2021-12-06 18:30:35,732 INFO L82 GeneralOperation]: Start removeRedundantFlow. Operand has 94 places, 92 transitions, 210 flow [2021-12-06 18:30:35,732 INFO L88 GeneralOperation]: Finished removeRedundantFlow, result has has 94 places, 92 transitions, 210 flow, removed 0 selfloop flow, removed 0 redundant places. [2021-12-06 18:30:35,734 INFO L242 Difference]: Finished difference. Result has 95 places, 90 transitions, 194 flow [2021-12-06 18:30:35,734 INFO L317 CegarLoopForPetriNet]: {PETRI_ALPHABET=96, PETRI_DIFFERENCE_MINUEND_FLOW=182, PETRI_DIFFERENCE_MINUEND_PLACES=92, PETRI_DIFFERENCE_MINUEND_TRANSITIONS=89, PETRI_DIFFERENCE_SUBTRAHEND_LETTERS_WITH_MORE_CHANGERS_THAN_LOOPERS=1, PETRI_DIFFERENCE_SUBTRAHEND_LOOPER_ONLY_LETTERS=87, PETRI_DIFFERENCE_SUBTRAHEND_STATES=3, PETRI_FLOW=194, PETRI_PLACES=95, PETRI_TRANSITIONS=90} [2021-12-06 18:30:35,735 INFO L334 CegarLoopForPetriNet]: 94 programPoint places, 1 predicate places. [2021-12-06 18:30:35,735 INFO L470 AbstractCegarLoop]: Abstraction has has 95 places, 90 transitions, 194 flow [2021-12-06 18:30:35,736 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 84.66666666666667) internal successors, (254), 3 states have internal predecessors, (254), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:30:35,736 INFO L246 CegarLoopForPetriNet]: Found error trace [2021-12-06 18:30:35,736 INFO L254 CegarLoopForPetriNet]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:30:35,736 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2021-12-06 18:30:35,736 INFO L402 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION] === [2021-12-06 18:30:35,737 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:30:35,737 INFO L85 PathProgramCache]: Analyzing trace with hash -951035470, now seen corresponding path program 1 times [2021-12-06 18:30:35,737 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:30:35,737 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1582526314] [2021-12-06 18:30:35,737 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:30:35,737 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:30:35,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:30:35,802 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:30:35,803 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:30:35,803 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1582526314] [2021-12-06 18:30:35,803 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1582526314] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 18:30:35,803 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1899222180] [2021-12-06 18:30:35,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:30:35,803 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 18:30:35,804 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:30:35,804 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 18:30:35,805 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2021-12-06 18:30:35,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:30:35,873 INFO L263 TraceCheckSpWp]: Trace formula consists of 152 conjuncts, 4 conjunts are in the unsatisfiable core [2021-12-06 18:30:35,877 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 18:30:35,994 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:30:35,994 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 18:30:36,069 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:30:36,069 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1899222180] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 18:30:36,069 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 18:30:36,069 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 10 [2021-12-06 18:30:36,069 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1216148368] [2021-12-06 18:30:36,070 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 18:30:36,070 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2021-12-06 18:30:36,070 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:30:36,071 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2021-12-06 18:30:36,071 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2021-12-06 18:30:36,073 INFO L499 CegarLoopForPetriNet]: Number of universal loopers: 81 out of 96 [2021-12-06 18:30:36,074 INFO L92 encePairwiseOnDemand]: Start differencePairwiseOnDemand. First operand has 95 places, 90 transitions, 194 flow. Second operand has 10 states, 10 states have (on average 83.0) internal successors, (830), 10 states have internal predecessors, (830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:30:36,074 INFO L101 encePairwiseOnDemand]: Universal subtrahend loopers provided by user. [2021-12-06 18:30:36,074 INFO L102 encePairwiseOnDemand]: Number of universal subtrahend loopers: 81 of 96 [2021-12-06 18:30:36,074 INFO L74 FinitePrefix]: Start finitePrefix. Operand will be constructed on-demand [2021-12-06 18:30:36,134 INFO L129 PetriNetUnfolder]: 3/104 cut-off events. [2021-12-06 18:30:36,135 INFO L130 PetriNetUnfolder]: For 3/3 co-relation queries the response was YES. [2021-12-06 18:30:36,136 INFO L84 FinitePrefix]: Finished finitePrefix Result has 138 conditions, 104 events. 3/104 cut-off events. For 3/3 co-relation queries the response was YES. Maximal size of possible extension queue 3. Compared 51 event pairs, 0 based on Foata normal form. 2/103 useless extension candidates. Maximal degree in co-relation 133. Up to 6 conditions per place. [2021-12-06 18:30:36,136 INFO L132 encePairwiseOnDemand]: 90/96 looper letters, 10 selfloop transitions, 9 changer transitions 0/98 dead transitions. [2021-12-06 18:30:36,136 INFO L138 encePairwiseOnDemand]: Finished differencePairwiseOnDemand. Result has 103 places, 98 transitions, 250 flow [2021-12-06 18:30:36,137 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2021-12-06 18:30:36,137 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9 states. [2021-12-06 18:30:36,139 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 750 transitions. [2021-12-06 18:30:36,140 INFO L544 CegarLoopForPetriNet]: DFA transition density 0.8680555555555556 [2021-12-06 18:30:36,140 INFO L72 ComplementDD]: Start complementDD. Operand 9 states and 750 transitions. [2021-12-06 18:30:36,140 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9 states and 750 transitions. [2021-12-06 18:30:36,141 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:30:36,141 INFO L117 ReachableStatesCopy]: Start reachableStatesCopy. Operand 9 states and 750 transitions. [2021-12-06 18:30:36,143 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends has 10 states, 9 states have (on average 83.33333333333333) internal successors, (750), 9 states have internal predecessors, (750), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:30:36,151 INFO L131 ReachableStatesCopy]: Finished reachableStatesCopy Result has 10 states, 10 states have (on average 96.0) internal successors, (960), 10 states have internal predecessors, (960), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:30:36,152 INFO L81 ComplementDD]: Finished complementDD. Result has 10 states, 10 states have (on average 96.0) internal successors, (960), 10 states have internal predecessors, (960), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:30:36,152 INFO L186 Difference]: Start difference. First operand has 95 places, 90 transitions, 194 flow. Second operand 9 states and 750 transitions. [2021-12-06 18:30:36,152 INFO L82 GeneralOperation]: Start removeRedundantFlow. Operand has 103 places, 98 transitions, 250 flow [2021-12-06 18:30:36,154 INFO L88 GeneralOperation]: Finished removeRedundantFlow, result has has 102 places, 98 transitions, 248 flow, removed 0 selfloop flow, removed 1 redundant places. [2021-12-06 18:30:36,156 INFO L242 Difference]: Finished difference. Result has 105 places, 96 transitions, 242 flow [2021-12-06 18:30:36,156 INFO L317 CegarLoopForPetriNet]: {PETRI_ALPHABET=96, PETRI_DIFFERENCE_MINUEND_FLOW=192, PETRI_DIFFERENCE_MINUEND_PLACES=94, PETRI_DIFFERENCE_MINUEND_TRANSITIONS=90, PETRI_DIFFERENCE_SUBTRAHEND_LETTERS_WITH_MORE_CHANGERS_THAN_LOOPERS=5, PETRI_DIFFERENCE_SUBTRAHEND_LOOPER_ONLY_LETTERS=84, PETRI_DIFFERENCE_SUBTRAHEND_STATES=9, PETRI_FLOW=242, PETRI_PLACES=105, PETRI_TRANSITIONS=96} [2021-12-06 18:30:36,157 INFO L334 CegarLoopForPetriNet]: 94 programPoint places, 11 predicate places. [2021-12-06 18:30:36,157 INFO L470 AbstractCegarLoop]: Abstraction has has 105 places, 96 transitions, 242 flow [2021-12-06 18:30:36,158 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 83.0) internal successors, (830), 10 states have internal predecessors, (830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:30:36,158 INFO L246 CegarLoopForPetriNet]: Found error trace [2021-12-06 18:30:36,159 INFO L254 CegarLoopForPetriNet]: trace histogram [3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:30:36,184 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2021-12-06 18:30:36,359 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable2 [2021-12-06 18:30:36,361 INFO L402 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION] === [2021-12-06 18:30:36,362 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:30:36,363 INFO L85 PathProgramCache]: Analyzing trace with hash 1666707666, now seen corresponding path program 2 times [2021-12-06 18:30:36,363 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:30:36,364 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [992789500] [2021-12-06 18:30:36,364 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:30:36,365 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:30:36,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:30:36,558 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:30:36,559 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:30:36,559 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [992789500] [2021-12-06 18:30:36,559 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [992789500] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 18:30:36,559 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [592057047] [2021-12-06 18:30:36,560 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-12-06 18:30:36,560 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 18:30:36,560 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:30:36,561 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 18:30:36,562 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2021-12-06 18:30:36,614 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-12-06 18:30:36,615 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 18:30:36,616 INFO L263 TraceCheckSpWp]: Trace formula consists of 176 conjuncts, 8 conjunts are in the unsatisfiable core [2021-12-06 18:30:36,617 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 18:30:36,708 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:30:36,708 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 18:30:36,807 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:30:36,807 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [592057047] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 18:30:36,807 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 18:30:36,807 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9] total 18 [2021-12-06 18:30:36,808 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1286851033] [2021-12-06 18:30:36,808 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 18:30:36,808 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2021-12-06 18:30:36,808 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:30:36,809 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2021-12-06 18:30:36,809 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=90, Invalid=216, Unknown=0, NotChecked=0, Total=306 [2021-12-06 18:30:36,811 INFO L499 CegarLoopForPetriNet]: Number of universal loopers: 81 out of 96 [2021-12-06 18:30:36,813 INFO L92 encePairwiseOnDemand]: Start differencePairwiseOnDemand. First operand has 105 places, 96 transitions, 242 flow. Second operand has 18 states, 18 states have (on average 83.0) internal successors, (1494), 18 states have internal predecessors, (1494), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:30:36,813 INFO L101 encePairwiseOnDemand]: Universal subtrahend loopers provided by user. [2021-12-06 18:30:36,813 INFO L102 encePairwiseOnDemand]: Number of universal subtrahend loopers: 81 of 96 [2021-12-06 18:30:36,813 INFO L74 FinitePrefix]: Start finitePrefix. Operand will be constructed on-demand [2021-12-06 18:30:36,939 INFO L129 PetriNetUnfolder]: 3/132 cut-off events. [2021-12-06 18:30:36,939 INFO L130 PetriNetUnfolder]: For 30/30 co-relation queries the response was YES. [2021-12-06 18:30:36,941 INFO L84 FinitePrefix]: Finished finitePrefix Result has 231 conditions, 132 events. 3/132 cut-off events. For 30/30 co-relation queries the response was YES. Maximal size of possible extension queue 3. Compared 51 event pairs, 0 based on Foata normal form. 4/133 useless extension candidates. Maximal degree in co-relation 224. Up to 11 conditions per place. [2021-12-06 18:30:36,941 INFO L132 encePairwiseOnDemand]: 90/96 looper letters, 14 selfloop transitions, 21 changer transitions 0/114 dead transitions. [2021-12-06 18:30:36,941 INFO L138 encePairwiseOnDemand]: Finished differencePairwiseOnDemand. Result has 125 places, 114 transitions, 408 flow [2021-12-06 18:30:36,942 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2021-12-06 18:30:36,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2021-12-06 18:30:36,945 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 1740 transitions. [2021-12-06 18:30:36,946 INFO L544 CegarLoopForPetriNet]: DFA transition density 0.8630952380952381 [2021-12-06 18:30:36,946 INFO L72 ComplementDD]: Start complementDD. Operand 21 states and 1740 transitions. [2021-12-06 18:30:36,946 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21 states and 1740 transitions. [2021-12-06 18:30:36,947 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:30:36,947 INFO L117 ReachableStatesCopy]: Start reachableStatesCopy. Operand 21 states and 1740 transitions. [2021-12-06 18:30:36,952 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends has 22 states, 21 states have (on average 82.85714285714286) internal successors, (1740), 21 states have internal predecessors, (1740), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:30:36,955 INFO L131 ReachableStatesCopy]: Finished reachableStatesCopy Result has 22 states, 22 states have (on average 96.0) internal successors, (2112), 22 states have internal predecessors, (2112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:30:36,956 INFO L81 ComplementDD]: Finished complementDD. Result has 22 states, 22 states have (on average 96.0) internal successors, (2112), 22 states have internal predecessors, (2112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:30:36,956 INFO L186 Difference]: Start difference. First operand has 105 places, 96 transitions, 242 flow. Second operand 21 states and 1740 transitions. [2021-12-06 18:30:36,956 INFO L82 GeneralOperation]: Start removeRedundantFlow. Operand has 125 places, 114 transitions, 408 flow [2021-12-06 18:30:36,959 INFO L88 GeneralOperation]: Finished removeRedundantFlow, result has has 124 places, 114 transitions, 394 flow, removed 6 selfloop flow, removed 1 redundant places. [2021-12-06 18:30:36,961 INFO L242 Difference]: Finished difference. Result has 129 places, 109 transitions, 366 flow [2021-12-06 18:30:36,961 INFO L317 CegarLoopForPetriNet]: {PETRI_ALPHABET=96, PETRI_DIFFERENCE_MINUEND_FLOW=236, PETRI_DIFFERENCE_MINUEND_PLACES=104, PETRI_DIFFERENCE_MINUEND_TRANSITIONS=96, PETRI_DIFFERENCE_SUBTRAHEND_LETTERS_WITH_MORE_CHANGERS_THAN_LOOPERS=10, PETRI_DIFFERENCE_SUBTRAHEND_LOOPER_ONLY_LETTERS=85, PETRI_DIFFERENCE_SUBTRAHEND_STATES=21, PETRI_FLOW=366, PETRI_PLACES=129, PETRI_TRANSITIONS=109} [2021-12-06 18:30:36,962 INFO L334 CegarLoopForPetriNet]: 94 programPoint places, 35 predicate places. [2021-12-06 18:30:36,962 INFO L470 AbstractCegarLoop]: Abstraction has has 129 places, 109 transitions, 366 flow [2021-12-06 18:30:36,962 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 83.0) internal successors, (1494), 18 states have internal predecessors, (1494), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:30:36,962 INFO L246 CegarLoopForPetriNet]: Found error trace [2021-12-06 18:30:36,963 INFO L254 CegarLoopForPetriNet]: trace histogram [7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:30:36,983 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Ended with exit code 0 [2021-12-06 18:30:37,163 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3,3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 18:30:37,165 INFO L402 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION] === [2021-12-06 18:30:37,166 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:30:37,166 INFO L85 PathProgramCache]: Analyzing trace with hash -1283180782, now seen corresponding path program 3 times [2021-12-06 18:30:37,166 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:30:37,167 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [941875301] [2021-12-06 18:30:37,167 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:30:37,167 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:30:37,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:30:37,409 INFO L134 CoverageAnalysis]: Checked inductivity of 154 backedges. 0 proven. 154 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:30:37,410 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:30:37,410 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [941875301] [2021-12-06 18:30:37,410 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [941875301] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 18:30:37,410 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [671459535] [2021-12-06 18:30:37,410 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-12-06 18:30:37,411 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 18:30:37,411 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:30:37,412 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 18:30:37,412 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2021-12-06 18:30:37,467 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2021-12-06 18:30:37,467 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 18:30:37,469 INFO L263 TraceCheckSpWp]: Trace formula consists of 224 conjuncts, 16 conjunts are in the unsatisfiable core [2021-12-06 18:30:37,472 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 18:30:37,582 INFO L134 CoverageAnalysis]: Checked inductivity of 154 backedges. 0 proven. 154 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:30:37,582 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 18:30:37,765 INFO L134 CoverageAnalysis]: Checked inductivity of 154 backedges. 0 proven. 154 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:30:37,765 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [671459535] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 18:30:37,766 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 18:30:37,766 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17] total 31 [2021-12-06 18:30:37,766 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1557030036] [2021-12-06 18:30:37,766 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 18:30:37,767 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 31 states [2021-12-06 18:30:37,767 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:30:37,767 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2021-12-06 18:30:37,768 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=255, Invalid=675, Unknown=0, NotChecked=0, Total=930 [2021-12-06 18:30:37,770 INFO L499 CegarLoopForPetriNet]: Number of universal loopers: 81 out of 96 [2021-12-06 18:30:37,773 INFO L92 encePairwiseOnDemand]: Start differencePairwiseOnDemand. First operand has 129 places, 109 transitions, 366 flow. Second operand has 31 states, 31 states have (on average 83.06451612903226) internal successors, (2575), 31 states have internal predecessors, (2575), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:30:37,773 INFO L101 encePairwiseOnDemand]: Universal subtrahend loopers provided by user. [2021-12-06 18:30:37,773 INFO L102 encePairwiseOnDemand]: Number of universal subtrahend loopers: 81 of 96 [2021-12-06 18:30:37,773 INFO L74 FinitePrefix]: Start finitePrefix. Operand will be constructed on-demand [2021-12-06 18:30:38,103 INFO L129 PetriNetUnfolder]: 3/181 cut-off events. [2021-12-06 18:30:38,104 INFO L130 PetriNetUnfolder]: For 236/236 co-relation queries the response was YES. [2021-12-06 18:30:38,106 INFO L84 FinitePrefix]: Finished finitePrefix Result has 427 conditions, 181 events. 3/181 cut-off events. For 236/236 co-relation queries the response was YES. Maximal size of possible extension queue 3. Compared 51 event pairs, 0 based on Foata normal form. 7/185 useless extension candidates. Maximal degree in co-relation 415. Up to 25 conditions per place. [2021-12-06 18:30:38,107 INFO L132 encePairwiseOnDemand]: 90/96 looper letters, 21 selfloop transitions, 42 changer transitions 0/142 dead transitions. [2021-12-06 18:30:38,107 INFO L138 encePairwiseOnDemand]: Finished differencePairwiseOnDemand. Result has 170 places, 142 transitions, 748 flow [2021-12-06 18:30:38,108 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2021-12-06 18:30:38,108 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42 states. [2021-12-06 18:30:38,116 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 3472 transitions. [2021-12-06 18:30:38,118 INFO L544 CegarLoopForPetriNet]: DFA transition density 0.8611111111111112 [2021-12-06 18:30:38,118 INFO L72 ComplementDD]: Start complementDD. Operand 42 states and 3472 transitions. [2021-12-06 18:30:38,118 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42 states and 3472 transitions. [2021-12-06 18:30:38,121 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 18:30:38,121 INFO L117 ReachableStatesCopy]: Start reachableStatesCopy. Operand 42 states and 3472 transitions. [2021-12-06 18:30:38,131 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends has 43 states, 42 states have (on average 82.66666666666667) internal successors, (3472), 42 states have internal predecessors, (3472), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:30:38,140 INFO L131 ReachableStatesCopy]: Finished reachableStatesCopy Result has 43 states, 43 states have (on average 96.0) internal successors, (4128), 43 states have internal predecessors, (4128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:30:38,142 INFO L81 ComplementDD]: Finished complementDD. Result has 43 states, 43 states have (on average 96.0) internal successors, (4128), 43 states have internal predecessors, (4128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:30:38,142 INFO L186 Difference]: Start difference. First operand has 129 places, 109 transitions, 366 flow. Second operand 42 states and 3472 transitions. [2021-12-06 18:30:38,142 INFO L82 GeneralOperation]: Start removeRedundantFlow. Operand has 170 places, 142 transitions, 748 flow [2021-12-06 18:30:38,148 INFO L88 GeneralOperation]: Finished removeRedundantFlow, result has has 164 places, 142 transitions, 710 flow, removed 13 selfloop flow, removed 6 redundant places. [2021-12-06 18:30:38,152 INFO L242 Difference]: Finished difference. Result has 172 places, 131 transitions, 614 flow [2021-12-06 18:30:38,152 INFO L317 CegarLoopForPetriNet]: {PETRI_ALPHABET=96, PETRI_DIFFERENCE_MINUEND_FLOW=342, PETRI_DIFFERENCE_MINUEND_PLACES=123, PETRI_DIFFERENCE_MINUEND_TRANSITIONS=109, PETRI_DIFFERENCE_SUBTRAHEND_LETTERS_WITH_MORE_CHANGERS_THAN_LOOPERS=22, PETRI_DIFFERENCE_SUBTRAHEND_LOOPER_ONLY_LETTERS=86, PETRI_DIFFERENCE_SUBTRAHEND_STATES=42, PETRI_FLOW=614, PETRI_PLACES=172, PETRI_TRANSITIONS=131} [2021-12-06 18:30:38,153 INFO L334 CegarLoopForPetriNet]: 94 programPoint places, 78 predicate places. [2021-12-06 18:30:38,153 INFO L470 AbstractCegarLoop]: Abstraction has has 172 places, 131 transitions, 614 flow [2021-12-06 18:30:38,154 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 31 states, 31 states have (on average 83.06451612903226) internal successors, (2575), 31 states have internal predecessors, (2575), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:30:38,154 INFO L246 CegarLoopForPetriNet]: Found error trace [2021-12-06 18:30:38,155 INFO L254 CegarLoopForPetriNet]: trace histogram [14, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:30:38,175 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Ended with exit code 0 [2021-12-06 18:30:38,355 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 18:30:38,355 INFO L402 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION] === [2021-12-06 18:30:38,356 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:30:38,356 INFO L85 PathProgramCache]: Analyzing trace with hash 2049692625, now seen corresponding path program 4 times [2021-12-06 18:30:38,356 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:30:38,356 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1219266209] [2021-12-06 18:30:38,356 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:30:38,357 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:30:38,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:30:39,422 INFO L134 CoverageAnalysis]: Checked inductivity of 651 backedges. 0 proven. 651 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:30:39,422 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:30:39,422 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1219266209] [2021-12-06 18:30:39,422 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1219266209] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 18:30:39,422 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [270276752] [2021-12-06 18:30:39,422 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-12-06 18:30:39,422 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 18:30:39,423 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:30:39,423 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 18:30:39,425 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d20071f2-e3f2-4775-a03d-8ee302af3dd8/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2021-12-06 18:30:39,479 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-12-06 18:30:39,480 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 18:30:39,481 INFO L263 TraceCheckSpWp]: Trace formula consists of 289 conjuncts, 47 conjunts are in the unsatisfiable core [2021-12-06 18:30:39,485 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 18:30:41,733 INFO L134 CoverageAnalysis]: Checked inductivity of 651 backedges. 486 proven. 165 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:30:41,733 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 18:39:35,727 INFO L134 CoverageAnalysis]: Checked inductivity of 651 backedges. 0 proven. 649 refuted. 2 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:39:35,727 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [270276752] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 18:39:35,727 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 18:39:35,727 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48, 48] total 139 [2021-12-06 18:39:35,727 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [651781312] [2021-12-06 18:39:35,728 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 18:39:35,728 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 139 states [2021-12-06 18:39:35,728 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:39:35,729 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 139 interpolants. [2021-12-06 18:39:35,734 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1240, Invalid=17791, Unknown=151, NotChecked=0, Total=19182 [2021-12-06 18:39:35,740 INFO L499 CegarLoopForPetriNet]: Number of universal loopers: 68 out of 96 [2021-12-06 18:39:35,748 INFO L92 encePairwiseOnDemand]: Start differencePairwiseOnDemand. First operand has 172 places, 131 transitions, 614 flow. Second operand has 139 states, 139 states have (on average 69.23741007194245) internal successors, (9624), 139 states have internal predecessors, (9624), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:39:35,748 INFO L101 encePairwiseOnDemand]: Universal subtrahend loopers provided by user. [2021-12-06 18:39:35,748 INFO L102 encePairwiseOnDemand]: Number of universal subtrahend loopers: 68 of 96 [2021-12-06 18:39:35,748 INFO L74 FinitePrefix]: Start finitePrefix. Operand will be constructed on-demand [2021-12-06 18:39:38,498 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse17 (* 2 c_~cur~0))) (let ((.cse6 (+ .cse17 c_~prev~0 3)) (.cse9 (* c_~i~0 (- 1))) (.cse3 (+ .cse17 c_~prev~0)) (.cse5 (* c_~j~0 (- 1))) (.cse10 (+ c_~prev~0 c_~cur~0 1))) (and (= c_~prev~0 0) (forall ((v_~j~0_8 Int)) (or (and (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse0 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_28 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse0 c_~prev~0 c_~cur~0 v_~cur~0_28 1)) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0 (* 2 v_~cur~0_28))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse0 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse1 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_28 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 v_~j~0_8) (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse1 c_~prev~0 c_~cur~0 v_~cur~0_28 1)) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0 (* 2 v_~cur~0_28))) (< (+ aux_mod_v_~next~0_20_56 (* 2 aux_mod_v_~cur~0_22_51) 10 v_~j~0_8) (+ (* 3 v_~prev~0_24) .cse1 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))) (< 1 v_~j~0_8))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse2 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse2 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_div_v_~cur~0_22_51 (+ .cse2 c_~prev~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56)))))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (<= c_~j~0 .cse3) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_mod_v_~next~0_20_56 0))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse4 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_28 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse4 c_~prev~0 c_~cur~0 v_~cur~0_28 1)) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0 (* 2 v_~cur~0_28))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse4 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (<= (div (+ .cse5 c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse6) (forall ((v_~cur~0_28 Int)) (or (< v_~cur~0_28 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse7 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse7 c_~cur~0 v_~cur~0_28 1)) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse7 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse8 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse8 c_~cur~0 v_~cur~0_28 1)) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse8 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26)))))))) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0)))))) (= c_~cur~0 1) (<= (div (+ .cse9 c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse6) (<= (div (+ (- 2) .cse9 c_~cur~0) (- 2)) .cse10) (<= c_~i~0 .cse3) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse11 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse11 c_~prev~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse11 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))))) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse12 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse12 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse12 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse13 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse13 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse13 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse14 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse14 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse14 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse15 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse15 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse15 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (<= (div (+ .cse5 (- 2) c_~cur~0) (- 2)) .cse10) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse16 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_28 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse16 c_~prev~0 c_~cur~0 v_~cur~0_28 1)) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse16 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)))))))) is different from false [2021-12-06 18:39:41,115 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse4 (+ (* 2 c_~cur~0) c_~prev~0 3))) (and (= c_~prev~0 0) (forall ((v_~j~0_8 Int)) (or (and (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse0 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_28 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse0 c_~prev~0 c_~cur~0 v_~cur~0_28 1)) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0 (* 2 v_~cur~0_28))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse0 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse1 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_28 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 v_~j~0_8) (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse1 c_~prev~0 c_~cur~0 v_~cur~0_28 1)) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0 (* 2 v_~cur~0_28))) (< (+ aux_mod_v_~next~0_20_56 (* 2 aux_mod_v_~cur~0_22_51) 10 v_~j~0_8) (+ (* 3 v_~prev~0_24) .cse1 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))) (< 1 v_~j~0_8))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse2 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse2 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_div_v_~cur~0_22_51 (+ .cse2 c_~prev~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56)))))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_mod_v_~next~0_20_56 0))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse3 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_28 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse3 c_~prev~0 c_~cur~0 v_~cur~0_28 1)) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0 (* 2 v_~cur~0_28))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse3 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (<= (div (+ (* c_~j~0 (- 1)) c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse4) (forall ((v_~cur~0_28 Int)) (or (< v_~cur~0_28 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse5 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse5 c_~cur~0 v_~cur~0_28 1)) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse5 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse6 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse6 c_~cur~0 v_~cur~0_28 1)) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse6 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26)))))))) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0)))))) (= c_~cur~0 1) (<= (div (+ (* c_~i~0 (- 1)) c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse4) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse7 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse7 c_~prev~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse7 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))))) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse8 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse8 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse8 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse9 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse9 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse9 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse10 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse10 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse10 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse11 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse11 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse11 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse12 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_28 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse12 c_~prev~0 c_~cur~0 v_~cur~0_28 1)) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse12 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28))))))) is different from false [2021-12-06 18:39:48,617 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse10 (* c_~j~0 (- 1))) (.cse7 (* c_~i~0 (- 1))) (.cse34 (* 2 c_~cur~0))) (let ((.cse3 (+ c_~next~0 1)) (.cse8 (+ c_~cur~0 4 (* 2 c_~next~0))) (.cse5 (+ c_~next~0 c_~cur~0 2)) (.cse11 (+ c_~next~0 c_~cur~0)) (.cse14 (+ .cse34 c_~prev~0 3)) (.cse2 (div (+ (- 2) .cse7 c_~cur~0) (- 2))) (.cse17 (div (+ .cse7 c_~next~0 (- 4)) (- 2))) (.cse12 (+ .cse34 c_~prev~0)) (.cse4 (div (+ .cse10 c_~next~0 (- 4)) (- 2))) (.cse25 (+ c_~next~0 c_~prev~0 2)) (.cse9 (div (+ .cse10 (- 2) c_~cur~0) (- 2))) (.cse21 (+ c_~prev~0 c_~cur~0 1))) (and (= c_~prev~0 0) (forall ((v_~j~0_8 Int)) (or (and (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse0 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_28 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse0 c_~prev~0 c_~cur~0 v_~cur~0_28 1)) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0 (* 2 v_~cur~0_28))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse0 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse1 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_28 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 v_~j~0_8) (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse1 c_~prev~0 c_~cur~0 v_~cur~0_28 1)) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0 (* 2 v_~cur~0_28))) (< (+ aux_mod_v_~next~0_20_56 (* 2 aux_mod_v_~cur~0_22_51) 10 v_~j~0_8) (+ (* 3 v_~prev~0_24) .cse1 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))) (< 1 v_~j~0_8))) (<= .cse2 .cse3) (<= .cse4 .cse5) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse6 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse6 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_div_v_~cur~0_22_51 (+ .cse6 c_~prev~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56)))))))) (<= (div (+ .cse7 c_~prev~0) (- 2)) c_~next~0) (<= (div (+ .cse7 c_~next~0 c_~cur~0 (- 8)) (- 2)) .cse8) (<= .cse9 .cse3) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (<= (div (+ .cse10 c_~next~0 c_~cur~0 (- 8)) (- 2)) .cse8) (<= c_~i~0 .cse11) (<= c_~j~0 .cse12) (<= (div (+ .cse10 c_~prev~0) (- 2)) c_~next~0) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_mod_v_~next~0_20_56 0))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse13 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_28 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse13 c_~prev~0 c_~cur~0 v_~cur~0_28 1)) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0 (* 2 v_~cur~0_28))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse13 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 c_~next~0) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (<= (div (+ .cse10 c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse14) (forall ((v_~cur~0_28 Int)) (or (< v_~cur~0_28 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse15 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse15 c_~cur~0 v_~cur~0_28 1)) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse15 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse16 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse16 c_~cur~0 v_~cur~0_28 1)) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse16 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26)))))))) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~prev~0_24 c_~next~0) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (<= .cse17 .cse5) (= c_~cur~0 1) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse18 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse18 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_28 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse18 c_~next~0 v_~cur~0_28 1)) (< v_~cur~0_26 (+ c_~next~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_28 v_~cur~0_26))))) (<= c_~j~0 .cse11) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse19 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse19 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse19 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse20 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse20 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse20 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))))) (<= (div (+ .cse7 c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse14) (<= .cse2 .cse21) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse22 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse22 c_~next~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse22 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_28 Int)) (or (< v_~cur~0_28 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse23 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse23 c_~cur~0 v_~cur~0_28 1)) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse23 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse24 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse24 c_~cur~0 v_~cur~0_28 1)) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse24 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26)))))))) (<= .cse17 .cse25) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse26 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse26 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse26 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0)))) (<= c_~i~0 .cse12) (<= .cse4 .cse25) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse27 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse27 c_~prev~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse27 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 c_~next~0) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56)))))))) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse28 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse28 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse28 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse29 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse29 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse29 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse30 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~cur~0_28 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse30 c_~next~0 v_~cur~0_28 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse30 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (< v_~cur~0_26 (+ c_~next~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_28 v_~cur~0_26))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse31 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse31 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse31 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse32 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse32 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse32 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (<= .cse9 .cse21) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse33 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_28 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse33 c_~prev~0 c_~cur~0 v_~cur~0_28 1)) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse33 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)))))))) is different from false [2021-12-06 18:41:43,841 WARN L227 SmtUtils]: Spent 11.87s on a formula simplification that was a NOOP. DAG size: 74 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2021-12-06 18:41:46,018 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse1 (+ c_~next~0 1)) (.cse2 (* c_~j~0 (- 1))) (.cse4 (+ c_~cur~0 4 (* 2 c_~next~0))) (.cse0 (* c_~i~0 (- 1))) (.cse3 (+ c_~next~0 c_~cur~0 2)) (.cse5 (+ c_~next~0 c_~cur~0))) (and (<= (div (+ (- 2) .cse0 c_~cur~0) (- 2)) .cse1) (<= (div (+ .cse2 c_~next~0 (- 4)) (- 2)) .cse3) (<= (div (+ .cse0 c_~next~0 c_~cur~0 (- 8)) (- 2)) .cse4) (<= (div (+ .cse2 (- 2) c_~cur~0) (- 2)) .cse1) (<= (div (+ .cse2 c_~next~0 c_~cur~0 (- 8)) (- 2)) .cse4) (<= c_~i~0 .cse5) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 c_~next~0) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~prev~0_24 c_~next~0) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (<= (div (+ .cse0 c_~next~0 (- 4)) (- 2)) .cse3) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse6 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse6 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_28 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse6 c_~next~0 v_~cur~0_28 1)) (< v_~cur~0_26 (+ c_~next~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_28 v_~cur~0_26))))) (<= c_~j~0 .cse5) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse7 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse7 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse7 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse8 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse8 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse8 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse9 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse9 c_~next~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse9 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_28 Int)) (or (< v_~cur~0_28 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse10 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse10 c_~cur~0 v_~cur~0_28 1)) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse10 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse11 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse11 c_~cur~0 v_~cur~0_28 1)) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse11 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26)))))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse12 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse12 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse12 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 c_~next~0) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56)))))))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse13 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~cur~0_28 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse13 c_~next~0 v_~cur~0_28 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse13 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (< v_~cur~0_26 (+ c_~next~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_28 v_~cur~0_26))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))))))) is different from false [2021-12-06 18:41:48,892 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse6 (+ c_~cur~0 4 (* 2 c_~next~0))) (.cse2 (* c_~j~0 (- 1))) (.cse3 (+ c_~next~0 c_~cur~0 2)) (.cse5 (* c_~i~0 (- 1))) (.cse8 (+ (* 2 c_~cur~0) c_~prev~0 3))) (and (= c_~prev~0 0) (forall ((v_~j~0_8 Int)) (or (and (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse0 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_28 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse0 c_~prev~0 c_~cur~0 v_~cur~0_28 1)) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0 (* 2 v_~cur~0_28))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse0 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse1 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_28 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 v_~j~0_8) (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse1 c_~prev~0 c_~cur~0 v_~cur~0_28 1)) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0 (* 2 v_~cur~0_28))) (< (+ aux_mod_v_~next~0_20_56 (* 2 aux_mod_v_~cur~0_22_51) 10 v_~j~0_8) (+ (* 3 v_~prev~0_24) .cse1 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))) (< 1 v_~j~0_8))) (<= (div (+ .cse2 c_~next~0 (- 4)) (- 2)) .cse3) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse4 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse4 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_div_v_~cur~0_22_51 (+ .cse4 c_~prev~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56)))))))) (<= (div (+ .cse5 c_~next~0 c_~cur~0 (- 8)) (- 2)) .cse6) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (<= (div (+ .cse2 c_~next~0 c_~cur~0 (- 8)) (- 2)) .cse6) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_mod_v_~next~0_20_56 0))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse7 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_28 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse7 c_~prev~0 c_~cur~0 v_~cur~0_28 1)) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0 (* 2 v_~cur~0_28))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse7 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 c_~next~0) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (<= (div (+ .cse2 c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse8) (forall ((v_~cur~0_28 Int)) (or (< v_~cur~0_28 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse9 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse9 c_~cur~0 v_~cur~0_28 1)) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse9 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse10 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse10 c_~cur~0 v_~cur~0_28 1)) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse10 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26)))))))) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~prev~0_24 c_~next~0) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (<= (div (+ .cse5 c_~next~0 (- 4)) (- 2)) .cse3) (= c_~cur~0 1) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse11 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse11 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_28 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse11 c_~next~0 v_~cur~0_28 1)) (< v_~cur~0_26 (+ c_~next~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_28 v_~cur~0_26))))) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse12 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse12 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse12 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse13 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse13 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse13 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))))) (<= (div (+ .cse5 c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse8) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse14 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse14 c_~next~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse14 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_28 Int)) (or (< v_~cur~0_28 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse15 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse15 c_~cur~0 v_~cur~0_28 1)) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse15 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse16 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse16 c_~cur~0 v_~cur~0_28 1)) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse16 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26)))))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse17 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse17 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse17 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse18 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse18 c_~prev~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse18 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 c_~next~0) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56)))))))) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse19 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse19 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse19 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse20 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse20 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse20 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse21 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~cur~0_28 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse21 c_~next~0 v_~cur~0_28 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse21 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (< v_~cur~0_26 (+ c_~next~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_28 v_~cur~0_26))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse22 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse22 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse22 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse23 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse23 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse23 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse24 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_28 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse24 c_~prev~0 c_~cur~0 v_~cur~0_28 1)) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse24 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28))))))) is different from false [2021-12-06 18:41:51,576 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse7 (+ c_~next~0 c_~prev~0)) (.cse5 (* c_~i~0 (- 1))) (.cse6 (* c_~j~0 (- 1))) (.cse11 (+ c_~next~0 c_~prev~0 2))) (and (forall ((aux_div_v_~cur~0_21_56 Int) (aux_mod_v_~cur~0_21_56 Int)) (or (<= (+ c_~prev~0 (* 5 aux_div_v_~cur~0_21_56)) (+ (* 2 c_~j~0) 15 (* 2 aux_mod_v_~cur~0_21_56))) (<= 2 aux_mod_v_~cur~0_21_56) (< (+ 6 c_~j~0 aux_mod_v_~cur~0_21_56) (+ (* 2 aux_div_v_~cur~0_21_56) c_~next~0 c_~prev~0)) (< aux_mod_v_~cur~0_21_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse0 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse0 c_~next~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse0 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~cur~0_26 (+ c_~next~0 c_~prev~0))))) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse1 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse1 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ .cse1 c_~prev~0 1)) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~prev~0 v_~cur~0_26))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse2 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse2 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ .cse2 c_~prev~0 1)) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~prev~0 v_~cur~0_26)))))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) (* 3 c_~prev~0))) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) c_~prev~0) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0))) (forall ((v_~cur~0_28 Int)) (or (< v_~cur~0_28 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse3 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse3 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (< v_~cur~0_26 (+ c_~prev~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 (+ c_~prev~0 v_~cur~0_28 v_~cur~0_26)) (< aux_div_v_~cur~0_22_51 (+ .cse3 c_~prev~0 v_~cur~0_28 1)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse4 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_26 (+ c_~prev~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~prev~0_24 (+ c_~prev~0 v_~cur~0_28 v_~cur~0_26)) (< aux_div_v_~cur~0_22_51 (+ .cse4 c_~prev~0 v_~cur~0_28 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse4 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (<= (div (+ .cse5 c_~prev~0) (- 2)) c_~next~0) (<= (div (+ .cse6 c_~prev~0) (- 2)) c_~next~0) (<= c_~j~0 .cse7) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse8 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse8 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse8 c_~next~0 v_~cur~0_28 1)) (< v_~cur~0_28 (+ c_~next~0 c_~prev~0)) (< v_~cur~0_26 (+ c_~next~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_28 v_~cur~0_26))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~prev~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 c_~next~0) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse9 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse9 c_~next~0 v_~cur~0_28 1)) (< v_~cur~0_28 (+ c_~next~0 c_~prev~0)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse9 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (< v_~cur~0_26 (+ c_~next~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_28 v_~cur~0_26))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) c_~prev~0) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) (* 3 c_~prev~0))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~prev~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< v_~prev~0_24 c_~next~0) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 c_~next~0) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56)))))))) (<= c_~i~0 .cse7) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse10 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse10 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse10 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0) (< v_~cur~0_26 (+ c_~next~0 c_~prev~0))))) (<= (div (+ .cse5 c_~next~0 (- 4)) (- 2)) .cse11) (<= (div (+ .cse6 c_~next~0 (- 4)) (- 2)) .cse11) (forall ((aux_div_v_~cur~0_21_56 Int) (aux_mod_v_~cur~0_21_56 Int)) (or (<= (+ c_~prev~0 (* 5 aux_div_v_~cur~0_21_56)) (+ 15 (* 2 aux_mod_v_~cur~0_21_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~cur~0_21_56) (< (+ 6 c_~i~0 aux_mod_v_~cur~0_21_56) (+ (* 2 aux_div_v_~cur~0_21_56) c_~next~0 c_~prev~0)) (< aux_mod_v_~cur~0_21_56 0))))) is different from false [2021-12-06 18:42:04,913 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse14 (* 2 c_~cur~0))) (let ((.cse0 (+ c_~prev~0 c_~cur~0)) (.cse4 (+ .cse14 c_~prev~0 3)) (.cse7 (* c_~i~0 (- 1))) (.cse2 (+ .cse14 c_~prev~0)) (.cse3 (* c_~j~0 (- 1))) (.cse8 (+ c_~prev~0 c_~cur~0 1))) (and (<= c_~j~0 .cse0) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse1 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse1 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_div_v_~cur~0_22_51 (+ .cse1 c_~prev~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56)))))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (<= c_~j~0 .cse2) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_mod_v_~next~0_20_56 0))) (<= (div (+ .cse3 c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse4) (forall ((v_~cur~0_28 Int)) (or (< v_~cur~0_28 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse5 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse5 c_~cur~0 v_~cur~0_28 1)) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse5 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse6 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse6 c_~cur~0 v_~cur~0_28 1)) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse6 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26)))))))) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0)))))) (<= c_~i~0 .cse0) (<= (div (+ .cse7 c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse4) (<= (div (+ (- 2) .cse7 c_~cur~0) (- 2)) .cse8) (<= c_~i~0 .cse2) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse9 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse9 c_~prev~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse9 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))))) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse10 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse10 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse10 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse11 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse11 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse11 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse12 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse12 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse12 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse13 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse13 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse13 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (<= (div (+ .cse3 (- 2) c_~cur~0) (- 2)) .cse8)))) is different from false [2021-12-06 18:42:11,128 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse8 (* c_~j~0 (- 1))) (.cse5 (* c_~i~0 (- 1))) (.cse26 (* 2 c_~cur~0))) (let ((.cse2 (+ c_~next~0 1)) (.cse6 (+ c_~cur~0 4 (* 2 c_~next~0))) (.cse0 (+ c_~prev~0 c_~cur~0)) (.cse4 (+ c_~next~0 c_~cur~0 2)) (.cse9 (+ c_~next~0 c_~cur~0)) (.cse13 (+ .cse26 c_~prev~0 3)) (.cse1 (div (+ (- 2) .cse5 c_~cur~0) (- 2))) (.cse11 (+ c_~next~0 c_~prev~0)) (.cse14 (div (+ .cse5 c_~next~0 (- 4)) (- 2))) (.cse10 (+ .cse26 c_~prev~0)) (.cse3 (div (+ .cse8 c_~next~0 (- 4)) (- 2))) (.cse22 (+ c_~next~0 c_~prev~0 2)) (.cse7 (div (+ .cse8 (- 2) c_~cur~0) (- 2))) (.cse18 (+ c_~prev~0 c_~cur~0 1))) (and (<= c_~j~0 .cse0) (<= .cse1 .cse2) (<= .cse3 .cse4) (<= (div (+ .cse5 c_~prev~0) (- 2)) c_~next~0) (<= (div (+ .cse5 c_~next~0 c_~cur~0 (- 8)) (- 2)) .cse6) (<= 1 c_~cur~0) (<= .cse7 .cse2) (<= (div (+ .cse8 c_~next~0 c_~cur~0 (- 8)) (- 2)) .cse6) (<= c_~i~0 .cse9) (<= c_~j~0 .cse10) (<= (div (+ .cse8 c_~prev~0) (- 2)) c_~next~0) (<= c_~j~0 .cse11) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse12 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_28 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse12 c_~prev~0 c_~cur~0 v_~cur~0_28 1)) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0 (* 2 v_~cur~0_28))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse12 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 c_~next~0) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (<= (div (+ .cse8 c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse13) (<= c_~i~0 c_~next~0) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~prev~0_24 c_~next~0) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (<= c_~i~0 .cse0) (<= 0 c_~prev~0) (<= .cse14 .cse4) (<= c_~j~0 c_~next~0) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse15 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse15 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_28 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse15 c_~next~0 v_~cur~0_28 1)) (< v_~cur~0_26 (+ c_~next~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_28 v_~cur~0_26))))) (<= c_~j~0 .cse9) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse16 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse16 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse16 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse17 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse17 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse17 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))))) (<= (div (+ .cse5 c_~prev~0 c_~cur~0 (- 6)) (- 2)) .cse13) (<= .cse1 .cse18) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse19 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse19 c_~next~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse19 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (<= c_~i~0 .cse11) (forall ((v_~cur~0_28 Int)) (or (< v_~cur~0_28 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse20 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse20 c_~cur~0 v_~cur~0_28 1)) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse20 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse21 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse21 c_~cur~0 v_~cur~0_28 1)) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse21 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26)))))))) (<= .cse14 .cse22) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse23 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse23 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse23 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0)))) (<= c_~i~0 .cse10) (<= .cse3 .cse22) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 c_~next~0) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56)))))))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse24 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~cur~0_28 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse24 c_~next~0 v_~cur~0_28 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse24 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (< v_~cur~0_26 (+ c_~next~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_28 v_~cur~0_26))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))))) (<= .cse7 .cse18) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse25 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~cur~0_28 (+ (* 2 c_~cur~0) c_~prev~0)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse25 c_~prev~0 c_~cur~0 v_~cur~0_28 1)) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_28 v_~cur~0_26)) (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse25 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)))))))) is different from false [2021-12-06 18:42:14,002 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse0 (* c_~j~0 (- 1))) (.cse3 (+ c_~cur~0 4 (* 2 c_~next~0))) (.cse2 (* c_~i~0 (- 1))) (.cse1 (+ c_~next~0 c_~cur~0 2))) (and (<= (div (+ .cse0 c_~next~0 (- 4)) (- 2)) .cse1) (<= (div (+ .cse2 c_~next~0 c_~cur~0 (- 8)) (- 2)) .cse3) (<= (div (+ .cse0 c_~next~0 c_~cur~0 (- 8)) (- 2)) .cse3) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 c_~next~0) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~prev~0_24 c_~next~0) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (<= (div (+ .cse2 c_~next~0 (- 4)) (- 2)) .cse1) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse4 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse4 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_28 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse4 c_~next~0 v_~cur~0_28 1)) (< v_~cur~0_26 (+ c_~next~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_28 v_~cur~0_26))))) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse5 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse5 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse5 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse6 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse6 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse6 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse7 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse7 c_~next~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse7 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_28 Int)) (or (< v_~cur~0_28 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse8 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse8 c_~cur~0 v_~cur~0_28 1)) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse8 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse9 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse9 c_~cur~0 v_~cur~0_28 1)) (< v_~cur~0_26 (+ c_~cur~0 (* 2 v_~cur~0_28))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse9 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_28 v_~cur~0_26)))))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse10 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ (* 2 c_~j~0) 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse10 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse10 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 c_~next~0) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56)))))))) (forall ((v_~cur~0_28 Int) (aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse11 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< v_~cur~0_28 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse11 c_~next~0 v_~cur~0_28 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 21 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 10) (+ (* 3 v_~prev~0_24) .cse11 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) v_~cur~0_28)) (< v_~cur~0_26 (+ c_~next~0 (* 2 v_~cur~0_28))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_28 v_~cur~0_26))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~i~0 8) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 20 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 c_~j~0 8) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 20 (* 2 aux_mod_v_~next~0_20_56))))))) is different from false