./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/pthread/fib_unsafe-5.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 839c364b Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/bin/uautomizer-DrprNOufMa/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/bin/uautomizer-DrprNOufMa/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/bin/uautomizer-DrprNOufMa/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/bin/uautomizer-DrprNOufMa/config/AutomizerReach.xml -i ../../sv-benchmarks/c/pthread/fib_unsafe-5.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/bin/uautomizer-DrprNOufMa/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/bin/uautomizer-DrprNOufMa --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 146f0d3d7f309689872842ec2e107172ef6d7d230f0dea419a95cb8899767aeb --- Real Ultimate output --- This is Ultimate 0.2.2-hotfix-svcomp22-839c364 [2021-12-06 20:49:33,067 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-06 20:49:33,068 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-06 20:49:33,092 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-06 20:49:33,093 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-06 20:49:33,094 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-06 20:49:33,095 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-06 20:49:33,097 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-06 20:49:33,098 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-06 20:49:33,099 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-06 20:49:33,100 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-06 20:49:33,101 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-06 20:49:33,101 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-06 20:49:33,102 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-06 20:49:33,103 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-06 20:49:33,104 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-06 20:49:33,105 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-06 20:49:33,106 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-06 20:49:33,107 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-06 20:49:33,109 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-06 20:49:33,110 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-06 20:49:33,111 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-06 20:49:33,113 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-06 20:49:33,113 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-06 20:49:33,116 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-06 20:49:33,117 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-06 20:49:33,117 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-06 20:49:33,118 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-06 20:49:33,118 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-06 20:49:33,119 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-06 20:49:33,119 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-06 20:49:33,120 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-06 20:49:33,121 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-06 20:49:33,121 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-06 20:49:33,122 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-06 20:49:33,122 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-06 20:49:33,123 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-06 20:49:33,123 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-06 20:49:33,123 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-06 20:49:33,124 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-06 20:49:33,124 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-06 20:49:33,125 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/bin/uautomizer-DrprNOufMa/config/svcomp-Reach-32bit-Automizer_Default.epf [2021-12-06 20:49:33,150 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-06 20:49:33,150 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-06 20:49:33,150 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-06 20:49:33,150 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-06 20:49:33,151 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2021-12-06 20:49:33,151 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2021-12-06 20:49:33,152 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-06 20:49:33,152 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-06 20:49:33,152 INFO L138 SettingsManager]: * Use SBE=true [2021-12-06 20:49:33,152 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-06 20:49:33,153 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-06 20:49:33,153 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-06 20:49:33,153 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-06 20:49:33,153 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-06 20:49:33,153 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2021-12-06 20:49:33,154 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2021-12-06 20:49:33,154 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2021-12-06 20:49:33,154 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-06 20:49:33,154 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-06 20:49:33,154 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-06 20:49:33,154 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2021-12-06 20:49:33,155 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-06 20:49:33,155 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-06 20:49:33,155 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2021-12-06 20:49:33,155 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2021-12-06 20:49:33,155 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-06 20:49:33,156 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2021-12-06 20:49:33,156 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2021-12-06 20:49:33,156 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-06 20:49:33,156 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2021-12-06 20:49:33,156 INFO L138 SettingsManager]: * Large block encoding in concurrent analysis=OFF [2021-12-06 20:49:33,156 INFO L138 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2021-12-06 20:49:33,157 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2021-12-06 20:49:33,157 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-06 20:49:33,157 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/bin/uautomizer-DrprNOufMa/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/bin/uautomizer-DrprNOufMa Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 146f0d3d7f309689872842ec2e107172ef6d7d230f0dea419a95cb8899767aeb [2021-12-06 20:49:33,357 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-06 20:49:33,373 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-06 20:49:33,375 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-06 20:49:33,376 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-06 20:49:33,376 INFO L275 PluginConnector]: CDTParser initialized [2021-12-06 20:49:33,378 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/bin/uautomizer-DrprNOufMa/../../sv-benchmarks/c/pthread/fib_unsafe-5.i [2021-12-06 20:49:33,418 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/bin/uautomizer-DrprNOufMa/data/b442f53f8/edb8149f23f34d67b69ad9ee7dc019ee/FLAG43bf9986d [2021-12-06 20:49:33,829 INFO L306 CDTParser]: Found 1 translation units. [2021-12-06 20:49:33,829 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/sv-benchmarks/c/pthread/fib_unsafe-5.i [2021-12-06 20:49:33,842 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/bin/uautomizer-DrprNOufMa/data/b442f53f8/edb8149f23f34d67b69ad9ee7dc019ee/FLAG43bf9986d [2021-12-06 20:49:33,852 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/bin/uautomizer-DrprNOufMa/data/b442f53f8/edb8149f23f34d67b69ad9ee7dc019ee [2021-12-06 20:49:33,854 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-06 20:49:33,855 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-06 20:49:33,856 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-06 20:49:33,856 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-06 20:49:33,858 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-06 20:49:33,859 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 08:49:33" (1/1) ... [2021-12-06 20:49:33,860 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@226f6d52 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 08:49:33, skipping insertion in model container [2021-12-06 20:49:33,860 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 08:49:33" (1/1) ... [2021-12-06 20:49:33,866 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-06 20:49:33,896 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-06 20:49:34,103 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/sv-benchmarks/c/pthread/fib_unsafe-5.i[30819,30832] [2021-12-06 20:49:34,106 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-06 20:49:34,112 INFO L203 MainTranslator]: Completed pre-run [2021-12-06 20:49:34,142 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/sv-benchmarks/c/pthread/fib_unsafe-5.i[30819,30832] [2021-12-06 20:49:34,143 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-06 20:49:34,170 INFO L208 MainTranslator]: Completed translation [2021-12-06 20:49:34,170 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 08:49:34 WrapperNode [2021-12-06 20:49:34,170 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-06 20:49:34,171 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-06 20:49:34,171 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-06 20:49:34,171 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-06 20:49:34,177 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 08:49:34" (1/1) ... [2021-12-06 20:49:34,187 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 08:49:34" (1/1) ... [2021-12-06 20:49:34,204 INFO L137 Inliner]: procedures = 164, calls = 26, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 71 [2021-12-06 20:49:34,204 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-06 20:49:34,205 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-06 20:49:34,205 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-06 20:49:34,205 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-06 20:49:34,211 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 08:49:34" (1/1) ... [2021-12-06 20:49:34,211 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 08:49:34" (1/1) ... [2021-12-06 20:49:34,214 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 08:49:34" (1/1) ... [2021-12-06 20:49:34,214 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 08:49:34" (1/1) ... [2021-12-06 20:49:34,219 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 08:49:34" (1/1) ... [2021-12-06 20:49:34,222 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 08:49:34" (1/1) ... [2021-12-06 20:49:34,223 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 08:49:34" (1/1) ... [2021-12-06 20:49:34,226 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-06 20:49:34,226 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-06 20:49:34,226 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-06 20:49:34,226 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-06 20:49:34,227 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 08:49:34" (1/1) ... [2021-12-06 20:49:34,234 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2021-12-06 20:49:34,245 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 20:49:34,255 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2021-12-06 20:49:34,257 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2021-12-06 20:49:34,293 INFO L130 BoogieDeclarations]: Found specification of procedure t1 [2021-12-06 20:49:34,293 INFO L138 BoogieDeclarations]: Found implementation of procedure t1 [2021-12-06 20:49:34,293 INFO L130 BoogieDeclarations]: Found specification of procedure t2 [2021-12-06 20:49:34,294 INFO L138 BoogieDeclarations]: Found implementation of procedure t2 [2021-12-06 20:49:34,294 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2021-12-06 20:49:34,294 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2021-12-06 20:49:34,294 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-06 20:49:34,294 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-12-06 20:49:34,294 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2021-12-06 20:49:34,294 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-06 20:49:34,294 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2021-12-06 20:49:34,295 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-06 20:49:34,295 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-06 20:49:34,296 WARN L209 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2021-12-06 20:49:34,389 INFO L236 CfgBuilder]: Building ICFG [2021-12-06 20:49:34,390 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-06 20:49:34,519 INFO L277 CfgBuilder]: Performing block encoding [2021-12-06 20:49:34,527 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-06 20:49:34,527 INFO L301 CfgBuilder]: Removed 3 assume(true) statements. [2021-12-06 20:49:34,529 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 08:49:34 BoogieIcfgContainer [2021-12-06 20:49:34,529 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-06 20:49:34,531 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2021-12-06 20:49:34,531 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2021-12-06 20:49:34,534 INFO L275 PluginConnector]: TraceAbstraction initialized [2021-12-06 20:49:34,534 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 06.12 08:49:33" (1/3) ... [2021-12-06 20:49:34,535 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@78d65743 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.12 08:49:34, skipping insertion in model container [2021-12-06 20:49:34,535 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 08:49:34" (2/3) ... [2021-12-06 20:49:34,535 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@78d65743 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.12 08:49:34, skipping insertion in model container [2021-12-06 20:49:34,535 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 08:49:34" (3/3) ... [2021-12-06 20:49:34,537 INFO L111 eAbstractionObserver]: Analyzing ICFG fib_unsafe-5.i [2021-12-06 20:49:34,541 WARN L149 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2021-12-06 20:49:34,541 INFO L204 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2021-12-06 20:49:34,542 INFO L163 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2021-12-06 20:49:34,542 INFO L513 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2021-12-06 20:49:34,567 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,567 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,568 WARN L322 ript$VariableManager]: TermVariabe t1Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,568 WARN L322 ript$VariableManager]: TermVariabe t1Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,568 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,568 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,568 WARN L322 ript$VariableManager]: TermVariabe t1Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,568 WARN L322 ript$VariableManager]: TermVariabe t1Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,569 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,569 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,569 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,569 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,570 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#t~post1| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,570 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#t~post1| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,570 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#t~post1| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,570 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#t~post1| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,570 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#t~post1| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,571 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#t~post1| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,571 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,571 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,571 WARN L322 ript$VariableManager]: TermVariabe t2Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,571 WARN L322 ript$VariableManager]: TermVariabe t2Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,572 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,572 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,572 WARN L322 ript$VariableManager]: TermVariabe t2Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,572 WARN L322 ript$VariableManager]: TermVariabe t2Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,572 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,573 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,573 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,573 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,573 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#t~post2| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,573 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#t~post2| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,574 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#t~post2| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,574 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#t~post2| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,574 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#t~post2| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,574 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#t~post2| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,577 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#t~post1| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,577 WARN L322 ript$VariableManager]: TermVariabe t1Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,578 WARN L322 ript$VariableManager]: TermVariabe t1Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,578 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,578 WARN L322 ript$VariableManager]: TermVariabe |t1Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,581 WARN L322 ript$VariableManager]: TermVariabe t2Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,581 WARN L322 ript$VariableManager]: TermVariabe t2Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,581 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,581 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#t~post2| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,581 WARN L322 ript$VariableManager]: TermVariabe |t2Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2021-12-06 20:49:34,582 INFO L148 ThreadInstanceAdder]: Constructed 0 joinOtherThreadTransitions. [2021-12-06 20:49:34,628 INFO L338 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2021-12-06 20:49:34,635 INFO L339 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mLoopAccelerationTechnique=FAST_UPR [2021-12-06 20:49:34,636 INFO L340 AbstractCegarLoop]: Starting to check reachability of 3 error locations. [2021-12-06 20:49:34,648 INFO L74 FinitePrefix]: Start finitePrefix. Operand has 96 places, 96 transitions, 202 flow [2021-12-06 20:49:34,690 INFO L129 PetriNetUnfolder]: 7/94 cut-off events. [2021-12-06 20:49:34,691 INFO L130 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2021-12-06 20:49:34,695 INFO L84 FinitePrefix]: Finished finitePrefix Result has 101 conditions, 94 events. 7/94 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 3. Compared 73 event pairs, 0 based on Foata normal form. 0/86 useless extension candidates. Maximal degree in co-relation 64. Up to 2 conditions per place. [2021-12-06 20:49:34,695 INFO L82 GeneralOperation]: Start removeDead. Operand has 96 places, 96 transitions, 202 flow [2021-12-06 20:49:34,700 INFO L88 GeneralOperation]: Finished RemoveDead, result has has 94 places, 94 transitions, 194 flow [2021-12-06 20:49:34,722 INFO L129 PetriNetUnfolder]: 7/85 cut-off events. [2021-12-06 20:49:34,722 INFO L130 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2021-12-06 20:49:34,722 INFO L246 CegarLoopForPetriNet]: Found error trace [2021-12-06 20:49:34,723 INFO L254 CegarLoopForPetriNet]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 20:49:34,723 INFO L402 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION] === [2021-12-06 20:49:34,728 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 20:49:34,728 INFO L85 PathProgramCache]: Analyzing trace with hash -1927097680, now seen corresponding path program 1 times [2021-12-06 20:49:34,735 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 20:49:34,736 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1209147582] [2021-12-06 20:49:34,736 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 20:49:34,737 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 20:49:34,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 20:49:34,918 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 20:49:34,918 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 20:49:34,919 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1209147582] [2021-12-06 20:49:34,919 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1209147582] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 20:49:34,919 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 20:49:34,920 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 20:49:34,921 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1585723720] [2021-12-06 20:49:34,921 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 20:49:34,928 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2021-12-06 20:49:34,928 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 20:49:34,947 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-12-06 20:49:34,948 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-12-06 20:49:34,950 INFO L499 CegarLoopForPetriNet]: Number of universal loopers: 89 out of 96 [2021-12-06 20:49:34,953 INFO L92 encePairwiseOnDemand]: Start differencePairwiseOnDemand. First operand has 94 places, 94 transitions, 194 flow. Second operand has 2 states, 2 states have (on average 90.5) internal successors, (181), 2 states have internal predecessors, (181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 20:49:34,953 INFO L101 encePairwiseOnDemand]: Universal subtrahend loopers provided by user. [2021-12-06 20:49:34,953 INFO L102 encePairwiseOnDemand]: Number of universal subtrahend loopers: 89 of 96 [2021-12-06 20:49:34,954 INFO L74 FinitePrefix]: Start finitePrefix. Operand will be constructed on-demand [2021-12-06 20:49:34,975 INFO L129 PetriNetUnfolder]: 3/89 cut-off events. [2021-12-06 20:49:34,976 INFO L130 PetriNetUnfolder]: For 2/2 co-relation queries the response was YES. [2021-12-06 20:49:34,976 INFO L84 FinitePrefix]: Finished finitePrefix Result has 99 conditions, 89 events. 3/89 cut-off events. For 2/2 co-relation queries the response was YES. Maximal size of possible extension queue 3. Compared 62 event pairs, 0 based on Foata normal form. 5/90 useless extension candidates. Maximal degree in co-relation 60. Up to 3 conditions per place. [2021-12-06 20:49:34,977 INFO L132 encePairwiseOnDemand]: 92/96 looper letters, 2 selfloop transitions, 0 changer transitions 0/89 dead transitions. [2021-12-06 20:49:34,977 INFO L138 encePairwiseOnDemand]: Finished differencePairwiseOnDemand. Result has 94 places, 89 transitions, 188 flow [2021-12-06 20:49:34,978 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-12-06 20:49:34,980 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2 states. [2021-12-06 20:49:34,985 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 184 transitions. [2021-12-06 20:49:34,987 INFO L544 CegarLoopForPetriNet]: DFA transition density 0.9583333333333334 [2021-12-06 20:49:34,987 INFO L72 ComplementDD]: Start complementDD. Operand 2 states and 184 transitions. [2021-12-06 20:49:34,988 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2 states and 184 transitions. [2021-12-06 20:49:34,989 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 20:49:34,990 INFO L117 ReachableStatesCopy]: Start reachableStatesCopy. Operand 2 states and 184 transitions. [2021-12-06 20:49:34,992 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends has 3 states, 2 states have (on average 92.0) internal successors, (184), 2 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 20:49:34,996 INFO L131 ReachableStatesCopy]: Finished reachableStatesCopy Result has 3 states, 3 states have (on average 96.0) internal successors, (288), 3 states have internal predecessors, (288), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 20:49:34,996 INFO L81 ComplementDD]: Finished complementDD. Result has 3 states, 3 states have (on average 96.0) internal successors, (288), 3 states have internal predecessors, (288), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 20:49:34,997 INFO L186 Difference]: Start difference. First operand has 94 places, 94 transitions, 194 flow. Second operand 2 states and 184 transitions. [2021-12-06 20:49:34,998 INFO L82 GeneralOperation]: Start removeRedundantFlow. Operand has 94 places, 89 transitions, 188 flow [2021-12-06 20:49:35,001 INFO L88 GeneralOperation]: Finished removeRedundantFlow, result has has 92 places, 89 transitions, 186 flow, removed 0 selfloop flow, removed 2 redundant places. [2021-12-06 20:49:35,003 INFO L242 Difference]: Finished difference. Result has 92 places, 89 transitions, 182 flow [2021-12-06 20:49:35,005 INFO L317 CegarLoopForPetriNet]: {PETRI_ALPHABET=96, PETRI_DIFFERENCE_MINUEND_FLOW=182, PETRI_DIFFERENCE_MINUEND_PLACES=91, PETRI_DIFFERENCE_MINUEND_TRANSITIONS=89, PETRI_DIFFERENCE_SUBTRAHEND_LETTERS_WITH_MORE_CHANGERS_THAN_LOOPERS=0, PETRI_DIFFERENCE_SUBTRAHEND_LOOPER_ONLY_LETTERS=89, PETRI_DIFFERENCE_SUBTRAHEND_STATES=2, PETRI_FLOW=182, PETRI_PLACES=92, PETRI_TRANSITIONS=89} [2021-12-06 20:49:35,008 INFO L334 CegarLoopForPetriNet]: 94 programPoint places, -2 predicate places. [2021-12-06 20:49:35,008 INFO L470 AbstractCegarLoop]: Abstraction has has 92 places, 89 transitions, 182 flow [2021-12-06 20:49:35,008 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 90.5) internal successors, (181), 2 states have internal predecessors, (181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 20:49:35,008 INFO L246 CegarLoopForPetriNet]: Found error trace [2021-12-06 20:49:35,008 INFO L254 CegarLoopForPetriNet]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 20:49:35,009 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2021-12-06 20:49:35,009 INFO L402 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION] === [2021-12-06 20:49:35,009 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 20:49:35,009 INFO L85 PathProgramCache]: Analyzing trace with hash 560415153, now seen corresponding path program 1 times [2021-12-06 20:49:35,010 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 20:49:35,010 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [650265187] [2021-12-06 20:49:35,010 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 20:49:35,010 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 20:49:35,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 20:49:35,076 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 20:49:35,076 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 20:49:35,076 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [650265187] [2021-12-06 20:49:35,076 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [650265187] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 20:49:35,076 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 20:49:35,077 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 20:49:35,077 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2082311713] [2021-12-06 20:49:35,077 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 20:49:35,078 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2021-12-06 20:49:35,078 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 20:49:35,078 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 20:49:35,078 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 20:49:35,080 INFO L499 CegarLoopForPetriNet]: Number of universal loopers: 83 out of 96 [2021-12-06 20:49:35,080 INFO L92 encePairwiseOnDemand]: Start differencePairwiseOnDemand. First operand has 92 places, 89 transitions, 182 flow. Second operand has 3 states, 3 states have (on average 84.66666666666667) internal successors, (254), 3 states have internal predecessors, (254), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 20:49:35,080 INFO L101 encePairwiseOnDemand]: Universal subtrahend loopers provided by user. [2021-12-06 20:49:35,080 INFO L102 encePairwiseOnDemand]: Number of universal subtrahend loopers: 83 of 96 [2021-12-06 20:49:35,080 INFO L74 FinitePrefix]: Start finitePrefix. Operand will be constructed on-demand [2021-12-06 20:49:35,107 INFO L129 PetriNetUnfolder]: 3/95 cut-off events. [2021-12-06 20:49:35,107 INFO L130 PetriNetUnfolder]: For 0/0 co-relation queries the response was YES. [2021-12-06 20:49:35,108 INFO L84 FinitePrefix]: Finished finitePrefix Result has 113 conditions, 95 events. 3/95 cut-off events. For 0/0 co-relation queries the response was YES. Maximal size of possible extension queue 3. Compared 60 event pairs, 0 based on Foata normal form. 0/91 useless extension candidates. Maximal degree in co-relation 110. Up to 6 conditions per place. [2021-12-06 20:49:35,109 INFO L132 encePairwiseOnDemand]: 93/96 looper letters, 9 selfloop transitions, 2 changer transitions 0/92 dead transitions. [2021-12-06 20:49:35,109 INFO L138 encePairwiseOnDemand]: Finished differencePairwiseOnDemand. Result has 94 places, 92 transitions, 210 flow [2021-12-06 20:49:35,109 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 20:49:35,109 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3 states. [2021-12-06 20:49:35,110 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 261 transitions. [2021-12-06 20:49:35,111 INFO L544 CegarLoopForPetriNet]: DFA transition density 0.90625 [2021-12-06 20:49:35,111 INFO L72 ComplementDD]: Start complementDD. Operand 3 states and 261 transitions. [2021-12-06 20:49:35,111 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3 states and 261 transitions. [2021-12-06 20:49:35,112 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 20:49:35,112 INFO L117 ReachableStatesCopy]: Start reachableStatesCopy. Operand 3 states and 261 transitions. [2021-12-06 20:49:35,114 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends has 4 states, 3 states have (on average 87.0) internal successors, (261), 3 states have internal predecessors, (261), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 20:49:35,116 INFO L131 ReachableStatesCopy]: Finished reachableStatesCopy Result has 4 states, 4 states have (on average 96.0) internal successors, (384), 4 states have internal predecessors, (384), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 20:49:35,116 INFO L81 ComplementDD]: Finished complementDD. Result has 4 states, 4 states have (on average 96.0) internal successors, (384), 4 states have internal predecessors, (384), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 20:49:35,116 INFO L186 Difference]: Start difference. First operand has 92 places, 89 transitions, 182 flow. Second operand 3 states and 261 transitions. [2021-12-06 20:49:35,116 INFO L82 GeneralOperation]: Start removeRedundantFlow. Operand has 94 places, 92 transitions, 210 flow [2021-12-06 20:49:35,117 INFO L88 GeneralOperation]: Finished removeRedundantFlow, result has has 94 places, 92 transitions, 210 flow, removed 0 selfloop flow, removed 0 redundant places. [2021-12-06 20:49:35,119 INFO L242 Difference]: Finished difference. Result has 95 places, 90 transitions, 194 flow [2021-12-06 20:49:35,119 INFO L317 CegarLoopForPetriNet]: {PETRI_ALPHABET=96, PETRI_DIFFERENCE_MINUEND_FLOW=182, PETRI_DIFFERENCE_MINUEND_PLACES=92, PETRI_DIFFERENCE_MINUEND_TRANSITIONS=89, PETRI_DIFFERENCE_SUBTRAHEND_LETTERS_WITH_MORE_CHANGERS_THAN_LOOPERS=1, PETRI_DIFFERENCE_SUBTRAHEND_LOOPER_ONLY_LETTERS=87, PETRI_DIFFERENCE_SUBTRAHEND_STATES=3, PETRI_FLOW=194, PETRI_PLACES=95, PETRI_TRANSITIONS=90} [2021-12-06 20:49:35,120 INFO L334 CegarLoopForPetriNet]: 94 programPoint places, 1 predicate places. [2021-12-06 20:49:35,120 INFO L470 AbstractCegarLoop]: Abstraction has has 95 places, 90 transitions, 194 flow [2021-12-06 20:49:35,120 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 84.66666666666667) internal successors, (254), 3 states have internal predecessors, (254), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 20:49:35,120 INFO L246 CegarLoopForPetriNet]: Found error trace [2021-12-06 20:49:35,120 INFO L254 CegarLoopForPetriNet]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 20:49:35,121 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2021-12-06 20:49:35,121 INFO L402 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION] === [2021-12-06 20:49:35,121 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 20:49:35,121 INFO L85 PathProgramCache]: Analyzing trace with hash -951035470, now seen corresponding path program 1 times [2021-12-06 20:49:35,121 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 20:49:35,121 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [192052262] [2021-12-06 20:49:35,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 20:49:35,122 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 20:49:35,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 20:49:35,191 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 20:49:35,191 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 20:49:35,191 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [192052262] [2021-12-06 20:49:35,191 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [192052262] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 20:49:35,191 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [50513516] [2021-12-06 20:49:35,191 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 20:49:35,192 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 20:49:35,192 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 20:49:35,193 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 20:49:35,194 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2021-12-06 20:49:35,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 20:49:35,258 INFO L263 TraceCheckSpWp]: Trace formula consists of 152 conjuncts, 4 conjunts are in the unsatisfiable core [2021-12-06 20:49:35,264 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 20:49:35,370 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 20:49:35,371 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 20:49:35,435 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 20:49:35,436 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [50513516] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 20:49:35,436 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 20:49:35,436 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 10 [2021-12-06 20:49:35,436 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [742637833] [2021-12-06 20:49:35,436 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 20:49:35,437 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2021-12-06 20:49:35,437 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 20:49:35,437 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2021-12-06 20:49:35,437 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2021-12-06 20:49:35,440 INFO L499 CegarLoopForPetriNet]: Number of universal loopers: 81 out of 96 [2021-12-06 20:49:35,441 INFO L92 encePairwiseOnDemand]: Start differencePairwiseOnDemand. First operand has 95 places, 90 transitions, 194 flow. Second operand has 10 states, 10 states have (on average 83.0) internal successors, (830), 10 states have internal predecessors, (830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 20:49:35,441 INFO L101 encePairwiseOnDemand]: Universal subtrahend loopers provided by user. [2021-12-06 20:49:35,441 INFO L102 encePairwiseOnDemand]: Number of universal subtrahend loopers: 81 of 96 [2021-12-06 20:49:35,441 INFO L74 FinitePrefix]: Start finitePrefix. Operand will be constructed on-demand [2021-12-06 20:49:35,505 INFO L129 PetriNetUnfolder]: 3/104 cut-off events. [2021-12-06 20:49:35,505 INFO L130 PetriNetUnfolder]: For 3/3 co-relation queries the response was YES. [2021-12-06 20:49:35,507 INFO L84 FinitePrefix]: Finished finitePrefix Result has 138 conditions, 104 events. 3/104 cut-off events. For 3/3 co-relation queries the response was YES. Maximal size of possible extension queue 3. Compared 51 event pairs, 0 based on Foata normal form. 2/103 useless extension candidates. Maximal degree in co-relation 133. Up to 6 conditions per place. [2021-12-06 20:49:35,507 INFO L132 encePairwiseOnDemand]: 90/96 looper letters, 10 selfloop transitions, 9 changer transitions 0/98 dead transitions. [2021-12-06 20:49:35,508 INFO L138 encePairwiseOnDemand]: Finished differencePairwiseOnDemand. Result has 103 places, 98 transitions, 250 flow [2021-12-06 20:49:35,508 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2021-12-06 20:49:35,508 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9 states. [2021-12-06 20:49:35,511 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 750 transitions. [2021-12-06 20:49:35,513 INFO L544 CegarLoopForPetriNet]: DFA transition density 0.8680555555555556 [2021-12-06 20:49:35,513 INFO L72 ComplementDD]: Start complementDD. Operand 9 states and 750 transitions. [2021-12-06 20:49:35,513 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9 states and 750 transitions. [2021-12-06 20:49:35,514 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 20:49:35,514 INFO L117 ReachableStatesCopy]: Start reachableStatesCopy. Operand 9 states and 750 transitions. [2021-12-06 20:49:35,517 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends has 10 states, 9 states have (on average 83.33333333333333) internal successors, (750), 9 states have internal predecessors, (750), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 20:49:35,521 INFO L131 ReachableStatesCopy]: Finished reachableStatesCopy Result has 10 states, 10 states have (on average 96.0) internal successors, (960), 10 states have internal predecessors, (960), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 20:49:35,522 INFO L81 ComplementDD]: Finished complementDD. Result has 10 states, 10 states have (on average 96.0) internal successors, (960), 10 states have internal predecessors, (960), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 20:49:35,522 INFO L186 Difference]: Start difference. First operand has 95 places, 90 transitions, 194 flow. Second operand 9 states and 750 transitions. [2021-12-06 20:49:35,523 INFO L82 GeneralOperation]: Start removeRedundantFlow. Operand has 103 places, 98 transitions, 250 flow [2021-12-06 20:49:35,524 INFO L88 GeneralOperation]: Finished removeRedundantFlow, result has has 102 places, 98 transitions, 248 flow, removed 0 selfloop flow, removed 1 redundant places. [2021-12-06 20:49:35,526 INFO L242 Difference]: Finished difference. Result has 105 places, 96 transitions, 242 flow [2021-12-06 20:49:35,527 INFO L317 CegarLoopForPetriNet]: {PETRI_ALPHABET=96, PETRI_DIFFERENCE_MINUEND_FLOW=192, PETRI_DIFFERENCE_MINUEND_PLACES=94, PETRI_DIFFERENCE_MINUEND_TRANSITIONS=90, PETRI_DIFFERENCE_SUBTRAHEND_LETTERS_WITH_MORE_CHANGERS_THAN_LOOPERS=5, PETRI_DIFFERENCE_SUBTRAHEND_LOOPER_ONLY_LETTERS=84, PETRI_DIFFERENCE_SUBTRAHEND_STATES=9, PETRI_FLOW=242, PETRI_PLACES=105, PETRI_TRANSITIONS=96} [2021-12-06 20:49:35,528 INFO L334 CegarLoopForPetriNet]: 94 programPoint places, 11 predicate places. [2021-12-06 20:49:35,528 INFO L470 AbstractCegarLoop]: Abstraction has has 105 places, 96 transitions, 242 flow [2021-12-06 20:49:35,529 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 83.0) internal successors, (830), 10 states have internal predecessors, (830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 20:49:35,529 INFO L246 CegarLoopForPetriNet]: Found error trace [2021-12-06 20:49:35,529 INFO L254 CegarLoopForPetriNet]: trace histogram [3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 20:49:35,549 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2021-12-06 20:49:35,730 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2,2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 20:49:35,731 INFO L402 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION] === [2021-12-06 20:49:35,732 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 20:49:35,733 INFO L85 PathProgramCache]: Analyzing trace with hash 1666707666, now seen corresponding path program 2 times [2021-12-06 20:49:35,733 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 20:49:35,734 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2133647603] [2021-12-06 20:49:35,734 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 20:49:35,735 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 20:49:35,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 20:49:35,931 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 20:49:35,931 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 20:49:35,931 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2133647603] [2021-12-06 20:49:35,931 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2133647603] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 20:49:35,932 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [384943234] [2021-12-06 20:49:35,932 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-12-06 20:49:35,932 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 20:49:35,932 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 20:49:35,933 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 20:49:35,934 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2021-12-06 20:49:35,984 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-12-06 20:49:35,984 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 20:49:35,985 INFO L263 TraceCheckSpWp]: Trace formula consists of 176 conjuncts, 8 conjunts are in the unsatisfiable core [2021-12-06 20:49:35,987 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 20:49:36,081 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 20:49:36,082 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 20:49:36,200 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 20:49:36,200 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [384943234] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 20:49:36,201 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 20:49:36,201 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9] total 18 [2021-12-06 20:49:36,201 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1892022036] [2021-12-06 20:49:36,201 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 20:49:36,202 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2021-12-06 20:49:36,202 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 20:49:36,202 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2021-12-06 20:49:36,203 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=90, Invalid=216, Unknown=0, NotChecked=0, Total=306 [2021-12-06 20:49:36,206 INFO L499 CegarLoopForPetriNet]: Number of universal loopers: 81 out of 96 [2021-12-06 20:49:36,208 INFO L92 encePairwiseOnDemand]: Start differencePairwiseOnDemand. First operand has 105 places, 96 transitions, 242 flow. Second operand has 18 states, 18 states have (on average 83.0) internal successors, (1494), 18 states have internal predecessors, (1494), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 20:49:36,208 INFO L101 encePairwiseOnDemand]: Universal subtrahend loopers provided by user. [2021-12-06 20:49:36,208 INFO L102 encePairwiseOnDemand]: Number of universal subtrahend loopers: 81 of 96 [2021-12-06 20:49:36,208 INFO L74 FinitePrefix]: Start finitePrefix. Operand will be constructed on-demand [2021-12-06 20:49:36,340 INFO L129 PetriNetUnfolder]: 3/132 cut-off events. [2021-12-06 20:49:36,340 INFO L130 PetriNetUnfolder]: For 30/30 co-relation queries the response was YES. [2021-12-06 20:49:36,341 INFO L84 FinitePrefix]: Finished finitePrefix Result has 231 conditions, 132 events. 3/132 cut-off events. For 30/30 co-relation queries the response was YES. Maximal size of possible extension queue 3. Compared 51 event pairs, 0 based on Foata normal form. 4/133 useless extension candidates. Maximal degree in co-relation 224. Up to 11 conditions per place. [2021-12-06 20:49:36,341 INFO L132 encePairwiseOnDemand]: 90/96 looper letters, 14 selfloop transitions, 21 changer transitions 0/114 dead transitions. [2021-12-06 20:49:36,341 INFO L138 encePairwiseOnDemand]: Finished differencePairwiseOnDemand. Result has 125 places, 114 transitions, 408 flow [2021-12-06 20:49:36,342 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2021-12-06 20:49:36,342 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2021-12-06 20:49:36,345 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 1740 transitions. [2021-12-06 20:49:36,346 INFO L544 CegarLoopForPetriNet]: DFA transition density 0.8630952380952381 [2021-12-06 20:49:36,346 INFO L72 ComplementDD]: Start complementDD. Operand 21 states and 1740 transitions. [2021-12-06 20:49:36,346 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21 states and 1740 transitions. [2021-12-06 20:49:36,347 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 20:49:36,347 INFO L117 ReachableStatesCopy]: Start reachableStatesCopy. Operand 21 states and 1740 transitions. [2021-12-06 20:49:36,351 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends has 22 states, 21 states have (on average 82.85714285714286) internal successors, (1740), 21 states have internal predecessors, (1740), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 20:49:36,355 INFO L131 ReachableStatesCopy]: Finished reachableStatesCopy Result has 22 states, 22 states have (on average 96.0) internal successors, (2112), 22 states have internal predecessors, (2112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 20:49:36,356 INFO L81 ComplementDD]: Finished complementDD. Result has 22 states, 22 states have (on average 96.0) internal successors, (2112), 22 states have internal predecessors, (2112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 20:49:36,356 INFO L186 Difference]: Start difference. First operand has 105 places, 96 transitions, 242 flow. Second operand 21 states and 1740 transitions. [2021-12-06 20:49:36,356 INFO L82 GeneralOperation]: Start removeRedundantFlow. Operand has 125 places, 114 transitions, 408 flow [2021-12-06 20:49:36,358 INFO L88 GeneralOperation]: Finished removeRedundantFlow, result has has 124 places, 114 transitions, 394 flow, removed 6 selfloop flow, removed 1 redundant places. [2021-12-06 20:49:36,360 INFO L242 Difference]: Finished difference. Result has 129 places, 109 transitions, 366 flow [2021-12-06 20:49:36,361 INFO L317 CegarLoopForPetriNet]: {PETRI_ALPHABET=96, PETRI_DIFFERENCE_MINUEND_FLOW=236, PETRI_DIFFERENCE_MINUEND_PLACES=104, PETRI_DIFFERENCE_MINUEND_TRANSITIONS=96, PETRI_DIFFERENCE_SUBTRAHEND_LETTERS_WITH_MORE_CHANGERS_THAN_LOOPERS=10, PETRI_DIFFERENCE_SUBTRAHEND_LOOPER_ONLY_LETTERS=85, PETRI_DIFFERENCE_SUBTRAHEND_STATES=21, PETRI_FLOW=366, PETRI_PLACES=129, PETRI_TRANSITIONS=109} [2021-12-06 20:49:36,361 INFO L334 CegarLoopForPetriNet]: 94 programPoint places, 35 predicate places. [2021-12-06 20:49:36,361 INFO L470 AbstractCegarLoop]: Abstraction has has 129 places, 109 transitions, 366 flow [2021-12-06 20:49:36,362 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 83.0) internal successors, (1494), 18 states have internal predecessors, (1494), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 20:49:36,362 INFO L246 CegarLoopForPetriNet]: Found error trace [2021-12-06 20:49:36,362 INFO L254 CegarLoopForPetriNet]: trace histogram [7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 20:49:36,395 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Ended with exit code 0 [2021-12-06 20:49:36,563 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3,3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 20:49:36,563 INFO L402 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION] === [2021-12-06 20:49:36,564 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 20:49:36,564 INFO L85 PathProgramCache]: Analyzing trace with hash -1283180782, now seen corresponding path program 3 times [2021-12-06 20:49:36,564 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 20:49:36,565 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1074347686] [2021-12-06 20:49:36,565 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 20:49:36,565 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 20:49:36,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 20:49:36,787 INFO L134 CoverageAnalysis]: Checked inductivity of 154 backedges. 0 proven. 154 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 20:49:36,787 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 20:49:36,787 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1074347686] [2021-12-06 20:49:36,788 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1074347686] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 20:49:36,788 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [453585683] [2021-12-06 20:49:36,788 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-12-06 20:49:36,788 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 20:49:36,788 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 20:49:36,789 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 20:49:36,790 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2021-12-06 20:49:36,847 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2021-12-06 20:49:36,847 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 20:49:36,848 INFO L263 TraceCheckSpWp]: Trace formula consists of 224 conjuncts, 16 conjunts are in the unsatisfiable core [2021-12-06 20:49:36,851 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 20:49:36,970 INFO L134 CoverageAnalysis]: Checked inductivity of 154 backedges. 0 proven. 154 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 20:49:36,970 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 20:49:37,128 INFO L134 CoverageAnalysis]: Checked inductivity of 154 backedges. 0 proven. 154 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 20:49:37,128 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [453585683] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 20:49:37,128 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 20:49:37,128 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17] total 27 [2021-12-06 20:49:37,128 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [388515488] [2021-12-06 20:49:37,128 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 20:49:37,129 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 27 states [2021-12-06 20:49:37,129 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 20:49:37,129 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2021-12-06 20:49:37,130 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=195, Invalid=507, Unknown=0, NotChecked=0, Total=702 [2021-12-06 20:49:37,131 INFO L499 CegarLoopForPetriNet]: Number of universal loopers: 81 out of 96 [2021-12-06 20:49:37,133 INFO L92 encePairwiseOnDemand]: Start differencePairwiseOnDemand. First operand has 129 places, 109 transitions, 366 flow. Second operand has 27 states, 27 states have (on average 83.07407407407408) internal successors, (2243), 27 states have internal predecessors, (2243), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 20:49:37,133 INFO L101 encePairwiseOnDemand]: Universal subtrahend loopers provided by user. [2021-12-06 20:49:37,133 INFO L102 encePairwiseOnDemand]: Number of universal subtrahend loopers: 81 of 96 [2021-12-06 20:49:37,133 INFO L74 FinitePrefix]: Start finitePrefix. Operand will be constructed on-demand [2021-12-06 20:49:37,388 INFO L129 PetriNetUnfolder]: 3/167 cut-off events. [2021-12-06 20:49:37,388 INFO L130 PetriNetUnfolder]: For 184/184 co-relation queries the response was YES. [2021-12-06 20:49:37,390 INFO L84 FinitePrefix]: Finished finitePrefix Result has 381 conditions, 167 events. 3/167 cut-off events. For 184/184 co-relation queries the response was YES. Maximal size of possible extension queue 3. Compared 51 event pairs, 0 based on Foata normal form. 5/169 useless extension candidates. Maximal degree in co-relation 369. Up to 21 conditions per place. [2021-12-06 20:49:37,391 INFO L132 encePairwiseOnDemand]: 90/96 looper letters, 19 selfloop transitions, 36 changer transitions 0/134 dead transitions. [2021-12-06 20:49:37,392 INFO L138 encePairwiseOnDemand]: Finished differencePairwiseOnDemand. Result has 164 places, 134 transitions, 668 flow [2021-12-06 20:49:37,392 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2021-12-06 20:49:37,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2021-12-06 20:49:37,399 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 2976 transitions. [2021-12-06 20:49:37,401 INFO L544 CegarLoopForPetriNet]: DFA transition density 0.8611111111111112 [2021-12-06 20:49:37,401 INFO L72 ComplementDD]: Start complementDD. Operand 36 states and 2976 transitions. [2021-12-06 20:49:37,401 INFO L73 IsDeterministic]: Start isDeterministic. Operand 36 states and 2976 transitions. [2021-12-06 20:49:37,404 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-06 20:49:37,404 INFO L117 ReachableStatesCopy]: Start reachableStatesCopy. Operand 36 states and 2976 transitions. [2021-12-06 20:49:37,412 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends has 37 states, 36 states have (on average 82.66666666666667) internal successors, (2976), 36 states have internal predecessors, (2976), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 20:49:37,422 INFO L131 ReachableStatesCopy]: Finished reachableStatesCopy Result has 37 states, 37 states have (on average 96.0) internal successors, (3552), 37 states have internal predecessors, (3552), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 20:49:37,423 INFO L81 ComplementDD]: Finished complementDD. Result has 37 states, 37 states have (on average 96.0) internal successors, (3552), 37 states have internal predecessors, (3552), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 20:49:37,424 INFO L186 Difference]: Start difference. First operand has 129 places, 109 transitions, 366 flow. Second operand 36 states and 2976 transitions. [2021-12-06 20:49:37,424 INFO L82 GeneralOperation]: Start removeRedundantFlow. Operand has 164 places, 134 transitions, 668 flow [2021-12-06 20:49:37,429 INFO L88 GeneralOperation]: Finished removeRedundantFlow, result has has 158 places, 134 transitions, 634 flow, removed 11 selfloop flow, removed 6 redundant places. [2021-12-06 20:49:37,432 INFO L242 Difference]: Finished difference. Result has 164 places, 125 transitions, 554 flow [2021-12-06 20:49:37,433 INFO L317 CegarLoopForPetriNet]: {PETRI_ALPHABET=96, PETRI_DIFFERENCE_MINUEND_FLOW=342, PETRI_DIFFERENCE_MINUEND_PLACES=123, PETRI_DIFFERENCE_MINUEND_TRANSITIONS=109, PETRI_DIFFERENCE_SUBTRAHEND_LETTERS_WITH_MORE_CHANGERS_THAN_LOOPERS=22, PETRI_DIFFERENCE_SUBTRAHEND_LOOPER_ONLY_LETTERS=86, PETRI_DIFFERENCE_SUBTRAHEND_STATES=36, PETRI_FLOW=554, PETRI_PLACES=164, PETRI_TRANSITIONS=125} [2021-12-06 20:49:37,434 INFO L334 CegarLoopForPetriNet]: 94 programPoint places, 70 predicate places. [2021-12-06 20:49:37,434 INFO L470 AbstractCegarLoop]: Abstraction has has 164 places, 125 transitions, 554 flow [2021-12-06 20:49:37,435 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 27 states, 27 states have (on average 83.07407407407408) internal successors, (2243), 27 states have internal predecessors, (2243), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 20:49:37,435 INFO L246 CegarLoopForPetriNet]: Found error trace [2021-12-06 20:49:37,435 INFO L254 CegarLoopForPetriNet]: trace histogram [12, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 20:49:37,456 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Ended with exit code 0 [2021-12-06 20:49:37,636 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 20:49:37,636 INFO L402 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION] === [2021-12-06 20:49:37,637 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 20:49:37,637 INFO L85 PathProgramCache]: Analyzing trace with hash 1938020081, now seen corresponding path program 4 times [2021-12-06 20:49:37,637 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 20:49:37,637 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [84322551] [2021-12-06 20:49:37,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 20:49:37,637 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 20:49:37,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 20:49:38,556 INFO L134 CoverageAnalysis]: Checked inductivity of 474 backedges. 0 proven. 474 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 20:49:38,557 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 20:49:38,557 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [84322551] [2021-12-06 20:49:38,557 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [84322551] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 20:49:38,557 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [118992682] [2021-12-06 20:49:38,557 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-12-06 20:49:38,557 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 20:49:38,558 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 20:49:38,558 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 20:49:38,561 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74e97ca4-0937-4bd2-8039-45df96952349/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2021-12-06 20:49:38,613 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-12-06 20:49:38,614 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 20:49:38,615 INFO L263 TraceCheckSpWp]: Trace formula consists of 267 conjuncts, 41 conjunts are in the unsatisfiable core [2021-12-06 20:49:38,620 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 20:49:40,442 INFO L134 CoverageAnalysis]: Checked inductivity of 474 backedges. 335 proven. 139 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 20:49:40,442 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 20:49:45,944 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) c_~cur~0) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 c_~cur~0) c_~prev~0 (* 2 aux_div_v_~next~0_20_56)))))) is different from false [2021-12-06 20:54:44,114 INFO L134 CoverageAnalysis]: Checked inductivity of 474 backedges. 0 proven. 416 refuted. 2 times theorem prover too weak. 0 trivial. 56 not checked. [2021-12-06 20:54:44,114 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [118992682] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 20:54:44,114 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 20:54:44,115 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 42, 42] total 121 [2021-12-06 20:54:44,115 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1618279626] [2021-12-06 20:54:44,115 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 20:54:44,116 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 121 states [2021-12-06 20:54:44,116 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 20:54:44,116 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 121 interpolants. [2021-12-06 20:54:44,121 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=932, Invalid=13277, Unknown=75, NotChecked=236, Total=14520 [2021-12-06 20:54:44,127 INFO L499 CegarLoopForPetriNet]: Number of universal loopers: 68 out of 96 [2021-12-06 20:54:44,133 INFO L92 encePairwiseOnDemand]: Start differencePairwiseOnDemand. First operand has 164 places, 125 transitions, 554 flow. Second operand has 121 states, 121 states have (on average 69.27272727272727) internal successors, (8382), 121 states have internal predecessors, (8382), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 20:54:44,133 INFO L101 encePairwiseOnDemand]: Universal subtrahend loopers provided by user. [2021-12-06 20:54:44,133 INFO L102 encePairwiseOnDemand]: Number of universal subtrahend loopers: 68 of 96 [2021-12-06 20:54:44,134 INFO L74 FinitePrefix]: Start finitePrefix. Operand will be constructed on-demand [2021-12-06 20:57:24,545 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse4 (* c_~j~0 (- 1))) (.cse8 (* c_~i~0 (- 1)))) (let ((.cse0 (div (+ .cse8 c_~cur~0 (- 3)) (- 2))) (.cse2 (+ c_~next~0 1)) (.cse5 (+ c_~cur~0 4 (* 2 c_~next~0))) (.cse16 (+ c_~next~0 c_~prev~0 2)) (.cse17 (div (+ .cse4 c_~next~0 (- 5)) (- 2))) (.cse15 (div (+ .cse8 c_~next~0 (- 5)) (- 2))) (.cse18 (+ c_~next~0 c_~cur~0 2)) (.cse14 (+ (* 2 c_~cur~0) c_~prev~0 3)) (.cse3 (div (+ .cse4 c_~cur~0 (- 3)) (- 2))) (.cse1 (+ c_~prev~0 c_~cur~0 1))) (and (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (<= .cse0 .cse1) (= c_~prev~0 0) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~prev~0_24 c_~next~0) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (<= .cse0 .cse2) (<= .cse3 .cse2) (<= (div (+ .cse4 (- 9) c_~next~0 c_~cur~0) (- 2)) .cse5) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse6 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse6 c_~prev~0 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse6 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse7 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse7 c_~prev~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse7 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51)))))) (<= (div (+ (- 9) .cse8 c_~next~0 c_~cur~0) (- 2)) .cse5) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse9 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse9 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse9 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse10 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse10 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_div_v_~cur~0_22_51 (+ .cse10 c_~prev~0 c_~cur~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 c_~next~0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 c_~next~0) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse11 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_div_v_~cur~0_22_51 (+ .cse11 c_~prev~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse11 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (= c_~cur~0 1) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse12 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse12 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse12 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse13 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse13 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse13 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (<= (div (+ .cse4 c_~prev~0 c_~cur~0 (- 7)) (- 2)) .cse14) (<= .cse15 .cse16) (<= .cse17 .cse16) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (<= .cse17 .cse18) (forall ((v_~j~0_8 Int)) (or (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse19 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse19 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_div_v_~cur~0_22_51 (+ .cse19 c_~prev~0 c_~cur~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse20 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 v_~j~0_8) (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse20 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 (* 2 aux_mod_v_~cur~0_22_51) 11 v_~j~0_8) (+ (* 3 v_~prev~0_24) .cse20 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0))))) (< 1 v_~j~0_8))) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse21 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse21 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse21 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse22 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse22 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse22 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (<= .cse15 .cse18) (<= (div (+ .cse8 c_~prev~0 c_~cur~0 (- 7)) (- 2)) .cse14) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse23 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse23 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse23 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (<= .cse3 .cse1) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56)))))))) is different from false [2021-12-06 20:57:27,347 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse4 (* c_~j~0 (- 1))) (.cse8 (* c_~i~0 (- 1)))) (let ((.cse0 (div (+ .cse8 c_~cur~0 (- 3)) (- 2))) (.cse2 (+ c_~next~0 1)) (.cse5 (+ c_~cur~0 4 (* 2 c_~next~0))) (.cse16 (+ c_~next~0 c_~prev~0 2)) (.cse17 (div (+ .cse4 c_~next~0 (- 5)) (- 2))) (.cse15 (div (+ .cse8 c_~next~0 (- 5)) (- 2))) (.cse18 (+ c_~next~0 c_~cur~0 2)) (.cse14 (+ (* 2 c_~cur~0) c_~prev~0 3)) (.cse3 (div (+ .cse4 c_~cur~0 (- 3)) (- 2))) (.cse1 (+ c_~prev~0 c_~cur~0 1))) (and (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (<= .cse0 .cse1) (= c_~prev~0 0) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~prev~0_24 c_~next~0) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (<= .cse0 .cse2) (<= .cse3 .cse2) (<= (div (+ .cse4 (- 9) c_~next~0 c_~cur~0) (- 2)) .cse5) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse6 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse6 c_~prev~0 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse6 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse7 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse7 c_~prev~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse7 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51)))))) (<= (div (+ (- 9) .cse8 c_~next~0 c_~cur~0) (- 2)) .cse5) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse9 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse9 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse9 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse10 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse10 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_div_v_~cur~0_22_51 (+ .cse10 c_~prev~0 c_~cur~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 c_~next~0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 c_~next~0) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse11 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_div_v_~cur~0_22_51 (+ .cse11 c_~prev~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse11 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (= c_~cur~0 1) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))))) (= c_~i~0 1) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse12 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse12 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse12 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse13 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse13 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse13 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (<= (div (+ .cse4 c_~prev~0 c_~cur~0 (- 7)) (- 2)) .cse14) (<= .cse15 .cse16) (<= .cse17 .cse16) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (<= .cse17 .cse18) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse19 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse19 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse19 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse20 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse20 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse20 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (<= .cse15 .cse18) (<= (div (+ .cse8 c_~prev~0 c_~cur~0 (- 7)) (- 2)) .cse14) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse21 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse21 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse21 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (<= .cse3 .cse1) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56)))))))) is different from false [2021-12-06 20:58:07,689 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse1 (+ c_~cur~0 4 (* 2 c_~next~0))) (.cse0 (* c_~j~0 (- 1))) (.cse11 (+ c_~next~0 c_~cur~0 2)) (.cse4 (* c_~i~0 (- 1))) (.cse10 (+ (* 2 c_~cur~0) c_~prev~0 3))) (and (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (= c_~prev~0 0) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~prev~0_24 c_~next~0) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (<= (div (+ .cse0 (- 9) c_~next~0 c_~cur~0) (- 2)) .cse1) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse2 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse2 c_~prev~0 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse2 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse3 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse3 c_~prev~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse3 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51)))))) (<= (div (+ (- 9) .cse4 c_~next~0 c_~cur~0) (- 2)) .cse1) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse5 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (< aux_div_v_~cur~0_22_51 (+ .cse5 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse5 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse6 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse6 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_div_v_~cur~0_22_51 (+ .cse6 c_~prev~0 c_~cur~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ c_~prev~0 c_~cur~0 1)) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~cur~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 c_~next~0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 c_~next~0) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse7 (* 2 c_~cur~0))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_div_v_~cur~0_22_51 (+ .cse7 c_~prev~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse7 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (= c_~cur~0 1) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 (+ c_~prev~0 c_~cur~0)) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse8 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse8 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse8 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse9 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse9 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse9 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (<= (div (+ .cse0 c_~prev~0 c_~cur~0 (- 7)) (- 2)) .cse10) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_22 (+ (* 2 c_~cur~0) c_~prev~0)) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (<= (div (+ .cse0 c_~next~0 (- 5)) (- 2)) .cse11) (forall ((v_~j~0_8 Int)) (or (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse12 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse12 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_div_v_~cur~0_22_51 (+ .cse12 c_~prev~0 c_~cur~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse13 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~prev~0 c_~cur~0 v_~cur~0_26)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 v_~j~0_8) (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse13 c_~prev~0 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 (* 2 aux_mod_v_~cur~0_22_51) 11 v_~j~0_8) (+ (* 3 v_~prev~0_24) .cse13 c_~prev~0 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< v_~cur~0_26 (+ (* 2 c_~cur~0) c_~prev~0)) (< aux_mod_v_~next~0_20_56 0))))) (< 1 v_~j~0_8))) (forall ((v_~prev~0_24 Int)) (or (< v_~prev~0_24 c_~cur~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((v_~cur~0_26 Int)) (or (< v_~cur~0_26 c_~next~0) (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse14 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse14 c_~cur~0 1)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse14 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse15 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~cur~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ .cse15 c_~cur~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse15 c_~cur~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))))))) (<= (div (+ .cse4 c_~next~0 (- 5)) (- 2)) .cse11) (<= (div (+ .cse4 c_~prev~0 c_~cur~0 (- 7)) (- 2)) .cse10) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse16 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse16 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< v_~cur~0_26 (+ c_~next~0 c_~cur~0)) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse16 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~cur~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))))))) is different from false [2021-12-06 20:58:09,864 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse0 (* c_~i~0 (- 1))) (.cse1 (+ c_~next~0 1)) (.cse7 (* c_~j~0 (- 1))) (.cse6 (+ c_~next~0 c_~prev~0 2))) (and (< (div (+ (- 1) .cse0 c_~prev~0) (- 2)) .cse1) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse2 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse2 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse2 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~cur~0_26 (+ c_~next~0 c_~prev~0))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse3 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_div_v_~cur~0_22_51 (+ .cse3 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~cur~0_26 (+ c_~next~0 c_~prev~0)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse3 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51)))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))))) (forall ((v_~cur~0_26 Int)) (or (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse4 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse4 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ .cse4 c_~prev~0 1)) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~prev~0 v_~cur~0_26))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse5 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse5 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ .cse5 c_~prev~0 1)) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~prev~0 v_~cur~0_26)))))) (< v_~cur~0_26 c_~next~0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~prev~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~prev~0_24 c_~next~0) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 c_~next~0) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))))) (forall ((aux_div_v_~cur~0_21_56 Int) (aux_mod_v_~cur~0_21_56 Int)) (or (<= (+ c_~prev~0 (* 5 aux_div_v_~cur~0_21_56)) (+ (* 2 c_~j~0) (* 2 aux_mod_v_~cur~0_21_56) 17)) (<= 2 aux_mod_v_~cur~0_21_56) (< (+ 7 c_~j~0 aux_mod_v_~cur~0_21_56) (+ (* 2 aux_div_v_~cur~0_21_56) c_~next~0 c_~prev~0)) (< aux_mod_v_~cur~0_21_56 0))) (forall ((aux_div_v_~cur~0_21_56 Int) (aux_mod_v_~cur~0_21_56 Int)) (or (< (+ 7 c_~i~0 aux_mod_v_~cur~0_21_56) (+ (* 2 aux_div_v_~cur~0_21_56) c_~next~0 c_~prev~0)) (<= 2 aux_mod_v_~cur~0_21_56) (<= (+ c_~prev~0 (* 5 aux_div_v_~cur~0_21_56)) (+ (* 2 aux_mod_v_~cur~0_21_56) 17 (* 2 c_~i~0))) (< aux_mod_v_~cur~0_21_56 0))) (<= (div (+ .cse0 c_~next~0 (- 5)) (- 2)) .cse6) (< (div (+ .cse7 (- 1) c_~prev~0) (- 2)) .cse1) (<= (div (+ .cse7 c_~next~0 (- 5)) (- 2)) .cse6) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~prev~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 c_~next~0) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) c_~prev~0) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) (* 3 c_~prev~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) c_~prev~0) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) (* 3 c_~prev~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< v_~cur~0_22 (+ c_~next~0 c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))))) is different from false [2021-12-06 20:59:06,589 WARN L227 SmtUtils]: Spent 17.63s on a formula simplification. DAG size of input: 93 DAG size of output: 63 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2021-12-06 20:59:09,365 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse9 (* c_~j~0 (- 1))) (.cse17 (* 2 c_~cur~0)) (.cse0 (* c_~i~0 (- 1)))) (let ((.cse2 (div (+ .cse0 c_~cur~0 (- 3)) (- 2))) (.cse10 (+ c_~cur~0 4 (* 2 c_~next~0))) (.cse1 (+ c_~next~0 1)) (.cse13 (+ c_~next~0 c_~prev~0 2)) (.cse14 (+ .cse17 c_~prev~0)) (.cse15 (div (+ .cse9 c_~next~0 (- 5)) (- 2))) (.cse12 (div (+ .cse0 c_~next~0 (- 5)) (- 2))) (.cse16 (+ c_~next~0 c_~cur~0 2)) (.cse11 (+ .cse17 c_~prev~0 3)) (.cse6 (div (+ .cse9 c_~cur~0 (- 3)) (- 2))) (.cse3 (+ c_~prev~0 c_~cur~0 1))) (and (< (div (+ (- 1) .cse0 c_~prev~0) (- 2)) .cse1) (<= .cse2 .cse3) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse4 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse4 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_div_v_~cur~0_22_51 (+ .cse4 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~cur~0_26 (+ c_~next~0 c_~prev~0))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (v_~cur~0_26 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse5 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (< v_~prev~0_24 (+ c_~next~0 v_~cur~0_26)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_div_v_~cur~0_22_51 (+ .cse5 c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< v_~cur~0_26 (+ c_~next~0 c_~prev~0)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse5 c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51)))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< v_~cur~0_22 (+ c_~next~0 c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))))) (<= .cse2 .cse1) (<= 1 c_~cur~0) (<= .cse6 .cse1) (forall ((v_~cur~0_26 Int)) (or (and (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse7 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse7 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ .cse7 c_~prev~0 1)) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~prev~0 v_~cur~0_26))))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (let ((.cse8 (* 2 v_~cur~0_26))) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) .cse8 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_div_v_~cur~0_22_51 (+ .cse8 c_~prev~0 1)) (< aux_mod_v_~next~0_20_56 0) (< v_~prev~0_24 (+ c_~prev~0 v_~cur~0_26)))))) (< v_~cur~0_26 c_~next~0))) (<= (div (+ .cse9 (- 9) c_~next~0 c_~cur~0) (- 2)) .cse10) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~prev~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< v_~prev~0_24 c_~next~0) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (forall ((v_~cur~0_22 Int)) (or (< v_~cur~0_22 c_~next~0) (and (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (aux_mod_v_~next~0_20_56 Int)) (or (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ (* 2 c_~j~0) 22 (* 2 aux_mod_v_~next~0_20_56))) (< (+ aux_mod_v_~next~0_20_56 9 c_~j~0) (+ (* 2 v_~cur~0_22) c_~prev~0 (* 2 aux_div_v_~next~0_20_56))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0)))))) (<= (div (+ (- 9) .cse0 c_~next~0 c_~cur~0) (- 2)) .cse10) (forall ((aux_div_v_~cur~0_21_56 Int) (aux_mod_v_~cur~0_21_56 Int)) (or (<= (+ c_~prev~0 (* 5 aux_div_v_~cur~0_21_56)) (+ (* 2 c_~j~0) (* 2 aux_mod_v_~cur~0_21_56) 17)) (<= 2 aux_mod_v_~cur~0_21_56) (< (+ 7 c_~j~0 aux_mod_v_~cur~0_21_56) (+ (* 2 aux_div_v_~cur~0_21_56) c_~next~0 c_~prev~0)) (< aux_mod_v_~cur~0_21_56 0))) (forall ((aux_div_v_~cur~0_21_56 Int) (aux_mod_v_~cur~0_21_56 Int)) (or (< (+ 7 c_~i~0 aux_mod_v_~cur~0_21_56) (+ (* 2 aux_div_v_~cur~0_21_56) c_~next~0 c_~prev~0)) (<= 2 aux_mod_v_~cur~0_21_56) (<= (+ c_~prev~0 (* 5 aux_div_v_~cur~0_21_56)) (+ (* 2 aux_mod_v_~cur~0_21_56) 17 (* 2 c_~i~0))) (< aux_mod_v_~cur~0_21_56 0))) (<= 0 c_~prev~0) (= c_~cur~0 1) (<= c_~i~0 1) (<= (div (+ .cse9 c_~prev~0 c_~cur~0 (- 7)) (- 2)) .cse11) (<= .cse12 .cse13) (< c_~i~0 .cse14) (< (div (+ .cse9 (- 1) c_~prev~0) (- 2)) .cse1) (<= .cse15 .cse13) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (v_~prev~0_24 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 c_~prev~0 1)) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) v_~prev~0_24) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< v_~prev~0_24 c_~next~0) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ (* 3 v_~prev~0_24) c_~next~0 c_~prev~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51))) (< aux_mod_v_~next~0_20_56 0))) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) c_~prev~0) (+ 23 aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (< (+ aux_mod_v_~next~0_20_56 c_~i~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) (* 3 c_~prev~0))) (<= 2 aux_mod_v_~next~0_20_56) (< aux_mod_v_~next~0_20_56 0))) (< c_~j~0 .cse14) (<= .cse15 .cse16) (forall ((aux_mod_v_~cur~0_22_51 Int) (aux_div_v_~next~0_20_56 Int) (aux_div_v_~cur~0_22_51 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< aux_mod_v_~cur~0_22_51 0) (<= 2 aux_mod_v_~cur~0_22_51) (< aux_div_v_~cur~0_22_51 (+ c_~next~0 1)) (<= 2 aux_mod_v_~next~0_20_56) (<= (+ (* 5 aux_div_v_~next~0_20_56) (* 2 aux_div_v_~cur~0_22_51) c_~prev~0) (+ 23 (* 2 c_~j~0) aux_mod_v_~cur~0_22_51 (* 2 aux_mod_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (< (+ aux_mod_v_~next~0_20_56 c_~j~0 (* 2 aux_mod_v_~cur~0_22_51) 11) (+ c_~next~0 (* 2 aux_div_v_~next~0_20_56) (* 4 aux_div_v_~cur~0_22_51) (* 3 c_~prev~0))))) (forall ((aux_div_v_~next~0_20_56 Int) (v_~cur~0_22 Int) (aux_mod_v_~next~0_20_56 Int)) (or (< v_~cur~0_22 (+ c_~next~0 c_~prev~0)) (<= 2 aux_mod_v_~next~0_20_56) (< (+ aux_mod_v_~next~0_20_56 9 c_~i~0) (+ (* 2 v_~cur~0_22) c_~next~0 (* 2 aux_div_v_~next~0_20_56))) (< aux_mod_v_~next~0_20_56 0) (<= (+ (* 5 aux_div_v_~next~0_20_56) v_~cur~0_22) (+ 22 (* 2 aux_mod_v_~next~0_20_56) (* 2 c_~i~0))))) (<= .cse12 .cse16) (<= (div (+ .cse0 c_~prev~0 c_~cur~0 (- 7)) (- 2)) .cse11) (<= .cse6 .cse3)))) is different from false