./Ultimate.py --spec ../../sv-benchmarks/c/properties/valid-memsafety.prp --file ../../sv-benchmarks/c/memsafety/20051113-1.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for memory safety (deref-memtrack) Using default analysis Version 839c364b Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/config/AutomizerMemDerefMemtrack.xml -i ../../sv-benchmarks/c/memsafety/20051113-1.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 2a43a02844acf962bfa6f77d0e1512c06ac1cc2fb3c3905e584a292a069b5426 --- Real Ultimate output --- This is Ultimate 0.2.2-hotfix-svcomp22-839c364 [2021-12-06 18:18:30,886 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-06 18:18:30,887 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-06 18:18:30,917 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-06 18:18:30,918 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-06 18:18:30,919 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-06 18:18:30,920 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-06 18:18:30,922 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-06 18:18:30,924 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-06 18:18:30,925 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-06 18:18:30,925 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-06 18:18:30,926 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-06 18:18:30,927 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-06 18:18:30,928 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-06 18:18:30,929 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-06 18:18:30,930 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-06 18:18:30,930 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-06 18:18:30,931 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-06 18:18:30,933 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-06 18:18:30,935 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-06 18:18:30,936 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-06 18:18:30,937 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-06 18:18:30,939 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-06 18:18:30,939 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-06 18:18:30,942 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-06 18:18:30,942 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-06 18:18:30,942 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-06 18:18:30,943 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-06 18:18:30,944 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-06 18:18:30,944 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-06 18:18:30,945 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-06 18:18:30,945 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-06 18:18:30,946 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-06 18:18:30,947 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-06 18:18:30,947 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-06 18:18:30,947 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-06 18:18:30,948 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-06 18:18:30,948 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-06 18:18:30,948 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-06 18:18:30,949 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-06 18:18:30,949 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-06 18:18:30,950 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Default.epf [2021-12-06 18:18:30,967 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-06 18:18:30,967 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-06 18:18:30,967 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-06 18:18:30,967 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-06 18:18:30,968 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2021-12-06 18:18:30,968 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2021-12-06 18:18:30,969 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-06 18:18:30,969 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-06 18:18:30,969 INFO L138 SettingsManager]: * Use SBE=true [2021-12-06 18:18:30,969 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-06 18:18:30,969 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-06 18:18:30,969 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-06 18:18:30,969 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-06 18:18:30,969 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-06 18:18:30,969 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-06 18:18:30,970 INFO L138 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2021-12-06 18:18:30,970 INFO L138 SettingsManager]: * Bitprecise bitfields=true [2021-12-06 18:18:30,970 INFO L138 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2021-12-06 18:18:30,970 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2021-12-06 18:18:30,970 INFO L138 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2021-12-06 18:18:30,970 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-06 18:18:30,970 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-06 18:18:30,970 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-06 18:18:30,970 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-06 18:18:30,971 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2021-12-06 18:18:30,971 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2021-12-06 18:18:30,971 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-06 18:18:30,971 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2021-12-06 18:18:30,971 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-06 18:18:30,971 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2021-12-06 18:18:30,971 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-06 18:18:30,971 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2a43a02844acf962bfa6f77d0e1512c06ac1cc2fb3c3905e584a292a069b5426 [2021-12-06 18:18:31,144 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-06 18:18:31,159 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-06 18:18:31,161 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-06 18:18:31,162 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-06 18:18:31,163 INFO L275 PluginConnector]: CDTParser initialized [2021-12-06 18:18:31,164 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/../../sv-benchmarks/c/memsafety/20051113-1.i [2021-12-06 18:18:31,211 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/data/1776e8957/f01af603368e4a3b9cf5cedfc7925a03/FLAGab95f160a [2021-12-06 18:18:31,628 INFO L306 CDTParser]: Found 1 translation units. [2021-12-06 18:18:31,628 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/sv-benchmarks/c/memsafety/20051113-1.i [2021-12-06 18:18:31,639 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/data/1776e8957/f01af603368e4a3b9cf5cedfc7925a03/FLAGab95f160a [2021-12-06 18:18:31,648 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/data/1776e8957/f01af603368e4a3b9cf5cedfc7925a03 [2021-12-06 18:18:31,650 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-06 18:18:31,651 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-06 18:18:31,652 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-06 18:18:31,652 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-06 18:18:31,655 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-06 18:18:31,655 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 06:18:31" (1/1) ... [2021-12-06 18:18:31,656 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@272faa59 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:18:31, skipping insertion in model container [2021-12-06 18:18:31,656 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 06:18:31" (1/1) ... [2021-12-06 18:18:31,661 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-06 18:18:31,693 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-06 18:18:31,892 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-06 18:18:31,898 INFO L203 MainTranslator]: Completed pre-run [2021-12-06 18:18:31,927 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-06 18:18:31,948 INFO L208 MainTranslator]: Completed translation [2021-12-06 18:18:31,948 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:18:31 WrapperNode [2021-12-06 18:18:31,948 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-06 18:18:31,949 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-06 18:18:31,949 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-06 18:18:31,949 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-06 18:18:31,955 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:18:31" (1/1) ... [2021-12-06 18:18:31,969 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:18:31" (1/1) ... [2021-12-06 18:18:31,991 INFO L137 Inliner]: procedures = 125, calls = 23, calls flagged for inlining = 5, calls inlined = 5, statements flattened = 77 [2021-12-06 18:18:31,991 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-06 18:18:31,992 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-06 18:18:31,992 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-06 18:18:31,992 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-06 18:18:31,998 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:18:31" (1/1) ... [2021-12-06 18:18:31,998 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:18:31" (1/1) ... [2021-12-06 18:18:32,001 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:18:31" (1/1) ... [2021-12-06 18:18:32,001 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:18:31" (1/1) ... [2021-12-06 18:18:32,006 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:18:31" (1/1) ... [2021-12-06 18:18:32,009 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:18:31" (1/1) ... [2021-12-06 18:18:32,010 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:18:31" (1/1) ... [2021-12-06 18:18:32,012 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-06 18:18:32,013 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-06 18:18:32,013 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-06 18:18:32,013 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-06 18:18:32,013 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:18:31" (1/1) ... [2021-12-06 18:18:32,019 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2021-12-06 18:18:32,026 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:18:32,036 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2021-12-06 18:18:32,038 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2021-12-06 18:18:32,064 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2021-12-06 18:18:32,064 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2021-12-06 18:18:32,065 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2021-12-06 18:18:32,065 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-06 18:18:32,065 INFO L130 BoogieDeclarations]: Found specification of procedure dummy_abort [2021-12-06 18:18:32,065 INFO L138 BoogieDeclarations]: Found implementation of procedure dummy_abort [2021-12-06 18:18:32,065 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-06 18:18:32,065 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-06 18:18:32,065 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-06 18:18:32,127 INFO L236 CfgBuilder]: Building ICFG [2021-12-06 18:18:32,128 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-06 18:18:32,298 INFO L277 CfgBuilder]: Performing block encoding [2021-12-06 18:18:32,304 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-06 18:18:32,305 INFO L301 CfgBuilder]: Removed 2 assume(true) statements. [2021-12-06 18:18:32,307 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 06:18:32 BoogieIcfgContainer [2021-12-06 18:18:32,307 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-06 18:18:32,309 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2021-12-06 18:18:32,309 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2021-12-06 18:18:32,312 INFO L275 PluginConnector]: TraceAbstraction initialized [2021-12-06 18:18:32,312 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 06.12 06:18:31" (1/3) ... [2021-12-06 18:18:32,312 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1d45db20 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.12 06:18:32, skipping insertion in model container [2021-12-06 18:18:32,313 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 06:18:31" (2/3) ... [2021-12-06 18:18:32,313 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1d45db20 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.12 06:18:32, skipping insertion in model container [2021-12-06 18:18:32,313 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 06:18:32" (3/3) ... [2021-12-06 18:18:32,316 INFO L111 eAbstractionObserver]: Analyzing ICFG 20051113-1.i [2021-12-06 18:18:32,321 INFO L204 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2021-12-06 18:18:32,321 INFO L163 ceAbstractionStarter]: Applying trace abstraction to program that has 25 error locations. [2021-12-06 18:18:32,360 INFO L338 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2021-12-06 18:18:32,365 INFO L339 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=false, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=All, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mLoopAccelerationTechnique=FAST_UPR [2021-12-06 18:18:32,365 INFO L340 AbstractCegarLoop]: Starting to check reachability of 25 error locations. [2021-12-06 18:18:32,376 INFO L276 IsEmpty]: Start isEmpty. Operand has 64 states, 35 states have (on average 1.9142857142857144) internal successors, (67), 62 states have internal predecessors, (67), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2021-12-06 18:18:32,380 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2021-12-06 18:18:32,381 INFO L506 BasicCegarLoop]: Found error trace [2021-12-06 18:18:32,381 INFO L514 BasicCegarLoop]: trace histogram [1, 1, 1] [2021-12-06 18:18:32,381 INFO L402 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATION (and 22 more)] === [2021-12-06 18:18:32,385 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:18:32,385 INFO L85 PathProgramCache]: Analyzing trace with hash 30849, now seen corresponding path program 1 times [2021-12-06 18:18:32,391 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:18:32,392 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2099916335] [2021-12-06 18:18:32,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:18:32,393 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:18:32,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:32,516 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:18:32,516 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:18:32,516 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2099916335] [2021-12-06 18:18:32,517 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2099916335] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:18:32,517 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:18:32,517 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 18:18:32,518 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [655055085] [2021-12-06 18:18:32,519 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:18:32,521 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2021-12-06 18:18:32,522 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:18:32,547 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 18:18:32,548 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 18:18:32,550 INFO L87 Difference]: Start difference. First operand has 64 states, 35 states have (on average 1.9142857142857144) internal successors, (67), 62 states have internal predecessors, (67), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand has 3 states, 2 states have (on average 1.5) internal successors, (3), 3 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:32,615 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:18:32,615 INFO L93 Difference]: Finished difference Result 63 states and 68 transitions. [2021-12-06 18:18:32,616 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 18:18:32,617 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 2 states have (on average 1.5) internal successors, (3), 3 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 3 [2021-12-06 18:18:32,618 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-12-06 18:18:32,625 INFO L225 Difference]: With dead ends: 63 [2021-12-06 18:18:32,625 INFO L226 Difference]: Without dead ends: 61 [2021-12-06 18:18:32,627 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 18:18:32,630 INFO L933 BasicCegarLoop]: 39 mSDtfsCounter, 61 mSDsluCounter, 1 mSDsCounter, 0 mSdLazyCounter, 32 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 63 SdHoareTripleChecker+Valid, 40 SdHoareTripleChecker+Invalid, 32 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 32 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2021-12-06 18:18:32,632 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [63 Valid, 40 Invalid, 32 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 32 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2021-12-06 18:18:32,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2021-12-06 18:18:32,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 61. [2021-12-06 18:18:32,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61 states, 34 states have (on average 1.8235294117647058) internal successors, (62), 59 states have internal predecessors, (62), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2021-12-06 18:18:32,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 66 transitions. [2021-12-06 18:18:32,661 INFO L78 Accepts]: Start accepts. Automaton has 61 states and 66 transitions. Word has length 3 [2021-12-06 18:18:32,661 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-12-06 18:18:32,661 INFO L470 AbstractCegarLoop]: Abstraction has 61 states and 66 transitions. [2021-12-06 18:18:32,661 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 2 states have (on average 1.5) internal successors, (3), 3 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:32,661 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 66 transitions. [2021-12-06 18:18:32,661 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2021-12-06 18:18:32,662 INFO L506 BasicCegarLoop]: Found error trace [2021-12-06 18:18:32,662 INFO L514 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2021-12-06 18:18:32,662 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2021-12-06 18:18:32,662 INFO L402 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATION (and 22 more)] === [2021-12-06 18:18:32,663 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:18:32,663 INFO L85 PathProgramCache]: Analyzing trace with hash 956356, now seen corresponding path program 1 times [2021-12-06 18:18:32,663 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:18:32,663 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1320295603] [2021-12-06 18:18:32,663 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:18:32,663 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:18:32,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:32,716 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:18:32,717 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:18:32,717 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1320295603] [2021-12-06 18:18:32,717 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1320295603] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:18:32,717 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:18:32,718 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 18:18:32,718 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [71457990] [2021-12-06 18:18:32,718 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:18:32,719 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2021-12-06 18:18:32,719 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:18:32,720 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 18:18:32,720 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 18:18:32,720 INFO L87 Difference]: Start difference. First operand 61 states and 66 transitions. Second operand has 3 states, 2 states have (on average 2.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:32,768 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:18:32,768 INFO L93 Difference]: Finished difference Result 60 states and 65 transitions. [2021-12-06 18:18:32,769 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 18:18:32,769 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 2 states have (on average 2.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 4 [2021-12-06 18:18:32,769 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-12-06 18:18:32,770 INFO L225 Difference]: With dead ends: 60 [2021-12-06 18:18:32,770 INFO L226 Difference]: Without dead ends: 60 [2021-12-06 18:18:32,770 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 18:18:32,771 INFO L933 BasicCegarLoop]: 38 mSDtfsCounter, 57 mSDsluCounter, 1 mSDsCounter, 0 mSdLazyCounter, 30 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 59 SdHoareTripleChecker+Valid, 39 SdHoareTripleChecker+Invalid, 30 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 30 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2021-12-06 18:18:32,772 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [59 Valid, 39 Invalid, 30 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 30 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2021-12-06 18:18:32,772 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states. [2021-12-06 18:18:32,776 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 60. [2021-12-06 18:18:32,776 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60 states, 34 states have (on average 1.7941176470588236) internal successors, (61), 58 states have internal predecessors, (61), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2021-12-06 18:18:32,777 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 65 transitions. [2021-12-06 18:18:32,777 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 65 transitions. Word has length 4 [2021-12-06 18:18:32,777 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-12-06 18:18:32,777 INFO L470 AbstractCegarLoop]: Abstraction has 60 states and 65 transitions. [2021-12-06 18:18:32,778 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 2 states have (on average 2.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:32,778 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 65 transitions. [2021-12-06 18:18:32,778 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2021-12-06 18:18:32,778 INFO L506 BasicCegarLoop]: Found error trace [2021-12-06 18:18:32,778 INFO L514 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:18:32,778 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2021-12-06 18:18:32,779 INFO L402 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr2REQUIRES_VIOLATION === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATION (and 22 more)] === [2021-12-06 18:18:32,779 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:18:32,779 INFO L85 PathProgramCache]: Analyzing trace with hash -1573926710, now seen corresponding path program 1 times [2021-12-06 18:18:32,779 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:18:32,779 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1739101024] [2021-12-06 18:18:32,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:18:32,780 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:18:32,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:32,832 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:18:32,832 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:18:32,833 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1739101024] [2021-12-06 18:18:32,833 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1739101024] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:18:32,833 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:18:32,833 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-06 18:18:32,833 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [605663297] [2021-12-06 18:18:32,833 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:18:32,833 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2021-12-06 18:18:32,833 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:18:32,834 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-06 18:18:32,834 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-12-06 18:18:32,834 INFO L87 Difference]: Start difference. First operand 60 states and 65 transitions. Second operand has 5 states, 4 states have (on average 1.75) internal successors, (7), 5 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:32,884 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:18:32,884 INFO L93 Difference]: Finished difference Result 53 states and 58 transitions. [2021-12-06 18:18:32,884 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 18:18:32,884 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 4 states have (on average 1.75) internal successors, (7), 5 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 7 [2021-12-06 18:18:32,884 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-12-06 18:18:32,885 INFO L225 Difference]: With dead ends: 53 [2021-12-06 18:18:32,885 INFO L226 Difference]: Without dead ends: 53 [2021-12-06 18:18:32,885 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-12-06 18:18:32,886 INFO L933 BasicCegarLoop]: 30 mSDtfsCounter, 98 mSDsluCounter, 2 mSDsCounter, 0 mSdLazyCounter, 38 mSolverCounterSat, 9 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 100 SdHoareTripleChecker+Valid, 32 SdHoareTripleChecker+Invalid, 47 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 9 IncrementalHoareTripleChecker+Valid, 38 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2021-12-06 18:18:32,887 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [100 Valid, 32 Invalid, 47 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [9 Valid, 38 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2021-12-06 18:18:32,887 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states. [2021-12-06 18:18:32,890 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 53. [2021-12-06 18:18:32,890 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 53 states, 34 states have (on average 1.588235294117647) internal successors, (54), 51 states have internal predecessors, (54), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2021-12-06 18:18:32,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 58 transitions. [2021-12-06 18:18:32,891 INFO L78 Accepts]: Start accepts. Automaton has 53 states and 58 transitions. Word has length 7 [2021-12-06 18:18:32,892 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-12-06 18:18:32,892 INFO L470 AbstractCegarLoop]: Abstraction has 53 states and 58 transitions. [2021-12-06 18:18:32,892 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 4 states have (on average 1.75) internal successors, (7), 5 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:32,892 INFO L276 IsEmpty]: Start isEmpty. Operand 53 states and 58 transitions. [2021-12-06 18:18:32,892 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2021-12-06 18:18:32,892 INFO L506 BasicCegarLoop]: Found error trace [2021-12-06 18:18:32,892 INFO L514 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:18:32,892 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2021-12-06 18:18:32,893 INFO L402 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr3REQUIRES_VIOLATION === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATION (and 22 more)] === [2021-12-06 18:18:32,893 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:18:32,893 INFO L85 PathProgramCache]: Analyzing trace with hash -1573926709, now seen corresponding path program 1 times [2021-12-06 18:18:32,893 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:18:32,893 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1661674408] [2021-12-06 18:18:32,893 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:18:32,894 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:18:32,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:32,926 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:18:32,927 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:18:32,927 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1661674408] [2021-12-06 18:18:32,927 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1661674408] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:18:32,927 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:18:32,927 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-06 18:18:32,927 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [998212092] [2021-12-06 18:18:32,927 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:18:32,928 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2021-12-06 18:18:32,928 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:18:32,928 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-06 18:18:32,928 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 18:18:32,928 INFO L87 Difference]: Start difference. First operand 53 states and 58 transitions. Second operand has 3 states, 2 states have (on average 3.5) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:32,957 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:18:32,957 INFO L93 Difference]: Finished difference Result 46 states and 51 transitions. [2021-12-06 18:18:32,957 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-06 18:18:32,958 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 2 states have (on average 3.5) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 7 [2021-12-06 18:18:32,958 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-12-06 18:18:32,958 INFO L225 Difference]: With dead ends: 46 [2021-12-06 18:18:32,958 INFO L226 Difference]: Without dead ends: 46 [2021-12-06 18:18:32,958 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-06 18:18:32,959 INFO L933 BasicCegarLoop]: 33 mSDtfsCounter, 38 mSDsluCounter, 2 mSDsCounter, 0 mSdLazyCounter, 22 mSolverCounterSat, 6 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 40 SdHoareTripleChecker+Valid, 35 SdHoareTripleChecker+Invalid, 28 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 22 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2021-12-06 18:18:32,960 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [40 Valid, 35 Invalid, 28 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 22 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2021-12-06 18:18:32,961 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states. [2021-12-06 18:18:32,963 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 46. [2021-12-06 18:18:32,963 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46 states, 34 states have (on average 1.3823529411764706) internal successors, (47), 44 states have internal predecessors, (47), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2021-12-06 18:18:32,964 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 51 transitions. [2021-12-06 18:18:32,964 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 51 transitions. Word has length 7 [2021-12-06 18:18:32,964 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-12-06 18:18:32,964 INFO L470 AbstractCegarLoop]: Abstraction has 46 states and 51 transitions. [2021-12-06 18:18:32,964 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 2 states have (on average 3.5) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:32,964 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 51 transitions. [2021-12-06 18:18:32,965 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2021-12-06 18:18:32,965 INFO L506 BasicCegarLoop]: Found error trace [2021-12-06 18:18:32,965 INFO L514 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:18:32,965 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2021-12-06 18:18:32,965 INFO L402 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr16REQUIRES_VIOLATION === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATION (and 22 more)] === [2021-12-06 18:18:32,965 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:18:32,965 INFO L85 PathProgramCache]: Analyzing trace with hash 1365553495, now seen corresponding path program 1 times [2021-12-06 18:18:32,966 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:18:32,966 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1362243924] [2021-12-06 18:18:32,966 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:18:32,966 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:18:32,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:33,024 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:18:33,024 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:18:33,024 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1362243924] [2021-12-06 18:18:33,025 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1362243924] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:18:33,025 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:18:33,025 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 18:18:33,025 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2055632689] [2021-12-06 18:18:33,025 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:18:33,025 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2021-12-06 18:18:33,025 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:18:33,026 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2021-12-06 18:18:33,026 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2021-12-06 18:18:33,026 INFO L87 Difference]: Start difference. First operand 46 states and 51 transitions. Second operand has 6 states, 5 states have (on average 3.0) internal successors, (15), 6 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:33,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:18:33,068 INFO L93 Difference]: Finished difference Result 44 states and 49 transitions. [2021-12-06 18:18:33,069 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-12-06 18:18:33,069 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 3.0) internal successors, (15), 6 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 15 [2021-12-06 18:18:33,069 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-12-06 18:18:33,069 INFO L225 Difference]: With dead ends: 44 [2021-12-06 18:18:33,069 INFO L226 Difference]: Without dead ends: 44 [2021-12-06 18:18:33,070 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2021-12-06 18:18:33,071 INFO L933 BasicCegarLoop]: 27 mSDtfsCounter, 72 mSDsluCounter, 8 mSDsCounter, 0 mSdLazyCounter, 49 mSolverCounterSat, 6 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 72 SdHoareTripleChecker+Valid, 35 SdHoareTripleChecker+Invalid, 55 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 49 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2021-12-06 18:18:33,071 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [72 Valid, 35 Invalid, 55 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 49 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2021-12-06 18:18:33,072 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states. [2021-12-06 18:18:33,074 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 44. [2021-12-06 18:18:33,074 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44 states, 34 states have (on average 1.3235294117647058) internal successors, (45), 42 states have internal predecessors, (45), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2021-12-06 18:18:33,075 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 49 transitions. [2021-12-06 18:18:33,075 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 49 transitions. Word has length 15 [2021-12-06 18:18:33,075 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-12-06 18:18:33,075 INFO L470 AbstractCegarLoop]: Abstraction has 44 states and 49 transitions. [2021-12-06 18:18:33,075 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 3.0) internal successors, (15), 6 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:33,075 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 49 transitions. [2021-12-06 18:18:33,076 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2021-12-06 18:18:33,076 INFO L506 BasicCegarLoop]: Found error trace [2021-12-06 18:18:33,076 INFO L514 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:18:33,076 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2021-12-06 18:18:33,076 INFO L402 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr17REQUIRES_VIOLATION === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATION (and 22 more)] === [2021-12-06 18:18:33,076 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:18:33,076 INFO L85 PathProgramCache]: Analyzing trace with hash 1365553496, now seen corresponding path program 1 times [2021-12-06 18:18:33,077 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:18:33,077 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1115169696] [2021-12-06 18:18:33,077 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:18:33,077 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:18:33,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:33,138 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:18:33,139 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:18:33,139 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1115169696] [2021-12-06 18:18:33,139 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1115169696] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:18:33,139 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:18:33,139 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:18:33,139 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1037115518] [2021-12-06 18:18:33,139 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:18:33,139 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2021-12-06 18:18:33,139 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:18:33,140 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 18:18:33,140 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 18:18:33,140 INFO L87 Difference]: Start difference. First operand 44 states and 49 transitions. Second operand has 4 states, 3 states have (on average 5.0) internal successors, (15), 4 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:33,172 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:18:33,172 INFO L93 Difference]: Finished difference Result 43 states and 48 transitions. [2021-12-06 18:18:33,172 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-12-06 18:18:33,172 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 3 states have (on average 5.0) internal successors, (15), 4 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 15 [2021-12-06 18:18:33,172 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-12-06 18:18:33,173 INFO L225 Difference]: With dead ends: 43 [2021-12-06 18:18:33,173 INFO L226 Difference]: Without dead ends: 43 [2021-12-06 18:18:33,173 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-12-06 18:18:33,174 INFO L933 BasicCegarLoop]: 31 mSDtfsCounter, 56 mSDsluCounter, 7 mSDsCounter, 0 mSdLazyCounter, 33 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 56 SdHoareTripleChecker+Valid, 38 SdHoareTripleChecker+Invalid, 37 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 33 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2021-12-06 18:18:33,174 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [56 Valid, 38 Invalid, 37 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 33 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2021-12-06 18:18:33,175 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states. [2021-12-06 18:18:33,177 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 43. [2021-12-06 18:18:33,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43 states, 34 states have (on average 1.2941176470588236) internal successors, (44), 41 states have internal predecessors, (44), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2021-12-06 18:18:33,178 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 48 transitions. [2021-12-06 18:18:33,178 INFO L78 Accepts]: Start accepts. Automaton has 43 states and 48 transitions. Word has length 15 [2021-12-06 18:18:33,178 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-12-06 18:18:33,178 INFO L470 AbstractCegarLoop]: Abstraction has 43 states and 48 transitions. [2021-12-06 18:18:33,178 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 3 states have (on average 5.0) internal successors, (15), 4 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:33,178 INFO L276 IsEmpty]: Start isEmpty. Operand 43 states and 48 transitions. [2021-12-06 18:18:33,179 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2021-12-06 18:18:33,179 INFO L506 BasicCegarLoop]: Found error trace [2021-12-06 18:18:33,179 INFO L514 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:18:33,179 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2021-12-06 18:18:33,179 INFO L402 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr19REQUIRES_VIOLATION === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATION (and 22 more)] === [2021-12-06 18:18:33,179 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:18:33,179 INFO L85 PathProgramCache]: Analyzing trace with hash -1963083303, now seen corresponding path program 1 times [2021-12-06 18:18:33,180 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:18:33,180 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2113266138] [2021-12-06 18:18:33,180 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:18:33,180 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:18:33,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:33,236 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:18:33,237 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:18:33,237 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2113266138] [2021-12-06 18:18:33,237 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2113266138] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:18:33,237 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:18:33,237 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:18:33,237 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1424663570] [2021-12-06 18:18:33,237 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:18:33,238 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2021-12-06 18:18:33,238 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:18:33,238 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 18:18:33,238 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 18:18:33,238 INFO L87 Difference]: Start difference. First operand 43 states and 48 transitions. Second operand has 4 states, 3 states have (on average 5.666666666666667) internal successors, (17), 4 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:33,289 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:18:33,289 INFO L93 Difference]: Finished difference Result 69 states and 79 transitions. [2021-12-06 18:18:33,290 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-12-06 18:18:33,290 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 3 states have (on average 5.666666666666667) internal successors, (17), 4 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 17 [2021-12-06 18:18:33,290 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-12-06 18:18:33,290 INFO L225 Difference]: With dead ends: 69 [2021-12-06 18:18:33,291 INFO L226 Difference]: Without dead ends: 69 [2021-12-06 18:18:33,291 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-12-06 18:18:33,292 INFO L933 BasicCegarLoop]: 30 mSDtfsCounter, 76 mSDsluCounter, 24 mSDsCounter, 0 mSdLazyCounter, 49 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 78 SdHoareTripleChecker+Valid, 54 SdHoareTripleChecker+Invalid, 54 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 49 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2021-12-06 18:18:33,292 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [78 Valid, 54 Invalid, 54 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 49 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2021-12-06 18:18:33,292 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states. [2021-12-06 18:18:33,296 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 46. [2021-12-06 18:18:33,297 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46 states, 37 states have (on average 1.2972972972972974) internal successors, (48), 44 states have internal predecessors, (48), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2021-12-06 18:18:33,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 52 transitions. [2021-12-06 18:18:33,297 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 52 transitions. Word has length 17 [2021-12-06 18:18:33,297 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-12-06 18:18:33,298 INFO L470 AbstractCegarLoop]: Abstraction has 46 states and 52 transitions. [2021-12-06 18:18:33,298 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 3 states have (on average 5.666666666666667) internal successors, (17), 4 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:33,298 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 52 transitions. [2021-12-06 18:18:33,298 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2021-12-06 18:18:33,298 INFO L506 BasicCegarLoop]: Found error trace [2021-12-06 18:18:33,298 INFO L514 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:18:33,299 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6 [2021-12-06 18:18:33,299 INFO L402 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr20REQUIRES_VIOLATION === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATION (and 22 more)] === [2021-12-06 18:18:33,299 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:18:33,299 INFO L85 PathProgramCache]: Analyzing trace with hash -58695891, now seen corresponding path program 1 times [2021-12-06 18:18:33,299 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:18:33,299 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1471990415] [2021-12-06 18:18:33,299 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:18:33,300 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:18:33,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:33,337 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:18:33,337 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:18:33,337 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1471990415] [2021-12-06 18:18:33,337 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1471990415] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:18:33,337 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:18:33,337 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-06 18:18:33,337 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1074822579] [2021-12-06 18:18:33,338 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:18:33,338 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2021-12-06 18:18:33,338 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:18:33,338 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-06 18:18:33,338 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-06 18:18:33,338 INFO L87 Difference]: Start difference. First operand 46 states and 52 transitions. Second operand has 5 states, 4 states have (on average 5.25) internal successors, (21), 5 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:33,378 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:18:33,379 INFO L93 Difference]: Finished difference Result 44 states and 50 transitions. [2021-12-06 18:18:33,379 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-06 18:18:33,379 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 4 states have (on average 5.25) internal successors, (21), 5 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 21 [2021-12-06 18:18:33,379 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-12-06 18:18:33,379 INFO L225 Difference]: With dead ends: 44 [2021-12-06 18:18:33,380 INFO L226 Difference]: Without dead ends: 44 [2021-12-06 18:18:33,380 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2021-12-06 18:18:33,381 INFO L933 BasicCegarLoop]: 27 mSDtfsCounter, 70 mSDsluCounter, 20 mSDsCounter, 0 mSdLazyCounter, 54 mSolverCounterSat, 7 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 70 SdHoareTripleChecker+Valid, 47 SdHoareTripleChecker+Invalid, 61 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 7 IncrementalHoareTripleChecker+Valid, 54 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2021-12-06 18:18:33,381 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [70 Valid, 47 Invalid, 61 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [7 Valid, 54 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2021-12-06 18:18:33,381 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states. [2021-12-06 18:18:33,383 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 44. [2021-12-06 18:18:33,384 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44 states, 37 states have (on average 1.2432432432432432) internal successors, (46), 42 states have internal predecessors, (46), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2021-12-06 18:18:33,384 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 50 transitions. [2021-12-06 18:18:33,384 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 50 transitions. Word has length 21 [2021-12-06 18:18:33,385 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-12-06 18:18:33,385 INFO L470 AbstractCegarLoop]: Abstraction has 44 states and 50 transitions. [2021-12-06 18:18:33,385 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 4 states have (on average 5.25) internal successors, (21), 5 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:33,385 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 50 transitions. [2021-12-06 18:18:33,385 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2021-12-06 18:18:33,385 INFO L506 BasicCegarLoop]: Found error trace [2021-12-06 18:18:33,386 INFO L514 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:18:33,386 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7 [2021-12-06 18:18:33,386 INFO L402 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr21REQUIRES_VIOLATION === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATION (and 22 more)] === [2021-12-06 18:18:33,386 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:18:33,386 INFO L85 PathProgramCache]: Analyzing trace with hash -58695890, now seen corresponding path program 1 times [2021-12-06 18:18:33,386 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:18:33,387 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [365986924] [2021-12-06 18:18:33,387 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:18:33,387 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:18:33,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:33,424 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:18:33,424 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:18:33,424 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [365986924] [2021-12-06 18:18:33,424 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [365986924] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:18:33,424 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:18:33,424 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 18:18:33,425 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [457194319] [2021-12-06 18:18:33,425 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:18:33,425 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2021-12-06 18:18:33,425 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:18:33,425 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-06 18:18:33,425 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-06 18:18:33,426 INFO L87 Difference]: Start difference. First operand 44 states and 50 transitions. Second operand has 5 states, 5 states have (on average 4.2) internal successors, (21), 5 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:33,445 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:18:33,445 INFO L93 Difference]: Finished difference Result 64 states and 73 transitions. [2021-12-06 18:18:33,445 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-12-06 18:18:33,446 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 4.2) internal successors, (21), 5 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 21 [2021-12-06 18:18:33,446 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-12-06 18:18:33,446 INFO L225 Difference]: With dead ends: 64 [2021-12-06 18:18:33,446 INFO L226 Difference]: Without dead ends: 64 [2021-12-06 18:18:33,446 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2021-12-06 18:18:33,447 INFO L933 BasicCegarLoop]: 44 mSDtfsCounter, 35 mSDsluCounter, 127 mSDsCounter, 0 mSdLazyCounter, 16 mSolverCounterSat, 6 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 35 SdHoareTripleChecker+Valid, 171 SdHoareTripleChecker+Invalid, 22 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 16 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2021-12-06 18:18:33,447 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [35 Valid, 171 Invalid, 22 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 16 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2021-12-06 18:18:33,448 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states. [2021-12-06 18:18:33,450 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 47. [2021-12-06 18:18:33,451 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47 states, 40 states have (on average 1.225) internal successors, (49), 45 states have internal predecessors, (49), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2021-12-06 18:18:33,451 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 53 transitions. [2021-12-06 18:18:33,451 INFO L78 Accepts]: Start accepts. Automaton has 47 states and 53 transitions. Word has length 21 [2021-12-06 18:18:33,451 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-12-06 18:18:33,451 INFO L470 AbstractCegarLoop]: Abstraction has 47 states and 53 transitions. [2021-12-06 18:18:33,452 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 4.2) internal successors, (21), 5 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:33,452 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 53 transitions. [2021-12-06 18:18:33,452 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2021-12-06 18:18:33,452 INFO L506 BasicCegarLoop]: Found error trace [2021-12-06 18:18:33,452 INFO L514 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:18:33,452 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8 [2021-12-06 18:18:33,453 INFO L402 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr19REQUIRES_VIOLATION === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATION (and 22 more)] === [2021-12-06 18:18:33,453 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:18:33,453 INFO L85 PathProgramCache]: Analyzing trace with hash -309999949, now seen corresponding path program 1 times [2021-12-06 18:18:33,453 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:18:33,453 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [209464769] [2021-12-06 18:18:33,453 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:18:33,453 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:18:33,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:33,522 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:18:33,522 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:18:33,522 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [209464769] [2021-12-06 18:18:33,522 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [209464769] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 18:18:33,522 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [90603209] [2021-12-06 18:18:33,522 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:18:33,522 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 18:18:33,523 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:18:33,523 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 18:18:33,524 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2021-12-06 18:18:33,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:33,580 INFO L263 TraceCheckSpWp]: Trace formula consists of 148 conjuncts, 18 conjunts are in the unsatisfiable core [2021-12-06 18:18:33,585 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 18:18:33,773 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:18:33,773 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 18:18:33,924 INFO L354 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2021-12-06 18:18:33,925 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 13 treesize of output 17 [2021-12-06 18:18:33,973 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:18:33,973 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [90603209] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 18:18:33,973 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 18:18:33,974 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 6] total 13 [2021-12-06 18:18:33,974 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1698368376] [2021-12-06 18:18:33,974 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 18:18:33,974 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2021-12-06 18:18:33,974 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:18:33,975 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2021-12-06 18:18:33,975 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=140, Unknown=0, NotChecked=0, Total=182 [2021-12-06 18:18:33,975 INFO L87 Difference]: Start difference. First operand 47 states and 53 transitions. Second operand has 14 states, 13 states have (on average 4.6923076923076925) internal successors, (61), 14 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:34,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:18:34,190 INFO L93 Difference]: Finished difference Result 111 states and 130 transitions. [2021-12-06 18:18:34,191 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2021-12-06 18:18:34,191 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 13 states have (on average 4.6923076923076925) internal successors, (61), 14 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 22 [2021-12-06 18:18:34,191 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-12-06 18:18:34,192 INFO L225 Difference]: With dead ends: 111 [2021-12-06 18:18:34,192 INFO L226 Difference]: Without dead ends: 111 [2021-12-06 18:18:34,193 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 33 SyntacticMatches, 1 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=86, Invalid=220, Unknown=0, NotChecked=0, Total=306 [2021-12-06 18:18:34,194 INFO L933 BasicCegarLoop]: 44 mSDtfsCounter, 422 mSDsluCounter, 104 mSDsCounter, 0 mSdLazyCounter, 182 mSolverCounterSat, 51 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 422 SdHoareTripleChecker+Valid, 148 SdHoareTripleChecker+Invalid, 233 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 51 IncrementalHoareTripleChecker+Valid, 182 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2021-12-06 18:18:34,194 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [422 Valid, 148 Invalid, 233 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [51 Valid, 182 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2021-12-06 18:18:34,195 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states. [2021-12-06 18:18:34,200 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 57. [2021-12-06 18:18:34,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57 states, 50 states have (on average 1.22) internal successors, (61), 55 states have internal predecessors, (61), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2021-12-06 18:18:34,201 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 65 transitions. [2021-12-06 18:18:34,201 INFO L78 Accepts]: Start accepts. Automaton has 57 states and 65 transitions. Word has length 22 [2021-12-06 18:18:34,201 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-12-06 18:18:34,202 INFO L470 AbstractCegarLoop]: Abstraction has 57 states and 65 transitions. [2021-12-06 18:18:34,202 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 13 states have (on average 4.6923076923076925) internal successors, (61), 14 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:34,202 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 65 transitions. [2021-12-06 18:18:34,203 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2021-12-06 18:18:34,203 INFO L506 BasicCegarLoop]: Found error trace [2021-12-06 18:18:34,203 INFO L514 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:18:34,224 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2021-12-06 18:18:34,404 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable9 [2021-12-06 18:18:34,405 INFO L402 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr21REQUIRES_VIOLATION === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATION (and 22 more)] === [2021-12-06 18:18:34,406 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:18:34,407 INFO L85 PathProgramCache]: Analyzing trace with hash -612311662, now seen corresponding path program 1 times [2021-12-06 18:18:34,407 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:18:34,407 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [890944205] [2021-12-06 18:18:34,407 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:18:34,408 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:18:34,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:34,562 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 19 [2021-12-06 18:18:34,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:34,568 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:18:34,568 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:18:34,568 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [890944205] [2021-12-06 18:18:34,568 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [890944205] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:18:34,568 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:18:34,568 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:18:34,568 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1773497813] [2021-12-06 18:18:34,569 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:18:34,569 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2021-12-06 18:18:34,569 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:18:34,570 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 18:18:34,570 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 18:18:34,570 INFO L87 Difference]: Start difference. First operand 57 states and 65 transitions. Second operand has 4 states, 3 states have (on average 7.333333333333333) internal successors, (22), 4 states have internal predecessors, (22), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2021-12-06 18:18:34,602 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:18:34,603 INFO L93 Difference]: Finished difference Result 56 states and 64 transitions. [2021-12-06 18:18:34,603 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-12-06 18:18:34,603 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 3 states have (on average 7.333333333333333) internal successors, (22), 4 states have internal predecessors, (22), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 24 [2021-12-06 18:18:34,603 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-12-06 18:18:34,604 INFO L225 Difference]: With dead ends: 56 [2021-12-06 18:18:34,604 INFO L226 Difference]: Without dead ends: 56 [2021-12-06 18:18:34,604 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-12-06 18:18:34,604 INFO L933 BasicCegarLoop]: 29 mSDtfsCounter, 32 mSDsluCounter, 15 mSDsCounter, 0 mSdLazyCounter, 37 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 32 SdHoareTripleChecker+Valid, 44 SdHoareTripleChecker+Invalid, 39 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 37 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2021-12-06 18:18:34,605 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [32 Valid, 44 Invalid, 39 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 37 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2021-12-06 18:18:34,605 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56 states. [2021-12-06 18:18:34,607 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56 to 56. [2021-12-06 18:18:34,607 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 56 states, 50 states have (on average 1.2) internal successors, (60), 54 states have internal predecessors, (60), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2021-12-06 18:18:34,608 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56 states to 56 states and 64 transitions. [2021-12-06 18:18:34,608 INFO L78 Accepts]: Start accepts. Automaton has 56 states and 64 transitions. Word has length 24 [2021-12-06 18:18:34,608 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-12-06 18:18:34,608 INFO L470 AbstractCegarLoop]: Abstraction has 56 states and 64 transitions. [2021-12-06 18:18:34,608 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 3 states have (on average 7.333333333333333) internal successors, (22), 4 states have internal predecessors, (22), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2021-12-06 18:18:34,609 INFO L276 IsEmpty]: Start isEmpty. Operand 56 states and 64 transitions. [2021-12-06 18:18:34,609 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2021-12-06 18:18:34,609 INFO L506 BasicCegarLoop]: Found error trace [2021-12-06 18:18:34,609 INFO L514 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:18:34,609 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10 [2021-12-06 18:18:34,609 INFO L402 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr23REQUIRES_VIOLATION === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATION (and 22 more)] === [2021-12-06 18:18:34,610 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:18:34,610 INFO L85 PathProgramCache]: Analyzing trace with hash -20987021, now seen corresponding path program 1 times [2021-12-06 18:18:34,610 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:18:34,610 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [181026096] [2021-12-06 18:18:34,610 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:18:34,610 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:18:34,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:34,650 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 19 [2021-12-06 18:18:34,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:34,653 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:18:34,654 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:18:34,654 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [181026096] [2021-12-06 18:18:34,654 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [181026096] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:18:34,654 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:18:34,654 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-06 18:18:34,654 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [20227811] [2021-12-06 18:18:34,654 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:18:34,655 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2021-12-06 18:18:34,655 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:18:34,655 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 18:18:34,655 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-06 18:18:34,655 INFO L87 Difference]: Start difference. First operand 56 states and 64 transitions. Second operand has 4 states, 3 states have (on average 8.0) internal successors, (24), 4 states have internal predecessors, (24), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2021-12-06 18:18:34,696 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:18:34,697 INFO L93 Difference]: Finished difference Result 68 states and 78 transitions. [2021-12-06 18:18:34,697 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-12-06 18:18:34,697 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 3 states have (on average 8.0) internal successors, (24), 4 states have internal predecessors, (24), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 26 [2021-12-06 18:18:34,697 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-12-06 18:18:34,698 INFO L225 Difference]: With dead ends: 68 [2021-12-06 18:18:34,698 INFO L226 Difference]: Without dead ends: 68 [2021-12-06 18:18:34,698 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-12-06 18:18:34,699 INFO L933 BasicCegarLoop]: 27 mSDtfsCounter, 37 mSDsluCounter, 22 mSDsCounter, 0 mSdLazyCounter, 47 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 38 SdHoareTripleChecker+Valid, 49 SdHoareTripleChecker+Invalid, 50 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 47 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2021-12-06 18:18:34,699 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [38 Valid, 49 Invalid, 50 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 47 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2021-12-06 18:18:34,700 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68 states. [2021-12-06 18:18:34,702 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68 to 59. [2021-12-06 18:18:34,703 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59 states, 53 states have (on average 1.2075471698113207) internal successors, (64), 57 states have internal predecessors, (64), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2021-12-06 18:18:34,703 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 68 transitions. [2021-12-06 18:18:34,704 INFO L78 Accepts]: Start accepts. Automaton has 59 states and 68 transitions. Word has length 26 [2021-12-06 18:18:34,704 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-12-06 18:18:34,704 INFO L470 AbstractCegarLoop]: Abstraction has 59 states and 68 transitions. [2021-12-06 18:18:34,704 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 3 states have (on average 8.0) internal successors, (24), 4 states have internal predecessors, (24), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2021-12-06 18:18:34,704 INFO L276 IsEmpty]: Start isEmpty. Operand 59 states and 68 transitions. [2021-12-06 18:18:34,705 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2021-12-06 18:18:34,705 INFO L506 BasicCegarLoop]: Found error trace [2021-12-06 18:18:34,705 INFO L514 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:18:34,705 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable11 [2021-12-06 18:18:34,705 INFO L402 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr24ASSERT_VIOLATIONMEMORY_LEAK === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATION (and 22 more)] === [2021-12-06 18:18:34,706 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:18:34,706 INFO L85 PathProgramCache]: Analyzing trace with hash 1184799620, now seen corresponding path program 1 times [2021-12-06 18:18:34,706 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:18:34,706 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2119513320] [2021-12-06 18:18:34,706 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:18:34,706 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:18:34,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:34,742 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 19 [2021-12-06 18:18:34,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:34,745 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:18:34,745 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:18:34,745 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2119513320] [2021-12-06 18:18:34,745 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2119513320] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:18:34,745 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:18:34,745 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 18:18:34,745 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2095559734] [2021-12-06 18:18:34,745 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:18:34,746 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2021-12-06 18:18:34,746 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:18:34,746 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-06 18:18:34,746 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-06 18:18:34,747 INFO L87 Difference]: Start difference. First operand 59 states and 68 transitions. Second operand has 5 states, 5 states have (on average 5.6) internal successors, (28), 5 states have internal predecessors, (28), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2021-12-06 18:18:34,765 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:18:34,765 INFO L93 Difference]: Finished difference Result 67 states and 76 transitions. [2021-12-06 18:18:34,766 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-12-06 18:18:34,766 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 5.6) internal successors, (28), 5 states have internal predecessors, (28), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 30 [2021-12-06 18:18:34,766 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-12-06 18:18:34,767 INFO L225 Difference]: With dead ends: 67 [2021-12-06 18:18:34,767 INFO L226 Difference]: Without dead ends: 67 [2021-12-06 18:18:34,767 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2021-12-06 18:18:34,768 INFO L933 BasicCegarLoop]: 44 mSDtfsCounter, 9 mSDsluCounter, 125 mSDsCounter, 0 mSdLazyCounter, 16 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 9 SdHoareTripleChecker+Valid, 169 SdHoareTripleChecker+Invalid, 20 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 16 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2021-12-06 18:18:34,768 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [9 Valid, 169 Invalid, 20 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 16 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2021-12-06 18:18:34,769 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states. [2021-12-06 18:18:34,771 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 62. [2021-12-06 18:18:34,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62 states, 56 states have (on average 1.1964285714285714) internal successors, (67), 60 states have internal predecessors, (67), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2021-12-06 18:18:34,772 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62 states to 62 states and 71 transitions. [2021-12-06 18:18:34,773 INFO L78 Accepts]: Start accepts. Automaton has 62 states and 71 transitions. Word has length 30 [2021-12-06 18:18:34,773 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-12-06 18:18:34,773 INFO L470 AbstractCegarLoop]: Abstraction has 62 states and 71 transitions. [2021-12-06 18:18:34,773 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 5.6) internal successors, (28), 5 states have internal predecessors, (28), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2021-12-06 18:18:34,773 INFO L276 IsEmpty]: Start isEmpty. Operand 62 states and 71 transitions. [2021-12-06 18:18:34,774 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2021-12-06 18:18:34,775 INFO L506 BasicCegarLoop]: Found error trace [2021-12-06 18:18:34,775 INFO L514 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:18:34,775 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable12 [2021-12-06 18:18:34,775 INFO L402 AbstractCegarLoop]: === Iteration 14 === Targeting ULTIMATE.startErr23REQUIRES_VIOLATION === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATION (and 22 more)] === [2021-12-06 18:18:34,775 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:18:34,775 INFO L85 PathProgramCache]: Analyzing trace with hash -416344648, now seen corresponding path program 1 times [2021-12-06 18:18:34,776 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:18:34,776 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1244972591] [2021-12-06 18:18:34,776 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:18:34,776 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:18:34,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:34,849 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 19 [2021-12-06 18:18:34,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:34,853 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-12-06 18:18:34,853 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:18:34,853 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1244972591] [2021-12-06 18:18:34,853 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1244972591] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:18:34,854 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:18:34,854 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2021-12-06 18:18:34,854 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1051227917] [2021-12-06 18:18:34,854 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:18:34,854 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2021-12-06 18:18:34,855 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:18:34,855 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2021-12-06 18:18:34,855 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2021-12-06 18:18:34,855 INFO L87 Difference]: Start difference. First operand 62 states and 71 transitions. Second operand has 7 states, 7 states have (on average 4.142857142857143) internal successors, (29), 7 states have internal predecessors, (29), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2021-12-06 18:18:34,947 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:18:34,947 INFO L93 Difference]: Finished difference Result 73 states and 83 transitions. [2021-12-06 18:18:34,947 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2021-12-06 18:18:34,948 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 4.142857142857143) internal successors, (29), 7 states have internal predecessors, (29), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 31 [2021-12-06 18:18:34,948 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-12-06 18:18:34,948 INFO L225 Difference]: With dead ends: 73 [2021-12-06 18:18:34,949 INFO L226 Difference]: Without dead ends: 73 [2021-12-06 18:18:34,949 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2021-12-06 18:18:34,950 INFO L933 BasicCegarLoop]: 41 mSDtfsCounter, 22 mSDsluCounter, 134 mSDsCounter, 0 mSdLazyCounter, 111 mSolverCounterSat, 9 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 22 SdHoareTripleChecker+Valid, 175 SdHoareTripleChecker+Invalid, 120 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 9 IncrementalHoareTripleChecker+Valid, 111 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2021-12-06 18:18:34,950 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [22 Valid, 175 Invalid, 120 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [9 Valid, 111 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2021-12-06 18:18:34,951 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states. [2021-12-06 18:18:34,953 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 66. [2021-12-06 18:18:34,954 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66 states, 59 states have (on average 1.1864406779661016) internal successors, (70), 63 states have internal predecessors, (70), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2021-12-06 18:18:34,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 76 transitions. [2021-12-06 18:18:34,954 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 76 transitions. Word has length 31 [2021-12-06 18:18:34,955 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-12-06 18:18:34,955 INFO L470 AbstractCegarLoop]: Abstraction has 66 states and 76 transitions. [2021-12-06 18:18:34,955 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 4.142857142857143) internal successors, (29), 7 states have internal predecessors, (29), 1 states have call successors, (1), 1 states have call predecessors, (1), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2021-12-06 18:18:34,955 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 76 transitions. [2021-12-06 18:18:34,956 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2021-12-06 18:18:34,956 INFO L506 BasicCegarLoop]: Found error trace [2021-12-06 18:18:34,956 INFO L514 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:18:34,956 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable13 [2021-12-06 18:18:34,957 INFO L402 AbstractCegarLoop]: === Iteration 15 === Targeting ULTIMATE.startErr24ASSERT_VIOLATIONMEMORY_LEAK === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATION (and 22 more)] === [2021-12-06 18:18:34,957 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:18:34,957 INFO L85 PathProgramCache]: Analyzing trace with hash 241915192, now seen corresponding path program 1 times [2021-12-06 18:18:34,957 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:18:34,957 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1881879172] [2021-12-06 18:18:34,957 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:18:34,958 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:18:34,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:35,022 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 19 [2021-12-06 18:18:35,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:35,025 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 28 [2021-12-06 18:18:35,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:35,027 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2021-12-06 18:18:35,027 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:18:35,027 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1881879172] [2021-12-06 18:18:35,027 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1881879172] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:18:35,027 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-06 18:18:35,027 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-06 18:18:35,027 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1016991250] [2021-12-06 18:18:35,028 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:18:35,028 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2021-12-06 18:18:35,028 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:18:35,028 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-06 18:18:35,028 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-06 18:18:35,028 INFO L87 Difference]: Start difference. First operand 66 states and 76 transitions. Second operand has 5 states, 5 states have (on average 5.6) internal successors, (28), 5 states have internal predecessors, (28), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2021-12-06 18:18:35,073 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:18:35,073 INFO L93 Difference]: Finished difference Result 65 states and 73 transitions. [2021-12-06 18:18:35,073 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-12-06 18:18:35,073 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 5.6) internal successors, (28), 5 states have internal predecessors, (28), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Word has length 33 [2021-12-06 18:18:35,074 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-12-06 18:18:35,074 INFO L225 Difference]: With dead ends: 65 [2021-12-06 18:18:35,074 INFO L226 Difference]: Without dead ends: 58 [2021-12-06 18:18:35,074 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 12 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2021-12-06 18:18:35,075 INFO L933 BasicCegarLoop]: 31 mSDtfsCounter, 24 mSDsluCounter, 57 mSDsCounter, 0 mSdLazyCounter, 58 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 25 SdHoareTripleChecker+Valid, 88 SdHoareTripleChecker+Invalid, 61 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 58 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2021-12-06 18:18:35,075 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [25 Valid, 88 Invalid, 61 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 58 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2021-12-06 18:18:35,075 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states. [2021-12-06 18:18:35,078 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 56. [2021-12-06 18:18:35,078 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 56 states, 50 states have (on average 1.18) internal successors, (59), 54 states have internal predecessors, (59), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2021-12-06 18:18:35,079 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56 states to 56 states and 63 transitions. [2021-12-06 18:18:35,079 INFO L78 Accepts]: Start accepts. Automaton has 56 states and 63 transitions. Word has length 33 [2021-12-06 18:18:35,079 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-12-06 18:18:35,079 INFO L470 AbstractCegarLoop]: Abstraction has 56 states and 63 transitions. [2021-12-06 18:18:35,079 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 5.6) internal successors, (28), 5 states have internal predecessors, (28), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2021-12-06 18:18:35,080 INFO L276 IsEmpty]: Start isEmpty. Operand 56 states and 63 transitions. [2021-12-06 18:18:35,080 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2021-12-06 18:18:35,080 INFO L506 BasicCegarLoop]: Found error trace [2021-12-06 18:18:35,081 INFO L514 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:18:35,081 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable14 [2021-12-06 18:18:35,081 INFO L402 AbstractCegarLoop]: === Iteration 16 === Targeting ULTIMATE.startErr19REQUIRES_VIOLATION === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATION (and 22 more)] === [2021-12-06 18:18:35,081 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:18:35,081 INFO L85 PathProgramCache]: Analyzing trace with hash 701429363, now seen corresponding path program 2 times [2021-12-06 18:18:35,081 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:18:35,082 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [892595325] [2021-12-06 18:18:35,082 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:18:35,082 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:18:35,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:35,174 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 10 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-06 18:18:35,174 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:18:35,174 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [892595325] [2021-12-06 18:18:35,174 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [892595325] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 18:18:35,174 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1323059347] [2021-12-06 18:18:35,175 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-12-06 18:18:35,175 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 18:18:35,175 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:18:35,176 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 18:18:35,176 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2021-12-06 18:18:35,223 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2021-12-06 18:18:35,223 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 18:18:35,224 INFO L263 TraceCheckSpWp]: Trace formula consists of 131 conjuncts, 5 conjunts are in the unsatisfiable core [2021-12-06 18:18:35,225 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 18:18:35,265 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2021-12-06 18:18:35,265 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2021-12-06 18:18:35,265 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1323059347] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-06 18:18:35,265 INFO L186 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2021-12-06 18:18:35,266 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [9] total 11 [2021-12-06 18:18:35,266 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [817812225] [2021-12-06 18:18:35,266 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-06 18:18:35,266 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2021-12-06 18:18:35,266 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:18:35,267 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-06 18:18:35,267 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=86, Unknown=0, NotChecked=0, Total=110 [2021-12-06 18:18:35,267 INFO L87 Difference]: Start difference. First operand 56 states and 63 transitions. Second operand has 4 states, 4 states have (on average 5.0) internal successors, (20), 4 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:35,275 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:18:35,275 INFO L93 Difference]: Finished difference Result 57 states and 64 transitions. [2021-12-06 18:18:35,275 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-06 18:18:35,275 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 5.0) internal successors, (20), 4 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 32 [2021-12-06 18:18:35,276 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-12-06 18:18:35,276 INFO L225 Difference]: With dead ends: 57 [2021-12-06 18:18:35,276 INFO L226 Difference]: Without dead ends: 57 [2021-12-06 18:18:35,276 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 37 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=86, Unknown=0, NotChecked=0, Total=110 [2021-12-06 18:18:35,277 INFO L933 BasicCegarLoop]: 42 mSDtfsCounter, 37 mSDsluCounter, 39 mSDsCounter, 0 mSdLazyCounter, 8 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 39 SdHoareTripleChecker+Valid, 81 SdHoareTripleChecker+Invalid, 9 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 8 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2021-12-06 18:18:35,277 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [39 Valid, 81 Invalid, 9 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 8 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2021-12-06 18:18:35,278 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states. [2021-12-06 18:18:35,280 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 57. [2021-12-06 18:18:35,280 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57 states, 51 states have (on average 1.1764705882352942) internal successors, (60), 55 states have internal predecessors, (60), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2021-12-06 18:18:35,280 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 64 transitions. [2021-12-06 18:18:35,281 INFO L78 Accepts]: Start accepts. Automaton has 57 states and 64 transitions. Word has length 32 [2021-12-06 18:18:35,281 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-12-06 18:18:35,281 INFO L470 AbstractCegarLoop]: Abstraction has 57 states and 64 transitions. [2021-12-06 18:18:35,281 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 5.0) internal successors, (20), 4 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:35,281 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 64 transitions. [2021-12-06 18:18:35,282 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2021-12-06 18:18:35,282 INFO L506 BasicCegarLoop]: Found error trace [2021-12-06 18:18:35,282 INFO L514 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:18:35,305 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Ended with exit code 0 [2021-12-06 18:18:35,483 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable15 [2021-12-06 18:18:35,484 INFO L402 AbstractCegarLoop]: === Iteration 17 === Targeting ULTIMATE.startErr19REQUIRES_VIOLATION === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATION (and 22 more)] === [2021-12-06 18:18:35,485 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:18:35,485 INFO L85 PathProgramCache]: Analyzing trace with hash 1203352596, now seen corresponding path program 1 times [2021-12-06 18:18:35,486 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:18:35,486 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1623019854] [2021-12-06 18:18:35,486 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:18:35,487 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:18:35,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:35,685 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 10 proven. 14 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-12-06 18:18:35,685 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:18:35,685 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1623019854] [2021-12-06 18:18:35,685 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1623019854] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 18:18:35,685 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [921924788] [2021-12-06 18:18:35,685 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:18:35,685 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 18:18:35,685 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:18:35,686 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 18:18:35,687 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2021-12-06 18:18:35,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:35,731 INFO L263 TraceCheckSpWp]: Trace formula consists of 189 conjuncts, 33 conjunts are in the unsatisfiable core [2021-12-06 18:18:35,734 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 18:18:35,757 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2021-12-06 18:18:35,772 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 18:18:35,773 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2021-12-06 18:18:35,781 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 18:18:35,782 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2021-12-06 18:18:35,791 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 18:18:35,792 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2021-12-06 18:18:35,800 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 18:18:35,801 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2021-12-06 18:18:35,813 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 18:18:35,813 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2021-12-06 18:18:35,825 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 18:18:35,826 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2021-12-06 18:18:35,950 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-12-06 18:18:35,963 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 21 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-12-06 18:18:35,963 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 18:18:36,036 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 21 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-12-06 18:18:36,036 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [921924788] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 18:18:36,036 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 18:18:36,036 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 8] total 17 [2021-12-06 18:18:36,037 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [451321359] [2021-12-06 18:18:36,037 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 18:18:36,037 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 17 states [2021-12-06 18:18:36,037 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:18:36,037 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2021-12-06 18:18:36,038 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=59, Invalid=213, Unknown=0, NotChecked=0, Total=272 [2021-12-06 18:18:36,038 INFO L87 Difference]: Start difference. First operand 57 states and 64 transitions. Second operand has 17 states, 17 states have (on average 4.117647058823529) internal successors, (70), 17 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:36,259 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:18:36,260 INFO L93 Difference]: Finished difference Result 97 states and 111 transitions. [2021-12-06 18:18:36,260 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2021-12-06 18:18:36,260 INFO L78 Accepts]: Start accepts. Automaton has has 17 states, 17 states have (on average 4.117647058823529) internal successors, (70), 17 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 33 [2021-12-06 18:18:36,260 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-12-06 18:18:36,261 INFO L225 Difference]: With dead ends: 97 [2021-12-06 18:18:36,261 INFO L226 Difference]: Without dead ends: 97 [2021-12-06 18:18:36,261 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 58 SyntacticMatches, 6 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 118 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=170, Invalid=480, Unknown=0, NotChecked=0, Total=650 [2021-12-06 18:18:36,262 INFO L933 BasicCegarLoop]: 68 mSDtfsCounter, 123 mSDsluCounter, 333 mSDsCounter, 0 mSdLazyCounter, 300 mSolverCounterSat, 35 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 123 SdHoareTripleChecker+Valid, 401 SdHoareTripleChecker+Invalid, 335 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 35 IncrementalHoareTripleChecker+Valid, 300 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2021-12-06 18:18:36,262 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [123 Valid, 401 Invalid, 335 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [35 Valid, 300 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2021-12-06 18:18:36,263 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states. [2021-12-06 18:18:36,264 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 55. [2021-12-06 18:18:36,264 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55 states, 50 states have (on average 1.14) internal successors, (57), 53 states have internal predecessors, (57), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2021-12-06 18:18:36,264 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 61 transitions. [2021-12-06 18:18:36,265 INFO L78 Accepts]: Start accepts. Automaton has 55 states and 61 transitions. Word has length 33 [2021-12-06 18:18:36,265 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-12-06 18:18:36,265 INFO L470 AbstractCegarLoop]: Abstraction has 55 states and 61 transitions. [2021-12-06 18:18:36,265 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 17 states, 17 states have (on average 4.117647058823529) internal successors, (70), 17 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:36,265 INFO L276 IsEmpty]: Start isEmpty. Operand 55 states and 61 transitions. [2021-12-06 18:18:36,265 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2021-12-06 18:18:36,265 INFO L506 BasicCegarLoop]: Found error trace [2021-12-06 18:18:36,266 INFO L514 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:18:36,288 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Ended with exit code 0 [2021-12-06 18:18:36,466 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable16 [2021-12-06 18:18:36,468 INFO L402 AbstractCegarLoop]: === Iteration 18 === Targeting ULTIMATE.startErr23REQUIRES_VIOLATION === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATION (and 22 more)] === [2021-12-06 18:18:36,468 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:18:36,469 INFO L85 PathProgramCache]: Analyzing trace with hash -149943807, now seen corresponding path program 1 times [2021-12-06 18:18:36,469 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:18:36,470 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1739528010] [2021-12-06 18:18:36,470 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:18:36,470 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:18:36,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:36,673 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2021-12-06 18:18:36,673 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:18:36,673 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1739528010] [2021-12-06 18:18:36,673 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1739528010] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 18:18:36,674 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1648265048] [2021-12-06 18:18:36,674 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:18:36,674 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 18:18:36,674 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:18:36,674 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 18:18:36,675 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2021-12-06 18:18:36,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:36,724 INFO L263 TraceCheckSpWp]: Trace formula consists of 197 conjuncts, 18 conjunts are in the unsatisfiable core [2021-12-06 18:18:36,726 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 18:18:36,880 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2021-12-06 18:18:36,881 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 18:18:37,019 INFO L354 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2021-12-06 18:18:37,020 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 13 treesize of output 17 [2021-12-06 18:18:37,052 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2021-12-06 18:18:37,052 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1648265048] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 18:18:37,052 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 18:18:37,052 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 6, 6] total 18 [2021-12-06 18:18:37,052 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [5045455] [2021-12-06 18:18:37,053 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 18:18:37,053 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2021-12-06 18:18:37,053 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:18:37,053 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2021-12-06 18:18:37,053 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=255, Unknown=0, NotChecked=0, Total=306 [2021-12-06 18:18:37,053 INFO L87 Difference]: Start difference. First operand 55 states and 61 transitions. Second operand has 18 states, 18 states have (on average 5.333333333333333) internal successors, (96), 18 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:37,277 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:18:37,277 INFO L93 Difference]: Finished difference Result 79 states and 88 transitions. [2021-12-06 18:18:37,277 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2021-12-06 18:18:37,278 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 5.333333333333333) internal successors, (96), 18 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 34 [2021-12-06 18:18:37,278 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-12-06 18:18:37,278 INFO L225 Difference]: With dead ends: 79 [2021-12-06 18:18:37,279 INFO L226 Difference]: Without dead ends: 79 [2021-12-06 18:18:37,279 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 91 GetRequests, 65 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 95 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=168, Invalid=588, Unknown=0, NotChecked=0, Total=756 [2021-12-06 18:18:37,280 INFO L933 BasicCegarLoop]: 23 mSDtfsCounter, 185 mSDsluCounter, 103 mSDsCounter, 0 mSdLazyCounter, 217 mSolverCounterSat, 47 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 185 SdHoareTripleChecker+Valid, 126 SdHoareTripleChecker+Invalid, 264 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 47 IncrementalHoareTripleChecker+Valid, 217 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2021-12-06 18:18:37,280 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [185 Valid, 126 Invalid, 264 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [47 Valid, 217 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2021-12-06 18:18:37,281 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79 states. [2021-12-06 18:18:37,283 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79 to 65. [2021-12-06 18:18:37,283 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65 states, 60 states have (on average 1.1333333333333333) internal successors, (68), 63 states have internal predecessors, (68), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2021-12-06 18:18:37,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 72 transitions. [2021-12-06 18:18:37,284 INFO L78 Accepts]: Start accepts. Automaton has 65 states and 72 transitions. Word has length 34 [2021-12-06 18:18:37,284 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-12-06 18:18:37,284 INFO L470 AbstractCegarLoop]: Abstraction has 65 states and 72 transitions. [2021-12-06 18:18:37,284 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 5.333333333333333) internal successors, (96), 18 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:37,284 INFO L276 IsEmpty]: Start isEmpty. Operand 65 states and 72 transitions. [2021-12-06 18:18:37,285 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2021-12-06 18:18:37,285 INFO L506 BasicCegarLoop]: Found error trace [2021-12-06 18:18:37,285 INFO L514 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:18:37,306 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Ended with exit code 0 [2021-12-06 18:18:37,486 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable17 [2021-12-06 18:18:37,486 INFO L402 AbstractCegarLoop]: === Iteration 19 === Targeting ULTIMATE.startErr24ASSERT_VIOLATIONMEMORY_LEAK === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATION (and 22 more)] === [2021-12-06 18:18:37,486 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:18:37,486 INFO L85 PathProgramCache]: Analyzing trace with hash 1336889422, now seen corresponding path program 1 times [2021-12-06 18:18:37,487 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:18:37,487 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [445146012] [2021-12-06 18:18:37,487 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:18:37,487 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:18:37,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:37,563 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2021-12-06 18:18:37,563 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:18:37,564 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [445146012] [2021-12-06 18:18:37,564 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [445146012] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 18:18:37,564 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [598535769] [2021-12-06 18:18:37,564 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:18:37,564 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 18:18:37,564 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:18:37,565 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 18:18:37,565 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2021-12-06 18:18:37,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:37,627 INFO L263 TraceCheckSpWp]: Trace formula consists of 228 conjuncts, 29 conjunts are in the unsatisfiable core [2021-12-06 18:18:37,629 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 18:18:37,651 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2021-12-06 18:18:37,794 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-12-06 18:18:37,808 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 10 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-12-06 18:18:37,808 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 18:18:37,930 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-12-06 18:18:37,930 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [598535769] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 18:18:37,930 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 18:18:37,930 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 10, 9] total 24 [2021-12-06 18:18:37,930 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [119063808] [2021-12-06 18:18:37,930 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 18:18:37,931 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 24 states [2021-12-06 18:18:37,931 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:18:37,931 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2021-12-06 18:18:37,931 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=83, Invalid=469, Unknown=0, NotChecked=0, Total=552 [2021-12-06 18:18:37,931 INFO L87 Difference]: Start difference. First operand 65 states and 72 transitions. Second operand has 24 states, 24 states have (on average 4.583333333333333) internal successors, (110), 24 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:38,268 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:18:38,268 INFO L93 Difference]: Finished difference Result 65 states and 70 transitions. [2021-12-06 18:18:38,268 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2021-12-06 18:18:38,268 INFO L78 Accepts]: Start accepts. Automaton has has 24 states, 24 states have (on average 4.583333333333333) internal successors, (110), 24 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 43 [2021-12-06 18:18:38,269 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-12-06 18:18:38,269 INFO L225 Difference]: With dead ends: 65 [2021-12-06 18:18:38,269 INFO L226 Difference]: Without dead ends: 65 [2021-12-06 18:18:38,269 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 112 GetRequests, 77 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 236 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=293, Invalid=1039, Unknown=0, NotChecked=0, Total=1332 [2021-12-06 18:18:38,270 INFO L933 BasicCegarLoop]: 27 mSDtfsCounter, 145 mSDsluCounter, 192 mSDsCounter, 0 mSdLazyCounter, 266 mSolverCounterSat, 70 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 145 SdHoareTripleChecker+Valid, 219 SdHoareTripleChecker+Invalid, 336 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 70 IncrementalHoareTripleChecker+Valid, 266 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2021-12-06 18:18:38,270 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [145 Valid, 219 Invalid, 336 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [70 Valid, 266 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2021-12-06 18:18:38,270 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65 states. [2021-12-06 18:18:38,272 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65 to 65. [2021-12-06 18:18:38,272 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65 states, 60 states have (on average 1.1) internal successors, (66), 63 states have internal predecessors, (66), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2021-12-06 18:18:38,272 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 70 transitions. [2021-12-06 18:18:38,272 INFO L78 Accepts]: Start accepts. Automaton has 65 states and 70 transitions. Word has length 43 [2021-12-06 18:18:38,272 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-12-06 18:18:38,272 INFO L470 AbstractCegarLoop]: Abstraction has 65 states and 70 transitions. [2021-12-06 18:18:38,272 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 24 states, 24 states have (on average 4.583333333333333) internal successors, (110), 24 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:38,273 INFO L276 IsEmpty]: Start isEmpty. Operand 65 states and 70 transitions. [2021-12-06 18:18:38,273 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2021-12-06 18:18:38,273 INFO L506 BasicCegarLoop]: Found error trace [2021-12-06 18:18:38,273 INFO L514 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:18:38,292 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Ended with exit code 0 [2021-12-06 18:18:38,474 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable18,6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 18:18:38,475 INFO L402 AbstractCegarLoop]: === Iteration 20 === Targeting ULTIMATE.startErr24ASSERT_VIOLATIONMEMORY_LEAK === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATION (and 22 more)] === [2021-12-06 18:18:38,476 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:18:38,476 INFO L85 PathProgramCache]: Analyzing trace with hash -990509317, now seen corresponding path program 2 times [2021-12-06 18:18:38,476 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:18:38,476 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [145575037] [2021-12-06 18:18:38,477 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:18:38,477 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:18:38,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:38,597 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 0 proven. 17 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2021-12-06 18:18:38,597 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:18:38,597 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [145575037] [2021-12-06 18:18:38,597 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [145575037] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 18:18:38,597 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [264302317] [2021-12-06 18:18:38,598 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-12-06 18:18:38,598 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 18:18:38,598 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:18:38,598 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 18:18:38,599 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2021-12-06 18:18:38,666 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-12-06 18:18:38,666 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 18:18:38,667 INFO L263 TraceCheckSpWp]: Trace formula consists of 262 conjuncts, 31 conjunts are in the unsatisfiable core [2021-12-06 18:18:38,669 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 18:18:38,689 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2021-12-06 18:18:38,899 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-12-06 18:18:38,915 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 7 proven. 23 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-12-06 18:18:38,915 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 18:18:39,031 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 19 proven. 11 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-12-06 18:18:39,031 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [264302317] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 18:18:39,031 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 18:18:39,032 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 11] total 27 [2021-12-06 18:18:39,032 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [314258869] [2021-12-06 18:18:39,032 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 18:18:39,032 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 27 states [2021-12-06 18:18:39,032 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:18:39,032 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2021-12-06 18:18:39,033 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=125, Invalid=577, Unknown=0, NotChecked=0, Total=702 [2021-12-06 18:18:39,033 INFO L87 Difference]: Start difference. First operand 65 states and 70 transitions. Second operand has 27 states, 27 states have (on average 4.518518518518518) internal successors, (122), 27 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:39,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:18:39,338 INFO L93 Difference]: Finished difference Result 67 states and 71 transitions. [2021-12-06 18:18:39,338 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2021-12-06 18:18:39,339 INFO L78 Accepts]: Start accepts. Automaton has has 27 states, 27 states have (on average 4.518518518518518) internal successors, (122), 27 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 53 [2021-12-06 18:18:39,339 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-12-06 18:18:39,339 INFO L225 Difference]: With dead ends: 67 [2021-12-06 18:18:39,339 INFO L226 Difference]: Without dead ends: 67 [2021-12-06 18:18:39,340 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 136 GetRequests, 96 SyntacticMatches, 1 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 405 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=421, Invalid=1219, Unknown=0, NotChecked=0, Total=1640 [2021-12-06 18:18:39,340 INFO L933 BasicCegarLoop]: 28 mSDtfsCounter, 158 mSDsluCounter, 154 mSDsCounter, 0 mSdLazyCounter, 269 mSolverCounterSat, 80 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 158 SdHoareTripleChecker+Valid, 182 SdHoareTripleChecker+Invalid, 349 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 80 IncrementalHoareTripleChecker+Valid, 269 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2021-12-06 18:18:39,341 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [158 Valid, 182 Invalid, 349 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [80 Valid, 269 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2021-12-06 18:18:39,341 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states. [2021-12-06 18:18:39,343 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 65. [2021-12-06 18:18:39,343 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65 states, 60 states have (on average 1.0833333333333333) internal successors, (65), 63 states have internal predecessors, (65), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2021-12-06 18:18:39,344 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 69 transitions. [2021-12-06 18:18:39,344 INFO L78 Accepts]: Start accepts. Automaton has 65 states and 69 transitions. Word has length 53 [2021-12-06 18:18:39,344 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-12-06 18:18:39,344 INFO L470 AbstractCegarLoop]: Abstraction has 65 states and 69 transitions. [2021-12-06 18:18:39,344 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 27 states, 27 states have (on average 4.518518518518518) internal successors, (122), 27 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:39,344 INFO L276 IsEmpty]: Start isEmpty. Operand 65 states and 69 transitions. [2021-12-06 18:18:39,345 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2021-12-06 18:18:39,345 INFO L506 BasicCegarLoop]: Found error trace [2021-12-06 18:18:39,345 INFO L514 BasicCegarLoop]: trace histogram [4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:18:39,365 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Ended with exit code 0 [2021-12-06 18:18:39,546 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable19,7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 18:18:39,547 INFO L402 AbstractCegarLoop]: === Iteration 21 === Targeting ULTIMATE.startErr23REQUIRES_VIOLATION === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATION (and 22 more)] === [2021-12-06 18:18:39,548 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:18:39,548 INFO L85 PathProgramCache]: Analyzing trace with hash 868555041, now seen corresponding path program 2 times [2021-12-06 18:18:39,549 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:18:39,549 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [709173209] [2021-12-06 18:18:39,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:18:39,549 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:18:39,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:39,724 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 10 proven. 35 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-12-06 18:18:39,725 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:18:39,725 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [709173209] [2021-12-06 18:18:39,725 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [709173209] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 18:18:39,725 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [485585762] [2021-12-06 18:18:39,725 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-12-06 18:18:39,725 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 18:18:39,725 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:18:39,726 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 18:18:39,727 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2021-12-06 18:18:39,794 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-12-06 18:18:39,794 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 18:18:39,795 INFO L263 TraceCheckSpWp]: Trace formula consists of 265 conjuncts, 33 conjunts are in the unsatisfiable core [2021-12-06 18:18:39,799 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 18:18:39,815 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2021-12-06 18:18:39,828 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 18:18:39,828 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2021-12-06 18:18:39,834 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 18:18:39,835 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2021-12-06 18:18:39,841 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 18:18:39,842 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2021-12-06 18:18:39,848 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 18:18:39,848 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2021-12-06 18:18:39,855 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 18:18:39,855 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2021-12-06 18:18:39,861 INFO L190 IndexEqualityManager]: detected not equals via solver [2021-12-06 18:18:39,862 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2021-12-06 18:18:40,027 INFO L388 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2021-12-06 18:18:40,040 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 21 proven. 3 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2021-12-06 18:18:40,041 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 18:18:40,135 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 21 proven. 3 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2021-12-06 18:18:40,135 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [485585762] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 18:18:40,135 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 18:18:40,135 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 9, 8] total 23 [2021-12-06 18:18:40,135 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [269796279] [2021-12-06 18:18:40,135 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 18:18:40,135 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 23 states [2021-12-06 18:18:40,136 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:18:40,136 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2021-12-06 18:18:40,136 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=82, Invalid=424, Unknown=0, NotChecked=0, Total=506 [2021-12-06 18:18:40,136 INFO L87 Difference]: Start difference. First operand 65 states and 69 transitions. Second operand has 23 states, 23 states have (on average 5.0) internal successors, (115), 23 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:40,433 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:18:40,434 INFO L93 Difference]: Finished difference Result 63 states and 66 transitions. [2021-12-06 18:18:40,434 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2021-12-06 18:18:40,434 INFO L78 Accepts]: Start accepts. Automaton has has 23 states, 23 states have (on average 5.0) internal successors, (115), 23 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 54 [2021-12-06 18:18:40,434 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-12-06 18:18:40,434 INFO L225 Difference]: With dead ends: 63 [2021-12-06 18:18:40,435 INFO L226 Difference]: Without dead ends: 63 [2021-12-06 18:18:40,435 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 137 GetRequests, 95 SyntacticMatches, 6 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 355 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=266, Invalid=1140, Unknown=0, NotChecked=0, Total=1406 [2021-12-06 18:18:40,436 INFO L933 BasicCegarLoop]: 26 mSDtfsCounter, 101 mSDsluCounter, 232 mSDsCounter, 0 mSdLazyCounter, 370 mSolverCounterSat, 51 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 101 SdHoareTripleChecker+Valid, 258 SdHoareTripleChecker+Invalid, 421 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 51 IncrementalHoareTripleChecker+Valid, 370 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2021-12-06 18:18:40,436 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [101 Valid, 258 Invalid, 421 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [51 Valid, 370 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2021-12-06 18:18:40,436 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states. [2021-12-06 18:18:40,437 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 63. [2021-12-06 18:18:40,438 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63 states, 59 states have (on average 1.0508474576271187) internal successors, (62), 61 states have internal predecessors, (62), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2021-12-06 18:18:40,438 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 66 transitions. [2021-12-06 18:18:40,438 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 66 transitions. Word has length 54 [2021-12-06 18:18:40,438 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-12-06 18:18:40,438 INFO L470 AbstractCegarLoop]: Abstraction has 63 states and 66 transitions. [2021-12-06 18:18:40,438 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 23 states, 23 states have (on average 5.0) internal successors, (115), 23 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:40,438 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 66 transitions. [2021-12-06 18:18:40,439 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2021-12-06 18:18:40,439 INFO L506 BasicCegarLoop]: Found error trace [2021-12-06 18:18:40,439 INFO L514 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:18:40,459 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Ended with exit code 0 [2021-12-06 18:18:40,639 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable20,8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 18:18:40,641 INFO L402 AbstractCegarLoop]: === Iteration 22 === Targeting ULTIMATE.startErr24ASSERT_VIOLATIONMEMORY_LEAK === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATION (and 22 more)] === [2021-12-06 18:18:40,641 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:18:40,642 INFO L85 PathProgramCache]: Analyzing trace with hash 679832114, now seen corresponding path program 3 times [2021-12-06 18:18:40,642 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:18:40,642 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1325319521] [2021-12-06 18:18:40,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:18:40,643 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:18:40,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:40,744 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2021-12-06 18:18:40,744 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:18:40,744 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1325319521] [2021-12-06 18:18:40,744 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1325319521] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 18:18:40,744 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [657632335] [2021-12-06 18:18:40,744 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-12-06 18:18:40,745 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 18:18:40,745 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:18:40,745 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 18:18:40,746 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2021-12-06 18:18:40,982 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2021-12-06 18:18:40,982 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 18:18:40,983 INFO L263 TraceCheckSpWp]: Trace formula consists of 211 conjuncts, 7 conjunts are in the unsatisfiable core [2021-12-06 18:18:40,985 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 18:18:41,047 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2021-12-06 18:18:41,047 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 18:18:41,114 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2021-12-06 18:18:41,114 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [657632335] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 18:18:41,115 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 18:18:41,115 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 9 [2021-12-06 18:18:41,115 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [663070538] [2021-12-06 18:18:41,115 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 18:18:41,115 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2021-12-06 18:18:41,116 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:18:41,116 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2021-12-06 18:18:41,116 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=43, Unknown=0, NotChecked=0, Total=72 [2021-12-06 18:18:41,116 INFO L87 Difference]: Start difference. First operand 63 states and 66 transitions. Second operand has 9 states, 9 states have (on average 4.777777777777778) internal successors, (43), 9 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:41,167 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:18:41,168 INFO L93 Difference]: Finished difference Result 66 states and 69 transitions. [2021-12-06 18:18:41,168 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-06 18:18:41,168 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 4.777777777777778) internal successors, (43), 9 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 58 [2021-12-06 18:18:41,168 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-12-06 18:18:41,169 INFO L225 Difference]: With dead ends: 66 [2021-12-06 18:18:41,169 INFO L226 Difference]: Without dead ends: 66 [2021-12-06 18:18:41,169 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 121 GetRequests, 111 SyntacticMatches, 1 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=65, Unknown=0, NotChecked=0, Total=110 [2021-12-06 18:18:41,170 INFO L933 BasicCegarLoop]: 40 mSDtfsCounter, 35 mSDsluCounter, 82 mSDsCounter, 0 mSdLazyCounter, 17 mSolverCounterSat, 8 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 37 SdHoareTripleChecker+Valid, 122 SdHoareTripleChecker+Invalid, 25 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 8 IncrementalHoareTripleChecker+Valid, 17 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2021-12-06 18:18:41,170 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [37 Valid, 122 Invalid, 25 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [8 Valid, 17 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2021-12-06 18:18:41,170 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states. [2021-12-06 18:18:41,172 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 66. [2021-12-06 18:18:41,172 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66 states, 62 states have (on average 1.0483870967741935) internal successors, (65), 64 states have internal predecessors, (65), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2021-12-06 18:18:41,173 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 69 transitions. [2021-12-06 18:18:41,173 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 69 transitions. Word has length 58 [2021-12-06 18:18:41,173 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-12-06 18:18:41,173 INFO L470 AbstractCegarLoop]: Abstraction has 66 states and 69 transitions. [2021-12-06 18:18:41,173 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 4.777777777777778) internal successors, (43), 9 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:41,173 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 69 transitions. [2021-12-06 18:18:41,174 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2021-12-06 18:18:41,174 INFO L506 BasicCegarLoop]: Found error trace [2021-12-06 18:18:41,174 INFO L514 BasicCegarLoop]: trace histogram [4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:18:41,195 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Ended with exit code 0 [2021-12-06 18:18:41,374 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable21,9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 18:18:41,375 INFO L402 AbstractCegarLoop]: === Iteration 23 === Targeting ULTIMATE.startErr24ASSERT_VIOLATIONMEMORY_LEAK === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATION (and 22 more)] === [2021-12-06 18:18:41,375 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:18:41,375 INFO L85 PathProgramCache]: Analyzing trace with hash -220059533, now seen corresponding path program 4 times [2021-12-06 18:18:41,375 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:18:41,375 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1651571555] [2021-12-06 18:18:41,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:18:41,375 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:18:41,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:41,488 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2021-12-06 18:18:41,488 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:18:41,488 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1651571555] [2021-12-06 18:18:41,488 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1651571555] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 18:18:41,488 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1960638959] [2021-12-06 18:18:41,488 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-12-06 18:18:41,488 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 18:18:41,489 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:18:41,489 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 18:18:41,490 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2021-12-06 18:18:41,845 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-12-06 18:18:41,845 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 18:18:41,847 INFO L263 TraceCheckSpWp]: Trace formula consists of 300 conjuncts, 14 conjunts are in the unsatisfiable core [2021-12-06 18:18:41,848 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 18:18:41,941 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2021-12-06 18:18:41,941 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 18:18:42,119 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2021-12-06 18:18:42,120 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1960638959] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 18:18:42,120 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 18:18:42,120 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8] total 18 [2021-12-06 18:18:42,120 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [335723944] [2021-12-06 18:18:42,120 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 18:18:42,120 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2021-12-06 18:18:42,121 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:18:42,121 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2021-12-06 18:18:42,121 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=104, Invalid=202, Unknown=0, NotChecked=0, Total=306 [2021-12-06 18:18:42,121 INFO L87 Difference]: Start difference. First operand 66 states and 69 transitions. Second operand has 18 states, 18 states have (on average 2.888888888888889) internal successors, (52), 18 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:42,879 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:18:42,880 INFO L93 Difference]: Finished difference Result 72 states and 75 transitions. [2021-12-06 18:18:42,880 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2021-12-06 18:18:42,881 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 2.888888888888889) internal successors, (52), 18 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 61 [2021-12-06 18:18:42,881 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-12-06 18:18:42,881 INFO L225 Difference]: With dead ends: 72 [2021-12-06 18:18:42,881 INFO L226 Difference]: Without dead ends: 72 [2021-12-06 18:18:42,881 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 134 GetRequests, 111 SyntacticMatches, 1 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 112 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=187, Invalid=365, Unknown=0, NotChecked=0, Total=552 [2021-12-06 18:18:42,882 INFO L933 BasicCegarLoop]: 40 mSDtfsCounter, 131 mSDsluCounter, 166 mSDsCounter, 0 mSdLazyCounter, 56 mSolverCounterSat, 33 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 131 SdHoareTripleChecker+Valid, 206 SdHoareTripleChecker+Invalid, 89 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 33 IncrementalHoareTripleChecker+Valid, 56 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2021-12-06 18:18:42,882 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [131 Valid, 206 Invalid, 89 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [33 Valid, 56 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2021-12-06 18:18:42,882 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72 states. [2021-12-06 18:18:42,884 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72 to 72. [2021-12-06 18:18:42,884 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 72 states, 68 states have (on average 1.0441176470588236) internal successors, (71), 70 states have internal predecessors, (71), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2021-12-06 18:18:42,885 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 75 transitions. [2021-12-06 18:18:42,885 INFO L78 Accepts]: Start accepts. Automaton has 72 states and 75 transitions. Word has length 61 [2021-12-06 18:18:42,885 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-12-06 18:18:42,885 INFO L470 AbstractCegarLoop]: Abstraction has 72 states and 75 transitions. [2021-12-06 18:18:42,885 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 2.888888888888889) internal successors, (52), 18 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:42,885 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 75 transitions. [2021-12-06 18:18:42,886 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2021-12-06 18:18:42,886 INFO L506 BasicCegarLoop]: Found error trace [2021-12-06 18:18:42,886 INFO L514 BasicCegarLoop]: trace histogram [10, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:18:42,906 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Ended with exit code 0 [2021-12-06 18:18:43,086 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable22,10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 18:18:43,088 INFO L402 AbstractCegarLoop]: === Iteration 24 === Targeting ULTIMATE.startErr24ASSERT_VIOLATIONMEMORY_LEAK === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATION (and 22 more)] === [2021-12-06 18:18:43,089 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:18:43,089 INFO L85 PathProgramCache]: Analyzing trace with hash -179470317, now seen corresponding path program 5 times [2021-12-06 18:18:43,090 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:18:43,090 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [354410494] [2021-12-06 18:18:43,091 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:18:43,091 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:18:43,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:43,291 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2021-12-06 18:18:43,292 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:18:43,292 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [354410494] [2021-12-06 18:18:43,292 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [354410494] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 18:18:43,292 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1771693980] [2021-12-06 18:18:43,292 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-12-06 18:18:43,292 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 18:18:43,292 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:18:43,293 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 18:18:43,299 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2021-12-06 18:18:44,341 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2021-12-06 18:18:44,341 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 18:18:44,344 INFO L263 TraceCheckSpWp]: Trace formula consists of 342 conjuncts, 26 conjunts are in the unsatisfiable core [2021-12-06 18:18:44,346 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 18:18:44,534 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2021-12-06 18:18:44,534 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 18:18:44,929 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2021-12-06 18:18:44,929 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1771693980] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 18:18:44,929 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 18:18:44,929 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14] total 36 [2021-12-06 18:18:44,929 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2017139116] [2021-12-06 18:18:44,929 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 18:18:44,930 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 36 states [2021-12-06 18:18:44,930 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:18:44,930 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2021-12-06 18:18:44,931 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=362, Invalid=898, Unknown=0, NotChecked=0, Total=1260 [2021-12-06 18:18:44,931 INFO L87 Difference]: Start difference. First operand 72 states and 75 transitions. Second operand has 36 states, 36 states have (on average 1.9444444444444444) internal successors, (70), 36 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:53,235 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:18:53,235 INFO L93 Difference]: Finished difference Result 84 states and 87 transitions. [2021-12-06 18:18:53,236 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2021-12-06 18:18:53,236 INFO L78 Accepts]: Start accepts. Automaton has has 36 states, 36 states have (on average 1.9444444444444444) internal successors, (70), 36 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 67 [2021-12-06 18:18:53,236 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-12-06 18:18:53,237 INFO L225 Difference]: With dead ends: 84 [2021-12-06 18:18:53,237 INFO L226 Difference]: Without dead ends: 84 [2021-12-06 18:18:53,237 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 158 GetRequests, 111 SyntacticMatches, 1 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 514 ImplicationChecksByTransitivity, 7.6s TimeCoverageRelationStatistics Valid=669, Invalid=1587, Unknown=0, NotChecked=0, Total=2256 [2021-12-06 18:18:53,238 INFO L933 BasicCegarLoop]: 40 mSDtfsCounter, 195 mSDsluCounter, 255 mSDsCounter, 0 mSdLazyCounter, 238 mSolverCounterSat, 66 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 195 SdHoareTripleChecker+Valid, 295 SdHoareTripleChecker+Invalid, 304 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 66 IncrementalHoareTripleChecker+Valid, 238 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.2s IncrementalHoareTripleChecker+Time [2021-12-06 18:18:53,238 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [195 Valid, 295 Invalid, 304 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [66 Valid, 238 Invalid, 0 Unknown, 0 Unchecked, 1.2s Time] [2021-12-06 18:18:53,238 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states. [2021-12-06 18:18:53,239 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 84. [2021-12-06 18:18:53,240 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 84 states, 80 states have (on average 1.0375) internal successors, (83), 82 states have internal predecessors, (83), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2021-12-06 18:18:53,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 87 transitions. [2021-12-06 18:18:53,240 INFO L78 Accepts]: Start accepts. Automaton has 84 states and 87 transitions. Word has length 67 [2021-12-06 18:18:53,240 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-12-06 18:18:53,240 INFO L470 AbstractCegarLoop]: Abstraction has 84 states and 87 transitions. [2021-12-06 18:18:53,240 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 36 states, 36 states have (on average 1.9444444444444444) internal successors, (70), 36 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:18:53,240 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states and 87 transitions. [2021-12-06 18:18:53,241 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2021-12-06 18:18:53,241 INFO L506 BasicCegarLoop]: Found error trace [2021-12-06 18:18:53,241 INFO L514 BasicCegarLoop]: trace histogram [22, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:18:53,245 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Ended with exit code 0 [2021-12-06 18:18:53,442 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable23 [2021-12-06 18:18:53,443 INFO L402 AbstractCegarLoop]: === Iteration 25 === Targeting ULTIMATE.startErr24ASSERT_VIOLATIONMEMORY_LEAK === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATION (and 22 more)] === [2021-12-06 18:18:53,444 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:18:53,444 INFO L85 PathProgramCache]: Analyzing trace with hash -595228845, now seen corresponding path program 6 times [2021-12-06 18:18:53,444 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:18:53,445 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1809016714] [2021-12-06 18:18:53,445 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:18:53,445 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:18:53,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:18:53,884 INFO L134 CoverageAnalysis]: Checked inductivity of 295 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2021-12-06 18:18:53,884 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:18:53,884 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1809016714] [2021-12-06 18:18:53,884 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1809016714] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 18:18:53,884 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1227634727] [2021-12-06 18:18:53,884 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-12-06 18:18:53,884 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 18:18:53,884 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:18:53,885 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 18:18:53,885 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2021-12-06 18:19:02,738 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 12 check-sat command(s) [2021-12-06 18:19:02,738 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-12-06 18:19:02,753 INFO L263 TraceCheckSpWp]: Trace formula consists of 426 conjuncts, 51 conjunts are in the unsatisfiable core [2021-12-06 18:19:02,755 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 18:19:03,318 INFO L134 CoverageAnalysis]: Checked inductivity of 295 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2021-12-06 18:19:03,318 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 18:19:04,330 INFO L134 CoverageAnalysis]: Checked inductivity of 295 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2021-12-06 18:19:04,330 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1227634727] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 18:19:04,330 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 18:19:04,330 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26] total 72 [2021-12-06 18:19:04,331 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [778396751] [2021-12-06 18:19:04,331 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 18:19:04,331 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 72 states [2021-12-06 18:19:04,331 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:19:04,332 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 72 interpolants. [2021-12-06 18:19:04,333 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1310, Invalid=3802, Unknown=0, NotChecked=0, Total=5112 [2021-12-06 18:19:04,333 INFO L87 Difference]: Start difference. First operand 84 states and 87 transitions. Second operand has 72 states, 72 states have (on average 1.4722222222222223) internal successors, (106), 72 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:19:31,775 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 3) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 12) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 18) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 5) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 19) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 7) 4294967296) .cse0) (<= |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 94) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 9) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 14) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 20) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 6) 4294967296) .cse0) (<= 94 |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1|) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 8) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 16) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 2) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 15) 4294967296) .cse0))) is different from false [2021-12-06 18:19:33,807 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 3) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 12) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 18) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 5) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 19) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 7) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 9) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 14) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 6) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 8) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 16) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 2) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 15) 4294967296) .cse0))) is different from false [2021-12-06 18:20:56,516 WARN L227 SmtUtils]: Spent 45.18s on a formula simplification that was a NOOP. DAG size: 79 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2021-12-06 18:20:58,522 WARN L534 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2021-12-06 18:21:00,518 WARN L534 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 1.40s for a HTC check with result INVALID. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2021-12-06 18:22:13,805 WARN L227 SmtUtils]: Spent 39.80s on a formula simplification that was a NOOP. DAG size: 75 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2021-12-06 18:22:15,528 WARN L534 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 1.72s for a HTC check with result INVALID. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2021-12-06 18:23:25,662 WARN L227 SmtUtils]: Spent 38.86s on a formula simplification that was a NOOP. DAG size: 71 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2021-12-06 18:23:27,668 WARN L534 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.01s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2021-12-06 18:24:22,552 WARN L227 SmtUtils]: Spent 34.58s on a formula simplification that was a NOOP. DAG size: 67 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2021-12-06 18:24:23,640 WARN L534 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 1.07s for a HTC check with result INVALID. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2021-12-06 18:25:12,259 WARN L227 SmtUtils]: Spent 26.36s on a formula simplification that was a NOOP. DAG size: 63 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2021-12-06 18:25:44,314 WARN L227 SmtUtils]: Spent 13.68s on a formula simplification that was a NOOP. DAG size: 59 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2021-12-06 18:26:07,753 WARN L227 SmtUtils]: Spent 10.76s on a formula simplification that was a NOOP. DAG size: 55 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2021-12-06 18:26:25,999 WARN L227 SmtUtils]: Spent 7.34s on a formula simplification that was a NOOP. DAG size: 51 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2021-12-06 18:27:10,710 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-06 18:27:10,710 INFO L93 Difference]: Finished difference Result 108 states and 111 transitions. [2021-12-06 18:27:10,711 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2021-12-06 18:27:10,711 INFO L78 Accepts]: Start accepts. Automaton has has 72 states, 72 states have (on average 1.4722222222222223) internal successors, (106), 72 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 79 [2021-12-06 18:27:10,711 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-12-06 18:27:10,712 INFO L225 Difference]: With dead ends: 108 [2021-12-06 18:27:10,712 INFO L226 Difference]: Without dead ends: 108 [2021-12-06 18:27:10,715 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 204 GetRequests, 111 SyntacticMatches, 1 SemanticMatches, 92 ConstructedPredicates, 2 IntricatePredicates, 0 DeprecatedPredicates, 2456 ImplicationChecksByTransitivity, 477.9s TimeCoverageRelationStatistics Valid=2636, Invalid=5738, Unknown=6, NotChecked=362, Total=8742 [2021-12-06 18:27:10,716 INFO L933 BasicCegarLoop]: 41 mSDtfsCounter, 1 mSDsluCounter, 935 mSDsCounter, 0 mSdLazyCounter, 835 mSolverCounterSat, 62 mSolverCounterUnsat, 2 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 10.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 976 SdHoareTripleChecker+Invalid, 901 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 62 IncrementalHoareTripleChecker+Valid, 835 IncrementalHoareTripleChecker+Invalid, 2 IncrementalHoareTripleChecker+Unknown, 2 IncrementalHoareTripleChecker+Unchecked, 10.1s IncrementalHoareTripleChecker+Time [2021-12-06 18:27:10,716 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [1 Valid, 976 Invalid, 901 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [62 Valid, 835 Invalid, 2 Unknown, 2 Unchecked, 10.1s Time] [2021-12-06 18:27:10,716 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108 states. [2021-12-06 18:27:10,718 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108 to 108. [2021-12-06 18:27:10,719 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108 states, 104 states have (on average 1.0288461538461537) internal successors, (107), 106 states have internal predecessors, (107), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2021-12-06 18:27:10,719 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 111 transitions. [2021-12-06 18:27:10,719 INFO L78 Accepts]: Start accepts. Automaton has 108 states and 111 transitions. Word has length 79 [2021-12-06 18:27:10,720 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-12-06 18:27:10,720 INFO L470 AbstractCegarLoop]: Abstraction has 108 states and 111 transitions. [2021-12-06 18:27:10,720 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 72 states, 72 states have (on average 1.4722222222222223) internal successors, (106), 72 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:27:10,720 INFO L276 IsEmpty]: Start isEmpty. Operand 108 states and 111 transitions. [2021-12-06 18:27:10,721 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 104 [2021-12-06 18:27:10,721 INFO L506 BasicCegarLoop]: Found error trace [2021-12-06 18:27:10,721 INFO L514 BasicCegarLoop]: trace histogram [46, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-06 18:27:10,728 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Ended with exit code 0 [2021-12-06 18:27:10,921 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable24 [2021-12-06 18:27:10,922 INFO L402 AbstractCegarLoop]: === Iteration 26 === Targeting ULTIMATE.startErr24ASSERT_VIOLATIONMEMORY_LEAK === [ULTIMATE.startErr0ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1ASSERT_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATION (and 22 more)] === [2021-12-06 18:27:10,922 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-06 18:27:10,922 INFO L85 PathProgramCache]: Analyzing trace with hash 51574227, now seen corresponding path program 7 times [2021-12-06 18:27:10,922 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-06 18:27:10,922 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1571221064] [2021-12-06 18:27:10,922 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-06 18:27:10,922 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-06 18:27:10,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:27:12,257 INFO L134 CoverageAnalysis]: Checked inductivity of 1123 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2021-12-06 18:27:12,257 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-06 18:27:12,257 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1571221064] [2021-12-06 18:27:12,257 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1571221064] provided 0 perfect and 1 imperfect interpolant sequences [2021-12-06 18:27:12,258 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [186245148] [2021-12-06 18:27:12,258 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-12-06 18:27:12,258 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-12-06 18:27:12,258 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 [2021-12-06 18:27:12,258 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-12-06 18:27:12,259 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_43b5b5c5-b0df-4edf-8bd7-78af2b7bc47a/bin/uautomizer-DrprNOufMa/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2021-12-06 18:27:12,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-06 18:27:12,848 INFO L263 TraceCheckSpWp]: Trace formula consists of 594 conjuncts, 97 conjunts are in the unsatisfiable core [2021-12-06 18:27:12,850 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-12-06 18:27:15,138 INFO L134 CoverageAnalysis]: Checked inductivity of 1123 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2021-12-06 18:27:15,138 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-12-06 18:27:19,216 INFO L134 CoverageAnalysis]: Checked inductivity of 1123 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2021-12-06 18:27:19,217 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [186245148] provided 0 perfect and 2 imperfect interpolant sequences [2021-12-06 18:27:19,217 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-12-06 18:27:19,217 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50, 50] total 144 [2021-12-06 18:27:19,217 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [245504251] [2021-12-06 18:27:19,217 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-12-06 18:27:19,217 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 144 states [2021-12-06 18:27:19,217 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-06 18:27:19,219 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 144 interpolants. [2021-12-06 18:27:19,224 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4934, Invalid=15658, Unknown=0, NotChecked=0, Total=20592 [2021-12-06 18:27:19,224 INFO L87 Difference]: Start difference. First operand 108 states and 111 transitions. Second operand has 144 states, 144 states have (on average 1.2361111111111112) internal successors, (178), 144 states have internal predecessors, (178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-06 18:27:22,346 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 3) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 31) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 43) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 12) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 36) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 41) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 22) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 18) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 5) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 19) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 7) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 23) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 34) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 37) 4294967296) .cse0) (<= |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 94) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 40) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 39) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 46) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 29) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 9) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 14) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 45) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 20) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 6) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 33) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 35) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 44) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 32) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 21) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 30) 4294967296) .cse0) (<= 94 |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1|) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 38) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 8) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 42) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 16) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 2) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 15) 4294967296) .cse0))) is different from false [2021-12-06 18:27:24,357 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 3) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 31) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 43) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 12) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 36) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 41) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 22) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 18) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 5) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 19) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 7) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 23) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 34) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 37) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 40) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 39) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 29) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 9) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 14) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 45) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 20) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 6) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 33) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 35) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 44) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 32) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 21) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 30) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 38) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 8) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 42) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 16) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 2) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 15) 4294967296) .cse0))) is different from false [2021-12-06 18:27:26,368 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 3) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 31) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 43) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 12) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 36) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 41) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 22) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 18) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 5) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 19) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 7) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 23) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 34) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 37) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 40) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 39) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 29) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 9) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 14) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 20) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 6) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 33) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 35) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 44) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 32) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 21) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 30) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 38) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 8) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 42) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 16) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 2) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 15) 4294967296) .cse0))) is different from false [2021-12-06 18:27:28,382 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 3) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 31) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 43) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 12) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 36) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 41) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 22) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 18) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 5) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 19) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 7) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 23) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 34) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 37) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 40) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 39) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 29) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 9) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 14) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 20) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 6) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 33) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 35) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 32) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 21) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 30) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 38) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 8) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 42) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 16) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 2) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 15) 4294967296) .cse0))) is different from false [2021-12-06 18:27:30,401 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 3) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 31) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 12) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 36) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 41) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 22) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 18) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 5) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 19) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 7) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 23) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 34) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 37) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 40) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 39) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 29) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 9) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 14) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 20) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 6) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 33) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 35) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 32) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 21) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 30) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 38) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 8) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 42) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 16) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 2) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 15) 4294967296) .cse0))) is different from false [2021-12-06 18:27:32,411 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 3) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 31) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 12) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 36) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 41) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 22) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 18) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 5) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 19) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 7) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 23) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 34) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 37) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 40) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 39) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 29) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 9) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 14) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 20) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 6) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 33) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 35) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 32) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 21) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 30) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 38) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 8) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 16) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 2) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 15) 4294967296) .cse0))) is different from false [2021-12-06 18:27:34,420 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 3) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 31) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 12) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 36) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 22) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 18) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 5) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 19) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 7) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 23) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 34) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 37) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 40) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 39) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 29) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 9) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 14) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 20) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 6) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 33) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 35) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 32) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 21) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 30) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 38) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 8) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 16) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 2) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 15) 4294967296) .cse0))) is different from false [2021-12-06 18:27:36,430 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 3) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 31) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 12) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 36) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 22) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 18) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 5) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 19) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 7) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 23) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 34) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 37) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 39) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 29) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 9) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 14) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 20) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 6) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 33) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 35) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 32) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 21) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 30) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 38) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 8) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 16) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 2) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 15) 4294967296) .cse0))) is different from false [2021-12-06 18:27:38,454 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 3) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 31) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 12) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 36) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 22) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 18) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 5) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 19) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 7) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 23) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 34) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 37) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 29) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 9) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 14) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 20) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 6) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 33) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 35) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 32) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 21) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 30) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 38) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 8) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 16) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 2) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 15) 4294967296) .cse0))) is different from false [2021-12-06 18:27:40,466 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 3) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 31) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 12) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 36) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 22) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 18) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 5) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 19) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 7) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 23) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 34) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 37) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 29) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 9) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 14) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 20) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 6) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 33) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 35) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 32) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 21) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 30) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 8) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 16) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 2) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 15) 4294967296) .cse0))) is different from false [2021-12-06 18:32:57,481 WARN L227 SmtUtils]: Spent 2.41m on a formula simplification that was a NOOP. DAG size: 151 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2021-12-06 18:32:59,487 WARN L534 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.01s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2021-12-06 18:33:01,496 WARN L534 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.01s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2021-12-06 18:33:03,506 WARN L534 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.01s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2021-12-06 18:33:05,514 WARN L534 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.01s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2021-12-06 18:33:07,524 WARN L534 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.01s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2021-12-06 18:33:09,536 WARN L534 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.01s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2021-12-06 18:33:11,550 WARN L534 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.01s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2021-12-06 18:33:13,558 WARN L534 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.01s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2021-12-06 18:33:15,565 WARN L534 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.01s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2021-12-06 18:33:17,572 WARN L534 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.01s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2021-12-06 18:33:19,730 WARN L534 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2021-12-06 18:33:21,737 WARN L534 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.01s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2021-12-06 18:33:23,750 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 3) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 31) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 12) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 22) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 18) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 5) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 19) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 7) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 23) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 34) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 29) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 9) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 14) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 20) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 6) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 33) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 35) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 32) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 21) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 30) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 8) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 16) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 2) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 15) 4294967296) .cse0))) is different from false [2021-12-06 18:33:25,761 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 3) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 31) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 12) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 22) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 18) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 5) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 19) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 7) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 23) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 34) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 29) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 9) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 14) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 20) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 6) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 33) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 32) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 21) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 30) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 8) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 16) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 2) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 15) 4294967296) .cse0))) is different from false [2021-12-06 18:33:27,771 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 3) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 31) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 12) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 22) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 18) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 5) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 19) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 7) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 23) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 29) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 9) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 14) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 20) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 6) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 33) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 32) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 21) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 30) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 8) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 16) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 2) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 15) 4294967296) .cse0))) is different from false [2021-12-06 18:33:29,782 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 3) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 31) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 12) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 22) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 18) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 5) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 19) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 7) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 23) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 29) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 9) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 14) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 20) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 6) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 32) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 21) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 30) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 8) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 16) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 2) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 15) 4294967296) .cse0))) is different from false [2021-12-06 18:33:31,790 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 3) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 31) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 12) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 22) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 18) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 5) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 19) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 7) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 23) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 29) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 9) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 14) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 20) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 6) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 21) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 30) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 8) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 16) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 2) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 15) 4294967296) .cse0))) is different from false [2021-12-06 18:33:33,800 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 3) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 12) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 22) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 18) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 5) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 19) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 7) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 23) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 29) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 9) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 14) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 20) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 6) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 21) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 30) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 8) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 16) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 2) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 15) 4294967296) .cse0))) is different from false [2021-12-06 18:33:35,808 WARN L838 $PredicateComparison]: unable to prove that (let ((.cse0 (mod |c_ULTIMATE.start_#Ultimate.C_memset_#amount#1| 4294967296))) (and (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 3) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 17) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 27) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 11) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 24) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 12) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 22) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 18) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 5) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 13) 4294967296) .cse0) (< (mod |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 28) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 19) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 7) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 23) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 29) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 9) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 14) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 25) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 20) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 6) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 21) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 4) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 1) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 26) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 8) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 10) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 16) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 2) 4294967296) .cse0) (< (mod (+ |c_ULTIMATE.start_#Ultimate.C_memset_#t~loopctr17#1| 15) 4294967296) .cse0))) is different from false