./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.14.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 839c364b Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.14.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 78a96934dff25285973ef889167a345947d7e73ab8a2ec405d96bd61e690530f --- Real Ultimate output --- This is Ultimate 0.2.2-839c364b5d67a0f615c82cb70ab247790648d4a9-839c364 [2021-12-14 23:43:21,085 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-14 23:43:21,087 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-14 23:43:21,116 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-14 23:43:21,116 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-14 23:43:21,117 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-14 23:43:21,118 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-14 23:43:21,119 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-14 23:43:21,120 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-14 23:43:21,120 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-14 23:43:21,121 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-14 23:43:21,122 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-14 23:43:21,122 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-14 23:43:21,122 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-14 23:43:21,123 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-14 23:43:21,124 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-14 23:43:21,125 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-14 23:43:21,125 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-14 23:43:21,126 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-14 23:43:21,127 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-14 23:43:21,128 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-14 23:43:21,129 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-14 23:43:21,130 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-14 23:43:21,131 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-14 23:43:21,132 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-14 23:43:21,133 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-14 23:43:21,133 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-14 23:43:21,134 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-14 23:43:21,134 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-14 23:43:21,135 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-14 23:43:21,135 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-14 23:43:21,135 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-14 23:43:21,136 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-14 23:43:21,136 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-14 23:43:21,137 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-14 23:43:21,137 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-14 23:43:21,138 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-14 23:43:21,138 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-14 23:43:21,138 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-14 23:43:21,139 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-14 23:43:21,139 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-14 23:43:21,140 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-14 23:43:21,159 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-14 23:43:21,159 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-14 23:43:21,160 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-14 23:43:21,160 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-14 23:43:21,161 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-14 23:43:21,161 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-14 23:43:21,161 INFO L138 SettingsManager]: * Use SBE=true [2021-12-14 23:43:21,161 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-14 23:43:21,161 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-14 23:43:21,161 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-14 23:43:21,162 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-14 23:43:21,162 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-14 23:43:21,162 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-14 23:43:21,162 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-14 23:43:21,162 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-14 23:43:21,162 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-14 23:43:21,163 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-14 23:43:21,163 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-14 23:43:21,163 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-14 23:43:21,163 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-14 23:43:21,163 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-14 23:43:21,164 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-14 23:43:21,164 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-14 23:43:21,164 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-14 23:43:21,164 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-14 23:43:21,164 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-14 23:43:21,164 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-14 23:43:21,165 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-14 23:43:21,165 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-14 23:43:21,165 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-14 23:43:21,165 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-14 23:43:21,165 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-14 23:43:21,166 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-14 23:43:21,166 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 78a96934dff25285973ef889167a345947d7e73ab8a2ec405d96bd61e690530f [2021-12-14 23:43:21,349 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-14 23:43:21,367 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-14 23:43:21,369 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-14 23:43:21,370 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-14 23:43:21,371 INFO L275 PluginConnector]: CDTParser initialized [2021-12-14 23:43:21,373 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.14.cil.c [2021-12-14 23:43:21,469 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a3c4e217e/1f8d307dfbd74f2595b9283d7ff13e74/FLAG5dc71a741 [2021-12-14 23:43:21,900 INFO L306 CDTParser]: Found 1 translation units. [2021-12-14 23:43:21,901 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.14.cil.c [2021-12-14 23:43:21,912 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a3c4e217e/1f8d307dfbd74f2595b9283d7ff13e74/FLAG5dc71a741 [2021-12-14 23:43:22,312 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a3c4e217e/1f8d307dfbd74f2595b9283d7ff13e74 [2021-12-14 23:43:22,314 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-14 23:43:22,315 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-14 23:43:22,316 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-14 23:43:22,316 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-14 23:43:22,319 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-14 23:43:22,319 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.12 11:43:22" (1/1) ... [2021-12-14 23:43:22,320 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2a154d86 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 11:43:22, skipping insertion in model container [2021-12-14 23:43:22,320 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.12 11:43:22" (1/1) ... [2021-12-14 23:43:22,324 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-14 23:43:22,364 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-14 23:43:22,508 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.14.cil.c[669,682] [2021-12-14 23:43:22,635 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-14 23:43:22,654 INFO L203 MainTranslator]: Completed pre-run [2021-12-14 23:43:22,661 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.14.cil.c[669,682] [2021-12-14 23:43:22,709 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-14 23:43:22,722 INFO L208 MainTranslator]: Completed translation [2021-12-14 23:43:22,722 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 11:43:22 WrapperNode [2021-12-14 23:43:22,722 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-14 23:43:22,723 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-14 23:43:22,723 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-14 23:43:22,724 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-14 23:43:22,728 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 11:43:22" (1/1) ... [2021-12-14 23:43:22,738 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 11:43:22" (1/1) ... [2021-12-14 23:43:22,815 INFO L137 Inliner]: procedures = 52, calls = 68, calls flagged for inlining = 63, calls inlined = 270, statements flattened = 4144 [2021-12-14 23:43:22,817 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-14 23:43:22,818 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-14 23:43:22,818 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-14 23:43:22,818 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-14 23:43:22,824 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 11:43:22" (1/1) ... [2021-12-14 23:43:22,824 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 11:43:22" (1/1) ... [2021-12-14 23:43:22,855 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 11:43:22" (1/1) ... [2021-12-14 23:43:22,856 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 11:43:22" (1/1) ... [2021-12-14 23:43:22,925 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 11:43:22" (1/1) ... [2021-12-14 23:43:22,977 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 11:43:22" (1/1) ... [2021-12-14 23:43:22,985 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 11:43:22" (1/1) ... [2021-12-14 23:43:22,997 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-14 23:43:22,998 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-14 23:43:22,999 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-14 23:43:22,999 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-14 23:43:23,000 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 11:43:22" (1/1) ... [2021-12-14 23:43:23,005 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-14 23:43:23,014 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-14 23:43:23,029 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-14 23:43:23,031 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-14 23:43:23,055 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-14 23:43:23,056 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-14 23:43:23,056 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-14 23:43:23,056 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-14 23:43:23,134 INFO L236 CfgBuilder]: Building ICFG [2021-12-14 23:43:23,135 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-14 23:43:24,663 INFO L277 CfgBuilder]: Performing block encoding [2021-12-14 23:43:24,678 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-14 23:43:24,678 INFO L301 CfgBuilder]: Removed 15 assume(true) statements. [2021-12-14 23:43:24,681 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.12 11:43:24 BoogieIcfgContainer [2021-12-14 23:43:24,681 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-14 23:43:24,681 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-14 23:43:24,682 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-14 23:43:24,684 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-14 23:43:24,684 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-14 23:43:24,684 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 14.12 11:43:22" (1/3) ... [2021-12-14 23:43:24,686 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@26d407f4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 14.12 11:43:24, skipping insertion in model container [2021-12-14 23:43:24,686 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-14 23:43:24,686 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 11:43:22" (2/3) ... [2021-12-14 23:43:24,686 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@26d407f4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 14.12 11:43:24, skipping insertion in model container [2021-12-14 23:43:24,687 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-14 23:43:24,687 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.12 11:43:24" (3/3) ... [2021-12-14 23:43:24,688 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.14.cil.c [2021-12-14 23:43:24,726 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-14 23:43:24,727 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-14 23:43:24,727 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-14 23:43:24,727 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-14 23:43:24,727 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-14 23:43:24,727 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-14 23:43:24,727 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-14 23:43:24,727 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-14 23:43:24,765 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1796 states, 1795 states have (on average 1.4991643454038996) internal successors, (2691), 1795 states have internal predecessors, (2691), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:24,818 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1629 [2021-12-14 23:43:24,819 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-14 23:43:24,819 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-14 23:43:24,833 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:24,833 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:24,833 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-14 23:43:24,836 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1796 states, 1795 states have (on average 1.4991643454038996) internal successors, (2691), 1795 states have internal predecessors, (2691), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:24,848 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1629 [2021-12-14 23:43:24,848 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-14 23:43:24,848 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-14 23:43:24,852 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:24,852 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:24,859 INFO L791 eck$LassoCheckResult]: Stem: 425#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1703#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 148#L1773true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 174#L841true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1363#L848true assume !(1 == ~m_i~0);~m_st~0 := 2; 1469#L848-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 431#L853-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 308#L858-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3#L863-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 749#L868-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 843#L873-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1599#L878-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1565#L883-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 1650#L888-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 384#L893-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 773#L898-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 1774#L903-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 696#L908-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 408#L1201true assume !(0 == ~M_E~0); 1177#L1201-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1596#L1206-1true assume !(0 == ~T2_E~0); 1156#L1211-1true assume !(0 == ~T3_E~0); 1303#L1216-1true assume !(0 == ~T4_E~0); 298#L1221-1true assume !(0 == ~T5_E~0); 1244#L1226-1true assume !(0 == ~T6_E~0); 105#L1231-1true assume !(0 == ~T7_E~0); 1388#L1236-1true assume !(0 == ~T8_E~0); 1225#L1241-1true assume 0 == ~T9_E~0;~T9_E~0 := 1; 321#L1246-1true assume !(0 == ~T10_E~0); 406#L1251-1true assume !(0 == ~T11_E~0); 876#L1256-1true assume !(0 == ~T12_E~0); 9#L1261-1true assume !(0 == ~E_M~0); 1568#L1266-1true assume !(0 == ~E_1~0); 1508#L1271-1true assume !(0 == ~E_2~0); 831#L1276-1true assume !(0 == ~E_3~0); 1503#L1281-1true assume 0 == ~E_4~0;~E_4~0 := 1; 786#L1286-1true assume !(0 == ~E_5~0); 238#L1291-1true assume !(0 == ~E_6~0); 1594#L1296-1true assume !(0 == ~E_7~0); 610#L1301-1true assume !(0 == ~E_8~0); 1099#L1306-1true assume !(0 == ~E_9~0); 1072#L1311-1true assume !(0 == ~E_10~0); 213#L1316-1true assume !(0 == ~E_11~0); 1457#L1321-1true assume 0 == ~E_12~0;~E_12~0 := 1; 623#L1326-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 739#L593true assume 1 == ~m_pc~0; 863#L594true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1468#L604true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1724#L605true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 794#L1492true assume !(0 != activate_threads_~tmp~1#1); 1227#L1492-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1125#L612true assume !(1 == ~t1_pc~0); 1658#L612-2true is_transmit1_triggered_~__retres1~1#1 := 0; 1534#L623true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 364#L624true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 154#L1500true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 437#L1500-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 390#L631true assume 1 == ~t2_pc~0; 351#L632true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47#L642true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 917#L643true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 525#L1508true assume !(0 != activate_threads_~tmp___1~0#1); 1307#L1508-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 192#L650true assume !(1 == ~t3_pc~0); 960#L650-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1217#L661true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 152#L662true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26#L1516true assume !(0 != activate_threads_~tmp___2~0#1); 970#L1516-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 767#L669true assume 1 == ~t4_pc~0; 1269#L670true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1782#L680true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 383#L681true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 122#L1524true assume !(0 != activate_threads_~tmp___3~0#1); 244#L1524-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 984#L688true assume !(1 == ~t5_pc~0); 130#L688-2true is_transmit5_triggered_~__retres1~5#1 := 0; 1467#L699true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 719#L700true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 664#L1532true assume !(0 != activate_threads_~tmp___4~0#1); 779#L1532-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1293#L707true assume 1 == ~t6_pc~0; 1339#L708true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 504#L718true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1289#L719true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1369#L1540true assume !(0 != activate_threads_~tmp___5~0#1); 726#L1540-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 407#L726true assume 1 == ~t7_pc~0; 343#L727true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 911#L737true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1578#L738true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1304#L1548true assume !(0 != activate_threads_~tmp___6~0#1); 63#L1548-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 295#L745true assume !(1 == ~t8_pc~0); 1109#L745-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1191#L756true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 948#L757true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 553#L1556true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1025#L1556-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1787#L764true assume 1 == ~t9_pc~0; 404#L765true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 797#L775true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1557#L776true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1434#L1564true assume !(0 != activate_threads_~tmp___8~0#1); 72#L1564-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1390#L783true assume !(1 == ~t10_pc~0); 99#L783-2true is_transmit10_triggered_~__retres1~10#1 := 0; 194#L794true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 119#L795true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 377#L1572true assume !(0 != activate_threads_~tmp___9~0#1); 1168#L1572-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1273#L802true assume 1 == ~t11_pc~0; 1142#L803true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 45#L813true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 751#L814true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 299#L1580true assume !(0 != activate_threads_~tmp___10~0#1); 363#L1580-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 534#L821true assume !(1 == ~t12_pc~0); 602#L821-2true is_transmit12_triggered_~__retres1~12#1 := 0; 1329#L832true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 48#L833true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1243#L1588true assume !(0 != activate_threads_~tmp___11~0#1); 1250#L1588-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 804#L1339true assume !(1 == ~M_E~0); 1455#L1339-2true assume !(1 == ~T1_E~0); 1311#L1344-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1722#L1349-1true assume !(1 == ~T3_E~0); 619#L1354-1true assume !(1 == ~T4_E~0); 992#L1359-1true assume !(1 == ~T5_E~0); 1541#L1364-1true assume !(1 == ~T6_E~0); 268#L1369-1true assume !(1 == ~T7_E~0); 963#L1374-1true assume !(1 == ~T8_E~0); 621#L1379-1true assume !(1 == ~T9_E~0); 691#L1384-1true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1760#L1389-1true assume !(1 == ~T11_E~0); 1232#L1394-1true assume !(1 == ~T12_E~0); 1628#L1399-1true assume !(1 == ~E_M~0); 1437#L1404-1true assume !(1 == ~E_1~0); 323#L1409-1true assume !(1 == ~E_2~0); 1406#L1414-1true assume !(1 == ~E_3~0); 864#L1419-1true assume !(1 == ~E_4~0); 126#L1424-1true assume 1 == ~E_5~0;~E_5~0 := 2; 627#L1429-1true assume !(1 == ~E_6~0); 1264#L1434-1true assume !(1 == ~E_7~0); 1602#L1439-1true assume !(1 == ~E_8~0); 146#L1444-1true assume !(1 == ~E_9~0); 816#L1449-1true assume !(1 == ~E_10~0); 354#L1454-1true assume !(1 == ~E_11~0); 1302#L1459-1true assume !(1 == ~E_12~0); 724#L1464-1true assume { :end_inline_reset_delta_events } true; 490#L1810-2true [2021-12-14 23:43:24,861 INFO L793 eck$LassoCheckResult]: Loop: 490#L1810-2true assume !false; 1335#L1811true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1770#L1176true assume false; 158#L1191true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1414#L841-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1054#L1201-3true assume 0 == ~M_E~0;~M_E~0 := 1; 821#L1201-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1598#L1206-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 722#L1211-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 190#L1216-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 467#L1221-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1023#L1226-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 230#L1231-3true assume !(0 == ~T7_E~0); 370#L1236-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1772#L1241-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1334#L1246-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1145#L1251-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 807#L1256-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 199#L1261-3true assume 0 == ~E_M~0;~E_M~0 := 1; 518#L1266-3true assume 0 == ~E_1~0;~E_1~0 := 1; 226#L1271-3true assume !(0 == ~E_2~0); 488#L1276-3true assume 0 == ~E_3~0;~E_3~0 := 1; 451#L1281-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1201#L1286-3true assume 0 == ~E_5~0;~E_5~0 := 1; 861#L1291-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1610#L1296-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1535#L1301-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1425#L1306-3true assume 0 == ~E_9~0;~E_9~0 := 1; 530#L1311-3true assume !(0 == ~E_10~0); 159#L1316-3true assume 0 == ~E_11~0;~E_11~0 := 1; 200#L1321-3true assume 0 == ~E_12~0;~E_12~0 := 1; 601#L1326-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1210#L593-42true assume 1 == ~m_pc~0; 949#L594-14true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1757#L604-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1501#L605-14true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1720#L1492-42true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 108#L1492-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 681#L612-42true assume 1 == ~t1_pc~0; 1728#L613-14true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1582#L623-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1291#L624-14true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 153#L1500-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1754#L1500-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 577#L631-42true assume 1 == ~t2_pc~0; 41#L632-14true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 568#L642-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1748#L643-14true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 486#L1508-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1635#L1508-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 240#L650-42true assume !(1 == ~t3_pc~0); 135#L650-44true is_transmit3_triggered_~__retres1~3#1 := 0; 1716#L661-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1348#L662-14true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 350#L1516-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1375#L1516-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1268#L669-42true assume 1 == ~t4_pc~0; 537#L670-14true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 998#L680-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1496#L681-14true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 871#L1524-42true assume !(0 != activate_threads_~tmp___3~0#1); 778#L1524-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 860#L688-42true assume !(1 == ~t5_pc~0); 1101#L688-44true is_transmit5_triggered_~__retres1~5#1 := 0; 1351#L699-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 86#L700-14true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 121#L1532-42true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1431#L1532-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36#L707-42true assume !(1 == ~t6_pc~0); 1679#L707-44true is_transmit6_triggered_~__retres1~6#1 := 0; 1695#L718-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1004#L719-14true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1292#L1540-42true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 753#L1540-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1033#L726-42true assume 1 == ~t7_pc~0; 1330#L727-14true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1070#L737-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1600#L738-14true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 532#L1548-42true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 605#L1548-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1186#L745-42true assume 1 == ~t8_pc~0; 632#L746-14true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1429#L756-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 206#L757-14true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30#L1556-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 422#L1556-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 515#L764-42true assume 1 == ~t9_pc~0; 1659#L765-14true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 792#L775-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 996#L776-14true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 166#L1564-42true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 195#L1564-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 243#L783-42true assume 1 == ~t10_pc~0; 11#L784-14true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 315#L794-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 392#L795-14true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1537#L1572-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1517#L1572-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 959#L802-42true assume !(1 == ~t11_pc~0); 1075#L802-44true is_transmit11_triggered_~__retres1~11#1 := 0; 75#L813-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1188#L814-14true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 52#L1580-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1550#L1580-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 802#L821-42true assume !(1 == ~t12_pc~0); 337#L821-44true is_transmit12_triggered_~__retres1~12#1 := 0; 1007#L832-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 10#L833-14true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1159#L1588-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 560#L1588-44true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 552#L1339-3true assume !(1 == ~M_E~0); 666#L1339-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 808#L1344-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 766#L1349-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 342#L1354-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 775#L1359-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1607#L1364-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1499#L1369-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1263#L1374-3true assume !(1 == ~T8_E~0); 241#L1379-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1149#L1384-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 341#L1389-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 479#L1394-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1707#L1399-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1279#L1404-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1224#L1409-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1333#L1414-3true assume !(1 == ~E_3~0); 1356#L1419-3true assume 1 == ~E_4~0;~E_4~0 := 2; 962#L1424-3true assume 1 == ~E_5~0;~E_5~0 := 2; 176#L1429-3true assume 1 == ~E_6~0;~E_6~0 := 2; 774#L1434-3true assume 1 == ~E_7~0;~E_7~0 := 2; 925#L1439-3true assume 1 == ~E_8~0;~E_8~0 := 2; 140#L1444-3true assume 1 == ~E_9~0;~E_9~0 := 2; 204#L1449-3true assume 1 == ~E_10~0;~E_10~0 := 2; 1424#L1454-3true assume !(1 == ~E_11~0); 770#L1459-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1769#L1464-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 505#L921-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1727#L988-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 232#L989-1true start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1456#L1829true assume !(0 == start_simulation_~tmp~3#1); 88#L1829-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1040#L921-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 556#L988-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 931#L989-2true stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 787#L1784true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1543#L1791true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 493#L1792true start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 219#L1842true assume !(0 != start_simulation_~tmp___0~1#1); 490#L1810-2true [2021-12-14 23:43:24,866 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:24,866 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 1 times [2021-12-14 23:43:24,872 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:24,873 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1344112790] [2021-12-14 23:43:24,873 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:24,874 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:24,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:25,048 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:25,049 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:25,049 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1344112790] [2021-12-14 23:43:25,050 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1344112790] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:25,050 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:25,050 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:25,051 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [962006270] [2021-12-14 23:43:25,052 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:25,055 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-14 23:43:25,056 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:25,056 INFO L85 PathProgramCache]: Analyzing trace with hash -1810120649, now seen corresponding path program 1 times [2021-12-14 23:43:25,056 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:25,056 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [397978319] [2021-12-14 23:43:25,068 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:25,075 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:25,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:25,115 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:25,116 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:25,116 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [397978319] [2021-12-14 23:43:25,116 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [397978319] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:25,116 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:25,116 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-14 23:43:25,116 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [891803961] [2021-12-14 23:43:25,117 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:25,118 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-14 23:43:25,119 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-14 23:43:25,138 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-12-14 23:43:25,139 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-12-14 23:43:25,143 INFO L87 Difference]: Start difference. First operand has 1796 states, 1795 states have (on average 1.4991643454038996) internal successors, (2691), 1795 states have internal predecessors, (2691), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 74.5) internal successors, (149), 2 states have internal predecessors, (149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:25,214 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-14 23:43:25,215 INFO L93 Difference]: Finished difference Result 1794 states and 2657 transitions. [2021-12-14 23:43:25,231 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-12-14 23:43:25,235 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1794 states and 2657 transitions. [2021-12-14 23:43:25,244 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-14 23:43:25,255 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1794 states to 1788 states and 2651 transitions. [2021-12-14 23:43:25,255 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2021-12-14 23:43:25,257 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2021-12-14 23:43:25,258 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2651 transitions. [2021-12-14 23:43:25,262 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-14 23:43:25,262 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2651 transitions. [2021-12-14 23:43:25,275 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2651 transitions. [2021-12-14 23:43:25,307 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2021-12-14 23:43:25,311 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.482662192393736) internal successors, (2651), 1787 states have internal predecessors, (2651), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:25,314 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2651 transitions. [2021-12-14 23:43:25,314 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2651 transitions. [2021-12-14 23:43:25,315 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2651 transitions. [2021-12-14 23:43:25,315 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-14 23:43:25,315 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2651 transitions. [2021-12-14 23:43:25,320 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-14 23:43:25,321 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-14 23:43:25,321 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-14 23:43:25,323 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:25,323 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:25,324 INFO L791 eck$LassoCheckResult]: Stem: 4388#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 4389#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 3909#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3910#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3964#L848 assume !(1 == ~m_i~0);~m_st~0 := 2; 5303#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4397#L853-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4200#L858-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3599#L863-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3600#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4822#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4933#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5369#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5370#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4328#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4329#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4851#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4770#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4363#L1201 assume !(0 == ~M_E~0); 4364#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5210#L1206-1 assume !(0 == ~T2_E~0); 5196#L1211-1 assume !(0 == ~T3_E~0); 5197#L1216-1 assume !(0 == ~T4_E~0); 4184#L1221-1 assume !(0 == ~T5_E~0); 4185#L1226-1 assume !(0 == ~T6_E~0); 3824#L1231-1 assume !(0 == ~T7_E~0); 3825#L1236-1 assume !(0 == ~T8_E~0); 5233#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4221#L1246-1 assume !(0 == ~T10_E~0); 4222#L1251-1 assume !(0 == ~T11_E~0); 4361#L1256-1 assume !(0 == ~T12_E~0); 3610#L1261-1 assume !(0 == ~E_M~0); 3611#L1266-1 assume !(0 == ~E_1~0); 5355#L1271-1 assume !(0 == ~E_2~0); 4917#L1276-1 assume !(0 == ~E_3~0); 4918#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4865#L1286-1 assume !(0 == ~E_5~0); 4075#L1291-1 assume !(0 == ~E_6~0); 4076#L1296-1 assume !(0 == ~E_7~0); 4651#L1301-1 assume !(0 == ~E_8~0); 4652#L1306-1 assume !(0 == ~E_9~0); 5132#L1311-1 assume !(0 == ~E_10~0); 4026#L1316-1 assume !(0 == ~E_11~0); 4027#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 4669#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4670#L593 assume 1 == ~m_pc~0; 4814#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3916#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5342#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4876#L1492 assume !(0 != activate_threads_~tmp~1#1); 4877#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5168#L612 assume !(1 == ~t1_pc~0); 5169#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5298#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4298#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3920#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3921#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4340#L631 assume 1 == ~t2_pc~0; 4275#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3697#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3698#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4534#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 4535#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3993#L650 assume !(1 == ~t3_pc~0); 3994#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4694#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3917#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3650#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 3651#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4843#L669 assume 1 == ~t4_pc~0; 4844#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5202#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4327#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3859#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 3860#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4084#L688 assume !(1 == ~t5_pc~0); 3875#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3876#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4794#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4728#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 4729#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4858#L707 assume 1 == ~t6_pc~0; 5267#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4504#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4505#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5265#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 4800#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4362#L726 assume 1 == ~t7_pc~0; 4261#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3960#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5001#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5275#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 3729#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3730#L745 assume !(1 == ~t8_pc~0); 4177#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4196#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5034#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4582#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4583#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5093#L764 assume 1 == ~t9_pc~0; 4360#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4202#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4879#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5326#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 3749#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3750#L783 assume !(1 == ~t10_pc~0); 3811#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3812#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3853#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3854#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 4316#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5204#L802 assume 1 == ~t11_pc~0; 5186#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3694#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3695#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4186#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 4187#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4297#L821 assume !(1 == ~t12_pc~0); 4548#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 4644#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3699#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 3700#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 5242#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4888#L1339 assume !(1 == ~M_E~0); 4889#L1339-2 assume !(1 == ~T1_E~0); 5277#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5278#L1349-1 assume !(1 == ~T3_E~0); 4662#L1354-1 assume !(1 == ~T4_E~0); 4663#L1359-1 assume !(1 == ~T5_E~0); 5064#L1364-1 assume !(1 == ~T6_E~0); 4127#L1369-1 assume !(1 == ~T7_E~0); 4128#L1374-1 assume !(1 == ~T8_E~0); 4665#L1379-1 assume !(1 == ~T9_E~0); 4666#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4765#L1389-1 assume !(1 == ~T11_E~0); 5236#L1394-1 assume !(1 == ~T12_E~0); 5237#L1399-1 assume !(1 == ~E_M~0); 5327#L1404-1 assume !(1 == ~E_1~0); 4226#L1409-1 assume !(1 == ~E_2~0); 4227#L1414-1 assume !(1 == ~E_3~0); 4953#L1419-1 assume !(1 == ~E_4~0); 3867#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 3868#L1429-1 assume !(1 == ~E_6~0); 4678#L1434-1 assume !(1 == ~E_7~0); 5257#L1439-1 assume !(1 == ~E_8~0); 3905#L1444-1 assume !(1 == ~E_9~0); 3906#L1449-1 assume !(1 == ~E_10~0); 4280#L1454-1 assume !(1 == ~E_11~0); 4281#L1459-1 assume !(1 == ~E_12~0); 4799#L1464-1 assume { :end_inline_reset_delta_events } true; 4039#L1810-2 [2021-12-14 23:43:25,324 INFO L793 eck$LassoCheckResult]: Loop: 4039#L1810-2 assume !false; 4483#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4399#L1176 assume !false; 4961#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4531#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3737#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4287#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4288#L1003 assume !(0 != eval_~tmp~0#1); 3929#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3930#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5120#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4903#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4904#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4797#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3988#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3989#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4455#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4059#L1231-3 assume !(0 == ~T7_E~0); 4060#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4306#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5288#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5189#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4894#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4005#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4006#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4051#L1271-3 assume !(0 == ~E_2~0); 4052#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4428#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4429#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4950#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4951#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5366#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5323#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4540#L1311-3 assume !(0 == ~E_10~0); 3931#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3932#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 4007#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4643#L593-42 assume !(1 == ~m_pc~0); 4801#L593-44 is_master_triggered_~__retres1~0#1 := 0; 4802#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5351#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5352#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3830#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3831#L612-42 assume !(1 == ~t1_pc~0); 4752#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 5145#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5266#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3918#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3919#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4614#L631-42 assume 1 == ~t2_pc~0; 3683#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3684#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4603#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4479#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4480#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4080#L650-42 assume 1 == ~t3_pc~0; 3642#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3643#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5294#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4273#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4274#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5258#L669-42 assume !(1 == ~t4_pc~0); 3640#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 3641#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5069#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4959#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 4856#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4857#L688-42 assume 1 == ~t5_pc~0; 4948#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5149#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3781#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3782#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3858#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3672#L707-42 assume !(1 == ~t6_pc~0); 3673#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 5330#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5074#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5075#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4824#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4825#L726-42 assume 1 == ~t7_pc~0; 5102#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5128#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5129#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4543#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4544#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4647#L745-42 assume 1 == ~t8_pc~0; 4684#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4686#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4013#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3658#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3659#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4384#L764-42 assume 1 == ~t9_pc~0; 4520#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4873#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4874#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3944#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3945#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3998#L783-42 assume !(1 == ~t10_pc~0); 3616#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 3615#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4210#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4343#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5360#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5044#L802-42 assume 1 == ~t11_pc~0; 4145#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3756#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3757#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3707#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3708#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4884#L821-42 assume 1 == ~t12_pc~0; 4885#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4250#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3612#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 3613#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4590#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4580#L1339-3 assume !(1 == ~M_E~0); 4581#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4732#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4842#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4259#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4260#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4853#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5349#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5256#L1374-3 assume !(1 == ~T8_E~0); 4081#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4082#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4257#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4258#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4467#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5263#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5231#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5232#L1414-3 assume !(1 == ~E_3~0); 5287#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5046#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3965#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3966#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4852#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3893#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3894#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4010#L1454-3 assume !(1 == ~E_11~0); 4847#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4848#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4506#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3803#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4063#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 4064#L1829 assume !(0 == start_simulation_~tmp~3#1); 3785#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 3786#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 4586#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4587#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 4866#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4867#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4487#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 4038#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 4039#L1810-2 [2021-12-14 23:43:25,325 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:25,325 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 2 times [2021-12-14 23:43:25,325 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:25,326 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [849069445] [2021-12-14 23:43:25,326 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:25,326 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:25,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:25,403 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:25,403 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:25,403 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [849069445] [2021-12-14 23:43:25,403 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [849069445] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:25,404 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:25,404 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:25,404 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1208495359] [2021-12-14 23:43:25,404 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:25,405 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-14 23:43:25,405 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:25,405 INFO L85 PathProgramCache]: Analyzing trace with hash -830311852, now seen corresponding path program 1 times [2021-12-14 23:43:25,405 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:25,406 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1554434194] [2021-12-14 23:43:25,406 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:25,406 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:25,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:25,478 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:25,479 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:25,479 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1554434194] [2021-12-14 23:43:25,479 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1554434194] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:25,479 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:25,479 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:25,480 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2065003692] [2021-12-14 23:43:25,480 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:25,480 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-14 23:43:25,480 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-14 23:43:25,481 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-14 23:43:25,481 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-14 23:43:25,481 INFO L87 Difference]: Start difference. First operand 1788 states and 2651 transitions. cyclomatic complexity: 864 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:25,518 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-14 23:43:25,519 INFO L93 Difference]: Finished difference Result 1788 states and 2650 transitions. [2021-12-14 23:43:25,519 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-14 23:43:25,520 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2650 transitions. [2021-12-14 23:43:25,534 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-14 23:43:25,542 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2650 transitions. [2021-12-14 23:43:25,542 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2021-12-14 23:43:25,543 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2021-12-14 23:43:25,543 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2650 transitions. [2021-12-14 23:43:25,545 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-14 23:43:25,545 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2650 transitions. [2021-12-14 23:43:25,547 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2650 transitions. [2021-12-14 23:43:25,560 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2021-12-14 23:43:25,563 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4821029082774049) internal successors, (2650), 1787 states have internal predecessors, (2650), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:25,567 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2650 transitions. [2021-12-14 23:43:25,567 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2650 transitions. [2021-12-14 23:43:25,567 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2650 transitions. [2021-12-14 23:43:25,567 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-14 23:43:25,567 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2650 transitions. [2021-12-14 23:43:25,574 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-14 23:43:25,574 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-14 23:43:25,574 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-14 23:43:25,577 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:25,577 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:25,579 INFO L791 eck$LassoCheckResult]: Stem: 7971#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 7972#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 7492#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7493#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7547#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 8886#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7980#L853-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 7783#L858-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 7182#L863-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7183#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8405#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8516#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8952#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8953#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7911#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 7912#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 8434#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 8353#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7946#L1201 assume !(0 == ~M_E~0); 7947#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8793#L1206-1 assume !(0 == ~T2_E~0); 8779#L1211-1 assume !(0 == ~T3_E~0); 8780#L1216-1 assume !(0 == ~T4_E~0); 7767#L1221-1 assume !(0 == ~T5_E~0); 7768#L1226-1 assume !(0 == ~T6_E~0); 7407#L1231-1 assume !(0 == ~T7_E~0); 7408#L1236-1 assume !(0 == ~T8_E~0); 8816#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7804#L1246-1 assume !(0 == ~T10_E~0); 7805#L1251-1 assume !(0 == ~T11_E~0); 7944#L1256-1 assume !(0 == ~T12_E~0); 7193#L1261-1 assume !(0 == ~E_M~0); 7194#L1266-1 assume !(0 == ~E_1~0); 8938#L1271-1 assume !(0 == ~E_2~0); 8500#L1276-1 assume !(0 == ~E_3~0); 8501#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 8448#L1286-1 assume !(0 == ~E_5~0); 7658#L1291-1 assume !(0 == ~E_6~0); 7659#L1296-1 assume !(0 == ~E_7~0); 8234#L1301-1 assume !(0 == ~E_8~0); 8235#L1306-1 assume !(0 == ~E_9~0); 8715#L1311-1 assume !(0 == ~E_10~0); 7609#L1316-1 assume !(0 == ~E_11~0); 7610#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 8252#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8253#L593 assume 1 == ~m_pc~0; 8397#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7499#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8925#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8459#L1492 assume !(0 != activate_threads_~tmp~1#1); 8460#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8751#L612 assume !(1 == ~t1_pc~0); 8752#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8881#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7881#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7503#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7504#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7923#L631 assume 1 == ~t2_pc~0; 7858#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7280#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7281#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8117#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 8118#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7576#L650 assume !(1 == ~t3_pc~0); 7577#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8277#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7500#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7233#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 7234#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8426#L669 assume 1 == ~t4_pc~0; 8427#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8785#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7910#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7442#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 7443#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7667#L688 assume !(1 == ~t5_pc~0); 7458#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7459#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8377#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8311#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 8312#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8441#L707 assume 1 == ~t6_pc~0; 8850#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8087#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8088#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8848#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 8383#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7945#L726 assume 1 == ~t7_pc~0; 7844#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7543#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8584#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8858#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 7312#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7313#L745 assume !(1 == ~t8_pc~0); 7760#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7779#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8617#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8165#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8166#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8676#L764 assume 1 == ~t9_pc~0; 7943#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7785#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8462#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8909#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 7332#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7333#L783 assume !(1 == ~t10_pc~0); 7394#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 7395#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7436#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 7437#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 7899#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8787#L802 assume 1 == ~t11_pc~0; 8769#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7277#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7278#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7769#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 7770#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7880#L821 assume !(1 == ~t12_pc~0); 8131#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 8227#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7282#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7283#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 8825#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8471#L1339 assume !(1 == ~M_E~0); 8472#L1339-2 assume !(1 == ~T1_E~0); 8860#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8861#L1349-1 assume !(1 == ~T3_E~0); 8245#L1354-1 assume !(1 == ~T4_E~0); 8246#L1359-1 assume !(1 == ~T5_E~0); 8647#L1364-1 assume !(1 == ~T6_E~0); 7710#L1369-1 assume !(1 == ~T7_E~0); 7711#L1374-1 assume !(1 == ~T8_E~0); 8248#L1379-1 assume !(1 == ~T9_E~0); 8249#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8348#L1389-1 assume !(1 == ~T11_E~0); 8819#L1394-1 assume !(1 == ~T12_E~0); 8820#L1399-1 assume !(1 == ~E_M~0); 8910#L1404-1 assume !(1 == ~E_1~0); 7809#L1409-1 assume !(1 == ~E_2~0); 7810#L1414-1 assume !(1 == ~E_3~0); 8536#L1419-1 assume !(1 == ~E_4~0); 7450#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 7451#L1429-1 assume !(1 == ~E_6~0); 8261#L1434-1 assume !(1 == ~E_7~0); 8840#L1439-1 assume !(1 == ~E_8~0); 7488#L1444-1 assume !(1 == ~E_9~0); 7489#L1449-1 assume !(1 == ~E_10~0); 7863#L1454-1 assume !(1 == ~E_11~0); 7864#L1459-1 assume !(1 == ~E_12~0); 8382#L1464-1 assume { :end_inline_reset_delta_events } true; 7622#L1810-2 [2021-12-14 23:43:25,580 INFO L793 eck$LassoCheckResult]: Loop: 7622#L1810-2 assume !false; 8066#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7982#L1176 assume !false; 8544#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8114#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7320#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7870#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7871#L1003 assume !(0 != eval_~tmp~0#1); 7512#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7513#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8703#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8486#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8487#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8380#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7571#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7572#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8038#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7642#L1231-3 assume !(0 == ~T7_E~0); 7643#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7889#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8871#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8772#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 8477#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 7588#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7589#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7634#L1271-3 assume !(0 == ~E_2~0); 7635#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8011#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8012#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8533#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8534#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8949#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8906#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8123#L1311-3 assume !(0 == ~E_10~0); 7514#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7515#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 7590#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8226#L593-42 assume !(1 == ~m_pc~0); 8384#L593-44 is_master_triggered_~__retres1~0#1 := 0; 8385#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8934#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8935#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7413#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7414#L612-42 assume 1 == ~t1_pc~0; 8336#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8728#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8849#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7501#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7502#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8197#L631-42 assume 1 == ~t2_pc~0; 7266#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7267#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8186#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8062#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8063#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7663#L650-42 assume 1 == ~t3_pc~0; 7225#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7226#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8877#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7856#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7857#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8841#L669-42 assume !(1 == ~t4_pc~0); 7223#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 7224#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8652#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8542#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 8439#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8440#L688-42 assume 1 == ~t5_pc~0; 8531#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8732#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7364#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7365#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7441#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7255#L707-42 assume !(1 == ~t6_pc~0); 7256#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 8913#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8657#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8658#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8407#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8408#L726-42 assume 1 == ~t7_pc~0; 8685#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8711#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8712#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8126#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8127#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8230#L745-42 assume 1 == ~t8_pc~0; 8267#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8269#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7596#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7241#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7242#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7967#L764-42 assume 1 == ~t9_pc~0; 8103#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8456#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8457#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7527#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7528#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7581#L783-42 assume 1 == ~t10_pc~0; 7197#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7198#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7793#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 7926#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8943#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8627#L802-42 assume 1 == ~t11_pc~0; 7728#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7339#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7340#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7290#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 7291#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8467#L821-42 assume 1 == ~t12_pc~0; 8468#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 7833#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7195#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7196#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 8173#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8163#L1339-3 assume !(1 == ~M_E~0); 8164#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8315#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8425#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7842#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7843#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8436#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8932#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8839#L1374-3 assume !(1 == ~T8_E~0); 7664#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7665#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 7840#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 7841#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8050#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8846#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8814#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8815#L1414-3 assume !(1 == ~E_3~0); 8870#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8629#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7548#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7549#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8435#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7476#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 7477#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 7593#L1454-3 assume !(1 == ~E_11~0); 8430#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 8431#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8089#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7386#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7646#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 7647#L1829 assume !(0 == start_simulation_~tmp~3#1); 7368#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 7369#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 8169#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 8170#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 8449#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8450#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8070#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 7621#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 7622#L1810-2 [2021-12-14 23:43:25,582 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:25,582 INFO L85 PathProgramCache]: Analyzing trace with hash -494851220, now seen corresponding path program 1 times [2021-12-14 23:43:25,582 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:25,582 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1859302961] [2021-12-14 23:43:25,582 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:25,583 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:25,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:25,638 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:25,638 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:25,639 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1859302961] [2021-12-14 23:43:25,639 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1859302961] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:25,639 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:25,639 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:25,639 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [330481908] [2021-12-14 23:43:25,639 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:25,640 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-14 23:43:25,640 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:25,640 INFO L85 PathProgramCache]: Analyzing trace with hash -1795658606, now seen corresponding path program 1 times [2021-12-14 23:43:25,641 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:25,641 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [235291284] [2021-12-14 23:43:25,641 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:25,641 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:25,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:25,689 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:25,689 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:25,689 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [235291284] [2021-12-14 23:43:25,690 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [235291284] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:25,690 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:25,690 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:25,690 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [198371768] [2021-12-14 23:43:25,690 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:25,691 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-14 23:43:25,691 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-14 23:43:25,691 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-14 23:43:25,691 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-14 23:43:25,692 INFO L87 Difference]: Start difference. First operand 1788 states and 2650 transitions. cyclomatic complexity: 863 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:25,713 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-14 23:43:25,713 INFO L93 Difference]: Finished difference Result 1788 states and 2649 transitions. [2021-12-14 23:43:25,713 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-14 23:43:25,714 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2649 transitions. [2021-12-14 23:43:25,746 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-14 23:43:25,752 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2649 transitions. [2021-12-14 23:43:25,752 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2021-12-14 23:43:25,753 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2021-12-14 23:43:25,754 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2649 transitions. [2021-12-14 23:43:25,755 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-14 23:43:25,755 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2649 transitions. [2021-12-14 23:43:25,757 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2649 transitions. [2021-12-14 23:43:25,770 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2021-12-14 23:43:25,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4815436241610738) internal successors, (2649), 1787 states have internal predecessors, (2649), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:25,776 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2649 transitions. [2021-12-14 23:43:25,776 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2649 transitions. [2021-12-14 23:43:25,776 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2649 transitions. [2021-12-14 23:43:25,776 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-14 23:43:25,776 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2649 transitions. [2021-12-14 23:43:25,782 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-14 23:43:25,782 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-14 23:43:25,782 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-14 23:43:25,784 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:25,784 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:25,784 INFO L791 eck$LassoCheckResult]: Stem: 11554#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 11555#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 11075#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11076#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11130#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 12469#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11563#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11366#L858-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 10765#L863-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 10766#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11988#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12099#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12535#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12536#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11494#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 11495#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12017#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 11936#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11529#L1201 assume !(0 == ~M_E~0); 11530#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12376#L1206-1 assume !(0 == ~T2_E~0); 12362#L1211-1 assume !(0 == ~T3_E~0); 12363#L1216-1 assume !(0 == ~T4_E~0); 11350#L1221-1 assume !(0 == ~T5_E~0); 11351#L1226-1 assume !(0 == ~T6_E~0); 10990#L1231-1 assume !(0 == ~T7_E~0); 10991#L1236-1 assume !(0 == ~T8_E~0); 12399#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11387#L1246-1 assume !(0 == ~T10_E~0); 11388#L1251-1 assume !(0 == ~T11_E~0); 11527#L1256-1 assume !(0 == ~T12_E~0); 10776#L1261-1 assume !(0 == ~E_M~0); 10777#L1266-1 assume !(0 == ~E_1~0); 12521#L1271-1 assume !(0 == ~E_2~0); 12083#L1276-1 assume !(0 == ~E_3~0); 12084#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 12031#L1286-1 assume !(0 == ~E_5~0); 11241#L1291-1 assume !(0 == ~E_6~0); 11242#L1296-1 assume !(0 == ~E_7~0); 11817#L1301-1 assume !(0 == ~E_8~0); 11818#L1306-1 assume !(0 == ~E_9~0); 12298#L1311-1 assume !(0 == ~E_10~0); 11192#L1316-1 assume !(0 == ~E_11~0); 11193#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 11835#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11836#L593 assume 1 == ~m_pc~0; 11980#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11082#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12508#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12042#L1492 assume !(0 != activate_threads_~tmp~1#1); 12043#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12334#L612 assume !(1 == ~t1_pc~0); 12335#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12464#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11464#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11086#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11087#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11506#L631 assume 1 == ~t2_pc~0; 11441#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10863#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10864#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11700#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 11701#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11159#L650 assume !(1 == ~t3_pc~0); 11160#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 11860#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11083#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10816#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 10817#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12009#L669 assume 1 == ~t4_pc~0; 12010#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12368#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11493#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11025#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 11026#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11250#L688 assume !(1 == ~t5_pc~0); 11041#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11042#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11960#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11894#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 11895#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12024#L707 assume 1 == ~t6_pc~0; 12433#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11670#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11671#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12431#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 11966#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11528#L726 assume 1 == ~t7_pc~0; 11427#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11126#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12167#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12441#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 10895#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10896#L745 assume !(1 == ~t8_pc~0); 11343#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 11362#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12200#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11748#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11749#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12259#L764 assume 1 == ~t9_pc~0; 11526#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11368#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12045#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12492#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 10915#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10916#L783 assume !(1 == ~t10_pc~0); 10977#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 10978#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11019#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 11020#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 11482#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12370#L802 assume 1 == ~t11_pc~0; 12352#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10860#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10861#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 11352#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 11353#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 11463#L821 assume !(1 == ~t12_pc~0); 11714#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 11810#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 10865#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 10866#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 12408#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12054#L1339 assume !(1 == ~M_E~0); 12055#L1339-2 assume !(1 == ~T1_E~0); 12443#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12444#L1349-1 assume !(1 == ~T3_E~0); 11828#L1354-1 assume !(1 == ~T4_E~0); 11829#L1359-1 assume !(1 == ~T5_E~0); 12230#L1364-1 assume !(1 == ~T6_E~0); 11293#L1369-1 assume !(1 == ~T7_E~0); 11294#L1374-1 assume !(1 == ~T8_E~0); 11831#L1379-1 assume !(1 == ~T9_E~0); 11832#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11931#L1389-1 assume !(1 == ~T11_E~0); 12402#L1394-1 assume !(1 == ~T12_E~0); 12403#L1399-1 assume !(1 == ~E_M~0); 12493#L1404-1 assume !(1 == ~E_1~0); 11392#L1409-1 assume !(1 == ~E_2~0); 11393#L1414-1 assume !(1 == ~E_3~0); 12119#L1419-1 assume !(1 == ~E_4~0); 11033#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 11034#L1429-1 assume !(1 == ~E_6~0); 11844#L1434-1 assume !(1 == ~E_7~0); 12423#L1439-1 assume !(1 == ~E_8~0); 11071#L1444-1 assume !(1 == ~E_9~0); 11072#L1449-1 assume !(1 == ~E_10~0); 11446#L1454-1 assume !(1 == ~E_11~0); 11447#L1459-1 assume !(1 == ~E_12~0); 11965#L1464-1 assume { :end_inline_reset_delta_events } true; 11205#L1810-2 [2021-12-14 23:43:25,785 INFO L793 eck$LassoCheckResult]: Loop: 11205#L1810-2 assume !false; 11649#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11565#L1176 assume !false; 12127#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11697#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10903#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11453#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 11454#L1003 assume !(0 != eval_~tmp~0#1); 11095#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11096#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12286#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12069#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12070#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11963#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11154#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11155#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11621#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11225#L1231-3 assume !(0 == ~T7_E~0); 11226#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11472#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 12454#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12355#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 12060#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 11171#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11172#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11217#L1271-3 assume !(0 == ~E_2~0); 11218#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11594#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11595#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12116#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12117#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12532#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12489#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11706#L1311-3 assume !(0 == ~E_10~0); 11097#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 11098#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 11173#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11809#L593-42 assume 1 == ~m_pc~0; 12202#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11968#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12517#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12518#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10996#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10997#L612-42 assume !(1 == ~t1_pc~0); 11918#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 12311#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12432#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11084#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11085#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11780#L631-42 assume 1 == ~t2_pc~0; 10849#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10850#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11769#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11645#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11646#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11246#L650-42 assume 1 == ~t3_pc~0; 10808#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10809#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12460#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11439#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11440#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12424#L669-42 assume !(1 == ~t4_pc~0); 10806#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 10807#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12235#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12125#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 12022#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12023#L688-42 assume 1 == ~t5_pc~0; 12114#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12315#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10947#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10948#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11024#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10838#L707-42 assume !(1 == ~t6_pc~0); 10839#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 12496#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12240#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12241#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11990#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11991#L726-42 assume 1 == ~t7_pc~0; 12268#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12294#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12295#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11709#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11710#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11813#L745-42 assume 1 == ~t8_pc~0; 11850#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11852#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11179#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10824#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 10825#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11550#L764-42 assume 1 == ~t9_pc~0; 11686#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12039#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12040#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 11110#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11111#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11164#L783-42 assume 1 == ~t10_pc~0; 10780#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 10781#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11376#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 11509#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12526#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12210#L802-42 assume !(1 == ~t11_pc~0); 11312#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 10922#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10923#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 10873#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 10874#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12050#L821-42 assume 1 == ~t12_pc~0; 12051#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 11416#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 10778#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 10779#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 11756#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11746#L1339-3 assume !(1 == ~M_E~0); 11747#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11898#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12008#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11425#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11426#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12019#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12515#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12422#L1374-3 assume !(1 == ~T8_E~0); 11247#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11248#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11423#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 11424#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 11633#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12429#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12397#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12398#L1414-3 assume !(1 == ~E_3~0); 12453#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12212#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11131#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11132#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12018#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11059#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 11060#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 11176#L1454-3 assume !(1 == ~E_11~0); 12013#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12014#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11672#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10969#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11229#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 11230#L1829 assume !(0 == start_simulation_~tmp~3#1); 10951#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 10952#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 11752#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11753#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 12032#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12033#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11653#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 11204#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 11205#L1810-2 [2021-12-14 23:43:25,785 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:25,785 INFO L85 PathProgramCache]: Analyzing trace with hash -833138770, now seen corresponding path program 1 times [2021-12-14 23:43:25,786 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:25,786 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1062056734] [2021-12-14 23:43:25,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:25,786 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:25,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:25,810 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:25,811 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:25,811 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1062056734] [2021-12-14 23:43:25,811 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1062056734] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:25,811 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:25,811 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:25,812 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1458114345] [2021-12-14 23:43:25,812 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:25,812 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-14 23:43:25,812 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:25,812 INFO L85 PathProgramCache]: Analyzing trace with hash 1706034771, now seen corresponding path program 1 times [2021-12-14 23:43:25,813 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:25,813 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [221375251] [2021-12-14 23:43:25,813 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:25,813 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:25,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:25,848 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:25,849 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:25,849 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [221375251] [2021-12-14 23:43:25,849 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [221375251] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:25,849 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:25,849 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:25,850 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [906881750] [2021-12-14 23:43:25,850 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:25,850 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-14 23:43:25,850 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-14 23:43:25,851 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-14 23:43:25,851 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-14 23:43:25,851 INFO L87 Difference]: Start difference. First operand 1788 states and 2649 transitions. cyclomatic complexity: 862 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:25,870 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-14 23:43:25,870 INFO L93 Difference]: Finished difference Result 1788 states and 2648 transitions. [2021-12-14 23:43:25,871 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-14 23:43:25,871 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2648 transitions. [2021-12-14 23:43:25,879 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-14 23:43:25,885 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2648 transitions. [2021-12-14 23:43:25,886 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2021-12-14 23:43:25,886 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2021-12-14 23:43:25,887 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2648 transitions. [2021-12-14 23:43:25,888 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-14 23:43:25,889 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2648 transitions. [2021-12-14 23:43:25,890 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2648 transitions. [2021-12-14 23:43:25,903 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2021-12-14 23:43:25,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4809843400447427) internal successors, (2648), 1787 states have internal predecessors, (2648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:25,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2648 transitions. [2021-12-14 23:43:25,909 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2648 transitions. [2021-12-14 23:43:25,909 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2648 transitions. [2021-12-14 23:43:25,909 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-14 23:43:25,909 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2648 transitions. [2021-12-14 23:43:25,915 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-14 23:43:25,916 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-14 23:43:25,916 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-14 23:43:25,917 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:25,917 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:25,918 INFO L791 eck$LassoCheckResult]: Stem: 15137#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 15138#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 14658#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14659#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14713#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 16052#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15146#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14949#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14348#L863-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 14349#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 15571#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 15682#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 16118#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16119#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15077#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 15078#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 15600#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 15519#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15112#L1201 assume !(0 == ~M_E~0); 15113#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15959#L1206-1 assume !(0 == ~T2_E~0); 15945#L1211-1 assume !(0 == ~T3_E~0); 15946#L1216-1 assume !(0 == ~T4_E~0); 14933#L1221-1 assume !(0 == ~T5_E~0); 14934#L1226-1 assume !(0 == ~T6_E~0); 14573#L1231-1 assume !(0 == ~T7_E~0); 14574#L1236-1 assume !(0 == ~T8_E~0); 15982#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14970#L1246-1 assume !(0 == ~T10_E~0); 14971#L1251-1 assume !(0 == ~T11_E~0); 15110#L1256-1 assume !(0 == ~T12_E~0); 14359#L1261-1 assume !(0 == ~E_M~0); 14360#L1266-1 assume !(0 == ~E_1~0); 16104#L1271-1 assume !(0 == ~E_2~0); 15666#L1276-1 assume !(0 == ~E_3~0); 15667#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 15614#L1286-1 assume !(0 == ~E_5~0); 14824#L1291-1 assume !(0 == ~E_6~0); 14825#L1296-1 assume !(0 == ~E_7~0); 15400#L1301-1 assume !(0 == ~E_8~0); 15401#L1306-1 assume !(0 == ~E_9~0); 15881#L1311-1 assume !(0 == ~E_10~0); 14775#L1316-1 assume !(0 == ~E_11~0); 14776#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 15418#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15419#L593 assume 1 == ~m_pc~0; 15563#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14665#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16091#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15625#L1492 assume !(0 != activate_threads_~tmp~1#1); 15626#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15917#L612 assume !(1 == ~t1_pc~0); 15918#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16047#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15047#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14669#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14670#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15089#L631 assume 1 == ~t2_pc~0; 15024#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14446#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14447#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15283#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 15284#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14742#L650 assume !(1 == ~t3_pc~0); 14743#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15443#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14666#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14399#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 14400#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15592#L669 assume 1 == ~t4_pc~0; 15593#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15951#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15076#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14608#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 14609#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14833#L688 assume !(1 == ~t5_pc~0); 14624#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 14625#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15543#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15477#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 15478#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15607#L707 assume 1 == ~t6_pc~0; 16016#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15253#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15254#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16014#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 15549#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15111#L726 assume 1 == ~t7_pc~0; 15010#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14709#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15750#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16024#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 14478#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14479#L745 assume !(1 == ~t8_pc~0); 14926#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14945#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15783#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15331#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15332#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15842#L764 assume 1 == ~t9_pc~0; 15109#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14951#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15628#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16075#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 14498#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14499#L783 assume !(1 == ~t10_pc~0); 14560#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 14561#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14602#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 14603#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 15065#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15953#L802 assume 1 == ~t11_pc~0; 15935#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14443#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14444#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 14935#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 14936#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15046#L821 assume !(1 == ~t12_pc~0); 15297#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 15393#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 14448#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 14449#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 15991#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15637#L1339 assume !(1 == ~M_E~0); 15638#L1339-2 assume !(1 == ~T1_E~0); 16026#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16027#L1349-1 assume !(1 == ~T3_E~0); 15411#L1354-1 assume !(1 == ~T4_E~0); 15412#L1359-1 assume !(1 == ~T5_E~0); 15813#L1364-1 assume !(1 == ~T6_E~0); 14876#L1369-1 assume !(1 == ~T7_E~0); 14877#L1374-1 assume !(1 == ~T8_E~0); 15414#L1379-1 assume !(1 == ~T9_E~0); 15415#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 15514#L1389-1 assume !(1 == ~T11_E~0); 15985#L1394-1 assume !(1 == ~T12_E~0); 15986#L1399-1 assume !(1 == ~E_M~0); 16076#L1404-1 assume !(1 == ~E_1~0); 14975#L1409-1 assume !(1 == ~E_2~0); 14976#L1414-1 assume !(1 == ~E_3~0); 15702#L1419-1 assume !(1 == ~E_4~0); 14616#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 14617#L1429-1 assume !(1 == ~E_6~0); 15427#L1434-1 assume !(1 == ~E_7~0); 16006#L1439-1 assume !(1 == ~E_8~0); 14654#L1444-1 assume !(1 == ~E_9~0); 14655#L1449-1 assume !(1 == ~E_10~0); 15029#L1454-1 assume !(1 == ~E_11~0); 15030#L1459-1 assume !(1 == ~E_12~0); 15548#L1464-1 assume { :end_inline_reset_delta_events } true; 14788#L1810-2 [2021-12-14 23:43:25,918 INFO L793 eck$LassoCheckResult]: Loop: 14788#L1810-2 assume !false; 15232#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15148#L1176 assume !false; 15710#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15280#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14486#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 15036#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 15037#L1003 assume !(0 != eval_~tmp~0#1); 14678#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14679#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15869#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15652#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15653#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15546#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14737#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14738#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15204#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14808#L1231-3 assume !(0 == ~T7_E~0); 14809#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15055#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16037#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15938#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 15643#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 14754#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14755#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14800#L1271-3 assume !(0 == ~E_2~0); 14801#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15177#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15178#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15699#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15700#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 16115#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16072#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15289#L1311-3 assume !(0 == ~E_10~0); 14680#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14681#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 14756#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15392#L593-42 assume 1 == ~m_pc~0; 15785#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15551#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16100#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16101#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14579#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14580#L612-42 assume !(1 == ~t1_pc~0); 15501#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 15894#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16015#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14667#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14668#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15363#L631-42 assume 1 == ~t2_pc~0; 14432#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14433#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15352#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15228#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15229#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14829#L650-42 assume 1 == ~t3_pc~0; 14391#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14392#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16043#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15022#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15023#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16007#L669-42 assume !(1 == ~t4_pc~0); 14389#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 14390#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15818#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15708#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 15605#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15606#L688-42 assume 1 == ~t5_pc~0; 15697#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15898#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14530#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14531#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14607#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14421#L707-42 assume !(1 == ~t6_pc~0); 14422#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 16079#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15823#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15824#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15573#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15574#L726-42 assume 1 == ~t7_pc~0; 15851#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15877#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15878#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15292#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15293#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15396#L745-42 assume 1 == ~t8_pc~0; 15433#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15435#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14762#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14407#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14408#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15133#L764-42 assume 1 == ~t9_pc~0; 15269#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15622#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15623#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14693#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 14694#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14747#L783-42 assume 1 == ~t10_pc~0; 14363#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 14364#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14959#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 15092#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16109#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15793#L802-42 assume 1 == ~t11_pc~0; 14894#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14505#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14506#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 14456#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14457#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15633#L821-42 assume 1 == ~t12_pc~0; 15634#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 14999#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 14361#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 14362#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 15339#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15329#L1339-3 assume !(1 == ~M_E~0); 15330#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15481#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15591#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15008#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15009#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15602#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16098#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16005#L1374-3 assume !(1 == ~T8_E~0); 14830#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14831#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 15006#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15007#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 15216#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16012#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15980#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15981#L1414-3 assume !(1 == ~E_3~0); 16036#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15795#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14714#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14715#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15601#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14642#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 14643#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 14759#L1454-3 assume !(1 == ~E_11~0); 15596#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 15597#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15255#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14552#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14812#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 14813#L1829 assume !(0 == start_simulation_~tmp~3#1); 14534#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 14535#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 15335#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 15336#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 15615#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15616#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15236#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 14787#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 14788#L1810-2 [2021-12-14 23:43:25,918 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:25,919 INFO L85 PathProgramCache]: Analyzing trace with hash -1259693268, now seen corresponding path program 1 times [2021-12-14 23:43:25,919 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:25,919 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1328505707] [2021-12-14 23:43:25,919 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:25,919 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:25,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:25,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:25,943 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:25,944 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1328505707] [2021-12-14 23:43:25,944 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1328505707] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:25,944 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:25,945 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:25,945 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [416218932] [2021-12-14 23:43:25,945 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:25,945 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-14 23:43:25,946 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:25,946 INFO L85 PathProgramCache]: Analyzing trace with hash -488091310, now seen corresponding path program 1 times [2021-12-14 23:43:25,946 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:25,946 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1230930540] [2021-12-14 23:43:25,946 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:25,947 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:25,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:25,996 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:25,997 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:25,997 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1230930540] [2021-12-14 23:43:25,997 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1230930540] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:25,997 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:25,997 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:25,998 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1081563030] [2021-12-14 23:43:25,998 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:25,998 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-14 23:43:25,998 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-14 23:43:25,999 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-14 23:43:25,999 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-14 23:43:25,999 INFO L87 Difference]: Start difference. First operand 1788 states and 2648 transitions. cyclomatic complexity: 861 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:26,021 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-14 23:43:26,021 INFO L93 Difference]: Finished difference Result 1788 states and 2647 transitions. [2021-12-14 23:43:26,021 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-14 23:43:26,024 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2647 transitions. [2021-12-14 23:43:26,034 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-14 23:43:26,043 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2647 transitions. [2021-12-14 23:43:26,044 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2021-12-14 23:43:26,045 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2021-12-14 23:43:26,045 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2647 transitions. [2021-12-14 23:43:26,048 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-14 23:43:26,048 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2647 transitions. [2021-12-14 23:43:26,049 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2647 transitions. [2021-12-14 23:43:26,088 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2021-12-14 23:43:26,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4804250559284116) internal successors, (2647), 1787 states have internal predecessors, (2647), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:26,093 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2647 transitions. [2021-12-14 23:43:26,093 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2647 transitions. [2021-12-14 23:43:26,093 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2647 transitions. [2021-12-14 23:43:26,093 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-14 23:43:26,093 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2647 transitions. [2021-12-14 23:43:26,098 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-14 23:43:26,098 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-14 23:43:26,098 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-14 23:43:26,099 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:26,099 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:26,100 INFO L791 eck$LassoCheckResult]: Stem: 18720#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 18721#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 18241#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18242#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18296#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 19635#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18729#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18532#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17931#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17932#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 19154#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 19267#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 19701#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19702#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18660#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18661#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 19183#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 19102#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18695#L1201 assume !(0 == ~M_E~0); 18696#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19542#L1206-1 assume !(0 == ~T2_E~0); 19528#L1211-1 assume !(0 == ~T3_E~0); 19529#L1216-1 assume !(0 == ~T4_E~0); 18517#L1221-1 assume !(0 == ~T5_E~0); 18518#L1226-1 assume !(0 == ~T6_E~0); 18156#L1231-1 assume !(0 == ~T7_E~0); 18157#L1236-1 assume !(0 == ~T8_E~0); 19565#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18556#L1246-1 assume !(0 == ~T10_E~0); 18557#L1251-1 assume !(0 == ~T11_E~0); 18693#L1256-1 assume !(0 == ~T12_E~0); 17944#L1261-1 assume !(0 == ~E_M~0); 17945#L1266-1 assume !(0 == ~E_1~0); 19687#L1271-1 assume !(0 == ~E_2~0); 19249#L1276-1 assume !(0 == ~E_3~0); 19250#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 19197#L1286-1 assume !(0 == ~E_5~0); 18407#L1291-1 assume !(0 == ~E_6~0); 18408#L1296-1 assume !(0 == ~E_7~0); 18983#L1301-1 assume !(0 == ~E_8~0); 18984#L1306-1 assume !(0 == ~E_9~0); 19464#L1311-1 assume !(0 == ~E_10~0); 18358#L1316-1 assume !(0 == ~E_11~0); 18359#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 19001#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19002#L593 assume 1 == ~m_pc~0; 19146#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18248#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19674#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19208#L1492 assume !(0 != activate_threads_~tmp~1#1); 19209#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19500#L612 assume !(1 == ~t1_pc~0); 19501#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19630#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18630#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18252#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18253#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18672#L631 assume 1 == ~t2_pc~0; 18607#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18029#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18030#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18866#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 18867#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18325#L650 assume !(1 == ~t3_pc~0); 18326#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19026#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18249#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17982#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 17983#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19175#L669 assume 1 == ~t4_pc~0; 19176#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19534#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18659#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18191#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 18192#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18416#L688 assume !(1 == ~t5_pc~0); 18207#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 18208#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19126#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19062#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 19063#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19193#L707 assume 1 == ~t6_pc~0; 19599#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18836#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18837#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19597#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 19134#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18694#L726 assume 1 == ~t7_pc~0; 18595#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18292#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19333#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19608#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 18061#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18062#L745 assume !(1 == ~t8_pc~0); 18509#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 18528#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19366#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18914#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18915#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19425#L764 assume 1 == ~t9_pc~0; 18692#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18534#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19211#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19658#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 18081#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18082#L783 assume !(1 == ~t10_pc~0); 18143#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 18144#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18185#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18186#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 18653#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19536#L802 assume 1 == ~t11_pc~0; 19518#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 18026#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18027#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 18519#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 18520#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 18629#L821 assume !(1 == ~t12_pc~0); 18880#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 18976#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 18033#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 18034#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 19574#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19220#L1339 assume !(1 == ~M_E~0); 19221#L1339-2 assume !(1 == ~T1_E~0); 19609#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19610#L1349-1 assume !(1 == ~T3_E~0); 18995#L1354-1 assume !(1 == ~T4_E~0); 18996#L1359-1 assume !(1 == ~T5_E~0); 19398#L1364-1 assume !(1 == ~T6_E~0); 18459#L1369-1 assume !(1 == ~T7_E~0); 18460#L1374-1 assume !(1 == ~T8_E~0); 18999#L1379-1 assume !(1 == ~T9_E~0); 19000#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19097#L1389-1 assume !(1 == ~T11_E~0); 19568#L1394-1 assume !(1 == ~T12_E~0); 19569#L1399-1 assume !(1 == ~E_M~0); 19659#L1404-1 assume !(1 == ~E_1~0); 18560#L1409-1 assume !(1 == ~E_2~0); 18561#L1414-1 assume !(1 == ~E_3~0); 19285#L1419-1 assume !(1 == ~E_4~0); 18199#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 18200#L1429-1 assume !(1 == ~E_6~0); 19010#L1434-1 assume !(1 == ~E_7~0); 19589#L1439-1 assume !(1 == ~E_8~0); 18237#L1444-1 assume !(1 == ~E_9~0); 18238#L1449-1 assume !(1 == ~E_10~0); 18612#L1454-1 assume !(1 == ~E_11~0); 18613#L1459-1 assume !(1 == ~E_12~0); 19131#L1464-1 assume { :end_inline_reset_delta_events } true; 18371#L1810-2 [2021-12-14 23:43:26,100 INFO L793 eck$LassoCheckResult]: Loop: 18371#L1810-2 assume !false; 18815#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18731#L1176 assume !false; 19293#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18865#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18069#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18619#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 18620#L1003 assume !(0 != eval_~tmp~0#1); 18263#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18264#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19452#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19235#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19236#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19130#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18320#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18321#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18787#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18391#L1231-3 assume !(0 == ~T7_E~0); 18392#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18638#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19620#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19521#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 19226#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 18337#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 18338#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18383#L1271-3 assume !(0 == ~E_2~0); 18384#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18760#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18761#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19282#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19283#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19698#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19655#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18872#L1311-3 assume !(0 == ~E_10~0); 18261#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 18262#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 18339#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18975#L593-42 assume 1 == ~m_pc~0; 19368#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19133#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19682#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19683#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18162#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18163#L612-42 assume !(1 == ~t1_pc~0); 19084#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 19477#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19598#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18250#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18251#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18946#L631-42 assume !(1 == ~t2_pc~0); 18017#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 18016#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18935#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18811#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18812#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18412#L650-42 assume 1 == ~t3_pc~0; 17974#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17975#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19626#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18605#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18606#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19590#L669-42 assume !(1 == ~t4_pc~0); 17972#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 17973#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19401#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19291#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 19188#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19189#L688-42 assume 1 == ~t5_pc~0; 19280#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19481#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18113#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18114#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18187#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18004#L707-42 assume !(1 == ~t6_pc~0); 18005#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 19662#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19406#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19407#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19156#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19157#L726-42 assume 1 == ~t7_pc~0; 19434#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19460#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19461#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18875#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18876#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18979#L745-42 assume 1 == ~t8_pc~0; 19016#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19018#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18345#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17990#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17991#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18716#L764-42 assume 1 == ~t9_pc~0; 18852#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19205#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19206#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18276#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18277#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18330#L783-42 assume 1 == ~t10_pc~0; 17946#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 17947#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18542#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18675#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19692#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19376#L802-42 assume 1 == ~t11_pc~0; 18477#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 18088#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18089#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 18039#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18040#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 19216#L821-42 assume 1 == ~t12_pc~0; 19217#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 18582#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 17942#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 17943#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 18922#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18912#L1339-3 assume !(1 == ~M_E~0); 18913#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19064#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19174#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18591#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18592#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19185#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19681#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19588#L1374-3 assume !(1 == ~T8_E~0); 18413#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18414#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 18589#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18590#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 18799#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19595#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19563#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19564#L1414-3 assume !(1 == ~E_3~0); 19619#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19378#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18297#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18298#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19184#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18225#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 18226#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 18342#L1454-3 assume !(1 == ~E_11~0); 19179#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 19180#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18838#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18135#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18395#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 18396#L1829 assume !(0 == start_simulation_~tmp~3#1); 18117#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18118#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18918#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18919#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 19198#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19199#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18819#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 18370#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 18371#L1810-2 [2021-12-14 23:43:26,100 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:26,101 INFO L85 PathProgramCache]: Analyzing trace with hash -719263762, now seen corresponding path program 1 times [2021-12-14 23:43:26,101 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:26,101 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [227465729] [2021-12-14 23:43:26,101 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:26,101 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:26,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:26,120 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:26,121 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:26,121 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [227465729] [2021-12-14 23:43:26,121 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [227465729] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:26,121 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:26,121 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:26,121 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1453322814] [2021-12-14 23:43:26,122 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:26,122 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-14 23:43:26,122 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:26,122 INFO L85 PathProgramCache]: Analyzing trace with hash -200631405, now seen corresponding path program 1 times [2021-12-14 23:43:26,123 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:26,123 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1219077933] [2021-12-14 23:43:26,123 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:26,123 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:26,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:26,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:26,147 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:26,147 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1219077933] [2021-12-14 23:43:26,147 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1219077933] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:26,147 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:26,148 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:26,148 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2141737973] [2021-12-14 23:43:26,148 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:26,148 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-14 23:43:26,148 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-14 23:43:26,149 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-14 23:43:26,149 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-14 23:43:26,149 INFO L87 Difference]: Start difference. First operand 1788 states and 2647 transitions. cyclomatic complexity: 860 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:26,175 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-14 23:43:26,175 INFO L93 Difference]: Finished difference Result 1788 states and 2646 transitions. [2021-12-14 23:43:26,175 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-14 23:43:26,176 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2646 transitions. [2021-12-14 23:43:26,182 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-14 23:43:26,188 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2646 transitions. [2021-12-14 23:43:26,188 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2021-12-14 23:43:26,189 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2021-12-14 23:43:26,189 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2646 transitions. [2021-12-14 23:43:26,191 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-14 23:43:26,191 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2646 transitions. [2021-12-14 23:43:26,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2646 transitions. [2021-12-14 23:43:26,204 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2021-12-14 23:43:26,206 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4798657718120805) internal successors, (2646), 1787 states have internal predecessors, (2646), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:26,209 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2646 transitions. [2021-12-14 23:43:26,209 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2646 transitions. [2021-12-14 23:43:26,210 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2646 transitions. [2021-12-14 23:43:26,210 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-14 23:43:26,210 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2646 transitions. [2021-12-14 23:43:26,214 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-14 23:43:26,214 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-14 23:43:26,214 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-14 23:43:26,216 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:26,216 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:26,216 INFO L791 eck$LassoCheckResult]: Stem: 22303#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 22304#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 21824#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21825#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21879#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 23218#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22312#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22115#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21514#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21515#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22737#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 22850#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23284#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 23285#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22243#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22244#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 22766#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 22685#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22278#L1201 assume !(0 == ~M_E~0); 22279#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23125#L1206-1 assume !(0 == ~T2_E~0); 23111#L1211-1 assume !(0 == ~T3_E~0); 23112#L1216-1 assume !(0 == ~T4_E~0); 22100#L1221-1 assume !(0 == ~T5_E~0); 22101#L1226-1 assume !(0 == ~T6_E~0); 21739#L1231-1 assume !(0 == ~T7_E~0); 21740#L1236-1 assume !(0 == ~T8_E~0); 23148#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22139#L1246-1 assume !(0 == ~T10_E~0); 22140#L1251-1 assume !(0 == ~T11_E~0); 22276#L1256-1 assume !(0 == ~T12_E~0); 21527#L1261-1 assume !(0 == ~E_M~0); 21528#L1266-1 assume !(0 == ~E_1~0); 23270#L1271-1 assume !(0 == ~E_2~0); 22832#L1276-1 assume !(0 == ~E_3~0); 22833#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 22780#L1286-1 assume !(0 == ~E_5~0); 21990#L1291-1 assume !(0 == ~E_6~0); 21991#L1296-1 assume !(0 == ~E_7~0); 22566#L1301-1 assume !(0 == ~E_8~0); 22567#L1306-1 assume !(0 == ~E_9~0); 23047#L1311-1 assume !(0 == ~E_10~0); 21941#L1316-1 assume !(0 == ~E_11~0); 21942#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 22584#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22585#L593 assume 1 == ~m_pc~0; 22729#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 21831#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23257#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22791#L1492 assume !(0 != activate_threads_~tmp~1#1); 22792#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23083#L612 assume !(1 == ~t1_pc~0); 23084#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23213#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22213#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21835#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21836#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22255#L631 assume 1 == ~t2_pc~0; 22190#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21612#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21613#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22449#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 22450#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21908#L650 assume !(1 == ~t3_pc~0); 21909#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22609#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21832#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21565#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 21566#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22758#L669 assume 1 == ~t4_pc~0; 22759#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 23117#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22242#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21774#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 21775#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21999#L688 assume !(1 == ~t5_pc~0); 21790#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 21791#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22709#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22643#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 22644#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22776#L707 assume 1 == ~t6_pc~0; 23182#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22419#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22420#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23180#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 22715#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22277#L726 assume 1 == ~t7_pc~0; 22178#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21875#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22916#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 23190#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 21644#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21645#L745 assume !(1 == ~t8_pc~0); 22092#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22111#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22949#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22497#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22498#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 23008#L764 assume 1 == ~t9_pc~0; 22275#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22117#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22794#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23241#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 21664#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21665#L783 assume !(1 == ~t10_pc~0); 21726#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 21727#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21768#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21769#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 22236#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23119#L802 assume 1 == ~t11_pc~0; 23101#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21609#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21610#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 22102#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 22103#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 22212#L821 assume !(1 == ~t12_pc~0); 22463#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 22559#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21616#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21617#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 23157#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22803#L1339 assume !(1 == ~M_E~0); 22804#L1339-2 assume !(1 == ~T1_E~0); 23192#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23193#L1349-1 assume !(1 == ~T3_E~0); 22578#L1354-1 assume !(1 == ~T4_E~0); 22579#L1359-1 assume !(1 == ~T5_E~0); 22979#L1364-1 assume !(1 == ~T6_E~0); 22042#L1369-1 assume !(1 == ~T7_E~0); 22043#L1374-1 assume !(1 == ~T8_E~0); 22580#L1379-1 assume !(1 == ~T9_E~0); 22581#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22680#L1389-1 assume !(1 == ~T11_E~0); 23151#L1394-1 assume !(1 == ~T12_E~0); 23152#L1399-1 assume !(1 == ~E_M~0); 23242#L1404-1 assume !(1 == ~E_1~0); 22141#L1409-1 assume !(1 == ~E_2~0); 22142#L1414-1 assume !(1 == ~E_3~0); 22868#L1419-1 assume !(1 == ~E_4~0); 21782#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 21783#L1429-1 assume !(1 == ~E_6~0); 22593#L1434-1 assume !(1 == ~E_7~0); 23172#L1439-1 assume !(1 == ~E_8~0); 21820#L1444-1 assume !(1 == ~E_9~0); 21821#L1449-1 assume !(1 == ~E_10~0); 22195#L1454-1 assume !(1 == ~E_11~0); 22196#L1459-1 assume !(1 == ~E_12~0); 22714#L1464-1 assume { :end_inline_reset_delta_events } true; 21954#L1810-2 [2021-12-14 23:43:26,216 INFO L793 eck$LassoCheckResult]: Loop: 21954#L1810-2 assume !false; 22398#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22314#L1176 assume !false; 22876#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22448#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 21652#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 22202#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22203#L1003 assume !(0 != eval_~tmp~0#1); 21844#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21845#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23035#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22818#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22819#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22712#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21903#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21904#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22370#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21976#L1231-3 assume !(0 == ~T7_E~0); 21977#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22223#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23203#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 23105#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 22809#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 21920#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 21921#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21966#L1271-3 assume !(0 == ~E_2~0); 21967#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22343#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22344#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22866#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22867#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23281#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23238#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22455#L1311-3 assume !(0 == ~E_10~0); 21846#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 21847#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 21922#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22558#L593-42 assume 1 == ~m_pc~0; 22952#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22717#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23266#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23267#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21748#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21749#L612-42 assume !(1 == ~t1_pc~0); 22667#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 23060#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23181#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21833#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21834#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22528#L631-42 assume !(1 == ~t2_pc~0); 21600#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 21599#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22516#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22394#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22395#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21992#L650-42 assume 1 == ~t3_pc~0; 21557#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21558#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23209#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22188#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22189#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23173#L669-42 assume !(1 == ~t4_pc~0); 21553#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 21554#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22984#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22874#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 22771#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22772#L688-42 assume !(1 == ~t5_pc~0); 22864#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 23064#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21696#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21697#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21770#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21585#L707-42 assume !(1 == ~t6_pc~0); 21586#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 23245#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22989#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22990#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22739#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22740#L726-42 assume 1 == ~t7_pc~0; 23017#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23043#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23044#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22458#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22459#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22562#L745-42 assume 1 == ~t8_pc~0; 22598#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22600#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21928#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21573#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21574#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22299#L764-42 assume 1 == ~t9_pc~0; 22435#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22788#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22789#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21859#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21860#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21913#L783-42 assume 1 == ~t10_pc~0; 21529#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21530#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22125#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22258#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23275#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22959#L802-42 assume 1 == ~t11_pc~0; 22060#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21671#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21672#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21622#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 21623#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 22799#L821-42 assume 1 == ~t12_pc~0; 22800#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 22165#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21525#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21526#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 22505#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22495#L1339-3 assume !(1 == ~M_E~0); 22496#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22647#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22757#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22174#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22175#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22768#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23264#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23171#L1374-3 assume !(1 == ~T8_E~0); 21996#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21997#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22172#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22173#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 22382#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 23178#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23146#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23147#L1414-3 assume !(1 == ~E_3~0); 23202#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22961#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21880#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21881#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22767#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21808#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21809#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 21925#L1454-3 assume !(1 == ~E_11~0); 22762#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 22763#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22421#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 21718#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21978#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 21979#L1829 assume !(0 == start_simulation_~tmp~3#1); 21700#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 21701#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 22501#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 22502#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 22781#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22782#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22402#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 21953#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 21954#L1810-2 [2021-12-14 23:43:26,217 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:26,217 INFO L85 PathProgramCache]: Analyzing trace with hash -563283220, now seen corresponding path program 1 times [2021-12-14 23:43:26,217 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:26,217 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1900849805] [2021-12-14 23:43:26,217 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:26,218 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:26,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:26,237 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:26,237 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:26,237 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1900849805] [2021-12-14 23:43:26,238 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1900849805] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:26,238 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:26,238 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:26,238 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1701719722] [2021-12-14 23:43:26,238 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:26,238 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-14 23:43:26,239 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:26,239 INFO L85 PathProgramCache]: Analyzing trace with hash -1685871596, now seen corresponding path program 1 times [2021-12-14 23:43:26,239 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:26,239 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [774886188] [2021-12-14 23:43:26,239 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:26,240 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:26,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:26,265 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:26,265 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:26,265 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [774886188] [2021-12-14 23:43:26,265 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [774886188] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:26,265 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:26,266 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:26,266 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [92355863] [2021-12-14 23:43:26,266 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:26,266 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-14 23:43:26,266 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-14 23:43:26,267 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-14 23:43:26,267 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-14 23:43:26,267 INFO L87 Difference]: Start difference. First operand 1788 states and 2646 transitions. cyclomatic complexity: 859 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:26,285 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-14 23:43:26,286 INFO L93 Difference]: Finished difference Result 1788 states and 2645 transitions. [2021-12-14 23:43:26,286 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-14 23:43:26,287 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2645 transitions. [2021-12-14 23:43:26,293 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-14 23:43:26,298 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2645 transitions. [2021-12-14 23:43:26,299 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2021-12-14 23:43:26,299 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2021-12-14 23:43:26,300 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2645 transitions. [2021-12-14 23:43:26,301 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-14 23:43:26,301 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2645 transitions. [2021-12-14 23:43:26,303 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2645 transitions. [2021-12-14 23:43:26,314 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2021-12-14 23:43:26,317 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4793064876957494) internal successors, (2645), 1787 states have internal predecessors, (2645), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:26,320 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2645 transitions. [2021-12-14 23:43:26,320 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2645 transitions. [2021-12-14 23:43:26,320 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2645 transitions. [2021-12-14 23:43:26,320 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-14 23:43:26,320 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2645 transitions. [2021-12-14 23:43:26,325 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-14 23:43:26,325 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-14 23:43:26,325 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-14 23:43:26,326 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:26,326 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:26,327 INFO L791 eck$LassoCheckResult]: Stem: 25886#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 25887#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 25407#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25408#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25462#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 26801#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25895#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25698#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25097#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25098#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26320#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26431#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 26867#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 26868#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25826#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25827#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 26349#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 26268#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25861#L1201 assume !(0 == ~M_E~0); 25862#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26708#L1206-1 assume !(0 == ~T2_E~0); 26694#L1211-1 assume !(0 == ~T3_E~0); 26695#L1216-1 assume !(0 == ~T4_E~0); 25683#L1221-1 assume !(0 == ~T5_E~0); 25684#L1226-1 assume !(0 == ~T6_E~0); 25322#L1231-1 assume !(0 == ~T7_E~0); 25323#L1236-1 assume !(0 == ~T8_E~0); 26731#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25719#L1246-1 assume !(0 == ~T10_E~0); 25720#L1251-1 assume !(0 == ~T11_E~0); 25859#L1256-1 assume !(0 == ~T12_E~0); 25110#L1261-1 assume !(0 == ~E_M~0); 25111#L1266-1 assume !(0 == ~E_1~0); 26853#L1271-1 assume !(0 == ~E_2~0); 26415#L1276-1 assume !(0 == ~E_3~0); 26416#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 26363#L1286-1 assume !(0 == ~E_5~0); 25573#L1291-1 assume !(0 == ~E_6~0); 25574#L1296-1 assume !(0 == ~E_7~0); 26149#L1301-1 assume !(0 == ~E_8~0); 26150#L1306-1 assume !(0 == ~E_9~0); 26630#L1311-1 assume !(0 == ~E_10~0); 25524#L1316-1 assume !(0 == ~E_11~0); 25525#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 26167#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26168#L593 assume 1 == ~m_pc~0; 26312#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25414#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26840#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26374#L1492 assume !(0 != activate_threads_~tmp~1#1); 26375#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26666#L612 assume !(1 == ~t1_pc~0); 26667#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26796#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25796#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25418#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25419#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25838#L631 assume 1 == ~t2_pc~0; 25773#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25195#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25196#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26032#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 26033#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25491#L650 assume !(1 == ~t3_pc~0); 25492#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26192#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25415#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25148#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 25149#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26341#L669 assume 1 == ~t4_pc~0; 26342#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26700#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25825#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25357#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 25358#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25582#L688 assume !(1 == ~t5_pc~0); 25373#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 25374#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26292#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26226#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 26227#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26359#L707 assume 1 == ~t6_pc~0; 26765#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26002#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26003#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26763#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 26298#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25860#L726 assume 1 == ~t7_pc~0; 25761#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25458#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26499#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26773#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 25227#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25228#L745 assume !(1 == ~t8_pc~0); 25675#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25694#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26532#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26080#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26081#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26591#L764 assume 1 == ~t9_pc~0; 25858#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25700#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26377#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26824#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 25247#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25248#L783 assume !(1 == ~t10_pc~0); 25309#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25310#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25351#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25352#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 25816#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26702#L802 assume 1 == ~t11_pc~0; 26684#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25192#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25193#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25685#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 25686#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25795#L821 assume !(1 == ~t12_pc~0); 26046#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 26142#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25199#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25200#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 26740#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26386#L1339 assume !(1 == ~M_E~0); 26387#L1339-2 assume !(1 == ~T1_E~0); 26775#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26776#L1349-1 assume !(1 == ~T3_E~0); 26161#L1354-1 assume !(1 == ~T4_E~0); 26162#L1359-1 assume !(1 == ~T5_E~0); 26562#L1364-1 assume !(1 == ~T6_E~0); 25625#L1369-1 assume !(1 == ~T7_E~0); 25626#L1374-1 assume !(1 == ~T8_E~0); 26163#L1379-1 assume !(1 == ~T9_E~0); 26164#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 26263#L1389-1 assume !(1 == ~T11_E~0); 26734#L1394-1 assume !(1 == ~T12_E~0); 26735#L1399-1 assume !(1 == ~E_M~0); 26825#L1404-1 assume !(1 == ~E_1~0); 25724#L1409-1 assume !(1 == ~E_2~0); 25725#L1414-1 assume !(1 == ~E_3~0); 26451#L1419-1 assume !(1 == ~E_4~0); 25365#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 25366#L1429-1 assume !(1 == ~E_6~0); 26176#L1434-1 assume !(1 == ~E_7~0); 26755#L1439-1 assume !(1 == ~E_8~0); 25403#L1444-1 assume !(1 == ~E_9~0); 25404#L1449-1 assume !(1 == ~E_10~0); 25778#L1454-1 assume !(1 == ~E_11~0); 25779#L1459-1 assume !(1 == ~E_12~0); 26297#L1464-1 assume { :end_inline_reset_delta_events } true; 25537#L1810-2 [2021-12-14 23:43:26,327 INFO L793 eck$LassoCheckResult]: Loop: 25537#L1810-2 assume !false; 25981#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25897#L1176 assume !false; 26459#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26029#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25235#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25785#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 25786#L1003 assume !(0 != eval_~tmp~0#1); 25427#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25428#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26618#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26401#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26402#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26295#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25486#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25487#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25953#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25557#L1231-3 assume !(0 == ~T7_E~0); 25558#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25806#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 26786#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 26687#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 26392#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 25503#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25504#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25549#L1271-3 assume !(0 == ~E_2~0); 25550#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25926#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 25927#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26449#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 26450#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 26864#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 26821#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 26038#L1311-3 assume !(0 == ~E_10~0); 25429#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25430#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 25505#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26141#L593-42 assume 1 == ~m_pc~0; 26535#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26300#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26849#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26850#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25328#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25329#L612-42 assume !(1 == ~t1_pc~0); 26250#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 26643#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26764#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25416#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25417#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26112#L631-42 assume 1 == ~t2_pc~0; 25184#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25185#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26101#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25977#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25978#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25578#L650-42 assume 1 == ~t3_pc~0; 25143#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25144#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26792#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25771#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25772#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26756#L669-42 assume !(1 == ~t4_pc~0); 25138#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 25139#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26567#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26457#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 26354#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26355#L688-42 assume 1 == ~t5_pc~0; 26446#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26647#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25281#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25282#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25356#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25170#L707-42 assume !(1 == ~t6_pc~0); 25171#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 26830#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26572#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26573#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26321#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26322#L726-42 assume 1 == ~t7_pc~0; 26598#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26626#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26627#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26041#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 26042#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26145#L745-42 assume 1 == ~t8_pc~0; 26181#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26183#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25509#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25156#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25157#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25882#L764-42 assume 1 == ~t9_pc~0; 26018#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26371#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26372#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25442#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25443#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25496#L783-42 assume 1 == ~t10_pc~0; 25112#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 25113#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25708#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25841#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26858#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26542#L802-42 assume 1 == ~t11_pc~0; 25641#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25254#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25255#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25205#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 25206#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 26382#L821-42 assume !(1 == ~t12_pc~0); 25747#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 25748#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25108#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25109#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 26088#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26075#L1339-3 assume !(1 == ~M_E~0); 26076#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26230#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26340#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25757#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25758#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26351#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26847#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26754#L1374-3 assume !(1 == ~T8_E~0); 25579#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25580#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25755#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25756#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 25965#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26761#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26729#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26730#L1414-3 assume !(1 == ~E_3~0); 26785#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 26544#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25463#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25464#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 26350#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25391#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25392#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 25508#L1454-3 assume !(1 == ~E_11~0); 26345#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 26346#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26004#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25301#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25561#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 25562#L1829 assume !(0 == start_simulation_~tmp~3#1); 25283#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25284#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 26084#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 26085#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 26364#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26365#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25985#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 25536#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 25537#L1810-2 [2021-12-14 23:43:26,327 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:26,328 INFO L85 PathProgramCache]: Analyzing trace with hash -973893586, now seen corresponding path program 1 times [2021-12-14 23:43:26,328 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:26,328 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1161989184] [2021-12-14 23:43:26,328 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:26,328 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:26,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:26,372 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:26,372 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:26,372 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1161989184] [2021-12-14 23:43:26,373 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1161989184] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:26,373 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:26,373 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:26,373 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [739104959] [2021-12-14 23:43:26,373 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:26,373 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-14 23:43:26,374 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:26,374 INFO L85 PathProgramCache]: Analyzing trace with hash -1361569005, now seen corresponding path program 1 times [2021-12-14 23:43:26,374 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:26,374 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [144119240] [2021-12-14 23:43:26,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:26,375 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:26,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:26,399 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:26,400 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:26,400 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [144119240] [2021-12-14 23:43:26,400 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [144119240] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:26,400 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:26,400 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:26,400 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1019076669] [2021-12-14 23:43:26,401 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:26,401 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-14 23:43:26,401 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-14 23:43:26,401 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-14 23:43:26,402 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-14 23:43:26,402 INFO L87 Difference]: Start difference. First operand 1788 states and 2645 transitions. cyclomatic complexity: 858 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:26,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-14 23:43:26,424 INFO L93 Difference]: Finished difference Result 1788 states and 2644 transitions. [2021-12-14 23:43:26,424 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-14 23:43:26,425 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2644 transitions. [2021-12-14 23:43:26,431 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-14 23:43:26,437 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2644 transitions. [2021-12-14 23:43:26,438 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2021-12-14 23:43:26,439 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2021-12-14 23:43:26,439 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2644 transitions. [2021-12-14 23:43:26,440 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-14 23:43:26,440 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2644 transitions. [2021-12-14 23:43:26,442 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2644 transitions. [2021-12-14 23:43:26,455 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2021-12-14 23:43:26,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4787472035794182) internal successors, (2644), 1787 states have internal predecessors, (2644), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:26,460 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2644 transitions. [2021-12-14 23:43:26,461 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2644 transitions. [2021-12-14 23:43:26,461 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2644 transitions. [2021-12-14 23:43:26,461 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-14 23:43:26,461 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2644 transitions. [2021-12-14 23:43:26,465 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-14 23:43:26,465 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-14 23:43:26,465 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-14 23:43:26,467 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:26,467 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:26,467 INFO L791 eck$LassoCheckResult]: Stem: 29469#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 29470#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 28990#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28991#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29045#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 30384#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29478#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29281#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28680#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28681#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29903#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30014#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 30450#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 30451#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29409#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29410#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29932#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 29851#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29444#L1201 assume !(0 == ~M_E~0); 29445#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30291#L1206-1 assume !(0 == ~T2_E~0); 30277#L1211-1 assume !(0 == ~T3_E~0); 30278#L1216-1 assume !(0 == ~T4_E~0); 29265#L1221-1 assume !(0 == ~T5_E~0); 29266#L1226-1 assume !(0 == ~T6_E~0); 28905#L1231-1 assume !(0 == ~T7_E~0); 28906#L1236-1 assume !(0 == ~T8_E~0); 30314#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29302#L1246-1 assume !(0 == ~T10_E~0); 29303#L1251-1 assume !(0 == ~T11_E~0); 29442#L1256-1 assume !(0 == ~T12_E~0); 28691#L1261-1 assume !(0 == ~E_M~0); 28692#L1266-1 assume !(0 == ~E_1~0); 30436#L1271-1 assume !(0 == ~E_2~0); 29998#L1276-1 assume !(0 == ~E_3~0); 29999#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 29946#L1286-1 assume !(0 == ~E_5~0); 29156#L1291-1 assume !(0 == ~E_6~0); 29157#L1296-1 assume !(0 == ~E_7~0); 29732#L1301-1 assume !(0 == ~E_8~0); 29733#L1306-1 assume !(0 == ~E_9~0); 30213#L1311-1 assume !(0 == ~E_10~0); 29107#L1316-1 assume !(0 == ~E_11~0); 29108#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 29750#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29751#L593 assume 1 == ~m_pc~0; 29895#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28997#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30423#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29957#L1492 assume !(0 != activate_threads_~tmp~1#1); 29958#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30249#L612 assume !(1 == ~t1_pc~0); 30250#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 30379#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29379#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29001#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29002#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29421#L631 assume 1 == ~t2_pc~0; 29356#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28778#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28779#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29615#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 29616#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29074#L650 assume !(1 == ~t3_pc~0); 29075#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29775#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28998#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28731#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 28732#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29924#L669 assume 1 == ~t4_pc~0; 29925#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30283#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29408#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28940#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 28941#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29165#L688 assume !(1 == ~t5_pc~0); 28956#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 28957#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29875#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29809#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 29810#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29939#L707 assume 1 == ~t6_pc~0; 30348#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29585#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29586#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30346#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 29881#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29443#L726 assume 1 == ~t7_pc~0; 29342#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29041#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30082#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30356#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 28810#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28811#L745 assume !(1 == ~t8_pc~0); 29258#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 29277#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30115#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29663#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29664#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30174#L764 assume 1 == ~t9_pc~0; 29441#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29283#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29960#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30407#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 28830#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28831#L783 assume !(1 == ~t10_pc~0); 28892#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 28893#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28934#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 28935#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 29397#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30285#L802 assume 1 == ~t11_pc~0; 30267#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28775#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28776#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 29267#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 29268#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29378#L821 assume !(1 == ~t12_pc~0); 29629#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 29725#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28780#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28781#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 30323#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29969#L1339 assume !(1 == ~M_E~0); 29970#L1339-2 assume !(1 == ~T1_E~0); 30358#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30359#L1349-1 assume !(1 == ~T3_E~0); 29743#L1354-1 assume !(1 == ~T4_E~0); 29744#L1359-1 assume !(1 == ~T5_E~0); 30145#L1364-1 assume !(1 == ~T6_E~0); 29208#L1369-1 assume !(1 == ~T7_E~0); 29209#L1374-1 assume !(1 == ~T8_E~0); 29746#L1379-1 assume !(1 == ~T9_E~0); 29747#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29846#L1389-1 assume !(1 == ~T11_E~0); 30317#L1394-1 assume !(1 == ~T12_E~0); 30318#L1399-1 assume !(1 == ~E_M~0); 30408#L1404-1 assume !(1 == ~E_1~0); 29307#L1409-1 assume !(1 == ~E_2~0); 29308#L1414-1 assume !(1 == ~E_3~0); 30034#L1419-1 assume !(1 == ~E_4~0); 28948#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 28949#L1429-1 assume !(1 == ~E_6~0); 29759#L1434-1 assume !(1 == ~E_7~0); 30338#L1439-1 assume !(1 == ~E_8~0); 28986#L1444-1 assume !(1 == ~E_9~0); 28987#L1449-1 assume !(1 == ~E_10~0); 29361#L1454-1 assume !(1 == ~E_11~0); 29362#L1459-1 assume !(1 == ~E_12~0); 29880#L1464-1 assume { :end_inline_reset_delta_events } true; 29120#L1810-2 [2021-12-14 23:43:26,468 INFO L793 eck$LassoCheckResult]: Loop: 29120#L1810-2 assume !false; 29564#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29480#L1176 assume !false; 30042#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29612#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 28818#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 29368#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 29369#L1003 assume !(0 != eval_~tmp~0#1); 29010#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29011#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30201#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29984#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29985#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29878#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29069#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29070#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29536#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29140#L1231-3 assume !(0 == ~T7_E~0); 29141#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29387#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30369#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30270#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29975#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 29086#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29087#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29132#L1271-3 assume !(0 == ~E_2~0); 29133#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29509#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29510#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30031#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30032#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30447#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30404#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29621#L1311-3 assume !(0 == ~E_10~0); 29012#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 29013#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 29088#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29724#L593-42 assume 1 == ~m_pc~0; 30117#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29883#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30432#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30433#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28911#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28912#L612-42 assume !(1 == ~t1_pc~0); 29833#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 30226#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30347#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28999#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29000#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29695#L631-42 assume 1 == ~t2_pc~0; 28764#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28765#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29684#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29560#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29561#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29161#L650-42 assume 1 == ~t3_pc~0; 28723#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28724#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30375#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29354#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29355#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30339#L669-42 assume !(1 == ~t4_pc~0); 28721#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 28722#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30150#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30040#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 29937#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29938#L688-42 assume 1 == ~t5_pc~0; 30029#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30230#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28862#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28863#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28939#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28753#L707-42 assume !(1 == ~t6_pc~0); 28754#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 30411#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30155#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30156#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29905#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29906#L726-42 assume 1 == ~t7_pc~0; 30183#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30209#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30210#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29624#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29625#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29728#L745-42 assume 1 == ~t8_pc~0; 29765#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29767#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29094#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28739#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28740#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29465#L764-42 assume 1 == ~t9_pc~0; 29601#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29954#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29955#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29025#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29026#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29079#L783-42 assume 1 == ~t10_pc~0; 28695#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28696#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29291#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29424#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30441#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30125#L802-42 assume 1 == ~t11_pc~0; 29226#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28837#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28838#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28788#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28789#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29965#L821-42 assume !(1 == ~t12_pc~0); 29330#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 29331#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28693#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28694#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 29671#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29661#L1339-3 assume !(1 == ~M_E~0); 29662#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29813#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29923#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29340#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29341#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29934#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30430#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30337#L1374-3 assume !(1 == ~T8_E~0); 29162#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29163#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29338#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29339#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 29548#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30344#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30312#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30313#L1414-3 assume !(1 == ~E_3~0); 30368#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30127#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29046#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29047#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 29933#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28974#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28975#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 29091#L1454-3 assume !(1 == ~E_11~0); 29928#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 29929#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29587#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 28884#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 29144#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 29145#L1829 assume !(0 == start_simulation_~tmp~3#1); 28866#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 28867#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 29667#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 29668#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 29947#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29948#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29568#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 29119#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 29120#L1810-2 [2021-12-14 23:43:26,468 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:26,468 INFO L85 PathProgramCache]: Analyzing trace with hash 813976236, now seen corresponding path program 1 times [2021-12-14 23:43:26,468 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:26,469 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1585425182] [2021-12-14 23:43:26,469 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:26,469 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:26,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:26,493 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:26,494 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:26,494 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1585425182] [2021-12-14 23:43:26,494 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1585425182] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:26,494 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:26,494 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:26,495 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1033601031] [2021-12-14 23:43:26,495 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:26,495 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-14 23:43:26,495 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:26,496 INFO L85 PathProgramCache]: Analyzing trace with hash -1361569005, now seen corresponding path program 2 times [2021-12-14 23:43:26,496 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:26,496 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [279697216] [2021-12-14 23:43:26,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:26,496 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:26,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:26,526 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:26,526 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:26,526 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [279697216] [2021-12-14 23:43:26,526 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [279697216] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:26,527 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:26,527 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:26,527 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [990640380] [2021-12-14 23:43:26,527 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:26,527 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-14 23:43:26,527 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-14 23:43:26,528 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-14 23:43:26,528 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-14 23:43:26,528 INFO L87 Difference]: Start difference. First operand 1788 states and 2644 transitions. cyclomatic complexity: 857 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:26,549 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-14 23:43:26,549 INFO L93 Difference]: Finished difference Result 1788 states and 2643 transitions. [2021-12-14 23:43:26,549 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-14 23:43:26,550 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2643 transitions. [2021-12-14 23:43:26,556 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-14 23:43:26,562 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2643 transitions. [2021-12-14 23:43:26,562 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2021-12-14 23:43:26,563 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2021-12-14 23:43:26,563 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2643 transitions. [2021-12-14 23:43:26,565 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-14 23:43:26,565 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2643 transitions. [2021-12-14 23:43:26,567 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2643 transitions. [2021-12-14 23:43:26,581 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2021-12-14 23:43:26,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4781879194630871) internal successors, (2643), 1787 states have internal predecessors, (2643), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:26,587 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2643 transitions. [2021-12-14 23:43:26,587 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2643 transitions. [2021-12-14 23:43:26,587 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2643 transitions. [2021-12-14 23:43:26,587 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-14 23:43:26,587 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2643 transitions. [2021-12-14 23:43:26,592 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-14 23:43:26,592 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-14 23:43:26,592 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-14 23:43:26,593 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:26,594 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:26,594 INFO L791 eck$LassoCheckResult]: Stem: 33052#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 33053#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 32573#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32574#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32628#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 33967#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33061#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32864#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32263#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32264#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33486#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33597#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 34033#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 34034#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 32992#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 32993#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33515#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33434#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33027#L1201 assume !(0 == ~M_E~0); 33028#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33874#L1206-1 assume !(0 == ~T2_E~0); 33860#L1211-1 assume !(0 == ~T3_E~0); 33861#L1216-1 assume !(0 == ~T4_E~0); 32848#L1221-1 assume !(0 == ~T5_E~0); 32849#L1226-1 assume !(0 == ~T6_E~0); 32488#L1231-1 assume !(0 == ~T7_E~0); 32489#L1236-1 assume !(0 == ~T8_E~0); 33897#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32885#L1246-1 assume !(0 == ~T10_E~0); 32886#L1251-1 assume !(0 == ~T11_E~0); 33025#L1256-1 assume !(0 == ~T12_E~0); 32274#L1261-1 assume !(0 == ~E_M~0); 32275#L1266-1 assume !(0 == ~E_1~0); 34019#L1271-1 assume !(0 == ~E_2~0); 33581#L1276-1 assume !(0 == ~E_3~0); 33582#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 33529#L1286-1 assume !(0 == ~E_5~0); 32739#L1291-1 assume !(0 == ~E_6~0); 32740#L1296-1 assume !(0 == ~E_7~0); 33315#L1301-1 assume !(0 == ~E_8~0); 33316#L1306-1 assume !(0 == ~E_9~0); 33796#L1311-1 assume !(0 == ~E_10~0); 32690#L1316-1 assume !(0 == ~E_11~0); 32691#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 33333#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33334#L593 assume 1 == ~m_pc~0; 33478#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 32580#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34006#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33540#L1492 assume !(0 != activate_threads_~tmp~1#1); 33541#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33832#L612 assume !(1 == ~t1_pc~0); 33833#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 33962#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32962#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32584#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32585#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33004#L631 assume 1 == ~t2_pc~0; 32939#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32361#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32362#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33198#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 33199#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32657#L650 assume !(1 == ~t3_pc~0); 32658#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33358#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32581#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32314#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 32315#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33507#L669 assume 1 == ~t4_pc~0; 33508#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33866#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32991#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32523#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 32524#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32748#L688 assume !(1 == ~t5_pc~0); 32539#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 32540#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33458#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33392#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 33393#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33522#L707 assume 1 == ~t6_pc~0; 33931#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33168#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33169#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33929#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 33464#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33026#L726 assume 1 == ~t7_pc~0; 32925#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32624#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33665#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33939#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 32393#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32394#L745 assume !(1 == ~t8_pc~0); 32841#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 32860#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33698#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33246#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33247#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33757#L764 assume 1 == ~t9_pc~0; 33024#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32866#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33543#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33990#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 32413#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32414#L783 assume !(1 == ~t10_pc~0); 32475#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 32476#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32517#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 32518#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 32980#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33868#L802 assume 1 == ~t11_pc~0; 33850#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32358#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32359#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32850#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 32851#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32961#L821 assume !(1 == ~t12_pc~0); 33212#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 33308#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32363#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32364#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 33906#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33552#L1339 assume !(1 == ~M_E~0); 33553#L1339-2 assume !(1 == ~T1_E~0); 33941#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33942#L1349-1 assume !(1 == ~T3_E~0); 33326#L1354-1 assume !(1 == ~T4_E~0); 33327#L1359-1 assume !(1 == ~T5_E~0); 33728#L1364-1 assume !(1 == ~T6_E~0); 32791#L1369-1 assume !(1 == ~T7_E~0); 32792#L1374-1 assume !(1 == ~T8_E~0); 33329#L1379-1 assume !(1 == ~T9_E~0); 33330#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33429#L1389-1 assume !(1 == ~T11_E~0); 33900#L1394-1 assume !(1 == ~T12_E~0); 33901#L1399-1 assume !(1 == ~E_M~0); 33991#L1404-1 assume !(1 == ~E_1~0); 32890#L1409-1 assume !(1 == ~E_2~0); 32891#L1414-1 assume !(1 == ~E_3~0); 33617#L1419-1 assume !(1 == ~E_4~0); 32531#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 32532#L1429-1 assume !(1 == ~E_6~0); 33342#L1434-1 assume !(1 == ~E_7~0); 33921#L1439-1 assume !(1 == ~E_8~0); 32569#L1444-1 assume !(1 == ~E_9~0); 32570#L1449-1 assume !(1 == ~E_10~0); 32944#L1454-1 assume !(1 == ~E_11~0); 32945#L1459-1 assume !(1 == ~E_12~0); 33463#L1464-1 assume { :end_inline_reset_delta_events } true; 32703#L1810-2 [2021-12-14 23:43:26,594 INFO L793 eck$LassoCheckResult]: Loop: 32703#L1810-2 assume !false; 33147#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33063#L1176 assume !false; 33625#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33195#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32401#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32951#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 32952#L1003 assume !(0 != eval_~tmp~0#1); 32593#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32594#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33784#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33567#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33568#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33461#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32652#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32653#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33119#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32723#L1231-3 assume !(0 == ~T7_E~0); 32724#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32970#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33952#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33853#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 33558#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 32669#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 32670#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32715#L1271-3 assume !(0 == ~E_2~0); 32716#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33092#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33093#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33614#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 33615#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34030#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 33987#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 33204#L1311-3 assume !(0 == ~E_10~0); 32595#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32596#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 32671#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33307#L593-42 assume 1 == ~m_pc~0; 33700#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 33466#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34015#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34016#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 32494#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32495#L612-42 assume !(1 == ~t1_pc~0); 33416#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 33809#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33930#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32582#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32583#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33278#L631-42 assume 1 == ~t2_pc~0; 32347#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32348#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33267#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33143#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33144#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32744#L650-42 assume 1 == ~t3_pc~0; 32306#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 32307#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33958#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32937#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32938#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33922#L669-42 assume !(1 == ~t4_pc~0); 32304#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 32305#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33733#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33623#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 33520#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33521#L688-42 assume 1 == ~t5_pc~0; 33612#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33813#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32445#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32446#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 32522#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32336#L707-42 assume !(1 == ~t6_pc~0); 32337#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 33994#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33738#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33739#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33488#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33489#L726-42 assume 1 == ~t7_pc~0; 33766#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33792#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33793#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33207#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33208#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33311#L745-42 assume 1 == ~t8_pc~0; 33348#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33350#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32677#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32322#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32323#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33048#L764-42 assume 1 == ~t9_pc~0; 33184#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33537#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33538#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32608#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 32609#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32662#L783-42 assume 1 == ~t10_pc~0; 32278#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 32279#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32874#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33007#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34024#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33708#L802-42 assume 1 == ~t11_pc~0; 32809#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32420#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32421#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32371#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32372#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33548#L821-42 assume !(1 == ~t12_pc~0); 32913#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 32914#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32276#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32277#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 33254#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33244#L1339-3 assume !(1 == ~M_E~0); 33245#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33396#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33506#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32923#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32924#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33517#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34013#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33920#L1374-3 assume !(1 == ~T8_E~0); 32745#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 32746#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32921#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 32922#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 33131#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33927#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33895#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33896#L1414-3 assume !(1 == ~E_3~0); 33951#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33710#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32629#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32630#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 33516#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 32557#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 32558#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32674#L1454-3 assume !(1 == ~E_11~0); 33511#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 33512#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33170#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32467#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32727#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 32728#L1829 assume !(0 == start_simulation_~tmp~3#1); 32449#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 32450#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 33250#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 33251#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 33530#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 33531#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33151#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 32702#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 32703#L1810-2 [2021-12-14 23:43:26,595 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:26,595 INFO L85 PathProgramCache]: Analyzing trace with hash -1345107858, now seen corresponding path program 1 times [2021-12-14 23:43:26,595 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:26,595 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [475955899] [2021-12-14 23:43:26,595 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:26,596 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:26,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:26,616 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:26,616 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:26,617 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [475955899] [2021-12-14 23:43:26,617 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [475955899] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:26,617 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:26,617 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:26,617 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2026574861] [2021-12-14 23:43:26,617 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:26,618 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-14 23:43:26,618 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:26,618 INFO L85 PathProgramCache]: Analyzing trace with hash -1361569005, now seen corresponding path program 3 times [2021-12-14 23:43:26,618 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:26,618 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1191374757] [2021-12-14 23:43:26,619 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:26,619 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:26,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:26,644 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:26,644 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:26,645 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1191374757] [2021-12-14 23:43:26,645 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1191374757] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:26,645 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:26,645 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:26,645 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [158538850] [2021-12-14 23:43:26,645 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:26,646 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-14 23:43:26,646 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-14 23:43:26,646 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-14 23:43:26,646 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-14 23:43:26,646 INFO L87 Difference]: Start difference. First operand 1788 states and 2643 transitions. cyclomatic complexity: 856 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:26,666 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-14 23:43:26,666 INFO L93 Difference]: Finished difference Result 1788 states and 2642 transitions. [2021-12-14 23:43:26,667 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-14 23:43:26,667 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2642 transitions. [2021-12-14 23:43:26,673 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-14 23:43:26,679 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2642 transitions. [2021-12-14 23:43:26,679 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2021-12-14 23:43:26,681 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2021-12-14 23:43:26,681 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2642 transitions. [2021-12-14 23:43:26,682 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-14 23:43:26,682 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2642 transitions. [2021-12-14 23:43:26,716 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2642 transitions. [2021-12-14 23:43:26,730 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2021-12-14 23:43:26,732 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4776286353467563) internal successors, (2642), 1787 states have internal predecessors, (2642), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:26,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2642 transitions. [2021-12-14 23:43:26,735 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2642 transitions. [2021-12-14 23:43:26,736 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2642 transitions. [2021-12-14 23:43:26,736 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-14 23:43:26,736 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2642 transitions. [2021-12-14 23:43:26,740 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-14 23:43:26,740 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-14 23:43:26,741 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-14 23:43:26,742 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:26,742 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:26,743 INFO L791 eck$LassoCheckResult]: Stem: 36635#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 36636#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 36156#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 36157#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36211#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 37550#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36644#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36447#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35846#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35847#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 37069#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37180#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37616#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37617#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36575#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36576#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37098#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 37017#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36610#L1201 assume !(0 == ~M_E~0); 36611#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37457#L1206-1 assume !(0 == ~T2_E~0); 37443#L1211-1 assume !(0 == ~T3_E~0); 37444#L1216-1 assume !(0 == ~T4_E~0); 36431#L1221-1 assume !(0 == ~T5_E~0); 36432#L1226-1 assume !(0 == ~T6_E~0); 36071#L1231-1 assume !(0 == ~T7_E~0); 36072#L1236-1 assume !(0 == ~T8_E~0); 37480#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36468#L1246-1 assume !(0 == ~T10_E~0); 36469#L1251-1 assume !(0 == ~T11_E~0); 36608#L1256-1 assume !(0 == ~T12_E~0); 35857#L1261-1 assume !(0 == ~E_M~0); 35858#L1266-1 assume !(0 == ~E_1~0); 37602#L1271-1 assume !(0 == ~E_2~0); 37164#L1276-1 assume !(0 == ~E_3~0); 37165#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 37112#L1286-1 assume !(0 == ~E_5~0); 36322#L1291-1 assume !(0 == ~E_6~0); 36323#L1296-1 assume !(0 == ~E_7~0); 36898#L1301-1 assume !(0 == ~E_8~0); 36899#L1306-1 assume !(0 == ~E_9~0); 37379#L1311-1 assume !(0 == ~E_10~0); 36273#L1316-1 assume !(0 == ~E_11~0); 36274#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 36916#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36917#L593 assume 1 == ~m_pc~0; 37061#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36163#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37589#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37123#L1492 assume !(0 != activate_threads_~tmp~1#1); 37124#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37415#L612 assume !(1 == ~t1_pc~0); 37416#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 37545#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36545#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36167#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36168#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36587#L631 assume 1 == ~t2_pc~0; 36522#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35944#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35945#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36781#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 36782#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36240#L650 assume !(1 == ~t3_pc~0); 36241#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 36941#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36164#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35897#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 35898#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37090#L669 assume 1 == ~t4_pc~0; 37091#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37449#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36574#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36106#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 36107#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36331#L688 assume !(1 == ~t5_pc~0); 36122#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 36123#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37041#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36975#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 36976#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37105#L707 assume 1 == ~t6_pc~0; 37514#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36751#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36752#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37512#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 37047#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36609#L726 assume 1 == ~t7_pc~0; 36508#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36207#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37248#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37522#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 35976#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35977#L745 assume !(1 == ~t8_pc~0); 36424#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 36443#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37281#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36829#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36830#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37340#L764 assume 1 == ~t9_pc~0; 36607#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36449#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37126#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37573#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 35996#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35997#L783 assume !(1 == ~t10_pc~0); 36058#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36059#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36100#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 36101#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 36563#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37451#L802 assume 1 == ~t11_pc~0; 37433#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 35941#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35942#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36433#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 36434#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 36544#L821 assume !(1 == ~t12_pc~0); 36795#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 36891#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 35946#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 35947#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 37489#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37135#L1339 assume !(1 == ~M_E~0); 37136#L1339-2 assume !(1 == ~T1_E~0); 37524#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37525#L1349-1 assume !(1 == ~T3_E~0); 36909#L1354-1 assume !(1 == ~T4_E~0); 36910#L1359-1 assume !(1 == ~T5_E~0); 37311#L1364-1 assume !(1 == ~T6_E~0); 36374#L1369-1 assume !(1 == ~T7_E~0); 36375#L1374-1 assume !(1 == ~T8_E~0); 36912#L1379-1 assume !(1 == ~T9_E~0); 36913#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 37012#L1389-1 assume !(1 == ~T11_E~0); 37483#L1394-1 assume !(1 == ~T12_E~0); 37484#L1399-1 assume !(1 == ~E_M~0); 37574#L1404-1 assume !(1 == ~E_1~0); 36473#L1409-1 assume !(1 == ~E_2~0); 36474#L1414-1 assume !(1 == ~E_3~0); 37200#L1419-1 assume !(1 == ~E_4~0); 36114#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 36115#L1429-1 assume !(1 == ~E_6~0); 36925#L1434-1 assume !(1 == ~E_7~0); 37504#L1439-1 assume !(1 == ~E_8~0); 36152#L1444-1 assume !(1 == ~E_9~0); 36153#L1449-1 assume !(1 == ~E_10~0); 36527#L1454-1 assume !(1 == ~E_11~0); 36528#L1459-1 assume !(1 == ~E_12~0); 37046#L1464-1 assume { :end_inline_reset_delta_events } true; 36286#L1810-2 [2021-12-14 23:43:26,755 INFO L793 eck$LassoCheckResult]: Loop: 36286#L1810-2 assume !false; 36730#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36646#L1176 assume !false; 37208#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 36778#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 35984#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36534#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 36535#L1003 assume !(0 != eval_~tmp~0#1); 36176#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36177#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37367#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37150#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37151#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 37044#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36235#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36236#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36702#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36306#L1231-3 assume !(0 == ~T7_E~0); 36307#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36553#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37535#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 37436#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 37141#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 36252#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 36253#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36298#L1271-3 assume !(0 == ~E_2~0); 36299#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36675#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36676#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 37197#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 37198#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 37613#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37570#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 36787#L1311-3 assume !(0 == ~E_10~0); 36178#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36179#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 36254#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36890#L593-42 assume 1 == ~m_pc~0; 37283#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 37049#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37598#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37599#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36077#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36078#L612-42 assume !(1 == ~t1_pc~0); 36999#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 37392#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37513#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36165#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36166#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36861#L631-42 assume 1 == ~t2_pc~0; 35930#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35931#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36850#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36726#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36727#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36327#L650-42 assume 1 == ~t3_pc~0; 35889#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 35890#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37541#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36520#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36521#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37505#L669-42 assume 1 == ~t4_pc~0; 36801#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 35888#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37316#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37206#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 37103#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37104#L688-42 assume 1 == ~t5_pc~0; 37195#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37396#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36028#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36029#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 36105#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35919#L707-42 assume !(1 == ~t6_pc~0); 35920#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 37577#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37321#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37322#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 37071#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37072#L726-42 assume 1 == ~t7_pc~0; 37349#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37375#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37376#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36790#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 36791#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36894#L745-42 assume 1 == ~t8_pc~0; 36931#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36933#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36260#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35905#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35906#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36631#L764-42 assume !(1 == ~t9_pc~0); 36768#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 37120#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37121#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36191#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36192#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36245#L783-42 assume 1 == ~t10_pc~0; 35861#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 35862#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36457#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 36590#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37607#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37291#L802-42 assume 1 == ~t11_pc~0; 36392#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 36003#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36004#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 35954#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35955#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37131#L821-42 assume !(1 == ~t12_pc~0); 36496#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 36497#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 35859#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 35860#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 36837#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36827#L1339-3 assume !(1 == ~M_E~0); 36828#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36979#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37089#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36506#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36507#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37100#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37596#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37503#L1374-3 assume !(1 == ~T8_E~0); 36328#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36329#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36504#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 36505#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 36714#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37510#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37478#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37479#L1414-3 assume !(1 == ~E_3~0); 37534#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37293#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36212#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 36213#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37099#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 36140#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 36141#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 36257#L1454-3 assume !(1 == ~E_11~0); 37094#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 37095#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 36753#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36050#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36310#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 36311#L1829 assume !(0 == start_simulation_~tmp~3#1); 36032#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 36033#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36833#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36834#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 37113#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37114#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 36734#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 36285#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 36286#L1810-2 [2021-12-14 23:43:26,756 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:26,756 INFO L85 PathProgramCache]: Analyzing trace with hash -1762996560, now seen corresponding path program 1 times [2021-12-14 23:43:26,756 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:26,756 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1968522497] [2021-12-14 23:43:26,756 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:26,756 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:26,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:26,804 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:26,804 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:26,804 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1968522497] [2021-12-14 23:43:26,804 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1968522497] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:26,804 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:26,804 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:26,804 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [914804868] [2021-12-14 23:43:26,805 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:26,805 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-14 23:43:26,805 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:26,805 INFO L85 PathProgramCache]: Analyzing trace with hash -1901825325, now seen corresponding path program 1 times [2021-12-14 23:43:26,805 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:26,805 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [642218559] [2021-12-14 23:43:26,805 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:26,806 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:26,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:26,841 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:26,841 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:26,842 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [642218559] [2021-12-14 23:43:26,842 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [642218559] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:26,842 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:26,842 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:26,842 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1484028056] [2021-12-14 23:43:26,842 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:26,842 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-14 23:43:26,842 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-14 23:43:26,843 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-14 23:43:26,843 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-14 23:43:26,843 INFO L87 Difference]: Start difference. First operand 1788 states and 2642 transitions. cyclomatic complexity: 855 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:26,863 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-14 23:43:26,864 INFO L93 Difference]: Finished difference Result 1788 states and 2641 transitions. [2021-12-14 23:43:26,864 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-14 23:43:26,865 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2641 transitions. [2021-12-14 23:43:26,871 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-14 23:43:26,880 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2641 transitions. [2021-12-14 23:43:26,881 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2021-12-14 23:43:26,881 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2021-12-14 23:43:26,881 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2641 transitions. [2021-12-14 23:43:26,883 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-14 23:43:26,883 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2641 transitions. [2021-12-14 23:43:26,885 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2641 transitions. [2021-12-14 23:43:26,899 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2021-12-14 23:43:26,910 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4770693512304252) internal successors, (2641), 1787 states have internal predecessors, (2641), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:26,913 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2641 transitions. [2021-12-14 23:43:26,913 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2641 transitions. [2021-12-14 23:43:26,913 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2641 transitions. [2021-12-14 23:43:26,913 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-14 23:43:26,914 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2641 transitions. [2021-12-14 23:43:26,918 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-14 23:43:26,918 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-14 23:43:26,918 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-14 23:43:26,919 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:26,919 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:26,920 INFO L791 eck$LassoCheckResult]: Stem: 40218#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 40219#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 39739#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39740#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39794#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 41133#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40227#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40030#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39429#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39430#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40652#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40763#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41199#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41200#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 40158#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 40159#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 40681#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 40600#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40193#L1201 assume !(0 == ~M_E~0); 40194#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41040#L1206-1 assume !(0 == ~T2_E~0); 41026#L1211-1 assume !(0 == ~T3_E~0); 41027#L1216-1 assume !(0 == ~T4_E~0); 40014#L1221-1 assume !(0 == ~T5_E~0); 40015#L1226-1 assume !(0 == ~T6_E~0); 39654#L1231-1 assume !(0 == ~T7_E~0); 39655#L1236-1 assume !(0 == ~T8_E~0); 41063#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 40051#L1246-1 assume !(0 == ~T10_E~0); 40052#L1251-1 assume !(0 == ~T11_E~0); 40191#L1256-1 assume !(0 == ~T12_E~0); 39440#L1261-1 assume !(0 == ~E_M~0); 39441#L1266-1 assume !(0 == ~E_1~0); 41185#L1271-1 assume !(0 == ~E_2~0); 40747#L1276-1 assume !(0 == ~E_3~0); 40748#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 40695#L1286-1 assume !(0 == ~E_5~0); 39905#L1291-1 assume !(0 == ~E_6~0); 39906#L1296-1 assume !(0 == ~E_7~0); 40481#L1301-1 assume !(0 == ~E_8~0); 40482#L1306-1 assume !(0 == ~E_9~0); 40962#L1311-1 assume !(0 == ~E_10~0); 39856#L1316-1 assume !(0 == ~E_11~0); 39857#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 40499#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40500#L593 assume 1 == ~m_pc~0; 40644#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 39746#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41172#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40706#L1492 assume !(0 != activate_threads_~tmp~1#1); 40707#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40998#L612 assume !(1 == ~t1_pc~0); 40999#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 41128#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40128#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39750#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39751#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40170#L631 assume 1 == ~t2_pc~0; 40105#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39527#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39528#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40364#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 40365#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39823#L650 assume !(1 == ~t3_pc~0); 39824#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 40524#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39747#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39480#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 39481#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40673#L669 assume 1 == ~t4_pc~0; 40674#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41032#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40157#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39689#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 39690#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39914#L688 assume !(1 == ~t5_pc~0); 39705#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 39706#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40624#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40558#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 40559#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40688#L707 assume 1 == ~t6_pc~0; 41097#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 40334#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40335#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41095#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 40630#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40192#L726 assume 1 == ~t7_pc~0; 40091#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39790#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40831#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41105#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 39559#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39560#L745 assume !(1 == ~t8_pc~0); 40007#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 40026#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40864#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40412#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 40413#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40923#L764 assume 1 == ~t9_pc~0; 40190#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40032#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40709#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41156#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 39579#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39580#L783 assume !(1 == ~t10_pc~0); 39641#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 39642#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39683#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 39684#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 40146#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41034#L802 assume 1 == ~t11_pc~0; 41016#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39524#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39525#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 40016#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 40017#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 40127#L821 assume !(1 == ~t12_pc~0); 40378#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 40474#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 39529#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 39530#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 41072#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40718#L1339 assume !(1 == ~M_E~0); 40719#L1339-2 assume !(1 == ~T1_E~0); 41107#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 41108#L1349-1 assume !(1 == ~T3_E~0); 40492#L1354-1 assume !(1 == ~T4_E~0); 40493#L1359-1 assume !(1 == ~T5_E~0); 40894#L1364-1 assume !(1 == ~T6_E~0); 39957#L1369-1 assume !(1 == ~T7_E~0); 39958#L1374-1 assume !(1 == ~T8_E~0); 40495#L1379-1 assume !(1 == ~T9_E~0); 40496#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40595#L1389-1 assume !(1 == ~T11_E~0); 41066#L1394-1 assume !(1 == ~T12_E~0); 41067#L1399-1 assume !(1 == ~E_M~0); 41157#L1404-1 assume !(1 == ~E_1~0); 40056#L1409-1 assume !(1 == ~E_2~0); 40057#L1414-1 assume !(1 == ~E_3~0); 40783#L1419-1 assume !(1 == ~E_4~0); 39697#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 39698#L1429-1 assume !(1 == ~E_6~0); 40508#L1434-1 assume !(1 == ~E_7~0); 41087#L1439-1 assume !(1 == ~E_8~0); 39735#L1444-1 assume !(1 == ~E_9~0); 39736#L1449-1 assume !(1 == ~E_10~0); 40110#L1454-1 assume !(1 == ~E_11~0); 40111#L1459-1 assume !(1 == ~E_12~0); 40629#L1464-1 assume { :end_inline_reset_delta_events } true; 39869#L1810-2 [2021-12-14 23:43:26,920 INFO L793 eck$LassoCheckResult]: Loop: 39869#L1810-2 assume !false; 40313#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40229#L1176 assume !false; 40791#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40361#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39567#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 40117#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 40118#L1003 assume !(0 != eval_~tmp~0#1); 39759#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 39760#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40950#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 40733#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40734#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 40627#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 39818#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 39819#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40285#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 39889#L1231-3 assume !(0 == ~T7_E~0); 39890#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40136#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41118#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 41019#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 40724#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 39835#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 39836#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 39881#L1271-3 assume !(0 == ~E_2~0); 39882#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40258#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40259#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 40780#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 40781#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 41196#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41153#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 40370#L1311-3 assume !(0 == ~E_10~0); 39761#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 39762#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 39837#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40473#L593-42 assume 1 == ~m_pc~0; 40866#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 40632#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41181#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41182#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 39660#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39661#L612-42 assume !(1 == ~t1_pc~0); 40582#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 40975#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41096#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39748#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39749#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40444#L631-42 assume 1 == ~t2_pc~0; 39513#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39514#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40433#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40309#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 40310#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39910#L650-42 assume 1 == ~t3_pc~0; 39472#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 39473#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41124#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40103#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 40104#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41088#L669-42 assume 1 == ~t4_pc~0; 40384#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39471#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40899#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40789#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 40686#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40687#L688-42 assume 1 == ~t5_pc~0; 40778#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40979#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39611#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39612#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 39688#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39502#L707-42 assume 1 == ~t6_pc~0; 39504#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41160#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40904#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40905#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40654#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40655#L726-42 assume 1 == ~t7_pc~0; 40932#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 40958#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40959#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40373#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 40374#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40477#L745-42 assume 1 == ~t8_pc~0; 40514#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40516#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39843#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39488#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39489#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40214#L764-42 assume 1 == ~t9_pc~0; 40350#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40703#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40704#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39774#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 39775#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39828#L783-42 assume 1 == ~t10_pc~0; 39444#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 39445#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40040#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40173#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41190#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40874#L802-42 assume 1 == ~t11_pc~0; 39975#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39586#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39587#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 39537#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 39538#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 40714#L821-42 assume 1 == ~t12_pc~0; 40715#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 40080#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 39442#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 39443#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 40420#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40410#L1339-3 assume !(1 == ~M_E~0); 40411#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40562#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40672#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40089#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40090#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 40683#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41179#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41086#L1374-3 assume !(1 == ~T8_E~0); 39911#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 39912#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40087#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40088#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 40297#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41093#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41061#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41062#L1414-3 assume !(1 == ~E_3~0); 41117#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 40876#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 39795#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 39796#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 40682#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 39723#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 39724#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 39840#L1454-3 assume !(1 == ~E_11~0); 40677#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 40678#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40336#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39633#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 39893#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 39894#L1829 assume !(0 == start_simulation_~tmp~3#1); 39615#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 39616#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 40416#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 40417#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 40696#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40697#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40317#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 39868#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 39869#L1810-2 [2021-12-14 23:43:26,920 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:26,920 INFO L85 PathProgramCache]: Analyzing trace with hash 1133017134, now seen corresponding path program 1 times [2021-12-14 23:43:26,920 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:26,921 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2069730476] [2021-12-14 23:43:26,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:26,921 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:26,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:26,944 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:26,944 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:26,944 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2069730476] [2021-12-14 23:43:26,944 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2069730476] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:26,945 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:26,946 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:26,946 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [222676996] [2021-12-14 23:43:26,946 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:26,946 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-14 23:43:26,946 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:26,946 INFO L85 PathProgramCache]: Analyzing trace with hash 1229697104, now seen corresponding path program 1 times [2021-12-14 23:43:26,947 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:26,947 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [451168201] [2021-12-14 23:43:26,947 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:26,947 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:26,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:26,973 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:26,974 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:26,974 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [451168201] [2021-12-14 23:43:26,974 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [451168201] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:26,974 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:26,974 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:26,975 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [135321079] [2021-12-14 23:43:26,975 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:26,975 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-14 23:43:26,975 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-14 23:43:26,975 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-14 23:43:26,976 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-14 23:43:26,976 INFO L87 Difference]: Start difference. First operand 1788 states and 2641 transitions. cyclomatic complexity: 854 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:26,996 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-14 23:43:26,996 INFO L93 Difference]: Finished difference Result 1788 states and 2640 transitions. [2021-12-14 23:43:26,996 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-14 23:43:26,998 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2640 transitions. [2021-12-14 23:43:27,004 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-14 23:43:27,008 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2640 transitions. [2021-12-14 23:43:27,008 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2021-12-14 23:43:27,009 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2021-12-14 23:43:27,009 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2640 transitions. [2021-12-14 23:43:27,010 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-14 23:43:27,011 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2640 transitions. [2021-12-14 23:43:27,012 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2640 transitions. [2021-12-14 23:43:27,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2021-12-14 23:43:27,025 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.476510067114094) internal successors, (2640), 1787 states have internal predecessors, (2640), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:27,027 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2640 transitions. [2021-12-14 23:43:27,028 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2640 transitions. [2021-12-14 23:43:27,028 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2640 transitions. [2021-12-14 23:43:27,028 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-14 23:43:27,028 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2640 transitions. [2021-12-14 23:43:27,032 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-14 23:43:27,032 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-14 23:43:27,032 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-14 23:43:27,033 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:27,034 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:27,034 INFO L791 eck$LassoCheckResult]: Stem: 43801#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 43802#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 43322#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 43323#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43377#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 44716#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43810#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43613#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43012#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43013#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 44235#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 44346#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 44782#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 44783#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 43741#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 43742#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 44264#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 44183#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43776#L1201 assume !(0 == ~M_E~0); 43777#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44623#L1206-1 assume !(0 == ~T2_E~0); 44609#L1211-1 assume !(0 == ~T3_E~0); 44610#L1216-1 assume !(0 == ~T4_E~0); 43597#L1221-1 assume !(0 == ~T5_E~0); 43598#L1226-1 assume !(0 == ~T6_E~0); 43237#L1231-1 assume !(0 == ~T7_E~0); 43238#L1236-1 assume !(0 == ~T8_E~0); 44646#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 43634#L1246-1 assume !(0 == ~T10_E~0); 43635#L1251-1 assume !(0 == ~T11_E~0); 43774#L1256-1 assume !(0 == ~T12_E~0); 43023#L1261-1 assume !(0 == ~E_M~0); 43024#L1266-1 assume !(0 == ~E_1~0); 44768#L1271-1 assume !(0 == ~E_2~0); 44330#L1276-1 assume !(0 == ~E_3~0); 44331#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 44278#L1286-1 assume !(0 == ~E_5~0); 43488#L1291-1 assume !(0 == ~E_6~0); 43489#L1296-1 assume !(0 == ~E_7~0); 44064#L1301-1 assume !(0 == ~E_8~0); 44065#L1306-1 assume !(0 == ~E_9~0); 44545#L1311-1 assume !(0 == ~E_10~0); 43439#L1316-1 assume !(0 == ~E_11~0); 43440#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 44082#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44083#L593 assume 1 == ~m_pc~0; 44227#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 43329#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44755#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44289#L1492 assume !(0 != activate_threads_~tmp~1#1); 44290#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44581#L612 assume !(1 == ~t1_pc~0); 44582#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 44711#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43711#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43333#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 43334#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43753#L631 assume 1 == ~t2_pc~0; 43688#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43110#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43111#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43947#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 43948#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43406#L650 assume !(1 == ~t3_pc~0); 43407#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 44107#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43330#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43063#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 43064#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44256#L669 assume 1 == ~t4_pc~0; 44257#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 44615#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43740#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43272#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 43273#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43497#L688 assume !(1 == ~t5_pc~0); 43288#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 43289#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44207#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44141#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 44142#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 44271#L707 assume 1 == ~t6_pc~0; 44680#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 43917#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43918#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44678#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 44213#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43775#L726 assume 1 == ~t7_pc~0; 43674#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 43373#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44414#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44688#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 43142#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43143#L745 assume !(1 == ~t8_pc~0); 43590#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 43609#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44447#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43995#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43996#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44506#L764 assume 1 == ~t9_pc~0; 43773#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43615#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44292#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 44739#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 43162#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43163#L783 assume !(1 == ~t10_pc~0); 43224#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 43225#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43266#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 43267#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 43729#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44617#L802 assume 1 == ~t11_pc~0; 44599#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 43107#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43108#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 43599#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 43600#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 43710#L821 assume !(1 == ~t12_pc~0); 43961#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 44057#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 43112#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 43113#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 44655#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44301#L1339 assume !(1 == ~M_E~0); 44302#L1339-2 assume !(1 == ~T1_E~0); 44690#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44691#L1349-1 assume !(1 == ~T3_E~0); 44075#L1354-1 assume !(1 == ~T4_E~0); 44076#L1359-1 assume !(1 == ~T5_E~0); 44477#L1364-1 assume !(1 == ~T6_E~0); 43540#L1369-1 assume !(1 == ~T7_E~0); 43541#L1374-1 assume !(1 == ~T8_E~0); 44078#L1379-1 assume !(1 == ~T9_E~0); 44079#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 44178#L1389-1 assume !(1 == ~T11_E~0); 44649#L1394-1 assume !(1 == ~T12_E~0); 44650#L1399-1 assume !(1 == ~E_M~0); 44740#L1404-1 assume !(1 == ~E_1~0); 43639#L1409-1 assume !(1 == ~E_2~0); 43640#L1414-1 assume !(1 == ~E_3~0); 44366#L1419-1 assume !(1 == ~E_4~0); 43280#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 43281#L1429-1 assume !(1 == ~E_6~0); 44091#L1434-1 assume !(1 == ~E_7~0); 44670#L1439-1 assume !(1 == ~E_8~0); 43318#L1444-1 assume !(1 == ~E_9~0); 43319#L1449-1 assume !(1 == ~E_10~0); 43693#L1454-1 assume !(1 == ~E_11~0); 43694#L1459-1 assume !(1 == ~E_12~0); 44212#L1464-1 assume { :end_inline_reset_delta_events } true; 43452#L1810-2 [2021-12-14 23:43:27,034 INFO L793 eck$LassoCheckResult]: Loop: 43452#L1810-2 assume !false; 43896#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 43812#L1176 assume !false; 44374#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 43944#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43150#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43700#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 43701#L1003 assume !(0 != eval_~tmp~0#1); 43342#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 43343#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 44533#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44316#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44317#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 44210#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 43401#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 43402#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 43868#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 43472#L1231-3 assume !(0 == ~T7_E~0); 43473#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 43719#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 44701#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 44602#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 44307#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 43418#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 43419#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 43464#L1271-3 assume !(0 == ~E_2~0); 43465#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 43841#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 43842#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 44363#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 44364#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 44779#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 44736#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 43953#L1311-3 assume !(0 == ~E_10~0); 43344#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 43345#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 43420#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44056#L593-42 assume 1 == ~m_pc~0; 44449#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 44215#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44764#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44765#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 43243#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43244#L612-42 assume !(1 == ~t1_pc~0); 44165#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 44558#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44679#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43331#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 43332#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44027#L631-42 assume 1 == ~t2_pc~0; 43096#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43097#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44016#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43892#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 43893#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43493#L650-42 assume !(1 == ~t3_pc~0); 43057#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 43056#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44707#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43686#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43687#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44671#L669-42 assume !(1 == ~t4_pc~0); 43053#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 43054#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44482#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44372#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 44269#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44270#L688-42 assume 1 == ~t5_pc~0; 44361#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44562#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43194#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 43195#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 43271#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43085#L707-42 assume !(1 == ~t6_pc~0); 43086#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 44743#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 44487#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44488#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 44237#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44238#L726-42 assume 1 == ~t7_pc~0; 44515#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 44541#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44542#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43956#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 43957#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 44060#L745-42 assume 1 == ~t8_pc~0; 44097#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 44099#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43426#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43071#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43072#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43797#L764-42 assume 1 == ~t9_pc~0; 43933#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44286#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44287#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43357#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 43358#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43411#L783-42 assume 1 == ~t10_pc~0; 43027#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 43028#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43623#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 43756#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 44773#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44457#L802-42 assume 1 == ~t11_pc~0; 43558#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 43169#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43170#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 43120#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 43121#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44297#L821-42 assume 1 == ~t12_pc~0; 44298#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 43663#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 43025#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 43026#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 44003#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43993#L1339-3 assume !(1 == ~M_E~0); 43994#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44145#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44255#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 43672#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43673#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44266#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44762#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 44669#L1374-3 assume !(1 == ~T8_E~0); 43494#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 43495#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43670#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43671#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 43880#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 44676#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44644#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44645#L1414-3 assume !(1 == ~E_3~0); 44700#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 44459#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43378#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 43379#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 44265#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 43306#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 43307#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 43423#L1454-3 assume !(1 == ~E_11~0); 44260#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 44261#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 43919#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43216#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43476#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 43477#L1829 assume !(0 == start_simulation_~tmp~3#1); 43198#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 43199#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43999#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 44000#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 44279#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44280#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43900#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 43451#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 43452#L1810-2 [2021-12-14 23:43:27,035 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:27,035 INFO L85 PathProgramCache]: Analyzing trace with hash -1544509712, now seen corresponding path program 1 times [2021-12-14 23:43:27,035 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:27,035 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1815451816] [2021-12-14 23:43:27,035 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:27,035 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:27,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:27,065 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:27,065 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:27,065 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1815451816] [2021-12-14 23:43:27,065 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1815451816] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:27,066 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:27,066 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-14 23:43:27,066 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1110283835] [2021-12-14 23:43:27,066 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:27,067 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-14 23:43:27,067 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:27,067 INFO L85 PathProgramCache]: Analyzing trace with hash 1696309331, now seen corresponding path program 1 times [2021-12-14 23:43:27,067 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:27,067 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [27928077] [2021-12-14 23:43:27,068 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:27,068 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:27,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:27,116 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:27,116 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:27,116 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [27928077] [2021-12-14 23:43:27,117 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [27928077] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:27,117 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:27,117 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:27,117 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [587541447] [2021-12-14 23:43:27,117 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:27,117 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-14 23:43:27,117 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-14 23:43:27,118 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-14 23:43:27,118 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-14 23:43:27,118 INFO L87 Difference]: Start difference. First operand 1788 states and 2640 transitions. cyclomatic complexity: 853 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:27,145 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-14 23:43:27,146 INFO L93 Difference]: Finished difference Result 1788 states and 2635 transitions. [2021-12-14 23:43:27,146 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-14 23:43:27,147 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2635 transitions. [2021-12-14 23:43:27,154 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-14 23:43:27,158 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2635 transitions. [2021-12-14 23:43:27,158 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2021-12-14 23:43:27,159 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2021-12-14 23:43:27,159 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2635 transitions. [2021-12-14 23:43:27,160 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-14 23:43:27,160 INFO L681 BuchiCegarLoop]: Abstraction has 1788 states and 2635 transitions. [2021-12-14 23:43:27,162 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2635 transitions. [2021-12-14 23:43:27,175 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2021-12-14 23:43:27,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4737136465324385) internal successors, (2635), 1787 states have internal predecessors, (2635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:27,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2635 transitions. [2021-12-14 23:43:27,179 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2635 transitions. [2021-12-14 23:43:27,179 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2635 transitions. [2021-12-14 23:43:27,179 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-14 23:43:27,179 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2635 transitions. [2021-12-14 23:43:27,183 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-14 23:43:27,183 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-14 23:43:27,183 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-14 23:43:27,184 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:27,184 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:27,185 INFO L791 eck$LassoCheckResult]: Stem: 47384#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 47385#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 46905#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46906#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46960#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 48299#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47393#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47196#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46595#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46596#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 47818#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 47931#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48365#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 48366#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47324#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47325#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 47847#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 47766#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47359#L1201 assume !(0 == ~M_E~0); 47360#L1201-2 assume !(0 == ~T1_E~0); 48206#L1206-1 assume !(0 == ~T2_E~0); 48192#L1211-1 assume !(0 == ~T3_E~0); 48193#L1216-1 assume !(0 == ~T4_E~0); 47181#L1221-1 assume !(0 == ~T5_E~0); 47182#L1226-1 assume !(0 == ~T6_E~0); 46820#L1231-1 assume !(0 == ~T7_E~0); 46821#L1236-1 assume !(0 == ~T8_E~0); 48229#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 47220#L1246-1 assume !(0 == ~T10_E~0); 47221#L1251-1 assume !(0 == ~T11_E~0); 47357#L1256-1 assume !(0 == ~T12_E~0); 46608#L1261-1 assume !(0 == ~E_M~0); 46609#L1266-1 assume !(0 == ~E_1~0); 48351#L1271-1 assume !(0 == ~E_2~0); 47913#L1276-1 assume !(0 == ~E_3~0); 47914#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 47861#L1286-1 assume !(0 == ~E_5~0); 47071#L1291-1 assume !(0 == ~E_6~0); 47072#L1296-1 assume !(0 == ~E_7~0); 47647#L1301-1 assume !(0 == ~E_8~0); 47648#L1306-1 assume !(0 == ~E_9~0); 48128#L1311-1 assume !(0 == ~E_10~0); 47022#L1316-1 assume !(0 == ~E_11~0); 47023#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 47665#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47666#L593 assume 1 == ~m_pc~0; 47810#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 46912#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48338#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47872#L1492 assume !(0 != activate_threads_~tmp~1#1); 47873#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48164#L612 assume !(1 == ~t1_pc~0); 48165#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 48294#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47294#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46916#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46917#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47336#L631 assume 1 == ~t2_pc~0; 47271#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46693#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46694#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47530#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 47531#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46989#L650 assume !(1 == ~t3_pc~0); 46990#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 47690#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46913#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46646#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 46647#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47839#L669 assume 1 == ~t4_pc~0; 47840#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 48198#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47323#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46855#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 46856#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47080#L688 assume !(1 == ~t5_pc~0); 46871#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 46872#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47790#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47726#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 47727#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47857#L707 assume 1 == ~t6_pc~0; 48263#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 47500#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47501#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48261#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 47798#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47358#L726 assume 1 == ~t7_pc~0; 47259#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46956#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47997#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 48272#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 46725#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46726#L745 assume !(1 == ~t8_pc~0); 47173#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 47192#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48030#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47578#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47579#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48089#L764 assume 1 == ~t9_pc~0; 47356#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47198#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47875#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 48322#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 46745#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46746#L783 assume !(1 == ~t10_pc~0); 46807#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 46808#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 46849#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46850#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 47317#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48200#L802 assume 1 == ~t11_pc~0; 48182#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46690#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46691#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 47183#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 47184#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47293#L821 assume !(1 == ~t12_pc~0); 47544#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 47640#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46697#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46698#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 48238#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47884#L1339 assume !(1 == ~M_E~0); 47885#L1339-2 assume !(1 == ~T1_E~0); 48273#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48274#L1349-1 assume !(1 == ~T3_E~0); 47659#L1354-1 assume !(1 == ~T4_E~0); 47660#L1359-1 assume !(1 == ~T5_E~0); 48062#L1364-1 assume !(1 == ~T6_E~0); 47123#L1369-1 assume !(1 == ~T7_E~0); 47124#L1374-1 assume !(1 == ~T8_E~0); 47663#L1379-1 assume !(1 == ~T9_E~0); 47664#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 47761#L1389-1 assume !(1 == ~T11_E~0); 48232#L1394-1 assume !(1 == ~T12_E~0); 48233#L1399-1 assume !(1 == ~E_M~0); 48323#L1404-1 assume !(1 == ~E_1~0); 47224#L1409-1 assume !(1 == ~E_2~0); 47225#L1414-1 assume !(1 == ~E_3~0); 47949#L1419-1 assume !(1 == ~E_4~0); 46863#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 46864#L1429-1 assume !(1 == ~E_6~0); 47674#L1434-1 assume !(1 == ~E_7~0); 48253#L1439-1 assume !(1 == ~E_8~0); 46901#L1444-1 assume !(1 == ~E_9~0); 46902#L1449-1 assume !(1 == ~E_10~0); 47276#L1454-1 assume !(1 == ~E_11~0); 47277#L1459-1 assume !(1 == ~E_12~0); 47795#L1464-1 assume { :end_inline_reset_delta_events } true; 47035#L1810-2 [2021-12-14 23:43:27,185 INFO L793 eck$LassoCheckResult]: Loop: 47035#L1810-2 assume !false; 47479#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47395#L1176 assume !false; 47957#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47529#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 46733#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47283#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 47284#L1003 assume !(0 != eval_~tmp~0#1); 46927#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46928#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 48116#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 47899#L1201-5 assume !(0 == ~T1_E~0); 47900#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 47794#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46984#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 46985#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47451#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 47055#L1231-3 assume !(0 == ~T7_E~0); 47056#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47302#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 48284#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 48185#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 47890#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 47001#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 47002#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 47047#L1271-3 assume !(0 == ~E_2~0); 47048#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 47424#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 47425#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47946#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 47947#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 48362#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 48319#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 47536#L1311-3 assume !(0 == ~E_10~0); 46925#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 46926#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 47003#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47639#L593-42 assume 1 == ~m_pc~0; 48032#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 47797#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48346#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48347#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 46826#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46827#L612-42 assume !(1 == ~t1_pc~0); 47748#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 48141#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48262#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46914#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46915#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47610#L631-42 assume 1 == ~t2_pc~0; 46679#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46680#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47599#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47475#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 47476#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47076#L650-42 assume !(1 == ~t3_pc~0); 46640#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 46639#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48290#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47269#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47270#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48254#L669-42 assume !(1 == ~t4_pc~0); 46636#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 46637#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48065#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47955#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 47852#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47853#L688-42 assume 1 == ~t5_pc~0; 47944#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 48145#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46777#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46778#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46851#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46668#L707-42 assume !(1 == ~t6_pc~0); 46669#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 48326#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 48070#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48071#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 47820#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47821#L726-42 assume 1 == ~t7_pc~0; 48098#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 48124#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48125#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47539#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 47540#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47643#L745-42 assume 1 == ~t8_pc~0; 47680#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 47682#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47009#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46654#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 46655#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47380#L764-42 assume 1 == ~t9_pc~0; 47516#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47869#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47870#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46940#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 46941#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46994#L783-42 assume 1 == ~t10_pc~0; 46610#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 46611#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47206#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 47339#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 48356#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48040#L802-42 assume 1 == ~t11_pc~0; 47141#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46752#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46753#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46703#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 46704#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47880#L821-42 assume 1 == ~t12_pc~0; 47881#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 47246#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46606#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46607#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 47586#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47576#L1339-3 assume !(1 == ~M_E~0); 47577#L1339-5 assume !(1 == ~T1_E~0); 47728#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47838#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47255#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47256#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 47849#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 48345#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 48252#L1374-3 assume !(1 == ~T8_E~0); 47077#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 47078#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 47253#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 47254#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 47463#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 48259#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 48227#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 48228#L1414-3 assume !(1 == ~E_3~0); 48283#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 48042#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 46961#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46962#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 47848#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 46889#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 46890#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 47006#L1454-3 assume !(1 == ~E_11~0); 47843#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 47844#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47502#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 46799#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47059#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 47060#L1829 assume !(0 == start_simulation_~tmp~3#1); 46781#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 46782#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 47582#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47583#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 47862#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 47863#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 47483#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 47034#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 47035#L1810-2 [2021-12-14 23:43:27,185 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:27,185 INFO L85 PathProgramCache]: Analyzing trace with hash -2089382286, now seen corresponding path program 1 times [2021-12-14 23:43:27,185 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:27,186 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [786384870] [2021-12-14 23:43:27,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:27,186 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:27,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:27,210 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:27,211 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:27,211 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [786384870] [2021-12-14 23:43:27,211 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [786384870] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:27,211 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:27,211 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:27,211 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2122894871] [2021-12-14 23:43:27,211 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:27,212 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-14 23:43:27,212 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:27,213 INFO L85 PathProgramCache]: Analyzing trace with hash 1093504531, now seen corresponding path program 1 times [2021-12-14 23:43:27,213 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:27,213 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [932333909] [2021-12-14 23:43:27,213 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:27,213 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:27,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:27,243 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:27,244 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:27,244 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [932333909] [2021-12-14 23:43:27,244 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [932333909] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:27,244 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:27,244 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:27,244 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1389159221] [2021-12-14 23:43:27,244 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:27,244 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-14 23:43:27,244 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-14 23:43:27,245 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-14 23:43:27,245 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-14 23:43:27,245 INFO L87 Difference]: Start difference. First operand 1788 states and 2635 transitions. cyclomatic complexity: 848 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:27,313 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-14 23:43:27,313 INFO L93 Difference]: Finished difference Result 3430 states and 5046 transitions. [2021-12-14 23:43:27,313 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-14 23:43:27,314 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3430 states and 5046 transitions. [2021-12-14 23:43:27,325 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3250 [2021-12-14 23:43:27,338 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3430 states to 3430 states and 5046 transitions. [2021-12-14 23:43:27,338 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3430 [2021-12-14 23:43:27,339 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3430 [2021-12-14 23:43:27,339 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3430 states and 5046 transitions. [2021-12-14 23:43:27,342 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-14 23:43:27,342 INFO L681 BuchiCegarLoop]: Abstraction has 3430 states and 5046 transitions. [2021-12-14 23:43:27,344 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3430 states and 5046 transitions. [2021-12-14 23:43:27,430 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3430 to 1788. [2021-12-14 23:43:27,431 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4725950782997763) internal successors, (2633), 1787 states have internal predecessors, (2633), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:27,434 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2633 transitions. [2021-12-14 23:43:27,434 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2633 transitions. [2021-12-14 23:43:27,434 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2633 transitions. [2021-12-14 23:43:27,434 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-14 23:43:27,434 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2633 transitions. [2021-12-14 23:43:27,438 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-14 23:43:27,438 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-14 23:43:27,439 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-14 23:43:27,440 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:27,440 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:27,440 INFO L791 eck$LassoCheckResult]: Stem: 52612#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 52613#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 52133#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 52134#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 52188#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 53527#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 52621#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 52424#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 51823#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 51824#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53046#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 53159#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 53593#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 53594#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 52552#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 52553#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 53075#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 52994#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 52587#L1201 assume !(0 == ~M_E~0); 52588#L1201-2 assume !(0 == ~T1_E~0); 53434#L1206-1 assume !(0 == ~T2_E~0); 53420#L1211-1 assume !(0 == ~T3_E~0); 53421#L1216-1 assume !(0 == ~T4_E~0); 52409#L1221-1 assume !(0 == ~T5_E~0); 52410#L1226-1 assume !(0 == ~T6_E~0); 52048#L1231-1 assume !(0 == ~T7_E~0); 52049#L1236-1 assume !(0 == ~T8_E~0); 53457#L1241-1 assume !(0 == ~T9_E~0); 52448#L1246-1 assume !(0 == ~T10_E~0); 52449#L1251-1 assume !(0 == ~T11_E~0); 52585#L1256-1 assume !(0 == ~T12_E~0); 51836#L1261-1 assume !(0 == ~E_M~0); 51837#L1266-1 assume !(0 == ~E_1~0); 53579#L1271-1 assume !(0 == ~E_2~0); 53141#L1276-1 assume !(0 == ~E_3~0); 53142#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 53089#L1286-1 assume !(0 == ~E_5~0); 52299#L1291-1 assume !(0 == ~E_6~0); 52300#L1296-1 assume !(0 == ~E_7~0); 52875#L1301-1 assume !(0 == ~E_8~0); 52876#L1306-1 assume !(0 == ~E_9~0); 53356#L1311-1 assume !(0 == ~E_10~0); 52250#L1316-1 assume !(0 == ~E_11~0); 52251#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 52893#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52894#L593 assume 1 == ~m_pc~0; 53038#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 52140#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53566#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53100#L1492 assume !(0 != activate_threads_~tmp~1#1); 53101#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53392#L612 assume !(1 == ~t1_pc~0); 53393#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 53522#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52522#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 52144#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52145#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52564#L631 assume 1 == ~t2_pc~0; 52499#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 51921#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51922#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 52758#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 52759#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52217#L650 assume !(1 == ~t3_pc~0); 52218#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 52918#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52141#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51874#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 51875#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53067#L669 assume 1 == ~t4_pc~0; 53068#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53426#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 52551#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 52083#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 52084#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 52308#L688 assume !(1 == ~t5_pc~0); 52099#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 52100#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53018#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 52952#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 52953#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53085#L707 assume 1 == ~t6_pc~0; 53491#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 52728#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 52729#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 53489#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 53026#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 52586#L726 assume 1 == ~t7_pc~0; 52487#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 52184#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53225#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53499#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 51953#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 51954#L745 assume !(1 == ~t8_pc~0); 52401#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 52420#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53258#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 52806#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 52807#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53317#L764 assume 1 == ~t9_pc~0; 52584#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 52426#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53103#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 53550#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 51973#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 51974#L783 assume !(1 == ~t10_pc~0); 52035#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 52036#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 52077#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 52078#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 52545#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 53428#L802 assume 1 == ~t11_pc~0; 53410#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 51918#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 51919#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 52411#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 52412#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 52521#L821 assume !(1 == ~t12_pc~0); 52772#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 52868#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 51925#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 51926#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 53466#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53112#L1339 assume !(1 == ~M_E~0); 53113#L1339-2 assume !(1 == ~T1_E~0); 53501#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 53502#L1349-1 assume !(1 == ~T3_E~0); 52887#L1354-1 assume !(1 == ~T4_E~0); 52888#L1359-1 assume !(1 == ~T5_E~0); 53290#L1364-1 assume !(1 == ~T6_E~0); 52351#L1369-1 assume !(1 == ~T7_E~0); 52352#L1374-1 assume !(1 == ~T8_E~0); 52891#L1379-1 assume !(1 == ~T9_E~0); 52892#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 52989#L1389-1 assume !(1 == ~T11_E~0); 53460#L1394-1 assume !(1 == ~T12_E~0); 53461#L1399-1 assume !(1 == ~E_M~0); 53551#L1404-1 assume !(1 == ~E_1~0); 52452#L1409-1 assume !(1 == ~E_2~0); 52453#L1414-1 assume !(1 == ~E_3~0); 53177#L1419-1 assume !(1 == ~E_4~0); 52091#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 52092#L1429-1 assume !(1 == ~E_6~0); 52902#L1434-1 assume !(1 == ~E_7~0); 53481#L1439-1 assume !(1 == ~E_8~0); 52129#L1444-1 assume !(1 == ~E_9~0); 52130#L1449-1 assume !(1 == ~E_10~0); 52504#L1454-1 assume !(1 == ~E_11~0); 52505#L1459-1 assume !(1 == ~E_12~0); 53023#L1464-1 assume { :end_inline_reset_delta_events } true; 52263#L1810-2 [2021-12-14 23:43:27,440 INFO L793 eck$LassoCheckResult]: Loop: 52263#L1810-2 assume !false; 52707#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 52626#L1176 assume !false; 53185#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 52757#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 51961#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 52511#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 52512#L1003 assume !(0 != eval_~tmp~0#1); 52155#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 52156#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 53344#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 53127#L1201-5 assume !(0 == ~T1_E~0); 53128#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 53022#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 52212#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 52213#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 52679#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 52285#L1231-3 assume !(0 == ~T7_E~0); 52286#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 52532#L1241-3 assume !(0 == ~T9_E~0); 53512#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 53414#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 53118#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 52230#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 52231#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 52275#L1271-3 assume !(0 == ~E_2~0); 52276#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 52652#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 52653#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 53174#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 53175#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 53590#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 53547#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 52764#L1311-3 assume !(0 == ~E_10~0); 52153#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 52154#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 52229#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52867#L593-42 assume !(1 == ~m_pc~0); 53024#L593-44 is_master_triggered_~__retres1~0#1 := 0; 53025#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53574#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53575#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 52051#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52052#L612-42 assume !(1 == ~t1_pc~0); 52976#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 53369#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53490#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 52142#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52143#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52838#L631-42 assume 1 == ~t2_pc~0; 51907#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 51908#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52827#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 52703#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 52704#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52304#L650-42 assume 1 == ~t3_pc~0; 51866#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 51867#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53518#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 52497#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 52498#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53482#L669-42 assume !(1 == ~t4_pc~0); 51864#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 51865#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53293#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53183#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 53080#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53081#L688-42 assume 1 == ~t5_pc~0; 53172#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 53373#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 52005#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 52006#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 52079#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 51896#L707-42 assume !(1 == ~t6_pc~0); 51897#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 53554#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53298#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 53299#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 53048#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53049#L726-42 assume 1 == ~t7_pc~0; 53326#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 53352#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53353#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 52767#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 52768#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 52871#L745-42 assume 1 == ~t8_pc~0; 52907#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 52909#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 52237#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 51882#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 51883#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 52608#L764-42 assume 1 == ~t9_pc~0; 52744#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 53097#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53098#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 52168#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 52169#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 52222#L783-42 assume !(1 == ~t10_pc~0); 51840#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 51839#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 52434#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 52567#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53584#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 53268#L802-42 assume 1 == ~t11_pc~0; 52369#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 51980#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 51981#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 51931#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 51932#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53108#L821-42 assume 1 == ~t12_pc~0; 53109#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 52474#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 51834#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 51835#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 52814#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52804#L1339-3 assume !(1 == ~M_E~0); 52805#L1339-5 assume !(1 == ~T1_E~0); 52956#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 53066#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 52483#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 52484#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 53077#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 53573#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 53480#L1374-3 assume !(1 == ~T8_E~0); 52305#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 52306#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 52481#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 52482#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 52691#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 53487#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 53455#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 53456#L1414-3 assume !(1 == ~E_3~0); 53511#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53270#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 52189#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 52190#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 53076#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 52117#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 52118#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 52234#L1454-3 assume !(1 == ~E_11~0); 53071#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 53072#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 52730#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 52027#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 52287#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 52288#L1829 assume !(0 == start_simulation_~tmp~3#1); 52009#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 52010#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 52810#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 52811#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 53090#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 53091#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 52711#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 52262#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 52263#L1810-2 [2021-12-14 23:43:27,441 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:27,441 INFO L85 PathProgramCache]: Analyzing trace with hash -1227548684, now seen corresponding path program 1 times [2021-12-14 23:43:27,441 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:27,441 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1271885574] [2021-12-14 23:43:27,441 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:27,442 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:27,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:27,465 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:27,465 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:27,465 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1271885574] [2021-12-14 23:43:27,465 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1271885574] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:27,465 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:27,466 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:27,466 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1526354031] [2021-12-14 23:43:27,466 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:27,466 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-14 23:43:27,466 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:27,466 INFO L85 PathProgramCache]: Analyzing trace with hash -34163050, now seen corresponding path program 1 times [2021-12-14 23:43:27,467 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:27,467 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1627486241] [2021-12-14 23:43:27,467 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:27,467 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:27,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:27,489 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:27,490 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:27,490 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1627486241] [2021-12-14 23:43:27,490 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1627486241] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:27,490 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:27,491 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:27,491 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [285867446] [2021-12-14 23:43:27,491 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:27,491 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-14 23:43:27,491 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-14 23:43:27,492 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-14 23:43:27,492 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-14 23:43:27,492 INFO L87 Difference]: Start difference. First operand 1788 states and 2633 transitions. cyclomatic complexity: 846 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:27,599 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-14 23:43:27,599 INFO L93 Difference]: Finished difference Result 3330 states and 4896 transitions. [2021-12-14 23:43:27,599 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-14 23:43:27,600 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3330 states and 4896 transitions. [2021-12-14 23:43:27,609 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3157 [2021-12-14 23:43:27,615 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3330 states to 3330 states and 4896 transitions. [2021-12-14 23:43:27,615 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3330 [2021-12-14 23:43:27,616 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3330 [2021-12-14 23:43:27,616 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3330 states and 4896 transitions. [2021-12-14 23:43:27,619 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-14 23:43:27,619 INFO L681 BuchiCegarLoop]: Abstraction has 3330 states and 4896 transitions. [2021-12-14 23:43:27,621 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3330 states and 4896 transitions. [2021-12-14 23:43:27,634 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3330 to 1788. [2021-12-14 23:43:27,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.471476510067114) internal successors, (2631), 1787 states have internal predecessors, (2631), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:27,638 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2631 transitions. [2021-12-14 23:43:27,638 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2631 transitions. [2021-12-14 23:43:27,638 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2631 transitions. [2021-12-14 23:43:27,638 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-14 23:43:27,638 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2631 transitions. [2021-12-14 23:43:27,644 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-14 23:43:27,644 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-14 23:43:27,644 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-14 23:43:27,645 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:27,645 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:27,646 INFO L791 eck$LassoCheckResult]: Stem: 57740#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 57741#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 57261#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 57262#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 57316#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 58655#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 57749#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 57552#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 56951#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 56952#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 58174#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 58285#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 58721#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 58722#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 57680#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 57681#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 58203#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 58122#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 57715#L1201 assume !(0 == ~M_E~0); 57716#L1201-2 assume !(0 == ~T1_E~0); 58562#L1206-1 assume !(0 == ~T2_E~0); 58548#L1211-1 assume !(0 == ~T3_E~0); 58549#L1216-1 assume !(0 == ~T4_E~0); 57536#L1221-1 assume !(0 == ~T5_E~0); 57537#L1226-1 assume !(0 == ~T6_E~0); 57176#L1231-1 assume !(0 == ~T7_E~0); 57177#L1236-1 assume !(0 == ~T8_E~0); 58585#L1241-1 assume !(0 == ~T9_E~0); 57573#L1246-1 assume !(0 == ~T10_E~0); 57574#L1251-1 assume !(0 == ~T11_E~0); 57713#L1256-1 assume !(0 == ~T12_E~0); 56962#L1261-1 assume !(0 == ~E_M~0); 56963#L1266-1 assume !(0 == ~E_1~0); 58707#L1271-1 assume !(0 == ~E_2~0); 58269#L1276-1 assume !(0 == ~E_3~0); 58270#L1281-1 assume !(0 == ~E_4~0); 58217#L1286-1 assume !(0 == ~E_5~0); 57427#L1291-1 assume !(0 == ~E_6~0); 57428#L1296-1 assume !(0 == ~E_7~0); 58003#L1301-1 assume !(0 == ~E_8~0); 58004#L1306-1 assume !(0 == ~E_9~0); 58484#L1311-1 assume !(0 == ~E_10~0); 57378#L1316-1 assume !(0 == ~E_11~0); 57379#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 58021#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 58022#L593 assume 1 == ~m_pc~0; 58166#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 57268#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58694#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 58228#L1492 assume !(0 != activate_threads_~tmp~1#1); 58229#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 58520#L612 assume !(1 == ~t1_pc~0); 58521#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 58650#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 57650#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 57272#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 57273#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 57692#L631 assume 1 == ~t2_pc~0; 57627#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 57049#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 57050#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 57886#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 57887#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 57345#L650 assume !(1 == ~t3_pc~0); 57346#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 58046#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 57269#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 57002#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 57003#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58195#L669 assume 1 == ~t4_pc~0; 58196#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 58554#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 57679#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 57211#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 57212#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 57436#L688 assume !(1 == ~t5_pc~0); 57227#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 57228#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58146#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 58080#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 58081#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58210#L707 assume 1 == ~t6_pc~0; 58619#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 57856#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 57857#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 58617#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 58152#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 57714#L726 assume 1 == ~t7_pc~0; 57613#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 57312#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 58353#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 58627#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 57081#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 57082#L745 assume !(1 == ~t8_pc~0); 57529#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 57548#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 58386#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 57934#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 57935#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 58445#L764 assume 1 == ~t9_pc~0; 57712#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 57554#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 58231#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 58678#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 57101#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 57102#L783 assume !(1 == ~t10_pc~0); 57163#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 57164#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 57205#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 57206#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 57668#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 58556#L802 assume 1 == ~t11_pc~0; 58538#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 57046#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 57047#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 57538#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 57539#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 57649#L821 assume !(1 == ~t12_pc~0); 57900#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 57996#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 57051#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 57052#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 58594#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 58240#L1339 assume !(1 == ~M_E~0); 58241#L1339-2 assume !(1 == ~T1_E~0); 58629#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 58630#L1349-1 assume !(1 == ~T3_E~0); 58014#L1354-1 assume !(1 == ~T4_E~0); 58015#L1359-1 assume !(1 == ~T5_E~0); 58416#L1364-1 assume !(1 == ~T6_E~0); 57479#L1369-1 assume !(1 == ~T7_E~0); 57480#L1374-1 assume !(1 == ~T8_E~0); 58017#L1379-1 assume !(1 == ~T9_E~0); 58018#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 58117#L1389-1 assume !(1 == ~T11_E~0); 58588#L1394-1 assume !(1 == ~T12_E~0); 58589#L1399-1 assume !(1 == ~E_M~0); 58679#L1404-1 assume !(1 == ~E_1~0); 57578#L1409-1 assume !(1 == ~E_2~0); 57579#L1414-1 assume !(1 == ~E_3~0); 58305#L1419-1 assume !(1 == ~E_4~0); 57219#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 57220#L1429-1 assume !(1 == ~E_6~0); 58030#L1434-1 assume !(1 == ~E_7~0); 58609#L1439-1 assume !(1 == ~E_8~0); 57257#L1444-1 assume !(1 == ~E_9~0); 57258#L1449-1 assume !(1 == ~E_10~0); 57632#L1454-1 assume !(1 == ~E_11~0); 57633#L1459-1 assume !(1 == ~E_12~0); 58151#L1464-1 assume { :end_inline_reset_delta_events } true; 57391#L1810-2 [2021-12-14 23:43:27,646 INFO L793 eck$LassoCheckResult]: Loop: 57391#L1810-2 assume !false; 57835#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 57751#L1176 assume !false; 58313#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 57883#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 57089#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 57639#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 57640#L1003 assume !(0 != eval_~tmp~0#1); 57281#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 57282#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 58472#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 58255#L1201-5 assume !(0 == ~T1_E~0); 58256#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 58149#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 57340#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 57341#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 57807#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 57411#L1231-3 assume !(0 == ~T7_E~0); 57412#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 57658#L1241-3 assume !(0 == ~T9_E~0); 58640#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 58541#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 58246#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 57357#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 57358#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 57403#L1271-3 assume !(0 == ~E_2~0); 57404#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 57780#L1281-3 assume !(0 == ~E_4~0); 57781#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 58302#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 58303#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 58718#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 58675#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 57892#L1311-3 assume !(0 == ~E_10~0); 57283#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 57284#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 57359#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57995#L593-42 assume 1 == ~m_pc~0; 58388#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 58154#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58703#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 58704#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 57182#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 57183#L612-42 assume !(1 == ~t1_pc~0); 58104#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 58497#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 58618#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 57270#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 57271#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 57966#L631-42 assume 1 == ~t2_pc~0; 57035#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 57036#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 57955#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 57831#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 57832#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 57432#L650-42 assume 1 == ~t3_pc~0; 56994#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 56995#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58646#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 57625#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 57626#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58610#L669-42 assume !(1 == ~t4_pc~0); 56992#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 56993#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58421#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 58311#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 58208#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 58209#L688-42 assume 1 == ~t5_pc~0; 58300#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 58501#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 57133#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 57134#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 57210#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 57024#L707-42 assume !(1 == ~t6_pc~0); 57025#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 58682#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58426#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 58427#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 58176#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58177#L726-42 assume 1 == ~t7_pc~0; 58454#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 58480#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 58481#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 57895#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 57896#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 57999#L745-42 assume 1 == ~t8_pc~0; 58036#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 58038#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 57365#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 57010#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 57011#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 57736#L764-42 assume 1 == ~t9_pc~0; 57872#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 58225#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 58226#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 57296#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 57297#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 57350#L783-42 assume 1 == ~t10_pc~0; 56966#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 56967#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 57562#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 57695#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 58712#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 58396#L802-42 assume 1 == ~t11_pc~0; 57497#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 57108#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 57109#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 57059#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 57060#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 58236#L821-42 assume !(1 == ~t12_pc~0); 57601#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 57602#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 56964#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 56965#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 57942#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57932#L1339-3 assume !(1 == ~M_E~0); 57933#L1339-5 assume !(1 == ~T1_E~0); 58084#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 58194#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 57611#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 57612#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 58205#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 58701#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 58608#L1374-3 assume !(1 == ~T8_E~0); 57433#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 57434#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 57609#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 57610#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 57819#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 58615#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 58583#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 58584#L1414-3 assume !(1 == ~E_3~0); 58639#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 58398#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 57317#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 57318#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 58204#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 57245#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 57246#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 57362#L1454-3 assume !(1 == ~E_11~0); 58199#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 58200#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 57858#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 57155#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 57415#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 57416#L1829 assume !(0 == start_simulation_~tmp~3#1); 57137#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 57138#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 57938#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 57939#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 58218#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 58219#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 57839#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 57390#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 57391#L1810-2 [2021-12-14 23:43:27,647 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:27,647 INFO L85 PathProgramCache]: Analyzing trace with hash 701383542, now seen corresponding path program 1 times [2021-12-14 23:43:27,647 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:27,647 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2050780306] [2021-12-14 23:43:27,647 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:27,647 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:27,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:27,669 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:27,669 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:27,669 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2050780306] [2021-12-14 23:43:27,669 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2050780306] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:27,669 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:27,670 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:27,670 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1727657196] [2021-12-14 23:43:27,670 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:27,670 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-14 23:43:27,670 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:27,671 INFO L85 PathProgramCache]: Analyzing trace with hash -999925801, now seen corresponding path program 1 times [2021-12-14 23:43:27,671 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:27,671 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [962140647] [2021-12-14 23:43:27,671 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:27,671 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:27,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:27,694 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:27,694 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:27,694 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [962140647] [2021-12-14 23:43:27,694 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [962140647] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:27,694 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:27,694 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:27,695 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [72059971] [2021-12-14 23:43:27,695 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:27,695 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-14 23:43:27,695 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-14 23:43:27,695 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-14 23:43:27,696 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-14 23:43:27,696 INFO L87 Difference]: Start difference. First operand 1788 states and 2631 transitions. cyclomatic complexity: 844 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:27,804 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-14 23:43:27,804 INFO L93 Difference]: Finished difference Result 3322 states and 4877 transitions. [2021-12-14 23:43:27,804 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-14 23:43:27,805 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3322 states and 4877 transitions. [2021-12-14 23:43:27,815 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3157 [2021-12-14 23:43:27,821 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3322 states to 3322 states and 4877 transitions. [2021-12-14 23:43:27,821 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3322 [2021-12-14 23:43:27,823 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3322 [2021-12-14 23:43:27,823 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3322 states and 4877 transitions. [2021-12-14 23:43:27,825 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-14 23:43:27,825 INFO L681 BuchiCegarLoop]: Abstraction has 3322 states and 4877 transitions. [2021-12-14 23:43:27,827 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3322 states and 4877 transitions. [2021-12-14 23:43:27,844 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3322 to 1788. [2021-12-14 23:43:27,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.470357941834452) internal successors, (2629), 1787 states have internal predecessors, (2629), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:27,848 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2629 transitions. [2021-12-14 23:43:27,848 INFO L704 BuchiCegarLoop]: Abstraction has 1788 states and 2629 transitions. [2021-12-14 23:43:27,848 INFO L587 BuchiCegarLoop]: Abstraction has 1788 states and 2629 transitions. [2021-12-14 23:43:27,848 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-14 23:43:27,848 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2629 transitions. [2021-12-14 23:43:27,852 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2021-12-14 23:43:27,852 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-14 23:43:27,852 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-14 23:43:27,853 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:27,853 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:27,853 INFO L791 eck$LassoCheckResult]: Stem: 62860#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 62861#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 62381#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 62382#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 62436#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 63775#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 62869#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 62672#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 62071#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 62072#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 63294#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 63405#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 63841#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 63842#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 62800#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 62801#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 63323#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 63242#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 62835#L1201 assume !(0 == ~M_E~0); 62836#L1201-2 assume !(0 == ~T1_E~0); 63682#L1206-1 assume !(0 == ~T2_E~0); 63668#L1211-1 assume !(0 == ~T3_E~0); 63669#L1216-1 assume !(0 == ~T4_E~0); 62656#L1221-1 assume !(0 == ~T5_E~0); 62657#L1226-1 assume !(0 == ~T6_E~0); 62296#L1231-1 assume !(0 == ~T7_E~0); 62297#L1236-1 assume !(0 == ~T8_E~0); 63705#L1241-1 assume !(0 == ~T9_E~0); 62693#L1246-1 assume !(0 == ~T10_E~0); 62694#L1251-1 assume !(0 == ~T11_E~0); 62833#L1256-1 assume !(0 == ~T12_E~0); 62082#L1261-1 assume !(0 == ~E_M~0); 62083#L1266-1 assume !(0 == ~E_1~0); 63827#L1271-1 assume !(0 == ~E_2~0); 63389#L1276-1 assume !(0 == ~E_3~0); 63390#L1281-1 assume !(0 == ~E_4~0); 63337#L1286-1 assume !(0 == ~E_5~0); 62547#L1291-1 assume !(0 == ~E_6~0); 62548#L1296-1 assume !(0 == ~E_7~0); 63123#L1301-1 assume !(0 == ~E_8~0); 63124#L1306-1 assume !(0 == ~E_9~0); 63604#L1311-1 assume !(0 == ~E_10~0); 62498#L1316-1 assume !(0 == ~E_11~0); 62499#L1321-1 assume !(0 == ~E_12~0); 63141#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 63142#L593 assume 1 == ~m_pc~0; 63286#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 62388#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 63814#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 63348#L1492 assume !(0 != activate_threads_~tmp~1#1); 63349#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63640#L612 assume !(1 == ~t1_pc~0); 63641#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 63770#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62770#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 62392#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62393#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62812#L631 assume 1 == ~t2_pc~0; 62747#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 62169#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62170#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 63006#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 63007#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62465#L650 assume !(1 == ~t3_pc~0); 62466#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 63166#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62389#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 62122#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 62123#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 63315#L669 assume 1 == ~t4_pc~0; 63316#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 63674#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62799#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 62331#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 62332#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62556#L688 assume !(1 == ~t5_pc~0); 62347#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 62348#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63266#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 63200#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 63201#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 63330#L707 assume 1 == ~t6_pc~0; 63739#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 62976#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 62977#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 63737#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 63272#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62834#L726 assume 1 == ~t7_pc~0; 62733#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 62432#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 63473#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 63747#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 62201#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 62202#L745 assume !(1 == ~t8_pc~0); 62649#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 62668#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 63506#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 63054#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 63055#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 63565#L764 assume 1 == ~t9_pc~0; 62832#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 62674#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 63351#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 63798#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 62221#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 62222#L783 assume !(1 == ~t10_pc~0); 62283#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 62284#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 62325#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 62326#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 62788#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 63676#L802 assume 1 == ~t11_pc~0; 63658#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 62166#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 62167#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 62658#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 62659#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 62769#L821 assume !(1 == ~t12_pc~0); 63020#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 63116#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 62171#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 62172#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 63714#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 63360#L1339 assume !(1 == ~M_E~0); 63361#L1339-2 assume !(1 == ~T1_E~0); 63749#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 63750#L1349-1 assume !(1 == ~T3_E~0); 63134#L1354-1 assume !(1 == ~T4_E~0); 63135#L1359-1 assume !(1 == ~T5_E~0); 63536#L1364-1 assume !(1 == ~T6_E~0); 62599#L1369-1 assume !(1 == ~T7_E~0); 62600#L1374-1 assume !(1 == ~T8_E~0); 63137#L1379-1 assume !(1 == ~T9_E~0); 63138#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 63237#L1389-1 assume !(1 == ~T11_E~0); 63708#L1394-1 assume !(1 == ~T12_E~0); 63709#L1399-1 assume !(1 == ~E_M~0); 63799#L1404-1 assume !(1 == ~E_1~0); 62698#L1409-1 assume !(1 == ~E_2~0); 62699#L1414-1 assume !(1 == ~E_3~0); 63425#L1419-1 assume !(1 == ~E_4~0); 62339#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 62340#L1429-1 assume !(1 == ~E_6~0); 63150#L1434-1 assume !(1 == ~E_7~0); 63729#L1439-1 assume !(1 == ~E_8~0); 62377#L1444-1 assume !(1 == ~E_9~0); 62378#L1449-1 assume !(1 == ~E_10~0); 62752#L1454-1 assume !(1 == ~E_11~0); 62753#L1459-1 assume !(1 == ~E_12~0); 63271#L1464-1 assume { :end_inline_reset_delta_events } true; 62511#L1810-2 [2021-12-14 23:43:27,854 INFO L793 eck$LassoCheckResult]: Loop: 62511#L1810-2 assume !false; 62955#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 62871#L1176 assume !false; 63433#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 63003#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 62209#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 62759#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 62760#L1003 assume !(0 != eval_~tmp~0#1); 62401#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 62402#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 63592#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 63375#L1201-5 assume !(0 == ~T1_E~0); 63376#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 63269#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 62460#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 62461#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 62927#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 62531#L1231-3 assume !(0 == ~T7_E~0); 62532#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 62778#L1241-3 assume !(0 == ~T9_E~0); 63760#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 63661#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 63366#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 62477#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 62478#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 62523#L1271-3 assume !(0 == ~E_2~0); 62524#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 62900#L1281-3 assume !(0 == ~E_4~0); 62901#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 63422#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 63423#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 63838#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 63795#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 63012#L1311-3 assume !(0 == ~E_10~0); 62403#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 62404#L1321-3 assume !(0 == ~E_12~0); 62479#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 63115#L593-42 assume 1 == ~m_pc~0; 63508#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 63274#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 63823#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 63824#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 62302#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 62303#L612-42 assume !(1 == ~t1_pc~0); 63224#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 63617#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63738#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 62390#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62391#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63086#L631-42 assume 1 == ~t2_pc~0; 62155#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 62156#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 63075#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 62951#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 62952#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62552#L650-42 assume 1 == ~t3_pc~0; 62114#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 62115#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 63766#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 62745#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 62746#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 63730#L669-42 assume !(1 == ~t4_pc~0); 62112#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 62113#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 63541#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 63431#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 63328#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 63329#L688-42 assume 1 == ~t5_pc~0; 63420#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 63621#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 62253#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 62254#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 62330#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 62144#L707-42 assume !(1 == ~t6_pc~0); 62145#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 63802#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 63546#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 63547#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 63296#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 63297#L726-42 assume 1 == ~t7_pc~0; 63574#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 63600#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 63601#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 63015#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 63016#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 63119#L745-42 assume 1 == ~t8_pc~0; 63156#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 63158#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 62485#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 62130#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 62131#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 62856#L764-42 assume 1 == ~t9_pc~0; 62992#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 63345#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 63346#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 62416#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 62417#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 62470#L783-42 assume 1 == ~t10_pc~0; 62086#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 62087#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 62682#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 62815#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 63832#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 63516#L802-42 assume 1 == ~t11_pc~0; 62617#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 62228#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 62229#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 62179#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 62180#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 63356#L821-42 assume !(1 == ~t12_pc~0); 62721#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 62722#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 62084#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 62085#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 63062#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 63052#L1339-3 assume !(1 == ~M_E~0); 63053#L1339-5 assume !(1 == ~T1_E~0); 63204#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 63314#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 62731#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 62732#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 63325#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 63821#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 63728#L1374-3 assume !(1 == ~T8_E~0); 62553#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 62554#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 62729#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 62730#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 62939#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 63735#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 63703#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 63704#L1414-3 assume !(1 == ~E_3~0); 63759#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 63518#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 62437#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 62438#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 63324#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 62365#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 62366#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 62482#L1454-3 assume !(1 == ~E_11~0); 63319#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 63320#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 62978#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 62275#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 62535#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 62536#L1829 assume !(0 == start_simulation_~tmp~3#1); 62257#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 62258#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 63058#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 63059#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 63338#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 63339#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 62959#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 62510#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 62511#L1810-2 [2021-12-14 23:43:27,854 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:27,854 INFO L85 PathProgramCache]: Analyzing trace with hash -1440476936, now seen corresponding path program 1 times [2021-12-14 23:43:27,854 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:27,855 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1754593558] [2021-12-14 23:43:27,855 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:27,855 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:27,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:27,875 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:27,875 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:27,875 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1754593558] [2021-12-14 23:43:27,876 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1754593558] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:27,876 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:27,876 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-14 23:43:27,876 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1285835649] [2021-12-14 23:43:27,876 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:27,876 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-14 23:43:27,877 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:27,877 INFO L85 PathProgramCache]: Analyzing trace with hash 2012869209, now seen corresponding path program 1 times [2021-12-14 23:43:27,877 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:27,877 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [106464967] [2021-12-14 23:43:27,877 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:27,877 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:27,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:27,900 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:27,901 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:27,901 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [106464967] [2021-12-14 23:43:27,901 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [106464967] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:27,901 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:27,901 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:27,901 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [872423914] [2021-12-14 23:43:27,901 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:27,902 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-14 23:43:27,902 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-14 23:43:27,902 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-14 23:43:27,902 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-14 23:43:27,903 INFO L87 Difference]: Start difference. First operand 1788 states and 2629 transitions. cyclomatic complexity: 842 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:27,993 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-14 23:43:27,993 INFO L93 Difference]: Finished difference Result 3391 states and 4949 transitions. [2021-12-14 23:43:27,994 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-14 23:43:27,994 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3391 states and 4949 transitions. [2021-12-14 23:43:28,003 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3228 [2021-12-14 23:43:28,019 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3391 states to 3391 states and 4949 transitions. [2021-12-14 23:43:28,020 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3391 [2021-12-14 23:43:28,022 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3391 [2021-12-14 23:43:28,022 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3391 states and 4949 transitions. [2021-12-14 23:43:28,025 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-14 23:43:28,025 INFO L681 BuchiCegarLoop]: Abstraction has 3391 states and 4949 transitions. [2021-12-14 23:43:28,027 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3391 states and 4949 transitions. [2021-12-14 23:43:28,093 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3391 to 3301. [2021-12-14 23:43:28,096 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3301 states, 3301 states have (on average 1.4607694637988489) internal successors, (4822), 3300 states have internal predecessors, (4822), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:28,100 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3301 states to 3301 states and 4822 transitions. [2021-12-14 23:43:28,100 INFO L704 BuchiCegarLoop]: Abstraction has 3301 states and 4822 transitions. [2021-12-14 23:43:28,100 INFO L587 BuchiCegarLoop]: Abstraction has 3301 states and 4822 transitions. [2021-12-14 23:43:28,100 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-14 23:43:28,100 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3301 states and 4822 transitions. [2021-12-14 23:43:28,106 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3138 [2021-12-14 23:43:28,106 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-14 23:43:28,106 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-14 23:43:28,107 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:28,108 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:28,108 INFO L791 eck$LassoCheckResult]: Stem: 68047#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 68048#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 67565#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 67566#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 67620#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 68986#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 68056#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 67858#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 67257#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 67258#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 68486#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 68600#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 69062#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 69063#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 67986#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 67987#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 68516#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 68431#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 68022#L1201 assume !(0 == ~M_E~0); 68023#L1201-2 assume !(0 == ~T1_E~0); 68884#L1206-1 assume !(0 == ~T2_E~0); 68869#L1211-1 assume !(0 == ~T3_E~0); 68870#L1216-1 assume !(0 == ~T4_E~0); 67843#L1221-1 assume !(0 == ~T5_E~0); 67844#L1226-1 assume !(0 == ~T6_E~0); 67480#L1231-1 assume !(0 == ~T7_E~0); 67481#L1236-1 assume !(0 == ~T8_E~0); 68911#L1241-1 assume !(0 == ~T9_E~0); 67882#L1246-1 assume !(0 == ~T10_E~0); 67883#L1251-1 assume !(0 == ~T11_E~0); 68020#L1256-1 assume !(0 == ~T12_E~0); 67269#L1261-1 assume !(0 == ~E_M~0); 67270#L1266-1 assume !(0 == ~E_1~0); 69047#L1271-1 assume !(0 == ~E_2~0); 68582#L1276-1 assume !(0 == ~E_3~0); 68583#L1281-1 assume !(0 == ~E_4~0); 68530#L1286-1 assume !(0 == ~E_5~0); 67731#L1291-1 assume !(0 == ~E_6~0); 67732#L1296-1 assume !(0 == ~E_7~0); 68310#L1301-1 assume !(0 == ~E_8~0); 68311#L1306-1 assume !(0 == ~E_9~0); 68805#L1311-1 assume !(0 == ~E_10~0); 67682#L1316-1 assume !(0 == ~E_11~0); 67683#L1321-1 assume !(0 == ~E_12~0); 68328#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68329#L593 assume !(1 == ~m_pc~0); 67571#L593-2 is_master_triggered_~__retres1~0#1 := 0; 67572#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69031#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 68541#L1492 assume !(0 != activate_threads_~tmp~1#1); 68542#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68841#L612 assume !(1 == ~t1_pc~0); 68842#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 68981#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 67956#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 67576#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 67577#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 67998#L631 assume 1 == ~t2_pc~0; 67933#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 67354#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 67355#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 68193#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 68194#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67649#L650 assume !(1 == ~t3_pc~0); 67650#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 68354#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 67573#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 67307#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 67308#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68508#L669 assume 1 == ~t4_pc~0; 68509#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 68875#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 67985#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 67515#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 67516#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 67740#L688 assume !(1 == ~t5_pc~0); 67531#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 67532#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 68456#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 68388#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 68389#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 68526#L707 assume 1 == ~t6_pc~0; 68947#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 68162#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 68163#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 68945#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 68467#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 68021#L726 assume 1 == ~t7_pc~0; 67921#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 67616#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 68667#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 68955#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 67386#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 67387#L745 assume !(1 == ~t8_pc~0); 67835#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 67854#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 68702#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 68241#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 68242#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 68766#L764 assume 1 == ~t9_pc~0; 68019#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 67860#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 68544#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 69013#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 67406#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 67407#L783 assume !(1 == ~t10_pc~0); 67468#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 67469#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 67509#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 67510#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 67979#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 68877#L802 assume 1 == ~t11_pc~0; 68859#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 67351#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 67352#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 67845#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 67846#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 67955#L821 assume !(1 == ~t12_pc~0); 68207#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 68303#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 67358#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 67359#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 68921#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68553#L1339 assume !(1 == ~M_E~0); 68554#L1339-2 assume !(1 == ~T1_E~0); 68958#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 68959#L1349-1 assume !(1 == ~T3_E~0); 68322#L1354-1 assume !(1 == ~T4_E~0); 68323#L1359-1 assume !(1 == ~T5_E~0); 68738#L1364-1 assume !(1 == ~T6_E~0); 67785#L1369-1 assume !(1 == ~T7_E~0); 67786#L1374-1 assume !(1 == ~T8_E~0); 68326#L1379-1 assume !(1 == ~T9_E~0); 68327#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 68426#L1389-1 assume !(1 == ~T11_E~0); 68914#L1394-1 assume !(1 == ~T12_E~0); 68915#L1399-1 assume !(1 == ~E_M~0); 69014#L1404-1 assume !(1 == ~E_1~0); 67886#L1409-1 assume !(1 == ~E_2~0); 67887#L1414-1 assume !(1 == ~E_3~0); 68619#L1419-1 assume !(1 == ~E_4~0); 67523#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 67524#L1429-1 assume !(1 == ~E_6~0); 68337#L1434-1 assume !(1 == ~E_7~0); 68936#L1439-1 assume !(1 == ~E_8~0); 67561#L1444-1 assume !(1 == ~E_9~0); 67562#L1449-1 assume !(1 == ~E_10~0); 67938#L1454-1 assume !(1 == ~E_11~0); 67939#L1459-1 assume !(1 == ~E_12~0); 68461#L1464-1 assume { :end_inline_reset_delta_events } true; 67695#L1810-2 [2021-12-14 23:43:28,108 INFO L793 eck$LassoCheckResult]: Loop: 67695#L1810-2 assume !false; 68141#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 68058#L1176 assume !false; 68627#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 68190#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 67394#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 67945#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 67946#L1003 assume !(0 != eval_~tmp~0#1); 67585#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 67586#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 68793#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 68568#L1201-5 assume !(0 == ~T1_E~0); 68569#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 68459#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 67644#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 67645#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 68114#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 67715#L1231-3 assume !(0 == ~T7_E~0); 67716#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 67964#L1241-3 assume !(0 == ~T9_E~0); 68971#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 68862#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 68559#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 67661#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 67662#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 67705#L1271-3 assume !(0 == ~E_2~0); 67706#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 68087#L1281-3 assume !(0 == ~E_4~0); 68088#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 68616#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 68617#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 69059#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 69010#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 68199#L1311-3 assume !(0 == ~E_10~0); 67587#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 67588#L1321-3 assume !(0 == ~E_12~0); 67663#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68302#L593-42 assume !(1 == ~m_pc~0); 68902#L593-44 is_master_triggered_~__retres1~0#1 := 0; 70437#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 70436#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 70435#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 70434#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 70433#L612-42 assume 1 == ~t1_pc~0; 70432#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 70430#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 70429#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 70428#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 70427#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 70426#L631-42 assume !(1 == ~t2_pc~0); 70425#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 70423#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 70422#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 70421#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 70420#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 70419#L650-42 assume !(1 == ~t3_pc~0); 70417#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 70416#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 70415#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 70414#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 70413#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 70412#L669-42 assume !(1 == ~t4_pc~0); 70411#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 70409#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 70408#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 70407#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 70406#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 70405#L688-42 assume 1 == ~t5_pc~0; 70403#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 70402#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 70401#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 70400#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 70399#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 70398#L707-42 assume !(1 == ~t6_pc~0); 70397#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 70395#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 70394#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 70393#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 70392#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 70391#L726-42 assume 1 == ~t7_pc~0; 70389#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 70388#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 70387#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 70386#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 70385#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 70384#L745-42 assume 1 == ~t8_pc~0; 70383#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 70381#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 70380#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 70379#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 70378#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 70377#L764-42 assume 1 == ~t9_pc~0; 70375#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 70374#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 70373#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 70372#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 70371#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 70370#L783-42 assume 1 == ~t10_pc~0; 70369#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 70367#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 70366#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 70365#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 70364#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 70363#L802-42 assume 1 == ~t11_pc~0; 70361#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 70360#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 70359#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 70276#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 70275#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 70274#L821-42 assume 1 == ~t12_pc~0; 70273#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 70270#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 70268#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 70266#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 70264#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 70262#L1339-3 assume !(1 == ~M_E~0); 70260#L1339-5 assume !(1 == ~T1_E~0); 70258#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 70256#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 70254#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 70252#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 70250#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 70248#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 70246#L1374-3 assume !(1 == ~T8_E~0); 70244#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 70242#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 70240#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 70238#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 70236#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 70234#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 70232#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 70230#L1414-3 assume !(1 == ~E_3~0); 70228#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 70226#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 70224#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 70222#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 70220#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 70218#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 70216#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 69009#L1454-3 assume !(1 == ~E_11~0); 68512#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 68513#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 68164#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 67460#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 67719#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 67720#L1829 assume !(0 == start_simulation_~tmp~3#1); 67442#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 67443#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 68245#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 68246#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 68531#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 68532#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 68144#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 67694#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 67695#L1810-2 [2021-12-14 23:43:28,109 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:28,109 INFO L85 PathProgramCache]: Analyzing trace with hash -1153017031, now seen corresponding path program 1 times [2021-12-14 23:43:28,109 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:28,109 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1268114705] [2021-12-14 23:43:28,109 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:28,109 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:28,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:28,135 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:28,135 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:28,135 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1268114705] [2021-12-14 23:43:28,135 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1268114705] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:28,135 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:28,135 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-14 23:43:28,136 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [494003806] [2021-12-14 23:43:28,136 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:28,136 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-14 23:43:28,136 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:28,136 INFO L85 PathProgramCache]: Analyzing trace with hash -244327142, now seen corresponding path program 1 times [2021-12-14 23:43:28,136 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:28,137 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [870334467] [2021-12-14 23:43:28,137 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:28,137 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:28,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:28,156 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:28,157 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:28,157 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [870334467] [2021-12-14 23:43:28,157 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [870334467] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:28,157 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:28,157 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:28,157 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1915239744] [2021-12-14 23:43:28,157 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:28,158 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-14 23:43:28,158 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-14 23:43:28,158 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-14 23:43:28,158 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-14 23:43:28,158 INFO L87 Difference]: Start difference. First operand 3301 states and 4822 transitions. cyclomatic complexity: 1523 Second operand has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:28,372 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-14 23:43:28,373 INFO L93 Difference]: Finished difference Result 9341 states and 13615 transitions. [2021-12-14 23:43:28,373 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-14 23:43:28,373 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9341 states and 13615 transitions. [2021-12-14 23:43:28,397 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 8963 [2021-12-14 23:43:28,413 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9341 states to 9341 states and 13615 transitions. [2021-12-14 23:43:28,413 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9341 [2021-12-14 23:43:28,418 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9341 [2021-12-14 23:43:28,418 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9341 states and 13615 transitions. [2021-12-14 23:43:28,423 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-14 23:43:28,423 INFO L681 BuchiCegarLoop]: Abstraction has 9341 states and 13615 transitions. [2021-12-14 23:43:28,426 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9341 states and 13615 transitions. [2021-12-14 23:43:28,465 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9341 to 3391. [2021-12-14 23:43:28,468 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3391 states, 3391 states have (on average 1.4485402536125036) internal successors, (4912), 3390 states have internal predecessors, (4912), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:28,472 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3391 states to 3391 states and 4912 transitions. [2021-12-14 23:43:28,472 INFO L704 BuchiCegarLoop]: Abstraction has 3391 states and 4912 transitions. [2021-12-14 23:43:28,472 INFO L587 BuchiCegarLoop]: Abstraction has 3391 states and 4912 transitions. [2021-12-14 23:43:28,473 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-14 23:43:28,473 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3391 states and 4912 transitions. [2021-12-14 23:43:28,480 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3225 [2021-12-14 23:43:28,480 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-14 23:43:28,480 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-14 23:43:28,481 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:28,481 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:28,481 INFO L791 eck$LassoCheckResult]: Stem: 80703#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 80704#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 80220#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 80221#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 80275#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 81696#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 80712#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 80513#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 79912#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 79913#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 81158#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 81276#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 81781#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 81782#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 80642#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 80643#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 81187#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 81102#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 80678#L1201 assume !(0 == ~M_E~0); 80679#L1201-2 assume !(0 == ~T1_E~0); 81585#L1206-1 assume !(0 == ~T2_E~0); 81569#L1211-1 assume !(0 == ~T3_E~0); 81570#L1216-1 assume !(0 == ~T4_E~0); 80497#L1221-1 assume !(0 == ~T5_E~0); 80498#L1226-1 assume !(0 == ~T6_E~0); 80135#L1231-1 assume !(0 == ~T7_E~0); 80136#L1236-1 assume !(0 == ~T8_E~0); 81617#L1241-1 assume !(0 == ~T9_E~0); 80534#L1246-1 assume !(0 == ~T10_E~0); 80535#L1251-1 assume !(0 == ~T11_E~0); 80676#L1256-1 assume !(0 == ~T12_E~0); 79922#L1261-1 assume !(0 == ~E_M~0); 79923#L1266-1 assume !(0 == ~E_1~0); 81763#L1271-1 assume !(0 == ~E_2~0); 81257#L1276-1 assume !(0 == ~E_3~0); 81258#L1281-1 assume !(0 == ~E_4~0); 81201#L1286-1 assume !(0 == ~E_5~0); 80386#L1291-1 assume !(0 == ~E_6~0); 80387#L1296-1 assume !(0 == ~E_7~0); 80976#L1301-1 assume !(0 == ~E_8~0); 80977#L1306-1 assume !(0 == ~E_9~0); 81494#L1311-1 assume !(0 == ~E_10~0); 80337#L1316-1 assume !(0 == ~E_11~0); 80338#L1321-1 assume !(0 == ~E_12~0); 80994#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 80995#L593 assume !(1 == ~m_pc~0); 80226#L593-2 is_master_triggered_~__retres1~0#1 := 0; 80227#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 81746#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 81213#L1492 assume !(0 != activate_threads_~tmp~1#1); 81214#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 81540#L612 assume !(1 == ~t1_pc~0); 81541#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 81775#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 81776#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 80231#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 80232#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 80654#L631 assume 1 == ~t2_pc~0; 80588#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 80009#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 80010#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 80854#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 80855#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 80304#L650 assume !(1 == ~t3_pc~0); 80305#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 81019#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 80228#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 79962#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 79963#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 81179#L669 assume 1 == ~t4_pc~0; 81180#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 81576#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 80641#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 80170#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 80171#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 80395#L688 assume !(1 == ~t5_pc~0); 80186#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 80187#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 81126#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 81054#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 81055#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 81194#L707 assume 1 == ~t6_pc~0; 81655#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 80824#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 80825#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 81653#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 81132#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 80677#L726 assume 1 == ~t7_pc~0; 80574#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 80271#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 81346#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 81663#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 80041#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 80042#L745 assume !(1 == ~t8_pc~0); 80490#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 80509#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 81383#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 80905#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 80906#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 81453#L764 assume 1 == ~t9_pc~0; 80675#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 80515#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 81216#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 81727#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 80061#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 80062#L783 assume !(1 == ~t10_pc~0); 80123#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 80124#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 80164#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 80165#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 80630#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 81578#L802 assume 1 == ~t11_pc~0; 81559#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 80006#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 80007#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 80499#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 80500#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 80610#L821 assume !(1 == ~t12_pc~0); 80869#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 80968#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 80011#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 80012#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 81628#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81225#L1339 assume !(1 == ~M_E~0); 81226#L1339-2 assume !(1 == ~T1_E~0); 81667#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 81668#L1349-1 assume !(1 == ~T3_E~0); 80987#L1354-1 assume !(1 == ~T4_E~0); 80988#L1359-1 assume !(1 == ~T5_E~0); 81422#L1364-1 assume !(1 == ~T6_E~0); 80440#L1369-1 assume !(1 == ~T7_E~0); 80441#L1374-1 assume !(1 == ~T8_E~0); 80990#L1379-1 assume !(1 == ~T9_E~0); 80991#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 81096#L1389-1 assume !(1 == ~T11_E~0); 81620#L1394-1 assume !(1 == ~T12_E~0); 81621#L1399-1 assume !(1 == ~E_M~0); 81728#L1404-1 assume !(1 == ~E_1~0); 80539#L1409-1 assume !(1 == ~E_2~0); 80540#L1414-1 assume !(1 == ~E_3~0); 81297#L1419-1 assume !(1 == ~E_4~0); 80178#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 80179#L1429-1 assume !(1 == ~E_6~0); 81003#L1434-1 assume !(1 == ~E_7~0); 81643#L1439-1 assume !(1 == ~E_8~0); 80216#L1444-1 assume !(1 == ~E_9~0); 80217#L1449-1 assume !(1 == ~E_10~0); 80593#L1454-1 assume !(1 == ~E_11~0); 80594#L1459-1 assume !(1 == ~E_12~0); 81131#L1464-1 assume { :end_inline_reset_delta_events } true; 80350#L1810-2 [2021-12-14 23:43:28,482 INFO L793 eck$LassoCheckResult]: Loop: 80350#L1810-2 assume !false; 80801#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 80714#L1176 assume !false; 81306#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 80851#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 80049#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 81360#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 81927#L1003 assume !(0 != eval_~tmp~0#1); 81928#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 83222#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 83220#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 83217#L1201-5 assume !(0 == ~T1_E~0); 83215#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 83213#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 83211#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 83209#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 83207#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 83204#L1231-3 assume !(0 == ~T7_E~0); 83202#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 83200#L1241-3 assume !(0 == ~T9_E~0); 83198#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 83196#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 83194#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 83191#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 83189#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 83185#L1271-3 assume !(0 == ~E_2~0); 80800#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 80743#L1281-3 assume !(0 == ~E_4~0); 80744#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 81294#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 81295#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 81777#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 81723#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 81724#L1311-3 assume !(0 == ~E_10~0); 83079#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 83078#L1321-3 assume !(0 == ~E_12~0); 80966#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 80967#L593-42 assume !(1 == ~m_pc~0); 81133#L593-44 is_master_triggered_~__retres1~0#1 := 0; 81134#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 81759#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 81760#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 80141#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 80142#L612-42 assume !(1 == ~t1_pc~0); 81510#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 81511#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 81654#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 80229#L1500-42 assume !(0 != activate_threads_~tmp___0~0#1); 80230#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 80937#L631-42 assume 1 == ~t2_pc~0; 79995#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 79996#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 80926#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 80796#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 80797#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 80391#L650-42 assume 1 == ~t3_pc~0; 79954#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 79955#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 81687#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 80586#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 80587#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 81644#L669-42 assume !(1 == ~t4_pc~0); 79952#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 79953#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81427#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 81304#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 81192#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 81193#L688-42 assume !(1 == ~t5_pc~0); 81293#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 81515#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 80093#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 80094#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 80169#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 79984#L707-42 assume !(1 == ~t6_pc~0); 79985#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 81731#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 81432#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 81433#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 81160#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 81161#L726-42 assume !(1 == ~t7_pc~0); 81463#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 81490#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 81491#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 80864#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 80865#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 80972#L745-42 assume 1 == ~t8_pc~0; 81009#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 81011#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 80324#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 79970#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 79971#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 80699#L764-42 assume !(1 == ~t9_pc~0); 80841#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 81209#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 81210#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 80255#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 80256#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 80309#L783-42 assume 1 == ~t10_pc~0; 79926#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 79927#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 80523#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 80657#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 81768#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 81396#L802-42 assume !(1 == ~t11_pc~0); 80459#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 80068#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 80069#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 80019#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 80020#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 81221#L821-42 assume !(1 == ~t12_pc~0); 80562#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 80563#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 79924#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 79925#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 80913#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 80903#L1339-3 assume !(1 == ~M_E~0); 80904#L1339-5 assume !(1 == ~T1_E~0); 81058#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 81178#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 80572#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 80573#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 81189#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 81757#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 81642#L1374-3 assume !(1 == ~T8_E~0); 80392#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 80393#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 80570#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 80571#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 80784#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 81649#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 81615#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 81616#L1414-3 assume !(1 == ~E_3~0); 81679#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 81398#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 80276#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 80277#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 81188#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 80204#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 80205#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 80321#L1454-3 assume !(1 == ~E_11~0); 81722#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 82045#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 81918#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 81904#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 81894#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 81864#L1829 assume !(0 == start_simulation_~tmp~3#1); 80097#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 80098#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 80909#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 80910#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 81202#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 81203#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 80805#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 80349#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 80350#L1810-2 [2021-12-14 23:43:28,482 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:28,482 INFO L85 PathProgramCache]: Analyzing trace with hash 198368187, now seen corresponding path program 1 times [2021-12-14 23:43:28,483 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:28,483 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1854427889] [2021-12-14 23:43:28,483 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:28,483 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:28,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:28,505 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:28,505 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:28,505 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1854427889] [2021-12-14 23:43:28,505 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1854427889] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:28,505 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:28,505 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:28,505 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [46067093] [2021-12-14 23:43:28,505 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:28,506 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-14 23:43:28,506 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:28,506 INFO L85 PathProgramCache]: Analyzing trace with hash 715434912, now seen corresponding path program 1 times [2021-12-14 23:43:28,506 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:28,506 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1545243417] [2021-12-14 23:43:28,506 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:28,507 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:28,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:28,527 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:28,527 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:28,527 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1545243417] [2021-12-14 23:43:28,527 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1545243417] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:28,527 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:28,527 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:28,528 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1211566783] [2021-12-14 23:43:28,528 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:28,528 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-14 23:43:28,528 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-14 23:43:28,528 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-14 23:43:28,529 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-14 23:43:28,529 INFO L87 Difference]: Start difference. First operand 3391 states and 4912 transitions. cyclomatic complexity: 1523 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:28,743 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-14 23:43:28,743 INFO L93 Difference]: Finished difference Result 8087 states and 11624 transitions. [2021-12-14 23:43:28,743 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-14 23:43:28,744 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8087 states and 11624 transitions. [2021-12-14 23:43:28,769 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 7821 [2021-12-14 23:43:28,786 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8087 states to 8087 states and 11624 transitions. [2021-12-14 23:43:28,786 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8087 [2021-12-14 23:43:28,790 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8087 [2021-12-14 23:43:28,791 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8087 states and 11624 transitions. [2021-12-14 23:43:28,797 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-14 23:43:28,797 INFO L681 BuchiCegarLoop]: Abstraction has 8087 states and 11624 transitions. [2021-12-14 23:43:28,800 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8087 states and 11624 transitions. [2021-12-14 23:43:28,854 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8087 to 6392. [2021-12-14 23:43:28,859 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6392 states, 6392 states have (on average 1.4414893617021276) internal successors, (9214), 6391 states have internal predecessors, (9214), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:28,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6392 states to 6392 states and 9214 transitions. [2021-12-14 23:43:28,868 INFO L704 BuchiCegarLoop]: Abstraction has 6392 states and 9214 transitions. [2021-12-14 23:43:28,868 INFO L587 BuchiCegarLoop]: Abstraction has 6392 states and 9214 transitions. [2021-12-14 23:43:28,869 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-14 23:43:28,869 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6392 states and 9214 transitions. [2021-12-14 23:43:28,880 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6226 [2021-12-14 23:43:28,880 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-14 23:43:28,880 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-14 23:43:28,881 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:28,882 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:28,882 INFO L791 eck$LassoCheckResult]: Stem: 92189#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 92190#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 91707#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 91708#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 91762#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 93176#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 92200#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 92000#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 91400#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 91401#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 92652#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 92767#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 93256#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 93257#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 92126#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 92127#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 92682#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 92596#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 92164#L1201 assume !(0 == ~M_E~0); 92165#L1201-2 assume !(0 == ~T1_E~0); 93069#L1206-1 assume !(0 == ~T2_E~0); 93053#L1211-1 assume !(0 == ~T3_E~0); 93054#L1216-1 assume !(0 == ~T4_E~0); 91984#L1221-1 assume !(0 == ~T5_E~0); 91985#L1226-1 assume !(0 == ~T6_E~0); 91622#L1231-1 assume !(0 == ~T7_E~0); 91623#L1236-1 assume !(0 == ~T8_E~0); 93096#L1241-1 assume !(0 == ~T9_E~0); 92020#L1246-1 assume !(0 == ~T10_E~0); 92021#L1251-1 assume !(0 == ~T11_E~0); 92162#L1256-1 assume !(0 == ~T12_E~0); 91410#L1261-1 assume !(0 == ~E_M~0); 91411#L1266-1 assume !(0 == ~E_1~0); 93241#L1271-1 assume !(0 == ~E_2~0); 92750#L1276-1 assume !(0 == ~E_3~0); 92751#L1281-1 assume !(0 == ~E_4~0); 92696#L1286-1 assume !(0 == ~E_5~0); 91873#L1291-1 assume !(0 == ~E_6~0); 91874#L1296-1 assume !(0 == ~E_7~0); 92468#L1301-1 assume !(0 == ~E_8~0); 92469#L1306-1 assume !(0 == ~E_9~0); 92984#L1311-1 assume !(0 == ~E_10~0); 91824#L1316-1 assume !(0 == ~E_11~0); 91825#L1321-1 assume !(0 == ~E_12~0); 92486#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 92487#L593 assume !(1 == ~m_pc~0); 91713#L593-2 is_master_triggered_~__retres1~0#1 := 0; 91714#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 93223#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 92708#L1492 assume !(0 != activate_threads_~tmp~1#1); 92709#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 93024#L612 assume !(1 == ~t1_pc~0); 93025#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 93252#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 92096#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 91718#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 91719#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 92139#L631 assume !(1 == ~t2_pc~0); 92140#L631-2 is_transmit2_triggered_~__retres1~2#1 := 0; 91496#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 91497#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 92337#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 92338#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 91791#L650 assume !(1 == ~t3_pc~0); 91792#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 92511#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 91715#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 91450#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 91451#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 92674#L669 assume 1 == ~t4_pc~0; 92675#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 93061#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 92125#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 91657#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 91658#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 91882#L688 assume !(1 == ~t5_pc~0); 91673#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 91674#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 92621#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 92548#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 92549#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 92689#L707 assume 1 == ~t6_pc~0; 93134#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 92307#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 92308#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 93131#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 92627#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 92163#L726 assume 1 == ~t7_pc~0; 92060#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 91758#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 92840#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 93142#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 91528#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 91529#L745 assume !(1 == ~t8_pc~0); 91978#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 91996#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 92879#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 92387#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 92388#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 92944#L764 assume 1 == ~t9_pc~0; 92161#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 92002#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 92711#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 93205#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 91548#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 91549#L783 assume !(1 == ~t10_pc~0); 91610#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 91611#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 91651#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 91652#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 92114#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 93063#L802 assume 1 == ~t11_pc~0; 93042#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 91493#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 91494#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 91986#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 91987#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 92095#L821 assume !(1 == ~t12_pc~0); 92351#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 92459#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 91498#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 91499#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 93105#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 92720#L1339 assume !(1 == ~M_E~0); 92721#L1339-2 assume !(1 == ~T1_E~0); 93144#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 93145#L1349-1 assume !(1 == ~T3_E~0); 92479#L1354-1 assume !(1 == ~T4_E~0); 92480#L1359-1 assume !(1 == ~T5_E~0); 92914#L1364-1 assume !(1 == ~T6_E~0); 91926#L1369-1 assume !(1 == ~T7_E~0); 91927#L1374-1 assume !(1 == ~T8_E~0); 92482#L1379-1 assume !(1 == ~T9_E~0); 92483#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 92588#L1389-1 assume !(1 == ~T11_E~0); 93099#L1394-1 assume !(1 == ~T12_E~0); 93100#L1399-1 assume !(1 == ~E_M~0); 93206#L1404-1 assume !(1 == ~E_1~0); 92025#L1409-1 assume !(1 == ~E_2~0); 92026#L1414-1 assume !(1 == ~E_3~0); 92787#L1419-1 assume !(1 == ~E_4~0); 91665#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 91666#L1429-1 assume !(1 == ~E_6~0); 92495#L1434-1 assume !(1 == ~E_7~0); 93122#L1439-1 assume !(1 == ~E_8~0); 91703#L1444-1 assume !(1 == ~E_9~0); 91704#L1449-1 assume !(1 == ~E_10~0); 92077#L1454-1 assume !(1 == ~E_11~0); 92078#L1459-1 assume !(1 == ~E_12~0); 92626#L1464-1 assume { :end_inline_reset_delta_events } true; 91837#L1810-2 [2021-12-14 23:43:28,882 INFO L793 eck$LassoCheckResult]: Loop: 91837#L1810-2 assume !false; 92285#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 92202#L1176 assume !false; 92797#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 92334#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 91536#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 92084#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 92085#L1003 assume !(0 != eval_~tmp~0#1); 91727#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 91728#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 92972#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 92736#L1201-5 assume !(0 == ~T1_E~0); 92737#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 92624#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 91786#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 91787#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 92258#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 91857#L1231-3 assume !(0 == ~T7_E~0); 91858#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 92104#L1241-3 assume !(0 == ~T9_E~0); 93160#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 93045#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 92726#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 91803#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 91804#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 91849#L1271-3 assume !(0 == ~E_2~0); 91850#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 92231#L1281-3 assume !(0 == ~E_4~0); 92232#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 92784#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 92785#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 93253#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 93202#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 92343#L1311-3 assume !(0 == ~E_10~0); 91729#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 91730#L1321-3 assume !(0 == ~E_12~0); 91805#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 92458#L593-42 assume !(1 == ~m_pc~0); 92628#L593-44 is_master_triggered_~__retres1~0#1 := 0; 92629#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 93237#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 93238#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 91628#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 91629#L612-42 assume 1 == ~t1_pc~0; 92575#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 93286#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 97555#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 97554#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 91717#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 92424#L631-42 assume !(1 == ~t2_pc~0); 92425#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 92410#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 92411#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 92281#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 92282#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 91878#L650-42 assume 1 == ~t3_pc~0; 91442#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 91443#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 93166#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 92072#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 92073#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 93123#L669-42 assume !(1 == ~t4_pc~0); 91440#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 91441#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 92919#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 92795#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 92687#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 92688#L688-42 assume !(1 == ~t5_pc~0); 92783#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 93002#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 91580#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 91581#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 91656#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 91472#L707-42 assume !(1 == ~t6_pc~0); 91473#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 93209#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 92924#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 92925#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 92654#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 92655#L726-42 assume 1 == ~t7_pc~0; 92953#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 92980#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 92981#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 92346#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 92347#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 92463#L745-42 assume 1 == ~t8_pc~0; 92501#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 92503#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 91811#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 91458#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 91459#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 92185#L764-42 assume 1 == ~t9_pc~0; 92323#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 92704#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 92705#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 91742#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 91743#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 91796#L783-42 assume 1 == ~t10_pc~0; 91414#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 91415#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 92009#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 92143#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 93247#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 92892#L802-42 assume !(1 == ~t11_pc~0); 91945#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 91555#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 91556#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 91506#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 91507#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 92716#L821-42 assume !(1 == ~t12_pc~0); 92048#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 92049#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 91412#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 91413#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 92396#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 92385#L1339-3 assume !(1 == ~M_E~0); 92386#L1339-5 assume !(1 == ~T1_E~0); 92552#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 92673#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 92058#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 92059#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 92684#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 93235#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 93121#L1374-3 assume !(1 == ~T8_E~0); 91879#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 91880#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 92056#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 92057#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 92270#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 93128#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 93094#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 93095#L1414-3 assume !(1 == ~E_3~0); 93159#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 92894#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 91763#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 91764#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 92683#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 91691#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 91692#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 91808#L1454-3 assume !(1 == ~E_11~0); 92678#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 92679#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 92309#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 91602#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 91861#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 91862#L1829 assume !(0 == start_simulation_~tmp~3#1); 91584#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 91585#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 92391#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 92392#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 92697#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 92698#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 92289#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 91836#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 91837#L1810-2 [2021-12-14 23:43:28,883 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:28,883 INFO L85 PathProgramCache]: Analyzing trace with hash 1315553148, now seen corresponding path program 1 times [2021-12-14 23:43:28,883 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:28,883 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [470395018] [2021-12-14 23:43:28,883 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:28,883 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:28,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:28,905 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:28,905 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:28,905 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [470395018] [2021-12-14 23:43:28,906 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [470395018] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:28,906 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:28,906 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-14 23:43:28,906 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [605171822] [2021-12-14 23:43:28,906 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:28,906 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-14 23:43:28,907 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:28,907 INFO L85 PathProgramCache]: Analyzing trace with hash 1701647708, now seen corresponding path program 1 times [2021-12-14 23:43:28,907 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:28,907 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1684857417] [2021-12-14 23:43:28,907 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:28,907 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:28,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:28,928 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:28,928 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:28,928 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1684857417] [2021-12-14 23:43:28,928 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1684857417] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:28,928 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:28,928 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:28,928 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1078133987] [2021-12-14 23:43:28,929 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:28,929 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-14 23:43:28,929 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-14 23:43:28,929 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-14 23:43:28,929 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-14 23:43:28,930 INFO L87 Difference]: Start difference. First operand 6392 states and 9214 transitions. cyclomatic complexity: 2824 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:29,020 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-14 23:43:29,020 INFO L93 Difference]: Finished difference Result 12183 states and 17485 transitions. [2021-12-14 23:43:29,020 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-14 23:43:29,021 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12183 states and 17485 transitions. [2021-12-14 23:43:29,064 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 12008 [2021-12-14 23:43:29,091 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12183 states to 12183 states and 17485 transitions. [2021-12-14 23:43:29,091 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12183 [2021-12-14 23:43:29,097 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12183 [2021-12-14 23:43:29,097 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12183 states and 17485 transitions. [2021-12-14 23:43:29,106 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-14 23:43:29,106 INFO L681 BuchiCegarLoop]: Abstraction has 12183 states and 17485 transitions. [2021-12-14 23:43:29,111 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12183 states and 17485 transitions. [2021-12-14 23:43:29,195 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12183 to 12175. [2021-12-14 23:43:29,208 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12175 states, 12175 states have (on average 1.435482546201232) internal successors, (17477), 12174 states have internal predecessors, (17477), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:29,226 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12175 states to 12175 states and 17477 transitions. [2021-12-14 23:43:29,227 INFO L704 BuchiCegarLoop]: Abstraction has 12175 states and 17477 transitions. [2021-12-14 23:43:29,227 INFO L587 BuchiCegarLoop]: Abstraction has 12175 states and 17477 transitions. [2021-12-14 23:43:29,227 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-14 23:43:29,227 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12175 states and 17477 transitions. [2021-12-14 23:43:29,293 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 12000 [2021-12-14 23:43:29,293 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-14 23:43:29,294 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-14 23:43:29,295 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:29,295 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:29,296 INFO L791 eck$LassoCheckResult]: Stem: 110773#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 110774#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 110290#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 110291#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 110344#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 111789#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 110784#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 110582#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 109982#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 109983#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 111240#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 111366#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 111898#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 111899#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 110708#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 110709#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 111270#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 111179#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 110747#L1201 assume !(0 == ~M_E~0); 110748#L1201-2 assume !(0 == ~T1_E~0); 111674#L1206-1 assume !(0 == ~T2_E~0); 111658#L1211-1 assume !(0 == ~T3_E~0); 111659#L1216-1 assume !(0 == ~T4_E~0); 110567#L1221-1 assume !(0 == ~T5_E~0); 110568#L1226-1 assume !(0 == ~T6_E~0); 110205#L1231-1 assume !(0 == ~T7_E~0); 110206#L1236-1 assume !(0 == ~T8_E~0); 111707#L1241-1 assume !(0 == ~T9_E~0); 110605#L1246-1 assume !(0 == ~T10_E~0); 110606#L1251-1 assume !(0 == ~T11_E~0); 110745#L1256-1 assume !(0 == ~T12_E~0); 109995#L1261-1 assume !(0 == ~E_M~0); 109996#L1266-1 assume !(0 == ~E_1~0); 111866#L1271-1 assume !(0 == ~E_2~0); 111347#L1276-1 assume !(0 == ~E_3~0); 111348#L1281-1 assume !(0 == ~E_4~0); 111287#L1286-1 assume !(0 == ~E_5~0); 110457#L1291-1 assume !(0 == ~E_6~0); 110458#L1296-1 assume !(0 == ~E_7~0); 111052#L1301-1 assume !(0 == ~E_8~0); 111053#L1306-1 assume !(0 == ~E_9~0); 111584#L1311-1 assume !(0 == ~E_10~0); 110407#L1316-1 assume !(0 == ~E_11~0); 110408#L1321-1 assume !(0 == ~E_12~0); 111070#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 111071#L593 assume !(1 == ~m_pc~0); 110296#L593-2 is_master_triggered_~__retres1~0#1 := 0; 110297#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 111844#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 111301#L1492 assume !(0 != activate_threads_~tmp~1#1); 111302#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 111627#L612 assume !(1 == ~t1_pc~0); 111628#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 111926#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 111969#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 110301#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 110302#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 110721#L631 assume !(1 == ~t2_pc~0); 110722#L631-2 is_transmit2_triggered_~__retres1~2#1 := 0; 110078#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 110079#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 110926#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 110927#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 110374#L650 assume !(1 == ~t3_pc~0); 110375#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 111095#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 110298#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 110033#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 110034#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 111263#L669 assume !(1 == ~t4_pc~0); 111264#L669-2 is_transmit4_triggered_~__retres1~4#1 := 0; 111664#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 110707#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 110240#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 110241#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 110466#L688 assume !(1 == ~t5_pc~0); 110256#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 110257#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 111205#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 111131#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 111132#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 111283#L707 assume 1 == ~t6_pc~0; 111748#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 110895#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 110896#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 111746#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 111216#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 110746#L726 assume 1 == ~t7_pc~0; 110644#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 110340#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 111435#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 111757#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 110110#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 110111#L745 assume !(1 == ~t8_pc~0); 110560#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 110578#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 111473#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 110973#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 110974#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 111541#L764 assume 1 == ~t9_pc~0; 110744#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 110584#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 111304#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 111824#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 110130#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 110131#L783 assume !(1 == ~t10_pc~0); 110192#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 110193#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 110234#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 110235#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 110701#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 111666#L802 assume 1 == ~t11_pc~0; 111648#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 110075#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 110076#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 110569#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 110570#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 110676#L821 assume !(1 == ~t12_pc~0); 110940#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 111043#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 110082#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 110083#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 111717#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 111315#L1339 assume !(1 == ~M_E~0); 111316#L1339-2 assume !(1 == ~T1_E~0); 111758#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 111759#L1349-1 assume !(1 == ~T3_E~0); 111064#L1354-1 assume !(1 == ~T4_E~0); 111065#L1359-1 assume !(1 == ~T5_E~0); 111514#L1364-1 assume !(1 == ~T6_E~0); 110508#L1369-1 assume !(1 == ~T7_E~0); 110509#L1374-1 assume !(1 == ~T8_E~0); 111068#L1379-1 assume !(1 == ~T9_E~0); 111069#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 111174#L1389-1 assume !(1 == ~T11_E~0); 111710#L1394-1 assume !(1 == ~T12_E~0); 111711#L1399-1 assume !(1 == ~E_M~0); 111825#L1404-1 assume !(1 == ~E_1~0); 110609#L1409-1 assume !(1 == ~E_2~0); 110610#L1414-1 assume !(1 == ~E_3~0); 111385#L1419-1 assume !(1 == ~E_4~0); 110248#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 110249#L1429-1 assume !(1 == ~E_6~0); 111079#L1434-1 assume !(1 == ~E_7~0); 111733#L1439-1 assume !(1 == ~E_8~0); 110286#L1444-1 assume !(1 == ~E_9~0); 110287#L1449-1 assume !(1 == ~E_10~0); 110659#L1454-1 assume !(1 == ~E_11~0); 110660#L1459-1 assume !(1 == ~E_12~0); 111210#L1464-1 assume { :end_inline_reset_delta_events } true; 111211#L1810-2 [2021-12-14 23:43:29,296 INFO L793 eck$LassoCheckResult]: Loop: 111211#L1810-2 assume !false; 115821#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 115816#L1176 assume !false; 115813#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 115806#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 115794#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 115791#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 115788#L1003 assume !(0 != eval_~tmp~0#1); 115789#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 117293#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 117291#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 117289#L1201-5 assume !(0 == ~T1_E~0); 117288#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 117287#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 117283#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 117281#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 117279#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 117278#L1231-3 assume !(0 == ~T7_E~0); 117277#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 117276#L1241-3 assume !(0 == ~T9_E~0); 117275#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 117274#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 117273#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 117272#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 117271#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 117270#L1271-3 assume !(0 == ~E_2~0); 117269#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 117268#L1281-3 assume !(0 == ~E_4~0); 117267#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 117266#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 117265#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 117264#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 117263#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 117262#L1311-3 assume !(0 == ~E_10~0); 117261#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 117260#L1321-3 assume !(0 == ~E_12~0); 117259#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 117258#L593-42 assume !(1 == ~m_pc~0); 117257#L593-44 is_master_triggered_~__retres1~0#1 := 0; 117256#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 117255#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 117254#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 117253#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 117251#L612-42 assume !(1 == ~t1_pc~0); 117249#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 117247#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 117246#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 117245#L1500-42 assume !(0 != activate_threads_~tmp___0~0#1); 117242#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 117240#L631-42 assume !(1 == ~t2_pc~0); 115460#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 117239#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 117238#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 117236#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 117234#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 117232#L650-42 assume !(1 == ~t3_pc~0); 117229#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 117227#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 117225#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 117223#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 117220#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 117218#L669-42 assume !(1 == ~t4_pc~0); 117216#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 117213#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 117211#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 117209#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 117208#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 117206#L688-42 assume 1 == ~t5_pc~0; 117203#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 117201#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 117199#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 117197#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 117194#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 117192#L707-42 assume 1 == ~t6_pc~0; 117189#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 117187#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 117185#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 117183#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 117181#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 117179#L726-42 assume !(1 == ~t7_pc~0); 117177#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 117174#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 117172#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 117170#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 117167#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 117165#L745-42 assume 1 == ~t8_pc~0; 117163#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 117160#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 117158#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 117156#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 117153#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 117151#L764-42 assume !(1 == ~t9_pc~0); 117149#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 117146#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 117144#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 117142#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 117139#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 117137#L783-42 assume 1 == ~t10_pc~0; 117135#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 117132#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 117130#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 117128#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 117125#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 117123#L802-42 assume !(1 == ~t11_pc~0); 117121#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 117118#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 117116#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 117114#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 117111#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 117109#L821-42 assume 1 == ~t12_pc~0; 117107#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 117104#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 117102#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 117100#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 117097#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 117095#L1339-3 assume !(1 == ~M_E~0); 117093#L1339-5 assume !(1 == ~T1_E~0); 117091#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 117089#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 117087#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 117084#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 117082#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 117080#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 117078#L1374-3 assume !(1 == ~T8_E~0); 117076#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 117074#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 117071#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 117069#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 117067#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 117065#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 117063#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 117061#L1414-3 assume !(1 == ~E_3~0); 117059#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 117057#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 117055#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 117053#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 117051#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 117049#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 117047#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 117045#L1454-3 assume !(1 == ~E_11~0); 117043#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 117041#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 117026#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 117018#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 117016#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 117005#L1829 assume !(0 == start_simulation_~tmp~3#1); 117003#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 116973#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 116967#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 116965#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 116963#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 116961#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 116959#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 116957#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 111211#L1810-2 [2021-12-14 23:43:29,297 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:29,297 INFO L85 PathProgramCache]: Analyzing trace with hash -1519420227, now seen corresponding path program 1 times [2021-12-14 23:43:29,297 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:29,297 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [962219232] [2021-12-14 23:43:29,297 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:29,298 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:29,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:29,324 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:29,324 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:29,325 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [962219232] [2021-12-14 23:43:29,325 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [962219232] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:29,325 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:29,325 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:29,325 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1562680963] [2021-12-14 23:43:29,325 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:29,326 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-14 23:43:29,326 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:29,326 INFO L85 PathProgramCache]: Analyzing trace with hash -208947873, now seen corresponding path program 1 times [2021-12-14 23:43:29,326 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:29,326 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2041628923] [2021-12-14 23:43:29,326 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:29,327 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:29,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:29,350 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:29,350 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:29,351 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2041628923] [2021-12-14 23:43:29,351 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2041628923] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:29,351 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:29,351 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:29,351 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1112401768] [2021-12-14 23:43:29,351 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:29,352 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-14 23:43:29,352 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-14 23:43:29,352 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-14 23:43:29,352 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-14 23:43:29,352 INFO L87 Difference]: Start difference. First operand 12175 states and 17477 transitions. cyclomatic complexity: 5306 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:29,605 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-14 23:43:29,605 INFO L93 Difference]: Finished difference Result 29424 states and 41968 transitions. [2021-12-14 23:43:29,605 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-14 23:43:29,606 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29424 states and 41968 transitions. [2021-12-14 23:43:29,757 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 28838 [2021-12-14 23:43:29,879 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29424 states to 29424 states and 41968 transitions. [2021-12-14 23:43:29,880 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29424 [2021-12-14 23:43:29,905 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29424 [2021-12-14 23:43:29,905 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29424 states and 41968 transitions. [2021-12-14 23:43:29,942 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-14 23:43:29,943 INFO L681 BuchiCegarLoop]: Abstraction has 29424 states and 41968 transitions. [2021-12-14 23:43:29,960 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29424 states and 41968 transitions. [2021-12-14 23:43:30,212 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29424 to 23306. [2021-12-14 23:43:30,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23306 states, 23306 states have (on average 1.4301038359220801) internal successors, (33330), 23305 states have internal predecessors, (33330), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:30,277 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23306 states to 23306 states and 33330 transitions. [2021-12-14 23:43:30,278 INFO L704 BuchiCegarLoop]: Abstraction has 23306 states and 33330 transitions. [2021-12-14 23:43:30,278 INFO L587 BuchiCegarLoop]: Abstraction has 23306 states and 33330 transitions. [2021-12-14 23:43:30,278 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-14 23:43:30,278 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23306 states and 33330 transitions. [2021-12-14 23:43:30,346 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 23120 [2021-12-14 23:43:30,347 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-14 23:43:30,347 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-14 23:43:30,349 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:30,349 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:30,349 INFO L791 eck$LassoCheckResult]: Stem: 152380#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 152381#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 151896#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 151897#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 151950#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 153398#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 152391#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 152190#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 151591#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 151592#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 152851#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 152971#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 153480#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 153481#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 152317#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 152318#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 152881#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 152788#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 152355#L1201 assume !(0 == ~M_E~0); 152356#L1201-2 assume !(0 == ~T1_E~0); 153289#L1206-1 assume !(0 == ~T2_E~0); 153269#L1211-1 assume !(0 == ~T3_E~0); 153270#L1216-1 assume !(0 == ~T4_E~0); 152175#L1221-1 assume !(0 == ~T5_E~0); 152176#L1226-1 assume !(0 == ~T6_E~0); 151811#L1231-1 assume !(0 == ~T7_E~0); 151812#L1236-1 assume !(0 == ~T8_E~0); 153316#L1241-1 assume !(0 == ~T9_E~0); 152214#L1246-1 assume !(0 == ~T10_E~0); 152215#L1251-1 assume !(0 == ~T11_E~0); 152353#L1256-1 assume !(0 == ~T12_E~0); 151603#L1261-1 assume !(0 == ~E_M~0); 151604#L1266-1 assume !(0 == ~E_1~0); 153464#L1271-1 assume !(0 == ~E_2~0); 152950#L1276-1 assume !(0 == ~E_3~0); 152951#L1281-1 assume !(0 == ~E_4~0); 152895#L1286-1 assume !(0 == ~E_5~0); 152064#L1291-1 assume !(0 == ~E_6~0); 152065#L1296-1 assume !(0 == ~E_7~0); 152661#L1301-1 assume !(0 == ~E_8~0); 152662#L1306-1 assume !(0 == ~E_9~0); 153198#L1311-1 assume !(0 == ~E_10~0); 152015#L1316-1 assume !(0 == ~E_11~0); 152016#L1321-1 assume !(0 == ~E_12~0); 152681#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 152682#L593 assume !(1 == ~m_pc~0); 151902#L593-2 is_master_triggered_~__retres1~0#1 := 0; 151903#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 153442#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 152907#L1492 assume !(0 != activate_threads_~tmp~1#1); 152908#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 153239#L612 assume !(1 == ~t1_pc~0); 153240#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 153475#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 153476#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 151907#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 151908#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 152330#L631 assume !(1 == ~t2_pc~0); 152331#L631-2 is_transmit2_triggered_~__retres1~2#1 := 0; 151685#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 151686#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 152533#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 152534#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 151979#L650 assume !(1 == ~t3_pc~0); 151980#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 152706#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 151904#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 151641#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 151642#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 152874#L669 assume !(1 == ~t4_pc~0); 152875#L669-2 is_transmit4_triggered_~__retres1~4#1 := 0; 153276#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 152316#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 151846#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 151847#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 152073#L688 assume !(1 == ~t5_pc~0); 151862#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 151863#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 152816#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 152745#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 152746#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 152891#L707 assume !(1 == ~t6_pc~0); 153125#L707-2 is_transmit6_triggered_~__retres1~6#1 := 0; 152503#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 152504#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 153354#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 152828#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 152354#L726 assume 1 == ~t7_pc~0; 152253#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 151946#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 153040#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 153365#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 151717#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 151718#L745 assume !(1 == ~t8_pc~0); 152168#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 152186#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 153076#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 152585#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 152586#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 153153#L764 assume 1 == ~t9_pc~0; 152352#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 152192#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 152910#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 153422#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 151737#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 151738#L783 assume !(1 == ~t10_pc~0); 151799#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 151800#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 151840#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 151841#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 152310#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 153278#L802 assume 1 == ~t11_pc~0; 153259#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 151682#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 151683#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 152177#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 152178#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 152285#L821 assume !(1 == ~t12_pc~0); 152547#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 152653#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 151689#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 151690#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 153325#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 152919#L1339 assume !(1 == ~M_E~0); 152920#L1339-2 assume !(1 == ~T1_E~0); 153366#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 153367#L1349-1 assume !(1 == ~T3_E~0); 152675#L1354-1 assume !(1 == ~T4_E~0); 152676#L1359-1 assume !(1 == ~T5_E~0); 153121#L1364-1 assume !(1 == ~T6_E~0); 152117#L1369-1 assume !(1 == ~T7_E~0); 152118#L1374-1 assume !(1 == ~T8_E~0); 152679#L1379-1 assume !(1 == ~T9_E~0); 152680#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 152783#L1389-1 assume !(1 == ~T11_E~0); 153319#L1394-1 assume !(1 == ~T12_E~0); 153320#L1399-1 assume !(1 == ~E_M~0); 153423#L1404-1 assume !(1 == ~E_1~0); 152218#L1409-1 assume !(1 == ~E_2~0); 152219#L1414-1 assume !(1 == ~E_3~0); 152989#L1419-1 assume !(1 == ~E_4~0); 151854#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 151855#L1429-1 assume !(1 == ~E_6~0); 152690#L1434-1 assume !(1 == ~E_7~0); 153341#L1439-1 assume !(1 == ~E_8~0); 151892#L1444-1 assume !(1 == ~E_9~0); 151893#L1449-1 assume !(1 == ~E_10~0); 152268#L1454-1 assume !(1 == ~E_11~0); 152269#L1459-1 assume !(1 == ~E_12~0); 152822#L1464-1 assume { :end_inline_reset_delta_events } true; 152028#L1810-2 [2021-12-14 23:43:30,350 INFO L793 eck$LassoCheckResult]: Loop: 152028#L1810-2 assume !false; 152480#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 152393#L1176 assume !false; 152997#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 152531#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 151725#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 152275#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 152276#L1003 assume !(0 != eval_~tmp~0#1); 151916#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 151917#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 153185#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 152936#L1201-5 assume !(0 == ~T1_E~0); 152937#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 152819#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 151974#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 151975#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 152449#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 152048#L1231-3 assume !(0 == ~T7_E~0); 152049#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 152295#L1241-3 assume !(0 == ~T9_E~0); 153380#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 153262#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 152926#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 151991#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 151992#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 152040#L1271-3 assume !(0 == ~E_2~0); 152041#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 152421#L1281-3 assume !(0 == ~E_4~0); 152422#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 152986#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 152987#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 153474#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 153419#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 152539#L1311-3 assume !(0 == ~E_10~0); 151918#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 151919#L1321-3 assume !(0 == ~E_12~0); 151993#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 152652#L593-42 assume !(1 == ~m_pc~0); 152826#L593-44 is_master_triggered_~__retres1~0#1 := 0; 152827#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 153459#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 153460#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 151820#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 151821#L612-42 assume !(1 == ~t1_pc~0); 152768#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 153211#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 153355#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 151905#L1500-42 assume !(0 != activate_threads_~tmp___0~0#1); 151906#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 152620#L631-42 assume !(1 == ~t2_pc~0); 152621#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 152608#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 152609#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 152475#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 152476#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 152069#L650-42 assume !(1 == ~t3_pc~0); 151635#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 151634#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 153389#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 152263#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 152264#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 153342#L669-42 assume !(1 == ~t4_pc~0); 151624#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 151625#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 153124#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 152995#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 152886#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 152887#L688-42 assume 1 == ~t5_pc~0; 152984#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 153215#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 151769#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 151770#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 151845#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 151655#L707-42 assume !(1 == ~t6_pc~0); 151656#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 153513#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 153127#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 153128#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 152852#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 152853#L726-42 assume 1 == ~t7_pc~0; 153160#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 153194#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 153195#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 152542#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 152543#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 152657#L745-42 assume 1 == ~t8_pc~0; 152696#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 152698#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 152000#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 151649#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 151650#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 152376#L764-42 assume 1 == ~t9_pc~0; 152519#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 152903#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 152904#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 151931#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 151932#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 151984#L783-42 assume !(1 == ~t10_pc~0); 151607#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 151606#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 152200#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 152334#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 153469#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 153089#L802-42 assume !(1 == ~t11_pc~0); 152134#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 151744#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 151745#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 151695#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 151696#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 152915#L821-42 assume 1 == ~t12_pc~0; 152916#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 152240#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 151601#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 151602#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 152594#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 152580#L1339-3 assume !(1 == ~M_E~0); 152581#L1339-5 assume !(1 == ~T1_E~0); 152747#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 152873#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 152249#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 152250#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 152883#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 153457#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 153340#L1374-3 assume !(1 == ~T8_E~0); 152070#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 152071#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 152247#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 152248#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 152464#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 153350#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 153314#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 153315#L1414-3 assume !(1 == ~E_3~0); 153379#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 153094#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 151951#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 151952#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 152882#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 151880#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 151881#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 151999#L1454-3 assume !(1 == ~E_11~0); 152877#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 152878#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 152505#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 151791#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 152052#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 152053#L1829 assume !(0 == start_simulation_~tmp~3#1); 151773#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 151774#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 152589#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 152590#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 152896#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 152897#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 152484#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 152027#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 152028#L1810-2 [2021-12-14 23:43:30,350 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:30,350 INFO L85 PathProgramCache]: Analyzing trace with hash -381791362, now seen corresponding path program 1 times [2021-12-14 23:43:30,350 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:30,351 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [347397521] [2021-12-14 23:43:30,351 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:30,351 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:30,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:30,380 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:30,381 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:30,381 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [347397521] [2021-12-14 23:43:30,383 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [347397521] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:30,383 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:30,383 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:30,383 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1688815575] [2021-12-14 23:43:30,383 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:30,384 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-14 23:43:30,384 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:30,384 INFO L85 PathProgramCache]: Analyzing trace with hash 773285215, now seen corresponding path program 1 times [2021-12-14 23:43:30,384 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:30,384 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [385981783] [2021-12-14 23:43:30,384 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:30,385 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:30,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:30,407 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:30,407 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:30,408 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [385981783] [2021-12-14 23:43:30,408 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [385981783] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:30,408 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:30,408 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:30,408 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1572649552] [2021-12-14 23:43:30,408 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:30,409 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-14 23:43:30,409 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-14 23:43:30,409 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-14 23:43:30,409 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-14 23:43:30,410 INFO L87 Difference]: Start difference. First operand 23306 states and 33330 transitions. cyclomatic complexity: 10028 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:30,896 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-14 23:43:30,896 INFO L93 Difference]: Finished difference Result 56397 states and 80163 transitions. [2021-12-14 23:43:30,897 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-14 23:43:30,897 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 56397 states and 80163 transitions. [2021-12-14 23:43:31,119 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 55392 [2021-12-14 23:43:31,268 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 56397 states to 56397 states and 80163 transitions. [2021-12-14 23:43:31,269 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 56397 [2021-12-14 23:43:31,298 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 56397 [2021-12-14 23:43:31,299 INFO L73 IsDeterministic]: Start isDeterministic. Operand 56397 states and 80163 transitions. [2021-12-14 23:43:31,331 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-14 23:43:31,331 INFO L681 BuchiCegarLoop]: Abstraction has 56397 states and 80163 transitions. [2021-12-14 23:43:31,361 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56397 states and 80163 transitions. [2021-12-14 23:43:31,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56397 to 44705. [2021-12-14 23:43:31,861 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44705 states, 44705 states have (on average 1.4251426014987139) internal successors, (63711), 44704 states have internal predecessors, (63711), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:31,943 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44705 states to 44705 states and 63711 transitions. [2021-12-14 23:43:31,944 INFO L704 BuchiCegarLoop]: Abstraction has 44705 states and 63711 transitions. [2021-12-14 23:43:31,944 INFO L587 BuchiCegarLoop]: Abstraction has 44705 states and 63711 transitions. [2021-12-14 23:43:31,944 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-12-14 23:43:31,944 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44705 states and 63711 transitions. [2021-12-14 23:43:32,244 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 44496 [2021-12-14 23:43:32,244 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-14 23:43:32,244 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-14 23:43:32,246 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:32,246 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:32,246 INFO L791 eck$LassoCheckResult]: Stem: 232090#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 232091#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 231609#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 231610#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 231662#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 233158#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 232101#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 231901#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 231304#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 231305#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 232573#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 232693#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 233263#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 233264#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 232027#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 232028#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 232603#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 232511#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 232064#L1201 assume !(0 == ~M_E~0); 232065#L1201-2 assume !(0 == ~T1_E~0); 233028#L1206-1 assume !(0 == ~T2_E~0); 233006#L1211-1 assume !(0 == ~T3_E~0); 233007#L1216-1 assume !(0 == ~T4_E~0); 231885#L1221-1 assume !(0 == ~T5_E~0); 231886#L1226-1 assume !(0 == ~T6_E~0); 231524#L1231-1 assume !(0 == ~T7_E~0); 231525#L1236-1 assume !(0 == ~T8_E~0); 233062#L1241-1 assume !(0 == ~T9_E~0); 231921#L1246-1 assume !(0 == ~T10_E~0); 231922#L1251-1 assume !(0 == ~T11_E~0); 232062#L1256-1 assume !(0 == ~T12_E~0); 231314#L1261-1 assume !(0 == ~E_M~0); 231315#L1266-1 assume !(0 == ~E_1~0); 233240#L1271-1 assume !(0 == ~E_2~0); 232675#L1276-1 assume !(0 == ~E_3~0); 232676#L1281-1 assume !(0 == ~E_4~0); 232617#L1286-1 assume !(0 == ~E_5~0); 231775#L1291-1 assume !(0 == ~E_6~0); 231776#L1296-1 assume !(0 == ~E_7~0); 232382#L1301-1 assume !(0 == ~E_8~0); 232383#L1306-1 assume !(0 == ~E_9~0); 232935#L1311-1 assume !(0 == ~E_10~0); 231725#L1316-1 assume !(0 == ~E_11~0); 231726#L1321-1 assume !(0 == ~E_12~0); 232400#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 232401#L593 assume !(1 == ~m_pc~0); 231615#L593-2 is_master_triggered_~__retres1~0#1 := 0; 231616#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 233214#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 232629#L1492 assume !(0 != activate_threads_~tmp~1#1); 232630#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 232978#L612 assume !(1 == ~t1_pc~0); 232979#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 233251#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 233252#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 231620#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 231621#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 232040#L631 assume !(1 == ~t2_pc~0); 232041#L631-2 is_transmit2_triggered_~__retres1~2#1 := 0; 231397#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 231398#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 232247#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 232248#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 231691#L650 assume !(1 == ~t3_pc~0); 231692#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 232427#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 231617#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 231353#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 231354#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 232594#L669 assume !(1 == ~t4_pc~0); 232595#L669-2 is_transmit4_triggered_~__retres1~4#1 := 0; 233014#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 232026#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 231559#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 231560#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 231784#L688 assume !(1 == ~t5_pc~0); 231575#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 231576#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 232540#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 232464#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 232465#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 232610#L707 assume !(1 == ~t6_pc~0); 232861#L707-2 is_transmit6_triggered_~__retres1~6#1 := 0; 232215#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 232216#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 233109#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 232548#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 232063#L726 assume !(1 == ~t7_pc~0); 231657#L726-2 is_transmit7_triggered_~__retres1~7#1 := 0; 231658#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 232771#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 233120#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 231429#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 231430#L745 assume !(1 == ~t8_pc~0); 231879#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 231897#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 232807#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 232300#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 232301#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 232889#L764 assume 1 == ~t9_pc~0; 232061#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 231903#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 232632#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 233194#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 231449#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 231450#L783 assume !(1 == ~t10_pc~0); 231512#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 231513#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 231553#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 231554#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 232015#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 233017#L802 assume 1 == ~t11_pc~0; 232995#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 231394#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 231395#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 231887#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 231888#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 231995#L821 assume !(1 == ~t12_pc~0); 232264#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 232373#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 231399#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 231400#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 233073#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 232641#L1339 assume !(1 == ~M_E~0); 232642#L1339-2 assume !(1 == ~T1_E~0); 233123#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 233124#L1349-1 assume !(1 == ~T3_E~0); 232393#L1354-1 assume !(1 == ~T4_E~0); 232394#L1359-1 assume !(1 == ~T5_E~0); 232855#L1364-1 assume !(1 == ~T6_E~0); 231828#L1369-1 assume !(1 == ~T7_E~0); 231829#L1374-1 assume !(1 == ~T8_E~0); 232396#L1379-1 assume !(1 == ~T9_E~0); 232397#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 232506#L1389-1 assume !(1 == ~T11_E~0); 233067#L1394-1 assume !(1 == ~T12_E~0); 233068#L1399-1 assume !(1 == ~E_M~0); 233195#L1404-1 assume !(1 == ~E_1~0); 231926#L1409-1 assume !(1 == ~E_2~0); 231927#L1414-1 assume !(1 == ~E_3~0); 232715#L1419-1 assume !(1 == ~E_4~0); 231567#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 231568#L1429-1 assume !(1 == ~E_6~0); 232409#L1434-1 assume !(1 == ~E_7~0); 233093#L1439-1 assume !(1 == ~E_8~0); 231605#L1444-1 assume !(1 == ~E_9~0); 231606#L1449-1 assume !(1 == ~E_10~0); 231977#L1454-1 assume !(1 == ~E_11~0); 231978#L1459-1 assume !(1 == ~E_12~0); 232546#L1464-1 assume { :end_inline_reset_delta_events } true; 232547#L1810-2 [2021-12-14 23:43:32,247 INFO L793 eck$LassoCheckResult]: Loop: 232547#L1810-2 assume !false; 266619#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 266614#L1176 assume !false; 266612#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 266606#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 266589#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 266583#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 266573#L1003 assume !(0 != eval_~tmp~0#1); 266574#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 275966#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 275964#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 275963#L1201-5 assume !(0 == ~T1_E~0); 275962#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 232544#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 231686#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 231687#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 232159#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 231759#L1231-3 assume !(0 == ~T7_E~0); 231760#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 232005#L1241-3 assume !(0 == ~T9_E~0); 233141#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 232998#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 232648#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 232649#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 275951#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 275950#L1271-3 assume !(0 == ~E_2~0); 275949#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 275948#L1281-3 assume !(0 == ~E_4~0); 275947#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 275946#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 275945#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 275944#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 275943#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 275942#L1311-3 assume !(0 == ~E_10~0); 275941#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 275940#L1321-3 assume !(0 == ~E_12~0); 275939#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 275938#L593-42 assume !(1 == ~m_pc~0); 275937#L593-44 is_master_triggered_~__retres1~0#1 := 0; 275936#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 275935#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 275934#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 275933#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 275931#L612-42 assume !(1 == ~t1_pc~0); 232949#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 232950#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 233110#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 231618#L1500-42 assume !(0 != activate_threads_~tmp___0~0#1); 231619#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 233322#L631-42 assume !(1 == ~t2_pc~0); 268104#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 274827#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 274825#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 274826#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 275920#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 275918#L650-42 assume 1 == ~t3_pc~0; 275916#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 275913#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 275911#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 275908#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 275906#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 275904#L669-42 assume !(1 == ~t4_pc~0); 274744#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 274745#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 275889#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 232723#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 232608#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 232609#L688-42 assume !(1 == ~t5_pc~0); 232711#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 232954#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 231482#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 231483#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 231558#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 233193#L707-42 assume !(1 == ~t6_pc~0); 271987#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 271985#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 271983#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 271980#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 271978#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 271976#L726-42 assume !(1 == ~t7_pc~0); 254362#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 271973#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 271971#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 271969#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 271967#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 271965#L745-42 assume !(1 == ~t8_pc~0); 271962#L745-44 is_transmit8_triggered_~__retres1~8#1 := 0; 271960#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 271958#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 271956#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 271954#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 271952#L764-42 assume 1 == ~t9_pc~0; 271949#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 271947#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 271945#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 271943#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 271941#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 271939#L783-42 assume !(1 == ~t10_pc~0); 271936#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 271934#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 271932#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 271930#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 271928#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 271926#L802-42 assume !(1 == ~t11_pc~0); 271924#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 271561#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 271558#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 271556#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 271554#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 271552#L821-42 assume !(1 == ~t12_pc~0); 271549#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 271547#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 271544#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 271542#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 271540#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 271538#L1339-3 assume !(1 == ~M_E~0); 271536#L1339-5 assume !(1 == ~T1_E~0); 271534#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 271532#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 271530#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 271528#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 271526#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 271524#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 271522#L1374-3 assume !(1 == ~T8_E~0); 271519#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 271517#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 271514#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 271512#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 271510#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 271509#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 271508#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 271507#L1414-3 assume !(1 == ~E_3~0); 271506#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 271505#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 271504#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 271503#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 271502#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 271501#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 271500#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 271498#L1454-3 assume !(1 == ~E_11~0); 271496#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 271494#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 271478#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 271470#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 271468#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 271463#L1829 assume !(0 == start_simulation_~tmp~3#1); 267522#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 267243#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 267238#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 267237#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 267236#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 267235#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 267170#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 266896#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 232547#L1810-2 [2021-12-14 23:43:32,247 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:32,247 INFO L85 PathProgramCache]: Analyzing trace with hash 195137279, now seen corresponding path program 1 times [2021-12-14 23:43:32,248 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:32,248 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [899427686] [2021-12-14 23:43:32,248 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:32,248 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:32,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:32,281 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:32,282 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:32,282 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [899427686] [2021-12-14 23:43:32,282 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [899427686] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:32,282 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:32,282 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-14 23:43:32,282 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1314086999] [2021-12-14 23:43:32,282 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:32,283 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-14 23:43:32,283 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:32,283 INFO L85 PathProgramCache]: Analyzing trace with hash 1803862370, now seen corresponding path program 1 times [2021-12-14 23:43:32,283 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:32,283 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2084115980] [2021-12-14 23:43:32,283 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:32,283 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:32,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:32,309 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:32,309 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:32,310 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2084115980] [2021-12-14 23:43:32,310 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2084115980] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:32,310 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:32,310 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:32,310 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [583246888] [2021-12-14 23:43:32,310 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:32,310 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-14 23:43:32,311 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-14 23:43:32,311 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-14 23:43:32,311 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-14 23:43:32,311 INFO L87 Difference]: Start difference. First operand 44705 states and 63711 transitions. cyclomatic complexity: 19010 Second operand has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:32,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-14 23:43:32,932 INFO L93 Difference]: Finished difference Result 107652 states and 154508 transitions. [2021-12-14 23:43:32,932 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-14 23:43:32,933 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 107652 states and 154508 transitions. [2021-12-14 23:43:33,529 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 107232 [2021-12-14 23:43:33,846 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 107652 states to 107652 states and 154508 transitions. [2021-12-14 23:43:33,846 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 107652 [2021-12-14 23:43:33,884 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 107652 [2021-12-14 23:43:33,884 INFO L73 IsDeterministic]: Start isDeterministic. Operand 107652 states and 154508 transitions. [2021-12-14 23:43:33,926 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-14 23:43:33,927 INFO L681 BuchiCegarLoop]: Abstraction has 107652 states and 154508 transitions. [2021-12-14 23:43:33,962 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107652 states and 154508 transitions. [2021-12-14 23:43:34,495 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107652 to 45908. [2021-12-14 23:43:34,535 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45908 states, 45908 states have (on average 1.4140019168772326) internal successors, (64914), 45907 states have internal predecessors, (64914), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:34,603 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45908 states to 45908 states and 64914 transitions. [2021-12-14 23:43:34,603 INFO L704 BuchiCegarLoop]: Abstraction has 45908 states and 64914 transitions. [2021-12-14 23:43:34,603 INFO L587 BuchiCegarLoop]: Abstraction has 45908 states and 64914 transitions. [2021-12-14 23:43:34,603 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-12-14 23:43:34,603 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45908 states and 64914 transitions. [2021-12-14 23:43:34,732 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 45696 [2021-12-14 23:43:34,732 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-14 23:43:34,732 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-14 23:43:34,734 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:34,734 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:34,735 INFO L791 eck$LassoCheckResult]: Stem: 384461#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 384462#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 383980#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 383981#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 384033#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 385532#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 384472#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 384269#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 383674#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 383675#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 384932#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 385054#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 385642#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 385643#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 384398#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 384399#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 384961#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 384874#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 384436#L1201 assume !(0 == ~M_E~0); 384437#L1201-2 assume !(0 == ~T1_E~0); 385398#L1206-1 assume !(0 == ~T2_E~0); 385377#L1211-1 assume !(0 == ~T3_E~0); 385378#L1216-1 assume !(0 == ~T4_E~0); 384253#L1221-1 assume !(0 == ~T5_E~0); 384254#L1226-1 assume !(0 == ~T6_E~0); 383894#L1231-1 assume !(0 == ~T7_E~0); 383895#L1236-1 assume !(0 == ~T8_E~0); 385440#L1241-1 assume !(0 == ~T9_E~0); 384290#L1246-1 assume !(0 == ~T10_E~0); 384291#L1251-1 assume !(0 == ~T11_E~0); 384434#L1256-1 assume !(0 == ~T12_E~0); 383684#L1261-1 assume !(0 == ~E_M~0); 383685#L1266-1 assume !(0 == ~E_1~0); 385616#L1271-1 assume !(0 == ~E_2~0); 385033#L1276-1 assume !(0 == ~E_3~0); 385034#L1281-1 assume !(0 == ~E_4~0); 384976#L1286-1 assume !(0 == ~E_5~0); 384146#L1291-1 assume !(0 == ~E_6~0); 384147#L1296-1 assume !(0 == ~E_7~0); 384748#L1301-1 assume !(0 == ~E_8~0); 384749#L1306-1 assume !(0 == ~E_9~0); 385296#L1311-1 assume !(0 == ~E_10~0); 384096#L1316-1 assume !(0 == ~E_11~0); 384097#L1321-1 assume !(0 == ~E_12~0); 384766#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 384767#L593 assume !(1 == ~m_pc~0); 383986#L593-2 is_master_triggered_~__retres1~0#1 := 0; 383987#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 385594#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 384988#L1492 assume !(0 != activate_threads_~tmp~1#1); 384989#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 385345#L612 assume !(1 == ~t1_pc~0); 385346#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 385629#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 384367#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 383991#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 383992#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 384410#L631 assume !(1 == ~t2_pc~0); 384411#L631-2 is_transmit2_triggered_~__retres1~2#1 := 0; 383767#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 383768#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 384613#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 384614#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 384062#L650 assume !(1 == ~t3_pc~0); 384063#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 384793#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 383988#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 383723#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 383724#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 384954#L669 assume !(1 == ~t4_pc~0); 384955#L669-2 is_transmit4_triggered_~__retres1~4#1 := 0; 385385#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 384397#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 383930#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 383931#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 384155#L688 assume !(1 == ~t5_pc~0); 383946#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 383947#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 384900#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 384830#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 384831#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 384968#L707 assume !(1 == ~t6_pc~0); 385220#L707-2 is_transmit6_triggered_~__retres1~6#1 := 0; 384582#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 384583#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 385482#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 384907#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 384435#L726 assume !(1 == ~t7_pc~0); 384028#L726-2 is_transmit7_triggered_~__retres1~7#1 := 0; 384029#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 385136#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 385494#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 383799#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 383800#L745 assume !(1 == ~t8_pc~0); 384247#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 385325#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 385407#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 384664#L1556 assume !(0 != activate_threads_~tmp___7~0#1); 384665#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 385247#L764 assume 1 == ~t9_pc~0; 384433#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 384271#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 384991#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 385569#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 383819#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 383820#L783 assume !(1 == ~t10_pc~0); 383882#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 383883#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 383923#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 383924#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 384386#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 385388#L802 assume 1 == ~t11_pc~0; 385366#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 383764#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 383765#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 384255#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 384256#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 384366#L821 assume !(1 == ~t12_pc~0); 384628#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 384739#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 383769#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 383770#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 385449#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 385000#L1339 assume !(1 == ~M_E~0); 385001#L1339-2 assume !(1 == ~T1_E~0); 385496#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 385497#L1349-1 assume !(1 == ~T3_E~0); 384759#L1354-1 assume !(1 == ~T4_E~0); 384760#L1359-1 assume !(1 == ~T5_E~0); 385214#L1364-1 assume !(1 == ~T6_E~0); 384196#L1369-1 assume !(1 == ~T7_E~0); 384197#L1374-1 assume !(1 == ~T8_E~0); 384762#L1379-1 assume !(1 == ~T9_E~0); 384763#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 384869#L1389-1 assume !(1 == ~T11_E~0); 385443#L1394-1 assume !(1 == ~T12_E~0); 385444#L1399-1 assume !(1 == ~E_M~0); 385570#L1404-1 assume !(1 == ~E_1~0); 384295#L1409-1 assume !(1 == ~E_2~0); 384296#L1414-1 assume !(1 == ~E_3~0); 385078#L1419-1 assume !(1 == ~E_4~0); 383938#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 383939#L1429-1 assume !(1 == ~E_6~0); 384775#L1434-1 assume !(1 == ~E_7~0); 385467#L1439-1 assume !(1 == ~E_8~0); 383976#L1444-1 assume !(1 == ~E_9~0); 383977#L1449-1 assume !(1 == ~E_10~0); 384348#L1454-1 assume !(1 == ~E_11~0); 384349#L1459-1 assume !(1 == ~E_12~0); 384905#L1464-1 assume { :end_inline_reset_delta_events } true; 384906#L1810-2 [2021-12-14 23:43:34,735 INFO L793 eck$LassoCheckResult]: Loop: 384906#L1810-2 assume !false; 421556#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 421551#L1176 assume !false; 421549#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 421540#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 421528#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 421526#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 421523#L1003 assume !(0 != eval_~tmp~0#1); 421524#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 429291#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 429289#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 429287#L1201-5 assume !(0 == ~T1_E~0); 429284#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 428072#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 428071#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 428070#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 428069#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 428068#L1231-3 assume !(0 == ~T7_E~0); 428067#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 428065#L1241-3 assume !(0 == ~T9_E~0); 428064#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 428063#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 428062#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 428060#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 428058#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 428056#L1271-3 assume !(0 == ~E_2~0); 428054#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 428052#L1281-3 assume !(0 == ~E_4~0); 428050#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 428046#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 428044#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 428042#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 428040#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 428037#L1311-3 assume !(0 == ~E_10~0); 428035#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 428033#L1321-3 assume !(0 == ~E_12~0); 428032#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 428030#L593-42 assume !(1 == ~m_pc~0); 428028#L593-44 is_master_triggered_~__retres1~0#1 := 0; 428026#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 428024#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 428022#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 428021#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 428019#L612-42 assume 1 == ~t1_pc~0; 428020#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 428018#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 428016#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 428012#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 428010#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 428009#L631-42 assume !(1 == ~t2_pc~0); 414583#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 428008#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 428007#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 428005#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 428002#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 428000#L650-42 assume 1 == ~t3_pc~0; 427998#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 427995#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 427993#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 427992#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 427988#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 427986#L669-42 assume !(1 == ~t4_pc~0); 427984#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 427982#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 427979#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 427977#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 427975#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 427974#L688-42 assume 1 == ~t5_pc~0; 427970#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 427968#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 427966#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 427964#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 427961#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 422114#L707-42 assume !(1 == ~t6_pc~0); 422110#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 422107#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 422104#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 422101#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 422098#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 422095#L726-42 assume !(1 == ~t7_pc~0); 415757#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 422089#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 422085#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 422081#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 422071#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 422070#L745-42 assume 1 == ~t8_pc~0; 422068#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 422066#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 422064#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 422062#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 422061#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 422060#L764-42 assume 1 == ~t9_pc~0; 422058#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 422057#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 422056#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 422055#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 422054#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 422053#L783-42 assume 1 == ~t10_pc~0; 422052#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 422050#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 422049#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 422048#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 422047#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 422046#L802-42 assume 1 == ~t11_pc~0; 422044#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 422043#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 422042#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 422041#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 422040#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 422039#L821-42 assume 1 == ~t12_pc~0; 422036#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 422033#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 422031#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 422028#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 422026#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 422024#L1339-3 assume !(1 == ~M_E~0); 422022#L1339-5 assume !(1 == ~T1_E~0); 422020#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 422018#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 422015#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 422013#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 422011#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 422009#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 422007#L1374-3 assume !(1 == ~T8_E~0); 422005#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 422002#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 422000#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 421998#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 421996#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 421994#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 421992#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 421989#L1414-3 assume !(1 == ~E_3~0); 421987#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 421985#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 421983#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 421981#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 421979#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 421977#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 421975#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 421973#L1454-3 assume !(1 == ~E_11~0); 421971#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 421969#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 421954#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 421946#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 421944#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 421904#L1829 assume !(0 == start_simulation_~tmp~3#1); 421902#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 421877#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 421872#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 421869#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 421867#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 421865#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 421863#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 421861#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 384906#L1810-2 [2021-12-14 23:43:34,736 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:34,736 INFO L85 PathProgramCache]: Analyzing trace with hash 639037953, now seen corresponding path program 1 times [2021-12-14 23:43:34,736 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:34,736 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [707116390] [2021-12-14 23:43:34,736 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:34,736 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:34,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:34,917 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:34,917 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:34,917 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [707116390] [2021-12-14 23:43:34,917 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [707116390] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:34,917 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:34,917 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:34,918 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [832606240] [2021-12-14 23:43:34,918 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:34,918 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-14 23:43:34,918 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:34,918 INFO L85 PathProgramCache]: Analyzing trace with hash 2007339034, now seen corresponding path program 1 times [2021-12-14 23:43:34,919 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:34,919 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [854476952] [2021-12-14 23:43:34,919 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:34,919 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:34,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:34,949 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:34,949 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:34,949 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [854476952] [2021-12-14 23:43:34,949 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [854476952] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:34,949 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:34,950 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:34,950 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1927269228] [2021-12-14 23:43:34,950 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:34,950 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-14 23:43:34,950 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-14 23:43:34,951 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-14 23:43:34,951 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-14 23:43:34,951 INFO L87 Difference]: Start difference. First operand 45908 states and 64914 transitions. cyclomatic complexity: 19010 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:35,515 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-14 23:43:35,515 INFO L93 Difference]: Finished difference Result 110755 states and 155711 transitions. [2021-12-14 23:43:35,515 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-14 23:43:35,516 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 110755 states and 155711 transitions. [2021-12-14 23:43:36,110 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 108864 [2021-12-14 23:43:36,404 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 110755 states to 110755 states and 155711 transitions. [2021-12-14 23:43:36,405 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 110755 [2021-12-14 23:43:36,467 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 110755 [2021-12-14 23:43:36,468 INFO L73 IsDeterministic]: Start isDeterministic. Operand 110755 states and 155711 transitions. [2021-12-14 23:43:36,519 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-14 23:43:36,520 INFO L681 BuchiCegarLoop]: Abstraction has 110755 states and 155711 transitions. [2021-12-14 23:43:36,576 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110755 states and 155711 transitions. [2021-12-14 23:43:37,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110755 to 88099. [2021-12-14 23:43:37,487 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 88099 states, 88099 states have (on average 1.4094938648565818) internal successors, (124175), 88098 states have internal predecessors, (124175), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:37,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88099 states to 88099 states and 124175 transitions. [2021-12-14 23:43:37,806 INFO L704 BuchiCegarLoop]: Abstraction has 88099 states and 124175 transitions. [2021-12-14 23:43:37,806 INFO L587 BuchiCegarLoop]: Abstraction has 88099 states and 124175 transitions. [2021-12-14 23:43:37,806 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-12-14 23:43:37,806 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 88099 states and 124175 transitions. [2021-12-14 23:43:38,081 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 87840 [2021-12-14 23:43:38,081 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-14 23:43:38,082 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-14 23:43:38,096 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:38,097 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:38,097 INFO L791 eck$LassoCheckResult]: Stem: 541136#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 541137#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 540652#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 540653#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 540706#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 542222#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 541147#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 540948#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 540347#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 540348#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 541620#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 541744#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 542334#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 542335#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 541071#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 541072#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 541650#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 541560#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 541107#L1201 assume !(0 == ~M_E~0); 541108#L1201-2 assume !(0 == ~T1_E~0); 542087#L1206-1 assume !(0 == ~T2_E~0); 542070#L1211-1 assume !(0 == ~T3_E~0); 542071#L1216-1 assume !(0 == ~T4_E~0); 540933#L1221-1 assume !(0 == ~T5_E~0); 540934#L1226-1 assume !(0 == ~T6_E~0); 540568#L1231-1 assume !(0 == ~T7_E~0); 540569#L1236-1 assume !(0 == ~T8_E~0); 542122#L1241-1 assume !(0 == ~T9_E~0); 540968#L1246-1 assume !(0 == ~T10_E~0); 540969#L1251-1 assume !(0 == ~T11_E~0); 541105#L1256-1 assume !(0 == ~T12_E~0); 540359#L1261-1 assume !(0 == ~E_M~0); 540360#L1266-1 assume !(0 == ~E_1~0); 542306#L1271-1 assume !(0 == ~E_2~0); 541724#L1276-1 assume !(0 == ~E_3~0); 541725#L1281-1 assume !(0 == ~E_4~0); 541666#L1286-1 assume !(0 == ~E_5~0); 540822#L1291-1 assume !(0 == ~E_6~0); 540823#L1296-1 assume !(0 == ~E_7~0); 541425#L1301-1 assume !(0 == ~E_8~0); 541426#L1306-1 assume !(0 == ~E_9~0); 541993#L1311-1 assume !(0 == ~E_10~0); 540773#L1316-1 assume !(0 == ~E_11~0); 540774#L1321-1 assume !(0 == ~E_12~0); 541444#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 541445#L593 assume !(1 == ~m_pc~0); 540658#L593-2 is_master_triggered_~__retres1~0#1 := 0; 540659#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 542281#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 541678#L1492 assume !(0 != activate_threads_~tmp~1#1); 541679#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 542040#L612 assume !(1 == ~t1_pc~0); 542041#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 542325#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 541042#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 540663#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 540664#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 541083#L631 assume !(1 == ~t2_pc~0); 541084#L631-2 is_transmit2_triggered_~__retres1~2#1 := 0; 540441#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 540442#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 541295#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 541296#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 540735#L650 assume !(1 == ~t3_pc~0); 540736#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 541471#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 540660#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 540396#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 540397#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 541643#L669 assume !(1 == ~t4_pc~0); 541644#L669-2 is_transmit4_triggered_~__retres1~4#1 := 0; 542077#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 541070#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 540602#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 540603#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 540831#L688 assume !(1 == ~t5_pc~0); 540618#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 540619#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 541587#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 541509#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 541510#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 541660#L707 assume !(1 == ~t6_pc~0); 541913#L707-2 is_transmit6_triggered_~__retres1~6#1 := 0; 541262#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 541263#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 542170#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 541594#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 541106#L726 assume !(1 == ~t7_pc~0); 540701#L726-2 is_transmit7_triggered_~__retres1~7#1 := 0; 540702#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 541825#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 542181#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 540473#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 540474#L745 assume !(1 == ~t8_pc~0); 540925#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 542022#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 542096#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 541345#L1556 assume !(0 != activate_threads_~tmp___7~0#1); 541346#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 541941#L764 assume !(1 == ~t9_pc~0); 540949#L764-2 is_transmit9_triggered_~__retres1~9#1 := 0; 540950#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 541681#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 542256#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 540493#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 540494#L783 assume !(1 == ~t10_pc~0); 540556#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 540557#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 540596#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 540597#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 541063#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 542079#L802 assume 1 == ~t11_pc~0; 542058#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 540438#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 540439#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 540935#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 540936#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 541041#L821 assume !(1 == ~t12_pc~0); 541309#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 541417#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 540445#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 540446#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 542134#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 541690#L1339 assume !(1 == ~M_E~0); 541691#L1339-2 assume !(1 == ~T1_E~0); 542184#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 542185#L1349-1 assume !(1 == ~T3_E~0); 541438#L1354-1 assume !(1 == ~T4_E~0); 541439#L1359-1 assume !(1 == ~T5_E~0); 541905#L1364-1 assume !(1 == ~T6_E~0); 540874#L1369-1 assume !(1 == ~T7_E~0); 540875#L1374-1 assume !(1 == ~T8_E~0); 541440#L1379-1 assume !(1 == ~T9_E~0); 541441#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 541554#L1389-1 assume !(1 == ~T11_E~0); 542127#L1394-1 assume !(1 == ~T12_E~0); 542128#L1399-1 assume !(1 == ~E_M~0); 542257#L1404-1 assume !(1 == ~E_1~0); 540973#L1409-1 assume !(1 == ~E_2~0); 540974#L1414-1 assume !(1 == ~E_3~0); 541765#L1419-1 assume !(1 == ~E_4~0); 540610#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 540611#L1429-1 assume !(1 == ~E_6~0); 541453#L1434-1 assume !(1 == ~E_7~0); 542154#L1439-1 assume !(1 == ~E_8~0); 540648#L1444-1 assume !(1 == ~E_9~0); 540649#L1449-1 assume !(1 == ~E_10~0); 541024#L1454-1 assume !(1 == ~E_11~0); 541025#L1459-1 assume !(1 == ~E_12~0); 541592#L1464-1 assume { :end_inline_reset_delta_events } true; 541593#L1810-2 [2021-12-14 23:43:38,104 INFO L793 eck$LassoCheckResult]: Loop: 541593#L1810-2 assume !false; 612375#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 612371#L1176 assume !false; 612370#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 612363#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 612351#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 612349#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 612346#L1003 assume !(0 != eval_~tmp~0#1); 612347#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 627662#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 627660#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 627658#L1201-5 assume !(0 == ~T1_E~0); 627655#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 627653#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 627651#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 627650#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 627647#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 627645#L1231-3 assume !(0 == ~T7_E~0); 627643#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 627641#L1241-3 assume !(0 == ~T9_E~0); 627639#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 627637#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 627634#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 627632#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 627630#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 627628#L1271-3 assume !(0 == ~E_2~0); 627626#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 627624#L1281-3 assume !(0 == ~E_4~0); 627621#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 627619#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 627617#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 627615#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 627613#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 627611#L1311-3 assume !(0 == ~E_10~0); 627608#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 627606#L1321-3 assume !(0 == ~E_12~0); 627604#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 627602#L593-42 assume !(1 == ~m_pc~0); 627600#L593-44 is_master_triggered_~__retres1~0#1 := 0; 627598#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 627597#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 627334#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 627333#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 627330#L612-42 assume !(1 == ~t1_pc~0); 627329#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 627328#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 627327#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 627326#L1500-42 assume !(0 != activate_threads_~tmp___0~0#1); 627324#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 612798#L631-42 assume !(1 == ~t2_pc~0); 612796#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 612794#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 612792#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 612790#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 612788#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 612786#L650-42 assume !(1 == ~t3_pc~0); 612783#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 612781#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 612779#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 612777#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 612774#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 612772#L669-42 assume !(1 == ~t4_pc~0); 612770#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 612768#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 612766#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 612764#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 612763#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 612761#L688-42 assume !(1 == ~t5_pc~0); 612759#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 612756#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 612754#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 612752#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 612751#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 612749#L707-42 assume !(1 == ~t6_pc~0); 592070#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 612746#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 612744#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 612740#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 612738#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 612736#L726-42 assume !(1 == ~t7_pc~0); 594542#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 612732#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 612730#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 612728#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 612727#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 612725#L745-42 assume !(1 == ~t8_pc~0); 612721#L745-44 is_transmit8_triggered_~__retres1~8#1 := 0; 612719#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 612717#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 612715#L1556-42 assume !(0 != activate_threads_~tmp___7~0#1); 612711#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 612709#L764-42 assume !(1 == ~t9_pc~0); 574220#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 612706#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 612704#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 612702#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 612699#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 612697#L783-42 assume 1 == ~t10_pc~0; 612695#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 612692#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 612690#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 612688#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 612685#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 612683#L802-42 assume !(1 == ~t11_pc~0); 612681#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 612678#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 612676#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 612675#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 612671#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 612669#L821-42 assume 1 == ~t12_pc~0; 612667#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 612665#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 612660#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 612656#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 612651#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 612650#L1339-3 assume !(1 == ~M_E~0); 612649#L1339-5 assume !(1 == ~T1_E~0); 612648#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 612647#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 612646#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 612645#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 612644#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 612643#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 612642#L1374-3 assume !(1 == ~T8_E~0); 612641#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 612640#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 612638#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 612636#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 612635#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 612634#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 612632#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 612630#L1414-3 assume !(1 == ~E_3~0); 612628#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 612626#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 612624#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 612622#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 612620#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 612617#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 612615#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 612613#L1454-3 assume !(1 == ~E_11~0); 612610#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 612608#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 612592#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 612584#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 612582#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 612426#L1829 assume !(0 == start_simulation_~tmp~3#1); 612423#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 612398#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 612393#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 612391#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 612389#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 612388#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 612384#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 612382#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 541593#L1810-2 [2021-12-14 23:43:38,105 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:38,105 INFO L85 PathProgramCache]: Analyzing trace with hash -1461803262, now seen corresponding path program 1 times [2021-12-14 23:43:38,105 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:38,105 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [385421037] [2021-12-14 23:43:38,106 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:38,106 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:38,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:38,164 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:38,164 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:38,164 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [385421037] [2021-12-14 23:43:38,165 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [385421037] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:38,165 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:38,165 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:38,165 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1095842271] [2021-12-14 23:43:38,165 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:38,165 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-14 23:43:38,166 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:38,166 INFO L85 PathProgramCache]: Analyzing trace with hash -782745116, now seen corresponding path program 1 times [2021-12-14 23:43:38,166 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:38,166 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [655401514] [2021-12-14 23:43:38,166 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:38,166 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:38,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:38,217 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:38,217 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:38,217 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [655401514] [2021-12-14 23:43:38,217 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [655401514] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:38,217 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:38,217 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:38,218 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1021232096] [2021-12-14 23:43:38,218 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:38,218 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-14 23:43:38,218 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-14 23:43:38,218 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-14 23:43:38,219 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-14 23:43:38,219 INFO L87 Difference]: Start difference. First operand 88099 states and 124175 transitions. cyclomatic complexity: 36080 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:39,248 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-14 23:43:39,248 INFO L93 Difference]: Finished difference Result 211666 states and 296668 transitions. [2021-12-14 23:43:39,249 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-14 23:43:39,249 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 211666 states and 296668 transitions. [2021-12-14 23:43:40,459 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 208064 [2021-12-14 23:43:41,169 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 211666 states to 211666 states and 296668 transitions. [2021-12-14 23:43:41,169 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 211666 [2021-12-14 23:43:41,231 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 211666 [2021-12-14 23:43:41,231 INFO L73 IsDeterministic]: Start isDeterministic. Operand 211666 states and 296668 transitions. [2021-12-14 23:43:41,298 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-14 23:43:41,299 INFO L681 BuchiCegarLoop]: Abstraction has 211666 states and 296668 transitions. [2021-12-14 23:43:41,409 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 211666 states and 296668 transitions. [2021-12-14 23:43:43,183 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 211666 to 168994. [2021-12-14 23:43:43,296 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 168994 states, 168994 states have (on average 1.4052806608518646) internal successors, (237484), 168993 states have internal predecessors, (237484), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:43,844 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 168994 states to 168994 states and 237484 transitions. [2021-12-14 23:43:43,845 INFO L704 BuchiCegarLoop]: Abstraction has 168994 states and 237484 transitions. [2021-12-14 23:43:43,845 INFO L587 BuchiCegarLoop]: Abstraction has 168994 states and 237484 transitions. [2021-12-14 23:43:43,845 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-12-14 23:43:43,845 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 168994 states and 237484 transitions. [2021-12-14 23:43:44,328 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 168640 [2021-12-14 23:43:44,328 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-14 23:43:44,328 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-14 23:43:44,336 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:44,336 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:44,336 INFO L791 eck$LassoCheckResult]: Stem: 840903#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 840904#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 840427#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 840428#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 840479#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 841989#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 840915#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 840717#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 840122#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 840123#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 841392#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 841514#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 842106#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 842107#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 840841#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 840842#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 841422#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 841331#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 840879#L1201 assume !(0 == ~M_E~0); 840880#L1201-2 assume !(0 == ~T1_E~0); 841866#L1206-1 assume !(0 == ~T2_E~0); 841850#L1211-1 assume !(0 == ~T3_E~0); 841851#L1216-1 assume !(0 == ~T4_E~0); 840701#L1221-1 assume !(0 == ~T5_E~0); 840702#L1226-1 assume !(0 == ~T6_E~0); 840341#L1231-1 assume !(0 == ~T7_E~0); 840342#L1236-1 assume !(0 == ~T8_E~0); 841899#L1241-1 assume !(0 == ~T9_E~0); 840736#L1246-1 assume !(0 == ~T10_E~0); 840737#L1251-1 assume !(0 == ~T11_E~0); 840877#L1256-1 assume !(0 == ~T12_E~0); 840132#L1261-1 assume !(0 == ~E_M~0); 840133#L1266-1 assume !(0 == ~E_1~0); 842081#L1271-1 assume !(0 == ~E_2~0); 841497#L1276-1 assume !(0 == ~E_3~0); 841498#L1281-1 assume !(0 == ~E_4~0); 841436#L1286-1 assume !(0 == ~E_5~0); 840592#L1291-1 assume !(0 == ~E_6~0); 840593#L1296-1 assume !(0 == ~E_7~0); 841194#L1301-1 assume !(0 == ~E_8~0); 841195#L1306-1 assume !(0 == ~E_9~0); 841766#L1311-1 assume !(0 == ~E_10~0); 840542#L1316-1 assume !(0 == ~E_11~0); 840543#L1321-1 assume !(0 == ~E_12~0); 841213#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 841214#L593 assume !(1 == ~m_pc~0); 840433#L593-2 is_master_triggered_~__retres1~0#1 := 0; 840434#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 842053#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 841451#L1492 assume !(0 != activate_threads_~tmp~1#1); 841452#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 841818#L612 assume !(1 == ~t1_pc~0); 841819#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 842094#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 840810#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 840438#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 840439#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 840854#L631 assume !(1 == ~t2_pc~0); 840855#L631-2 is_transmit2_triggered_~__retres1~2#1 := 0; 840215#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 840216#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 841060#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 841061#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 840508#L650 assume !(1 == ~t3_pc~0); 840509#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 841240#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 840435#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 840171#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 840172#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 841415#L669 assume !(1 == ~t4_pc~0); 841416#L669-2 is_transmit4_triggered_~__retres1~4#1 := 0; 841856#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 840840#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 840375#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 840376#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 840601#L688 assume !(1 == ~t5_pc~0); 840393#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 840394#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 841360#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 841281#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 841282#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 841429#L707 assume !(1 == ~t6_pc~0); 841688#L707-2 is_transmit6_triggered_~__retres1~6#1 := 0; 841026#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 841027#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 841940#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 841367#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 840878#L726 assume !(1 == ~t7_pc~0); 840474#L726-2 is_transmit7_triggered_~__retres1~7#1 := 0; 840475#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 841596#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 841950#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 840247#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 840248#L745 assume !(1 == ~t8_pc~0); 840695#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 841798#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 841876#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 841111#L1556 assume !(0 != activate_threads_~tmp___7~0#1); 841112#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 841715#L764 assume !(1 == ~t9_pc~0); 840718#L764-2 is_transmit9_triggered_~__retres1~9#1 := 0; 840719#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 841454#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 842027#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 840267#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 840268#L783 assume !(1 == ~t10_pc~0); 840329#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 840330#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 840369#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 840370#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 840830#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 841858#L802 assume !(1 == ~t11_pc~0); 841671#L802-2 is_transmit11_triggered_~__retres1~11#1 := 0; 840212#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 840213#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 840703#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 840704#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 840809#L821 assume !(1 == ~t12_pc~0); 841075#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 841186#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 840217#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 840218#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 841909#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 841463#L1339 assume !(1 == ~M_E~0); 841464#L1339-2 assume !(1 == ~T1_E~0); 841952#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 841953#L1349-1 assume !(1 == ~T3_E~0); 841206#L1354-1 assume !(1 == ~T4_E~0); 841207#L1359-1 assume !(1 == ~T5_E~0); 841682#L1364-1 assume !(1 == ~T6_E~0); 840644#L1369-1 assume !(1 == ~T7_E~0); 840645#L1374-1 assume !(1 == ~T8_E~0); 841209#L1379-1 assume !(1 == ~T9_E~0); 841210#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 841326#L1389-1 assume !(1 == ~T11_E~0); 841902#L1394-1 assume !(1 == ~T12_E~0); 841903#L1399-1 assume !(1 == ~E_M~0); 842028#L1404-1 assume !(1 == ~E_1~0); 840741#L1409-1 assume !(1 == ~E_2~0); 840742#L1414-1 assume !(1 == ~E_3~0); 841538#L1419-1 assume !(1 == ~E_4~0); 840385#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 840386#L1429-1 assume !(1 == ~E_6~0); 841222#L1434-1 assume !(1 == ~E_7~0); 841926#L1439-1 assume !(1 == ~E_8~0); 840423#L1444-1 assume !(1 == ~E_9~0); 840424#L1449-1 assume !(1 == ~E_10~0); 840792#L1454-1 assume !(1 == ~E_11~0); 840793#L1459-1 assume !(1 == ~E_12~0); 841365#L1464-1 assume { :end_inline_reset_delta_events } true; 841366#L1810-2 [2021-12-14 23:43:44,337 INFO L793 eck$LassoCheckResult]: Loop: 841366#L1810-2 assume !false; 905851#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 905822#L1176 assume !false; 905819#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 905716#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 905697#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 905693#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 905685#L1003 assume !(0 != eval_~tmp~0#1); 905686#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 922520#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 922514#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 922506#L1201-5 assume !(0 == ~T1_E~0); 922499#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 922417#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 922413#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 922411#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 922409#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 922407#L1231-3 assume !(0 == ~T7_E~0); 922404#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 922402#L1241-3 assume !(0 == ~T9_E~0); 922399#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 922397#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 922395#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 922384#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 922376#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 922367#L1271-3 assume !(0 == ~E_2~0); 922359#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 922350#L1281-3 assume !(0 == ~E_4~0); 922341#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 922340#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 922337#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 922335#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 922333#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 922331#L1311-3 assume !(0 == ~E_10~0); 922329#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 922327#L1321-3 assume !(0 == ~E_12~0); 922325#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 922323#L593-42 assume !(1 == ~m_pc~0); 922321#L593-44 is_master_triggered_~__retres1~0#1 := 0; 922319#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 922317#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 922315#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 922304#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 922295#L612-42 assume 1 == ~t1_pc~0; 922286#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 922277#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 922268#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 922259#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 922251#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 922244#L631-42 assume !(1 == ~t2_pc~0); 920699#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 922227#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 922219#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 922211#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 922204#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 922197#L650-42 assume !(1 == ~t3_pc~0); 922190#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 922169#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 922167#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 922165#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 922163#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 922161#L669-42 assume !(1 == ~t4_pc~0); 922159#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 922158#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 922155#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 922153#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 922151#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 922149#L688-42 assume !(1 == ~t5_pc~0); 922146#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 922143#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 922141#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 922139#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 922137#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 917135#L707-42 assume !(1 == ~t6_pc~0); 917133#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 917131#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 917129#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 917127#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 917125#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 908794#L726-42 assume !(1 == ~t7_pc~0); 908792#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 908790#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 908787#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 908785#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 908783#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 908780#L745-42 assume !(1 == ~t8_pc~0); 908765#L745-44 is_transmit8_triggered_~__retres1~8#1 := 0; 908761#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 908759#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 908757#L1556-42 assume !(0 != activate_threads_~tmp___7~0#1); 908754#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 908752#L764-42 assume !(1 == ~t9_pc~0); 907425#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 908750#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 908748#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 908746#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 908744#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 908742#L783-42 assume 1 == ~t10_pc~0; 908740#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 908738#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 908735#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 908733#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 908731#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 908729#L802-42 assume !(1 == ~t11_pc~0); 873286#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 908724#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 908722#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 908720#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 908718#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 908715#L821-42 assume 1 == ~t12_pc~0; 908713#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 908711#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 908710#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 908708#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 908706#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 908705#L1339-3 assume !(1 == ~M_E~0); 908704#L1339-5 assume !(1 == ~T1_E~0); 908703#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 908701#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 908700#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 908699#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 908698#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 908697#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 908696#L1374-3 assume !(1 == ~T8_E~0); 908695#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 908694#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 908693#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 908691#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 908690#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 908689#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 908688#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 908687#L1414-3 assume !(1 == ~E_3~0); 908686#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 908685#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 908684#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 908683#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 908682#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 908680#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 908678#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 908677#L1454-3 assume !(1 == ~E_11~0); 908676#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 908675#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 908417#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 908393#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 908383#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 908329#L1829 assume !(0 == start_simulation_~tmp~3#1); 907917#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 905985#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 905980#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 905979#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 905977#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 905975#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 905973#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 905971#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 841366#L1810-2 [2021-12-14 23:43:44,337 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:44,337 INFO L85 PathProgramCache]: Analyzing trace with hash 1876235651, now seen corresponding path program 1 times [2021-12-14 23:43:44,337 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:44,337 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [551105388] [2021-12-14 23:43:44,338 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:44,338 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:44,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:44,363 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:44,363 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:44,364 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [551105388] [2021-12-14 23:43:44,364 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [551105388] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:44,364 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:44,364 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-14 23:43:44,364 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [265892693] [2021-12-14 23:43:44,364 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:44,364 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-14 23:43:44,365 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:44,365 INFO L85 PathProgramCache]: Analyzing trace with hash 634035937, now seen corresponding path program 1 times [2021-12-14 23:43:44,365 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:44,365 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1515691878] [2021-12-14 23:43:44,365 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:44,365 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:44,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:44,385 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:44,386 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:44,386 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1515691878] [2021-12-14 23:43:44,386 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1515691878] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:44,386 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:44,386 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:44,386 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1888655932] [2021-12-14 23:43:44,386 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:44,387 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-14 23:43:44,387 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-14 23:43:44,387 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-14 23:43:44,387 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-14 23:43:44,387 INFO L87 Difference]: Start difference. First operand 168994 states and 237484 transitions. cyclomatic complexity: 68494 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:45,616 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-14 23:43:45,616 INFO L93 Difference]: Finished difference Result 168994 states and 237098 transitions. [2021-12-14 23:43:45,617 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-14 23:43:45,618 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 168994 states and 237098 transitions. [2021-12-14 23:43:46,252 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 168640 [2021-12-14 23:43:47,265 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 168994 states to 168994 states and 237098 transitions. [2021-12-14 23:43:47,265 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 168994 [2021-12-14 23:43:47,347 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 168994 [2021-12-14 23:43:47,348 INFO L73 IsDeterministic]: Start isDeterministic. Operand 168994 states and 237098 transitions. [2021-12-14 23:43:47,423 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-14 23:43:47,423 INFO L681 BuchiCegarLoop]: Abstraction has 168994 states and 237098 transitions. [2021-12-14 23:43:47,519 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 168994 states and 237098 transitions. [2021-12-14 23:43:48,855 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 168994 to 168994. [2021-12-14 23:43:48,999 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 168994 states, 168994 states have (on average 1.4029965560907487) internal successors, (237098), 168993 states have internal predecessors, (237098), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:49,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 168994 states to 168994 states and 237098 transitions. [2021-12-14 23:43:49,282 INFO L704 BuchiCegarLoop]: Abstraction has 168994 states and 237098 transitions. [2021-12-14 23:43:49,282 INFO L587 BuchiCegarLoop]: Abstraction has 168994 states and 237098 transitions. [2021-12-14 23:43:49,282 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-12-14 23:43:49,282 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 168994 states and 237098 transitions. [2021-12-14 23:43:50,469 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 168640 [2021-12-14 23:43:50,469 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-14 23:43:50,470 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-14 23:43:50,476 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:50,476 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:50,477 INFO L791 eck$LassoCheckResult]: Stem: 1178905#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1178906#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1178419#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1178420#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1178471#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 1180068#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1178914#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1178711#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1178117#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1178118#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1179398#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1179530#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1180207#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1180208#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1178842#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1178843#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1179428#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1179338#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1178880#L1201 assume !(0 == ~M_E~0); 1178881#L1201-2 assume !(0 == ~T1_E~0); 1179906#L1206-1 assume !(0 == ~T2_E~0); 1179883#L1211-1 assume !(0 == ~T3_E~0); 1179884#L1216-1 assume !(0 == ~T4_E~0); 1178695#L1221-1 assume !(0 == ~T5_E~0); 1178696#L1226-1 assume !(0 == ~T6_E~0); 1178333#L1231-1 assume !(0 == ~T7_E~0); 1178334#L1236-1 assume !(0 == ~T8_E~0); 1179954#L1241-1 assume !(0 == ~T9_E~0); 1178736#L1246-1 assume !(0 == ~T10_E~0); 1178737#L1251-1 assume !(0 == ~T11_E~0); 1178878#L1256-1 assume !(0 == ~T12_E~0); 1178129#L1261-1 assume !(0 == ~E_M~0); 1178130#L1266-1 assume !(0 == ~E_1~0); 1180174#L1271-1 assume !(0 == ~E_2~0); 1179509#L1276-1 assume !(0 == ~E_3~0); 1179510#L1281-1 assume !(0 == ~E_4~0); 1179444#L1286-1 assume !(0 == ~E_5~0); 1178586#L1291-1 assume !(0 == ~E_6~0); 1178587#L1296-1 assume !(0 == ~E_7~0); 1179194#L1301-1 assume !(0 == ~E_8~0); 1179195#L1306-1 assume !(0 == ~E_9~0); 1179795#L1311-1 assume !(0 == ~E_10~0); 1178537#L1316-1 assume !(0 == ~E_11~0); 1178538#L1321-1 assume !(0 == ~E_12~0); 1179214#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1179215#L593 assume !(1 == ~m_pc~0); 1178425#L593-2 is_master_triggered_~__retres1~0#1 := 0; 1178426#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1180142#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1179456#L1492 assume !(0 != activate_threads_~tmp~1#1); 1179457#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1179850#L612 assume !(1 == ~t1_pc~0); 1179851#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1180192#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1178810#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1178430#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 1178431#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1178854#L631 assume !(1 == ~t2_pc~0); 1178855#L631-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1178209#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1178210#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1179063#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 1179064#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1178500#L650 assume !(1 == ~t3_pc~0); 1178501#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1179243#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1178427#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1178166#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 1178167#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1179421#L669 assume !(1 == ~t4_pc~0); 1179422#L669-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1179893#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1178841#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1178367#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 1178368#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1178595#L688 assume !(1 == ~t5_pc~0); 1178385#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1178386#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1179366#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1179290#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 1179291#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1179439#L707 assume !(1 == ~t6_pc~0); 1179710#L707-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1179030#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1179031#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1180004#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 1179376#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1178879#L726 assume !(1 == ~t7_pc~0); 1178466#L726-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1178467#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1179610#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1180020#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 1178241#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1178242#L745 assume !(1 == ~t8_pc~0); 1178687#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1179831#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1179920#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1179112#L1556 assume !(0 != activate_threads_~tmp___7~0#1); 1179113#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1179739#L764 assume !(1 == ~t9_pc~0); 1178712#L764-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1178713#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1179460#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1180114#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 1178261#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1178262#L783 assume !(1 == ~t10_pc~0); 1178321#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1178322#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1178361#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1178362#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 1178835#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1179895#L802 assume !(1 == ~t11_pc~0); 1179689#L802-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1178206#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1178207#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1178697#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 1178698#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1178809#L821 assume !(1 == ~t12_pc~0); 1179077#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1179184#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1178213#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1178214#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 1179967#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1179471#L1339 assume !(1 == ~M_E~0); 1179472#L1339-2 assume !(1 == ~T1_E~0); 1180023#L1344-1 assume !(1 == ~T2_E~0); 1180024#L1349-1 assume !(1 == ~T3_E~0); 1179208#L1354-1 assume !(1 == ~T4_E~0); 1179209#L1359-1 assume !(1 == ~T5_E~0); 1179705#L1364-1 assume !(1 == ~T6_E~0); 1178636#L1369-1 assume !(1 == ~T7_E~0); 1178637#L1374-1 assume !(1 == ~T8_E~0); 1179212#L1379-1 assume !(1 == ~T9_E~0); 1179213#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1179332#L1389-1 assume !(1 == ~T11_E~0); 1179959#L1394-1 assume !(1 == ~T12_E~0); 1179960#L1399-1 assume !(1 == ~E_M~0); 1180115#L1404-1 assume !(1 == ~E_1~0); 1178740#L1409-1 assume !(1 == ~E_2~0); 1178741#L1414-1 assume !(1 == ~E_3~0); 1179550#L1419-1 assume !(1 == ~E_4~0); 1178377#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1178378#L1429-1 assume !(1 == ~E_6~0); 1179223#L1434-1 assume !(1 == ~E_7~0); 1179987#L1439-1 assume !(1 == ~E_8~0); 1178415#L1444-1 assume !(1 == ~E_9~0); 1178416#L1449-1 assume !(1 == ~E_10~0); 1178790#L1454-1 assume !(1 == ~E_11~0); 1178791#L1459-1 assume !(1 == ~E_12~0); 1179371#L1464-1 assume { :end_inline_reset_delta_events } true; 1179372#L1810-2 [2021-12-14 23:43:50,477 INFO L793 eck$LassoCheckResult]: Loop: 1179372#L1810-2 assume !false; 1277212#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1277208#L1176 assume !false; 1277207#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1277204#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1277192#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1277190#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1277187#L1003 assume !(0 != eval_~tmp~0#1); 1277188#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1345552#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1345550#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1345549#L1201-5 assume !(0 == ~T1_E~0); 1345548#L1206-3 assume !(0 == ~T2_E~0); 1345547#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1345545#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1345543#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1345541#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1345539#L1231-3 assume !(0 == ~T7_E~0); 1345537#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1345535#L1241-3 assume !(0 == ~T9_E~0); 1345533#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1345531#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1345529#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1345527#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1345525#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1345523#L1271-3 assume !(0 == ~E_2~0); 1345521#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1345519#L1281-3 assume !(0 == ~E_4~0); 1345517#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1345515#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1345513#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1345511#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1345509#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1345507#L1311-3 assume !(0 == ~E_10~0); 1345505#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1345503#L1321-3 assume !(0 == ~E_12~0); 1345501#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1345499#L593-42 assume !(1 == ~m_pc~0); 1345497#L593-44 is_master_triggered_~__retres1~0#1 := 0; 1345495#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1345493#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1345491#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1345489#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1345486#L612-42 assume !(1 == ~t1_pc~0); 1345484#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 1345738#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1345737#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1345466#L1500-42 assume !(0 != activate_threads_~tmp___0~0#1); 1345463#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1342374#L631-42 assume !(1 == ~t2_pc~0); 1342372#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1342370#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1342369#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1342367#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1342365#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1342363#L650-42 assume !(1 == ~t3_pc~0); 1342360#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 1342358#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1342357#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1342354#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1342352#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1342351#L669-42 assume !(1 == ~t4_pc~0); 1342350#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 1342349#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1342348#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1342347#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 1342345#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1342342#L688-42 assume !(1 == ~t5_pc~0); 1342340#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 1342337#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1342335#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1342333#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1337369#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1277412#L707-42 assume !(1 == ~t6_pc~0); 1277411#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 1277410#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1277409#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1277407#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1277405#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1277404#L726-42 assume !(1 == ~t7_pc~0); 1274826#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 1277403#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1277401#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1277400#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1277399#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1277397#L745-42 assume 1 == ~t8_pc~0; 1277395#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1277396#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1277402#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1277386#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1277384#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1277382#L764-42 assume !(1 == ~t9_pc~0); 1230469#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 1277380#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1277378#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1277376#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1277374#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1277372#L783-42 assume 1 == ~t10_pc~0; 1277369#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1277366#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1277364#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1277361#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1277359#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1277357#L802-42 assume !(1 == ~t11_pc~0); 1214653#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 1277355#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1277353#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1277351#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1277349#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1277347#L821-42 assume 1 == ~t12_pc~0; 1277344#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1277341#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1277339#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1277337#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1277335#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1277333#L1339-3 assume !(1 == ~M_E~0); 1277332#L1339-5 assume !(1 == ~T1_E~0); 1277330#L1344-3 assume !(1 == ~T2_E~0); 1277328#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1277326#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1277324#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1277322#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1277319#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1277317#L1374-3 assume !(1 == ~T8_E~0); 1277315#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1277313#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1277311#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1277309#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1277307#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1277305#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1277303#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1277301#L1414-3 assume !(1 == ~E_3~0); 1277299#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1277297#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1277295#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1277293#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1277291#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1277289#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1277287#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1277285#L1454-3 assume !(1 == ~E_11~0); 1277283#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1277281#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1277266#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1277258#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1277256#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1277252#L1829 assume !(0 == start_simulation_~tmp~3#1); 1277251#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1277241#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1277234#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1277232#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 1277230#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1277229#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1277224#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1277220#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 1179372#L1810-2 [2021-12-14 23:43:50,477 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:50,478 INFO L85 PathProgramCache]: Analyzing trace with hash 2016784261, now seen corresponding path program 1 times [2021-12-14 23:43:50,478 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:50,478 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [255414176] [2021-12-14 23:43:50,478 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:50,478 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:50,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:50,514 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:50,514 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:50,514 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [255414176] [2021-12-14 23:43:50,514 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [255414176] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:50,514 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:50,514 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:50,515 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [880723054] [2021-12-14 23:43:50,515 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:50,515 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-14 23:43:50,515 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:50,515 INFO L85 PathProgramCache]: Analyzing trace with hash -115092127, now seen corresponding path program 1 times [2021-12-14 23:43:50,516 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:50,516 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [874672137] [2021-12-14 23:43:50,516 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:50,516 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:50,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:50,535 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:50,536 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:50,536 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [874672137] [2021-12-14 23:43:50,536 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [874672137] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:50,536 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:50,536 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:50,536 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [35951115] [2021-12-14 23:43:50,537 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:50,537 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-14 23:43:50,537 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-14 23:43:50,537 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-14 23:43:50,537 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-14 23:43:50,538 INFO L87 Difference]: Start difference. First operand 168994 states and 237098 transitions. cyclomatic complexity: 68108 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:51,516 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-14 23:43:51,517 INFO L93 Difference]: Finished difference Result 353383 states and 495980 transitions. [2021-12-14 23:43:51,517 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-14 23:43:51,518 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 353383 states and 495980 transitions. [2021-12-14 23:43:53,671 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 352704 [2021-12-14 23:43:54,980 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 353383 states to 353383 states and 495980 transitions. [2021-12-14 23:43:54,980 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 353383 [2021-12-14 23:43:55,157 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 353383 [2021-12-14 23:43:55,158 INFO L73 IsDeterministic]: Start isDeterministic. Operand 353383 states and 495980 transitions. [2021-12-14 23:43:55,322 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-14 23:43:55,322 INFO L681 BuchiCegarLoop]: Abstraction has 353383 states and 495980 transitions. [2021-12-14 23:43:55,491 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 353383 states and 495980 transitions. [2021-12-14 23:43:58,087 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 353383 to 184535. [2021-12-14 23:43:58,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 184535 states, 184535 states have (on average 1.4053756739913839) internal successors, (259341), 184534 states have internal predecessors, (259341), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:43:58,517 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 184535 states to 184535 states and 259341 transitions. [2021-12-14 23:43:58,517 INFO L704 BuchiCegarLoop]: Abstraction has 184535 states and 259341 transitions. [2021-12-14 23:43:58,517 INFO L587 BuchiCegarLoop]: Abstraction has 184535 states and 259341 transitions. [2021-12-14 23:43:58,517 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-12-14 23:43:58,518 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 184535 states and 259341 transitions. [2021-12-14 23:43:59,103 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 184064 [2021-12-14 23:43:59,104 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-14 23:43:59,104 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-14 23:43:59,115 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:59,115 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:43:59,117 INFO L791 eck$LassoCheckResult]: Stem: 1701302#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1701303#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1700810#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1700811#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1700864#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 1702445#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1701311#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1701107#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1700504#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1700505#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1701786#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1701917#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1702595#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1702596#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1701237#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1701238#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1701816#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1701723#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1701277#L1201 assume !(0 == ~M_E~0); 1701278#L1201-2 assume !(0 == ~T1_E~0); 1702283#L1206-1 assume !(0 == ~T2_E~0); 1702261#L1211-1 assume !(0 == ~T3_E~0); 1702262#L1216-1 assume !(0 == ~T4_E~0); 1701092#L1221-1 assume !(0 == ~T5_E~0); 1701093#L1226-1 assume !(0 == ~T6_E~0); 1700724#L1231-1 assume !(0 == ~T7_E~0); 1700725#L1236-1 assume !(0 == ~T8_E~0); 1702325#L1241-1 assume !(0 == ~T9_E~0); 1701130#L1246-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1701131#L1251-1 assume !(0 == ~T11_E~0); 1701950#L1256-1 assume !(0 == ~T12_E~0); 1701951#L1261-1 assume !(0 == ~E_M~0); 1702599#L1266-1 assume !(0 == ~E_1~0); 1702600#L1271-1 assume !(0 == ~E_2~0); 1701894#L1276-1 assume !(0 == ~E_3~0); 1701895#L1281-1 assume !(0 == ~E_4~0); 1701831#L1286-1 assume !(0 == ~E_5~0); 1700980#L1291-1 assume !(0 == ~E_6~0); 1700981#L1296-1 assume !(0 == ~E_7~0); 1701587#L1301-1 assume !(0 == ~E_8~0); 1701588#L1306-1 assume !(0 == ~E_9~0); 1702168#L1311-1 assume !(0 == ~E_10~0); 1702169#L1316-1 assume !(0 == ~E_11~0); 1702522#L1321-1 assume !(0 == ~E_12~0); 1702523#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1701777#L593 assume !(1 == ~m_pc~0); 1701778#L593-2 is_master_triggered_~__retres1~0#1 := 0; 1702532#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1702533#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1701844#L1492 assume !(0 != activate_threads_~tmp~1#1); 1701845#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1702229#L612 assume !(1 == ~t1_pc~0); 1702230#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1702580#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1702581#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1700822#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 1700823#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1701249#L631 assume !(1 == ~t2_pc~0); 1701250#L631-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1700597#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1700598#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1702005#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 1702391#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1702392#L650 assume !(1 == ~t3_pc~0); 1702733#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1702320#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1702321#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1700553#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 1700554#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1702063#L669 assume !(1 == ~t4_pc~0); 1702269#L669-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1702270#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1701236#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1700758#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 1700759#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1700989#L688 assume !(1 == ~t5_pc~0); 1700776#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1700777#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1701753#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1701754#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 1701826#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1701827#L707 assume !(1 == ~t6_pc~0); 1702726#L707-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1702725#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1702374#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1702375#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 1701763#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1701764#L726 assume !(1 == ~t7_pc~0); 1700859#L726-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1700860#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1702605#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1702606#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 1700629#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1700630#L745 assume !(1 == ~t8_pc~0); 1702207#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1702208#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1702724#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1701507#L1556 assume !(0 != activate_threads_~tmp___7~0#1); 1701508#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1702117#L764 assume !(1 == ~t9_pc~0); 1701108#L764-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1701109#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1702591#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1702592#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 1700649#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1700650#L783 assume !(1 == ~t10_pc~0); 1700711#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1700712#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1702713#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1701229#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 1701230#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1702365#L802 assume !(1 == ~t11_pc~0); 1702068#L802-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1702069#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1701787#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1701788#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 1701202#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1701203#L821 assume !(1 == ~t12_pc~0); 1701575#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1701576#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1700601#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1700602#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 1702343#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1702344#L1339 assume !(1 == ~M_E~0); 1702519#L1339-2 assume !(1 == ~T1_E~0); 1702520#L1344-1 assume !(1 == ~T2_E~0); 1702668#L1349-1 assume !(1 == ~T3_E~0); 1702669#L1354-1 assume !(1 == ~T4_E~0); 1702711#L1359-1 assume !(1 == ~T5_E~0); 1702584#L1364-1 assume !(1 == ~T6_E~0); 1702585#L1369-1 assume !(1 == ~T7_E~0); 1702710#L1374-1 assume !(1 == ~T8_E~0); 1701602#L1379-1 assume !(1 == ~T9_E~0); 1701603#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1701718#L1389-1 assume !(1 == ~T11_E~0); 1702330#L1394-1 assume !(1 == ~T12_E~0); 1702331#L1399-1 assume !(1 == ~E_M~0); 1702501#L1404-1 assume !(1 == ~E_1~0); 1701133#L1409-1 assume !(1 == ~E_2~0); 1701134#L1414-1 assume !(1 == ~E_3~0); 1701937#L1419-1 assume !(1 == ~E_4~0); 1700768#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1700769#L1429-1 assume !(1 == ~E_6~0); 1701615#L1434-1 assume !(1 == ~E_7~0); 1702357#L1439-1 assume !(1 == ~E_8~0); 1700806#L1444-1 assume !(1 == ~E_9~0); 1700807#L1449-1 assume !(1 == ~E_10~0); 1701184#L1454-1 assume !(1 == ~E_11~0); 1701185#L1459-1 assume !(1 == ~E_12~0); 1701759#L1464-1 assume { :end_inline_reset_delta_events } true; 1701760#L1810-2 [2021-12-14 23:43:59,119 INFO L793 eck$LassoCheckResult]: Loop: 1701760#L1810-2 assume !false; 1846620#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1846616#L1176 assume !false; 1846614#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1846604#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1846592#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1846590#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1846586#L1003 assume !(0 != eval_~tmp~0#1); 1846587#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1848241#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1848239#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1848237#L1201-5 assume !(0 == ~T1_E~0); 1848235#L1206-3 assume !(0 == ~T2_E~0); 1848233#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1848231#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1848228#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1848226#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1848224#L1231-3 assume !(0 == ~T7_E~0); 1848222#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1848220#L1241-3 assume !(0 == ~T9_E~0); 1848218#L1246-3 assume !(0 == ~T10_E~0); 1848219#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1869945#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1869944#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1869943#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1869941#L1271-3 assume !(0 == ~E_2~0); 1869938#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1869936#L1281-3 assume !(0 == ~E_4~0); 1869934#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1869932#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1869930#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1869926#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1869924#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1869922#L1311-3 assume !(0 == ~E_10~0); 1869920#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1869917#L1321-3 assume !(0 == ~E_12~0); 1869915#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1869914#L593-42 assume !(1 == ~m_pc~0); 1869913#L593-44 is_master_triggered_~__retres1~0#1 := 0; 1869911#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1869910#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1869909#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1869908#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1869906#L612-42 assume !(1 == ~t1_pc~0); 1869904#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 1869902#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1869901#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1869900#L1500-42 assume !(0 != activate_threads_~tmp___0~0#1); 1869897#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1869895#L631-42 assume !(1 == ~t2_pc~0); 1854663#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1869891#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1869889#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1869887#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1869885#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1869883#L650-42 assume !(1 == ~t3_pc~0); 1869878#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 1869876#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1869874#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1869872#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1869869#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1869867#L669-42 assume !(1 == ~t4_pc~0); 1869863#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 1869862#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1869859#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1869857#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 1869855#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1869853#L688-42 assume 1 == ~t5_pc~0; 1869850#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1869848#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1869845#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1869843#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1869665#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1869424#L707-42 assume !(1 == ~t6_pc~0); 1869422#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 1869420#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1869418#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1869415#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1869413#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1869411#L726-42 assume !(1 == ~t7_pc~0); 1761750#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 1869408#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1869406#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1869404#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1869402#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1869400#L745-42 assume !(1 == ~t8_pc~0); 1869396#L745-44 is_transmit8_triggered_~__retres1~8#1 := 0; 1869393#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1869391#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1869389#L1556-42 assume !(0 != activate_threads_~tmp___7~0#1); 1869386#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1869384#L764-42 assume !(1 == ~t9_pc~0); 1812733#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 1869381#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1869379#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1869377#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1869375#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1869373#L783-42 assume !(1 == ~t10_pc~0); 1869370#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 1869367#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1869365#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1869363#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1869361#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1846884#L802-42 assume !(1 == ~t11_pc~0); 1846881#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 1846878#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1846875#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1846869#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1846866#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1846863#L821-42 assume 1 == ~t12_pc~0; 1846860#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1846855#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1846852#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1846850#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1846848#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1846845#L1339-3 assume !(1 == ~M_E~0); 1846842#L1339-5 assume !(1 == ~T1_E~0); 1846839#L1344-3 assume !(1 == ~T2_E~0); 1846836#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1846832#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1846828#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1846825#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1846822#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1846819#L1374-3 assume !(1 == ~T8_E~0); 1846816#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1846792#L1384-3 assume !(1 == ~T10_E~0); 1846785#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1846783#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1846781#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1846779#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1846778#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1846776#L1414-3 assume !(1 == ~E_3~0); 1846773#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1846771#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1846769#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1846767#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1846765#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1846761#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1846759#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1846757#L1454-3 assume !(1 == ~E_11~0); 1846755#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1846752#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1846735#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1846727#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1846725#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1846667#L1829 assume !(0 == start_simulation_~tmp~3#1); 1846665#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1846640#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1846635#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1846633#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 1846631#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1846628#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1846626#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1846624#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 1701760#L1810-2 [2021-12-14 23:43:59,119 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:59,119 INFO L85 PathProgramCache]: Analyzing trace with hash -227774137, now seen corresponding path program 1 times [2021-12-14 23:43:59,119 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:59,119 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [947447851] [2021-12-14 23:43:59,120 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:59,137 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:59,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:59,176 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:59,176 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:59,176 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [947447851] [2021-12-14 23:43:59,176 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [947447851] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:59,176 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:59,177 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:59,177 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1060389807] [2021-12-14 23:43:59,177 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:59,178 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-14 23:43:59,178 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:43:59,178 INFO L85 PathProgramCache]: Analyzing trace with hash 830627364, now seen corresponding path program 1 times [2021-12-14 23:43:59,178 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:43:59,178 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [557120382] [2021-12-14 23:43:59,178 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:43:59,178 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:43:59,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:43:59,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:43:59,207 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:43:59,207 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [557120382] [2021-12-14 23:43:59,207 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [557120382] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:43:59,207 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:43:59,207 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:43:59,207 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [289549966] [2021-12-14 23:43:59,207 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:43:59,208 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-14 23:43:59,208 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-14 23:43:59,209 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-14 23:43:59,209 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-14 23:43:59,209 INFO L87 Difference]: Start difference. First operand 184535 states and 259341 transitions. cyclomatic complexity: 74810 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:44:00,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-14 23:44:00,254 INFO L93 Difference]: Finished difference Result 168994 states and 236712 transitions. [2021-12-14 23:44:00,254 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-14 23:44:00,258 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 168994 states and 236712 transitions. [2021-12-14 23:44:01,031 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 168640 [2021-12-14 23:44:01,488 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 168994 states to 168994 states and 236712 transitions. [2021-12-14 23:44:01,488 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 168994 [2021-12-14 23:44:01,610 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 168994 [2021-12-14 23:44:01,611 INFO L73 IsDeterministic]: Start isDeterministic. Operand 168994 states and 236712 transitions. [2021-12-14 23:44:01,716 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-14 23:44:01,716 INFO L681 BuchiCegarLoop]: Abstraction has 168994 states and 236712 transitions. [2021-12-14 23:44:01,827 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 168994 states and 236712 transitions. [2021-12-14 23:44:03,315 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 168994 to 168994. [2021-12-14 23:44:03,459 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 168994 states, 168994 states have (on average 1.400712451329633) internal successors, (236712), 168993 states have internal predecessors, (236712), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:44:04,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 168994 states to 168994 states and 236712 transitions. [2021-12-14 23:44:04,212 INFO L704 BuchiCegarLoop]: Abstraction has 168994 states and 236712 transitions. [2021-12-14 23:44:04,212 INFO L587 BuchiCegarLoop]: Abstraction has 168994 states and 236712 transitions. [2021-12-14 23:44:04,212 INFO L425 BuchiCegarLoop]: ======== Iteration 29============ [2021-12-14 23:44:04,212 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 168994 states and 236712 transitions. [2021-12-14 23:44:04,753 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 168640 [2021-12-14 23:44:04,754 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-14 23:44:04,754 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-14 23:44:04,760 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:44:04,760 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-14 23:44:04,760 INFO L791 eck$LassoCheckResult]: Stem: 2054829#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 2054830#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 2054352#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2054353#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2054404#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 2055964#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2054840#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2054639#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2054043#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2054044#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2055323#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2055454#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2056101#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2056102#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2054768#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 2054769#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 2055359#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 2055261#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2054805#L1201 assume !(0 == ~M_E~0); 2054806#L1201-2 assume !(0 == ~T1_E~0); 2055819#L1206-1 assume !(0 == ~T2_E~0); 2055799#L1211-1 assume !(0 == ~T3_E~0); 2055800#L1216-1 assume !(0 == ~T4_E~0); 2054623#L1221-1 assume !(0 == ~T5_E~0); 2054624#L1226-1 assume !(0 == ~T6_E~0); 2054263#L1231-1 assume !(0 == ~T7_E~0); 2054264#L1236-1 assume !(0 == ~T8_E~0); 2055862#L1241-1 assume !(0 == ~T9_E~0); 2054660#L1246-1 assume !(0 == ~T10_E~0); 2054661#L1251-1 assume !(0 == ~T11_E~0); 2054803#L1256-1 assume !(0 == ~T12_E~0); 2054054#L1261-1 assume !(0 == ~E_M~0); 2054055#L1266-1 assume !(0 == ~E_1~0); 2056072#L1271-1 assume !(0 == ~E_2~0); 2055436#L1276-1 assume !(0 == ~E_3~0); 2055437#L1281-1 assume !(0 == ~E_4~0); 2055373#L1286-1 assume !(0 == ~E_5~0); 2054517#L1291-1 assume !(0 == ~E_6~0); 2054518#L1296-1 assume !(0 == ~E_7~0); 2055123#L1301-1 assume !(0 == ~E_8~0); 2055124#L1306-1 assume !(0 == ~E_9~0); 2055716#L1311-1 assume !(0 == ~E_10~0); 2054467#L1316-1 assume !(0 == ~E_11~0); 2054468#L1321-1 assume !(0 == ~E_12~0); 2055145#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2055146#L593 assume !(1 == ~m_pc~0); 2054358#L593-2 is_master_triggered_~__retres1~0#1 := 0; 2054359#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2056043#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2055385#L1492 assume !(0 != activate_threads_~tmp~1#1); 2055386#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2055766#L612 assume !(1 == ~t1_pc~0); 2055767#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2056090#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2054737#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2054363#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 2054364#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2054780#L631 assume !(1 == ~t2_pc~0); 2054781#L631-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2054137#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2054138#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2054983#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 2054984#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2054434#L650 assume !(1 == ~t3_pc~0); 2054435#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2055171#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2054360#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2054093#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 2054094#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2055352#L669 assume !(1 == ~t4_pc~0); 2055353#L669-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2055808#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2054767#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2054298#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 2054299#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2054526#L688 assume !(1 == ~t5_pc~0); 2054316#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2054317#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2055288#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2055209#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 2055210#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2055366#L707 assume !(1 == ~t6_pc~0); 2055632#L707-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2054950#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2054951#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2055909#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 2055297#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2054804#L726 assume !(1 == ~t7_pc~0); 2054399#L726-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2054400#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2055541#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2055919#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 2054169#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2054170#L745 assume !(1 == ~t8_pc~0); 2054617#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2055746#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2055830#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2055034#L1556 assume !(0 != activate_threads_~tmp___7~0#1); 2055035#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2055660#L764 assume !(1 == ~t9_pc~0); 2054640#L764-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2054641#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2055389#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 2056013#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 2054189#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2054190#L783 assume !(1 == ~t10_pc~0); 2054251#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 2054252#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2054291#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 2054292#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 2054756#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2055810#L802 assume !(1 == ~t11_pc~0); 2055613#L802-2 is_transmit11_triggered_~__retres1~11#1 := 0; 2054133#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2054134#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 2054625#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 2054626#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 2054736#L821 assume !(1 == ~t12_pc~0); 2054997#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 2055111#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 2054139#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 2054140#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 2055874#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2055399#L1339 assume !(1 == ~M_E~0); 2055400#L1339-2 assume !(1 == ~T1_E~0); 2055921#L1344-1 assume !(1 == ~T2_E~0); 2055922#L1349-1 assume !(1 == ~T3_E~0); 2055138#L1354-1 assume !(1 == ~T4_E~0); 2055139#L1359-1 assume !(1 == ~T5_E~0); 2055625#L1364-1 assume !(1 == ~T6_E~0); 2054569#L1369-1 assume !(1 == ~T7_E~0); 2054570#L1374-1 assume !(1 == ~T8_E~0); 2055141#L1379-1 assume !(1 == ~T9_E~0); 2055142#L1384-1 assume !(1 == ~T10_E~0); 2055256#L1389-1 assume !(1 == ~T11_E~0); 2055867#L1394-1 assume !(1 == ~T12_E~0); 2055868#L1399-1 assume !(1 == ~E_M~0); 2056014#L1404-1 assume !(1 == ~E_1~0); 2054665#L1409-1 assume !(1 == ~E_2~0); 2054666#L1414-1 assume !(1 == ~E_3~0); 2055478#L1419-1 assume !(1 == ~E_4~0); 2054308#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 2054309#L1429-1 assume !(1 == ~E_6~0); 2055154#L1434-1 assume !(1 == ~E_7~0); 2055892#L1439-1 assume !(1 == ~E_8~0); 2054348#L1444-1 assume !(1 == ~E_9~0); 2054349#L1449-1 assume !(1 == ~E_10~0); 2054718#L1454-1 assume !(1 == ~E_11~0); 2054719#L1459-1 assume !(1 == ~E_12~0); 2055295#L1464-1 assume { :end_inline_reset_delta_events } true; 2055296#L1810-2 [2021-12-14 23:44:04,761 INFO L793 eck$LassoCheckResult]: Loop: 2055296#L1810-2 assume !false; 2121931#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2121926#L1176 assume !false; 2121924#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 2121914#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 2121902#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 2121900#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2121896#L1003 assume !(0 != eval_~tmp~0#1); 2121897#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2199503#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2199502#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2199501#L1201-5 assume !(0 == ~T1_E~0); 2199500#L1206-3 assume !(0 == ~T2_E~0); 2199498#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2199497#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2199496#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2199495#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2199494#L1231-3 assume !(0 == ~T7_E~0); 2199493#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2199492#L1241-3 assume !(0 == ~T9_E~0); 2199490#L1246-3 assume !(0 == ~T10_E~0); 2199488#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 2199486#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 2199484#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2199482#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2199480#L1271-3 assume !(0 == ~E_2~0); 2199477#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2199475#L1281-3 assume !(0 == ~E_4~0); 2199473#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2199471#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2199469#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2199467#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2199464#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2199462#L1311-3 assume !(0 == ~E_10~0); 2199460#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 2199458#L1321-3 assume !(0 == ~E_12~0); 2199456#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2199454#L593-42 assume !(1 == ~m_pc~0); 2199452#L593-44 is_master_triggered_~__retres1~0#1 := 0; 2199450#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2199447#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2199445#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2199443#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2199438#L612-42 assume !(1 == ~t1_pc~0); 2199436#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 2199433#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2199431#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2199429#L1500-42 assume !(0 != activate_threads_~tmp___0~0#1); 2199426#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2199424#L631-42 assume !(1 == ~t2_pc~0); 2196364#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 2199420#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2199418#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2199416#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2199414#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2199412#L650-42 assume 1 == ~t3_pc~0; 2199409#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2199407#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2199404#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2199402#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2199400#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2199398#L669-42 assume !(1 == ~t4_pc~0); 2199396#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 2199394#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2199393#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2199391#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 2199389#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2199387#L688-42 assume !(1 == ~t5_pc~0); 2199385#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 2199382#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2199379#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2199377#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2199375#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2199372#L707-42 assume !(1 == ~t6_pc~0); 2197561#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 2199369#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2199368#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2199366#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2199364#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2199362#L726-42 assume !(1 == ~t7_pc~0); 2137041#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 2199359#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2199356#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2199354#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2199352#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2199350#L745-42 assume !(1 == ~t8_pc~0); 2199346#L745-44 is_transmit8_triggered_~__retres1~8#1 := 0; 2199344#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2199342#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2199340#L1556-42 assume !(0 != activate_threads_~tmp___7~0#1); 2199337#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2199335#L764-42 assume !(1 == ~t9_pc~0); 2195232#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 2199331#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2199329#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 2199327#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2191525#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2191521#L783-42 assume 1 == ~t10_pc~0; 2191519#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 2191516#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2191514#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 2191511#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2191509#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2122199#L802-42 assume !(1 == ~t11_pc~0); 2122198#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 2122197#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2122196#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 2122195#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2122194#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 2122193#L821-42 assume 1 == ~t12_pc~0; 2122192#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 2122190#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 2122189#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 2122188#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 2122187#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2122185#L1339-3 assume !(1 == ~M_E~0); 2122184#L1339-5 assume !(1 == ~T1_E~0); 2122183#L1344-3 assume !(1 == ~T2_E~0); 2122182#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2122180#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2122178#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2122176#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2122174#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2122172#L1374-3 assume !(1 == ~T8_E~0); 2122170#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2122166#L1384-3 assume !(1 == ~T10_E~0); 2122164#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 2122162#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 2122160#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2122157#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2122155#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2122153#L1414-3 assume !(1 == ~E_3~0); 2122150#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2122148#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2122146#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2122144#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2122142#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2122140#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2122137#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 2122135#L1454-3 assume !(1 == ~E_11~0); 2122133#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 2122131#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 2122116#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 2122107#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 2122105#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 2121984#L1829 assume !(0 == start_simulation_~tmp~3#1); 2121982#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 2121949#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 2121944#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 2121942#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 2121940#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2121938#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2121937#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 2121935#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 2055296#L1810-2 [2021-12-14 23:44:04,761 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:44:04,761 INFO L85 PathProgramCache]: Analyzing trace with hash 428436359, now seen corresponding path program 1 times [2021-12-14 23:44:04,762 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:44:04,762 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1976189741] [2021-12-14 23:44:04,762 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:44:04,762 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:44:04,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:44:04,789 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:44:04,789 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:44:04,789 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1976189741] [2021-12-14 23:44:04,789 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1976189741] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:44:04,789 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:44:04,790 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:44:04,790 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1104074706] [2021-12-14 23:44:04,790 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:44:04,790 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-14 23:44:04,790 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-14 23:44:04,791 INFO L85 PathProgramCache]: Analyzing trace with hash 1215686499, now seen corresponding path program 1 times [2021-12-14 23:44:04,791 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-14 23:44:04,791 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [332833780] [2021-12-14 23:44:04,791 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-14 23:44:04,791 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-14 23:44:04,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-14 23:44:04,813 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-14 23:44:04,813 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-14 23:44:04,813 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [332833780] [2021-12-14 23:44:04,814 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [332833780] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-14 23:44:04,814 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-14 23:44:04,814 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-14 23:44:04,814 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2111680824] [2021-12-14 23:44:04,814 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-14 23:44:04,814 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-14 23:44:04,814 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-14 23:44:04,815 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-14 23:44:04,815 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-14 23:44:04,815 INFO L87 Difference]: Start difference. First operand 168994 states and 236712 transitions. cyclomatic complexity: 67722 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-14 23:44:06,395 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-14 23:44:06,395 INFO L93 Difference]: Finished difference Result 350951 states and 489022 transitions. [2021-12-14 23:44:06,395 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-14 23:44:06,396 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 350951 states and 489022 transitions. [2021-12-14 23:44:07,838 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 350144 [2021-12-14 23:44:09,164 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 350951 states to 350951 states and 489022 transitions. [2021-12-14 23:44:09,165 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 350951 [2021-12-14 23:44:09,329 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 350951 [2021-12-14 23:44:09,329 INFO L73 IsDeterministic]: Start isDeterministic. Operand 350951 states and 489022 transitions. [2021-12-14 23:44:09,492 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-14 23:44:09,492 INFO L681 BuchiCegarLoop]: Abstraction has 350951 states and 489022 transitions. [2021-12-14 23:44:09,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 350951 states and 489022 transitions.